arch/arm/mach-pxa/include/mach/pxa-regs.h

   1 /*
   2  *  arch/arm/mach-pxa/include/mach/pxa-regs.h
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    Jun 15, 2001
   6  *  Copyright:  MontaVista Software Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __PXA_REGS_H
  14 #define __PXA_REGS_H
  15
  16
  17 /*
  18  * PXA Chip selects
  19  */
  20
  21 #define PXA_CS0_PHYS    0x00000000
  22 #define PXA_CS1_PHYS    0x04000000
  23 #define PXA_CS2_PHYS    0x08000000
  24 #define PXA_CS3_PHYS    0x0C000000
  25 #define PXA_CS4_PHYS    0x10000000
  26 #define PXA_CS5_PHYS    0x14000000
  27
  28
  29 /*
  30  * Personal Computer Memory Card International Association (PCMCIA) sockets
  31  */
  32
  33 #define PCMCIAPrtSp     0x04000000      /* PCMCIA Partition Space [byte]   */
  34 #define PCMCIASp        (4*PCMCIAPrtSp) /* PCMCIA Space [byte]             */
  35 #define PCMCIAIOSp      PCMCIAPrtSp     /* PCMCIA I/O Space [byte]         */
  36 #define PCMCIAAttrSp    PCMCIAPrtSp     /* PCMCIA Attribute Space [byte]   */
  37 #define PCMCIAMemSp     PCMCIAPrtSp     /* PCMCIA Memory Space [byte]      */
  38
  39 #define PCMCIA0Sp       PCMCIASp        /* PCMCIA 0 Space [byte]           */
  40 #define PCMCIA0IOSp     PCMCIAIOSp      /* PCMCIA 0 I/O Space [byte]       */
  41 #define PCMCIA0AttrSp   PCMCIAAttrSp    /* PCMCIA 0 Attribute Space [byte] */
  42 #define PCMCIA0MemSp    PCMCIAMemSp     /* PCMCIA 0 Memory Space [byte]    */
  43
  44 #define PCMCIA1Sp       PCMCIASp        /* PCMCIA 1 Space [byte]           */
  45 #define PCMCIA1IOSp     PCMCIAIOSp      /* PCMCIA 1 I/O Space [byte]       */
  46 #define PCMCIA1AttrSp   PCMCIAAttrSp    /* PCMCIA 1 Attribute Space [byte] */
  47 #define PCMCIA1MemSp    PCMCIAMemSp     /* PCMCIA 1 Memory Space [byte]    */
  48
  49 #define _PCMCIA(Nb)                     /* PCMCIA [0..1]                   */ \
  50                         (0x20000000 + (Nb)*PCMCIASp)
  51 #define _PCMCIAIO(Nb)   _PCMCIA (Nb)    /* PCMCIA I/O [0..1]               */
  52 #define _PCMCIAAttr(Nb)                 /* PCMCIA Attribute [0..1]         */ \
  53                         (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
  54 #define _PCMCIAMem(Nb)                  /* PCMCIA Memory [0..1]            */ \
  55                         (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
  56
  57 #define _PCMCIA0        _PCMCIA (0)     /* PCMCIA 0                        */
  58 #define _PCMCIA0IO      _PCMCIAIO (0)   /* PCMCIA 0 I/O                    */
  59 #define _PCMCIA0Attr    _PCMCIAAttr (0) /* PCMCIA 0 Attribute              */
  60 #define _PCMCIA0Mem     _PCMCIAMem (0)  /* PCMCIA 0 Memory                 */
  61
  62 #define _PCMCIA1        _PCMCIA (1)     /* PCMCIA 1                        */
  63 #define _PCMCIA1IO      _PCMCIAIO (1)   /* PCMCIA 1 I/O                    */
  64 #define _PCMCIA1Attr    _PCMCIAAttr (1) /* PCMCIA 1 Attribute              */
  65 #define _PCMCIA1Mem     _PCMCIAMem (1)  /* PCMCIA 1 Memory                 */
  66
  67
  68
  69 /*
  70  * DMA Controller
  71  */
  72 #define DCSR(x)         __REG2(0x40000000, (x) << 2)
  73
  74 #define DCSR_RUN        (1 << 31)       /* Run Bit (read / write) */
  75 #define DCSR_NODESC     (1 << 30)       /* No-Descriptor Fetch (read / write) */
  76 #define DCSR_STOPIRQEN  (1 << 29)       /* Stop Interrupt Enable (read / write) */
  77 #define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
  78 #define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
  79 #define DCSR_ENDINTR    (1 << 2)        /* End Interrupt (read / write) */
  80 #define DCSR_STARTINTR  (1 << 1)        /* Start Interrupt (read / write) */
  81 #define DCSR_BUSERR     (1 << 0)        /* Bus Error Interrupt (read / write) */
  82
  83 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  84 #define DCSR_EORIRQEN   (1 << 28)       /* End of Receive Interrupt Enable (R/W) */
  85 #define DCSR_EORJMPEN   (1 << 27)       /* Jump to next descriptor on EOR */
  86 #define DCSR_EORSTOPEN  (1 << 26)       /* STOP on an EOR */
  87 #define DCSR_SETCMPST   (1 << 25)       /* Set Descriptor Compare Status */
  88 #define DCSR_CLRCMPST   (1 << 24)       /* Clear Descriptor Compare Status */
  89 #define DCSR_CMPST      (1 << 10)       /* The Descriptor Compare Status */
  90 #define DCSR_EORINTR    (1 << 9)        /* The end of Receive */
  91 #endif
  92
  93 #define DALGN           __REG(0x400000a0)  /* DMA Alignment Register */
  94 #define DINT            __REG(0x400000f0)  /* DMA Interrupt Register */
  95
  96 #define DRCMR(n)        (*(((n) < 64) ? \
  97                         &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
  98                         &__REG2(0x40001100, ((n) & 0x3f) << 2)))
  99
 100 #define DRCMR_MAPVLD    (1 << 7)        /* Map Valid (read / write) */
 101 #define DRCMR_CHLNUM    0x1f            /* mask for Channel Number (read / write) */
 102
 103 #define DDADR(x)        __REG2(0x40000200, (x) << 4)
 104 #define DSADR(x)        __REG2(0x40000204, (x) << 4)
 105 #define DTADR(x)        __REG2(0x40000208, (x) << 4)
 106 #define DCMD(x)         __REG2(0x4000020c, (x) << 4)
 107
 108 #define DDADR_DESCADDR  0xfffffff0      /* Address of next descriptor (mask) */
 109 #define DDADR_STOP      (1 << 0)        /* Stop (read / write) */
 110
 111 #define DCMD_INCSRCADDR (1 << 31)       /* Source Address Increment Setting. */
 112 #define DCMD_INCTRGADDR (1 << 30)       /* Target Address Increment Setting. */
 113 #define DCMD_FLOWSRC    (1 << 29)       /* Flow Control by the source. */
 114 #define DCMD_FLOWTRG    (1 << 28)       /* Flow Control by the target. */
 115 #define DCMD_STARTIRQEN (1 << 22)       /* Start Interrupt Enable */
 116 #define DCMD_ENDIRQEN   (1 << 21)       /* End Interrupt Enable */
 117 #define DCMD_ENDIAN     (1 << 18)       /* Device Endian-ness. */
 118 #define DCMD_BURST8     (1 << 16)       /* 8 byte burst */
 119 #define DCMD_BURST16    (2 << 16)       /* 16 byte burst */
 120 #define DCMD_BURST32    (3 << 16)       /* 32 byte burst */
 121 #define DCMD_WIDTH1     (1 << 14)       /* 1 byte width */
 122 #define DCMD_WIDTH2     (2 << 14)       /* 2 byte width (HalfWord) */
 123 #define DCMD_WIDTH4     (3 << 14)       /* 4 byte width (Word) */
 124 #define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
 125
 126
 127 /*
 128  * UARTs
 129  */
 130
 131 /* Full Function UART (FFUART) */
 132 #define FFUART          FFRBR
 133 #define FFRBR           __REG(0x40100000)  /* Receive Buffer Register (read only) */
 134 #define FFTHR           __REG(0x40100000)  /* Transmit Holding Register (write only) */
 135 #define FFIER           __REG(0x40100004)  /* Interrupt Enable Register (read/write) */
 136 #define FFIIR           __REG(0x40100008)  /* Interrupt ID Register (read only) */
 137 #define FFFCR           __REG(0x40100008)  /* FIFO Control Register (write only) */
 138 #define FFLCR           __REG(0x4010000C)  /* Line Control Register (read/write) */
 139 #define FFMCR           __REG(0x40100010)  /* Modem Control Register (read/write) */
 140 #define FFLSR           __REG(0x40100014)  /* Line Status Register (read only) */
 141 #define FFMSR           __REG(0x40100018)  /* Modem Status Register (read only) */
 142 #define FFSPR           __REG(0x4010001C)  /* Scratch Pad Register (read/write) */
 143 #define FFISR           __REG(0x40100020)  /* Infrared Selection Register (read/write) */
 144 #define FFDLL           __REG(0x40100000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
 145 #define FFDLH           __REG(0x40100004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
 146
 147 /* Bluetooth UART (BTUART) */
 148 #define BTUART          BTRBR
 149 #define BTRBR           __REG(0x40200000)  /* Receive Buffer Register (read only) */
 150 #define BTTHR           __REG(0x40200000)  /* Transmit Holding Register (write only) */
 151 #define BTIER           __REG(0x40200004)  /* Interrupt Enable Register (read/write) */
 152 #define BTIIR           __REG(0x40200008)  /* Interrupt ID Register (read only) */
 153 #define BTFCR           __REG(0x40200008)  /* FIFO Control Register (write only) */
 154 #define BTLCR           __REG(0x4020000C)  /* Line Control Register (read/write) */
 155 #define BTMCR           __REG(0x40200010)  /* Modem Control Register (read/write) */
 156 #define BTLSR           __REG(0x40200014)  /* Line Status Register (read only) */
 157 #define BTMSR           __REG(0x40200018)  /* Modem Status Register (read only) */
 158 #define BTSPR           __REG(0x4020001C)  /* Scratch Pad Register (read/write) */
 159 #define BTISR           __REG(0x40200020)  /* Infrared Selection Register (read/write) */
 160 #define BTDLL           __REG(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
 161 #define BTDLH           __REG(0x40200004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
 162
 163 /* Standard UART (STUART) */
 164 #define STUART          STRBR
 165 #define STRBR           __REG(0x40700000)  /* Receive Buffer Register (read only) */
 166 #define STTHR           __REG(0x40700000)  /* Transmit Holding Register (write only) */
 167 #define STIER           __REG(0x40700004)  /* Interrupt Enable Register (read/write) */
 168 #define STIIR           __REG(0x40700008)  /* Interrupt ID Register (read only) */
 169 #define STFCR           __REG(0x40700008)  /* FIFO Control Register (write only) */
 170 #define STLCR           __REG(0x4070000C)  /* Line Control Register (read/write) */
 171 #define STMCR           __REG(0x40700010)  /* Modem Control Register (read/write) */
 172 #define STLSR           __REG(0x40700014)  /* Line Status Register (read only) */
 173 #define STMSR           __REG(0x40700018)  /* Reserved */
 174 #define STSPR           __REG(0x4070001C)  /* Scratch Pad Register (read/write) */
 175 #define STISR           __REG(0x40700020)  /* Infrared Selection Register (read/write) */
 176 #define STDLL           __REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
 177 #define STDLH           __REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
 178
 179 /* Hardware UART (HWUART) */
 180 #define HWUART          HWRBR
 181 #define HWRBR           __REG(0x41600000)  /* Receive Buffer Register (read only) */
 182 #define HWTHR           __REG(0x41600000)  /* Transmit Holding Register (write only) */
 183 #define HWIER           __REG(0x41600004)  /* Interrupt Enable Register (read/write) */
 184 #define HWIIR           __REG(0x41600008)  /* Interrupt ID Register (read only) */
 185 #define HWFCR           __REG(0x41600008)  /* FIFO Control Register (write only) */
 186 #define HWLCR           __REG(0x4160000C)  /* Line Control Register (read/write) */
 187 #define HWMCR           __REG(0x41600010)  /* Modem Control Register (read/write) */
 188 #define HWLSR           __REG(0x41600014)  /* Line Status Register (read only) */
 189 #define HWMSR           __REG(0x41600018)  /* Modem Status Register (read only) */
 190 #define HWSPR           __REG(0x4160001C)  /* Scratch Pad Register (read/write) */
 191 #define HWISR           __REG(0x41600020)  /* Infrared Selection Register (read/write) */
 192 #define HWFOR           __REG(0x41600024)  /* Receive FIFO Occupancy Register (read only) */
 193 #define HWABR           __REG(0x41600028)  /* Auto-Baud Control Register (read/write) */
 194 #define HWACR           __REG(0x4160002C)  /* Auto-Baud Count Register (read only) */
 195 #define HWDLL           __REG(0x41600000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
 196 #define HWDLH           __REG(0x41600004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
 197
 198 #define IER_DMAE        (1 << 7)        /* DMA Requests Enable */
 199 #define IER_UUE         (1 << 6)        /* UART Unit Enable */
 200 #define IER_NRZE        (1 << 5)        /* NRZ coding Enable */
 201 #define IER_RTIOE       (1 << 4)        /* Receiver Time Out Interrupt Enable */
 202 #define IER_MIE         (1 << 3)        /* Modem Interrupt Enable */
 203 #define IER_RLSE        (1 << 2)        /* Receiver Line Status Interrupt Enable */
 204 #define IER_TIE         (1 << 1)        /* Transmit Data request Interrupt Enable */
 205 #define IER_RAVIE       (1 << 0)        /* Receiver Data Available Interrupt Enable */
 206
 207 #define IIR_FIFOES1     (1 << 7)        /* FIFO Mode Enable Status */
 208 #define IIR_FIFOES0     (1 << 6)        /* FIFO Mode Enable Status */
 209 #define IIR_TOD         (1 << 3)        /* Time Out Detected */
 210 #define IIR_IID2        (1 << 2)        /* Interrupt Source Encoded */
 211 #define IIR_IID1        (1 << 1)        /* Interrupt Source Encoded */
 212 #define IIR_IP          (1 << 0)        /* Interrupt Pending (active low) */
 213
 214 #define FCR_ITL2        (1 << 7)        /* Interrupt Trigger Level */
 215 #define FCR_ITL1        (1 << 6)        /* Interrupt Trigger Level */
 216 #define FCR_RESETTF     (1 << 2)        /* Reset Transmitter FIFO */
 217 #define FCR_RESETRF     (1 << 1)        /* Reset Receiver FIFO */
 218 #define FCR_TRFIFOE     (1 << 0)        /* Transmit and Receive FIFO Enable */
 219 #define FCR_ITL_1       (0)
 220 #define FCR_ITL_8       (FCR_ITL1)
 221 #define FCR_ITL_16      (FCR_ITL2)
 222 #define FCR_ITL_32      (FCR_ITL2|FCR_ITL1)
 223
 224 #define LCR_DLAB        (1 << 7)        /* Divisor Latch Access Bit */
 225 #define LCR_SB          (1 << 6)        /* Set Break */
 226 #define LCR_STKYP       (1 << 5)        /* Sticky Parity */
 227 #define LCR_EPS         (1 << 4)        /* Even Parity Select */
 228 #define LCR_PEN         (1 << 3)        /* Parity Enable */
 229 #define LCR_STB         (1 << 2)        /* Stop Bit */
 230 #define LCR_WLS1        (1 << 1)        /* Word Length Select */
 231 #define LCR_WLS0        (1 << 0)        /* Word Length Select */
 232
 233 #define LSR_FIFOE       (1 << 7)        /* FIFO Error Status */
 234 #define LSR_TEMT        (1 << 6)        /* Transmitter Empty */
 235 #define LSR_TDRQ        (1 << 5)        /* Transmit Data Request */
 236 #define LSR_BI          (1 << 4)        /* Break Interrupt */
 237 #define LSR_FE          (1 << 3)        /* Framing Error */
 238 #define LSR_PE          (1 << 2)        /* Parity Error */
 239 #define LSR_OE          (1 << 1)        /* Overrun Error */
 240 #define LSR_DR          (1 << 0)        /* Data Ready */
 241
 242 #define MCR_LOOP        (1 << 4)
 243 #define MCR_OUT2        (1 << 3)        /* force MSR_DCD in loopback mode */
 244 #define MCR_OUT1        (1 << 2)        /* force MSR_RI in loopback mode */
 245 #define MCR_RTS         (1 << 1)        /* Request to Send */
 246 #define MCR_DTR         (1 << 0)        /* Data Terminal Ready */
 247
 248 #define MSR_DCD         (1 << 7)        /* Data Carrier Detect */
 249 #define MSR_RI          (1 << 6)        /* Ring Indicator */
 250 #define MSR_DSR         (1 << 5)        /* Data Set Ready */
 251 #define MSR_CTS         (1 << 4)        /* Clear To Send */
 252 #define MSR_DDCD        (1 << 3)        /* Delta Data Carrier Detect */
 253 #define MSR_TERI        (1 << 2)        /* Trailing Edge Ring Indicator */
 254 #define MSR_DDSR        (1 << 1)        /* Delta Data Set Ready */
 255 #define MSR_DCTS        (1 << 0)        /* Delta Clear To Send */
 256
 257 /*
 258  * IrSR (Infrared Selection Register)
 259  */
 260 #define STISR_RXPL      (1 << 4)        /* Receive Data Polarity */
 261 #define STISR_TXPL      (1 << 3)        /* Transmit Data Polarity */
 262 #define STISR_XMODE     (1 << 2)        /* Transmit Pulse Width Select */
 263 #define STISR_RCVEIR    (1 << 1)        /* Receiver SIR Enable */
 264 #define STISR_XMITIR    (1 << 0)        /* Transmitter SIR Enable */
 265
 266
 267 /*
 268  * I2C registers - moved into drivers/i2c/busses/i2c-pxa.c
 269  */
 270
 271 /*
 272  * Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c
 273  */
 274
 275 /*
 276  * AC97 Controller registers
 277  */
 278
 279 #define POCR            __REG(0x40500000)  /* PCM Out Control Register */
 280 #define POCR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
 281 #define POCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
 282
 283 #define PICR            __REG(0x40500004)  /* PCM In Control Register */
 284 #define PICR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
 285 #define PICR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
 286
 287 #define MCCR            __REG(0x40500008)  /* Mic In Control Register */
 288 #define MCCR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
 289 #define MCCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
 290
 291 #define GCR             __REG(0x4050000C)  /* Global Control Register */
 292 #ifdef CONFIG_PXA3xx
 293 #define GCR_CLKBPB      (1 << 31)       /* Internal clock enable */
 294 #endif
 295 #define GCR_nDMAEN      (1 << 24)       /* non DMA Enable */
 296 #define GCR_CDONE_IE    (1 << 19)       /* Command Done Interrupt Enable */
 297 #define GCR_SDONE_IE    (1 << 18)       /* Status Done Interrupt Enable */
 298 #define GCR_SECRDY_IEN  (1 << 9)        /* Secondary Ready Interrupt Enable */
 299 #define GCR_PRIRDY_IEN  (1 << 8)        /* Primary Ready Interrupt Enable */
 300 #define GCR_SECRES_IEN  (1 << 5)        /* Secondary Resume Interrupt Enable */
 301 #define GCR_PRIRES_IEN  (1 << 4)        /* Primary Resume Interrupt Enable */
 302 #define GCR_ACLINK_OFF  (1 << 3)        /* AC-link Shut Off */
 303 #define GCR_WARM_RST    (1 << 2)        /* AC97 Warm Reset */
 304 #define GCR_COLD_RST    (1 << 1)        /* AC'97 Cold Reset (0 = active) */
 305 #define GCR_GIE         (1 << 0)        /* Codec GPI Interrupt Enable */
 306
 307 #define POSR            __REG(0x40500010)  /* PCM Out Status Register */
 308 #define POSR_FIFOE      (1 << 4)        /* FIFO error */
 309 #define POSR_FSR        (1 << 2)        /* FIFO Service Request */
 310
 311 #define PISR            __REG(0x40500014)  /* PCM In Status Register */
 312 #define PISR_FIFOE      (1 << 4)        /* FIFO error */
 313 #define PISR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
 314 #define PISR_FSR        (1 << 2)        /* FIFO Service Request */
 315
 316 #define MCSR            __REG(0x40500018)  /* Mic In Status Register */
 317 #define MCSR_FIFOE      (1 << 4)        /* FIFO error */
 318 #define MCSR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
 319 #define MCSR_FSR        (1 << 2)        /* FIFO Service Request */
 320
 321 #define GSR             __REG(0x4050001C)  /* Global Status Register */
 322 #define GSR_CDONE       (1 << 19)       /* Command Done */
 323 #define GSR_SDONE       (1 << 18)       /* Status Done */
 324 #define GSR_RDCS        (1 << 15)       /* Read Completion Status */
 325 #define GSR_BIT3SLT12   (1 << 14)       /* Bit 3 of slot 12 */
 326 #define GSR_BIT2SLT12   (1 << 13)       /* Bit 2 of slot 12 */
 327 #define GSR_BIT1SLT12   (1 << 12)       /* Bit 1 of slot 12 */
 328 #define GSR_SECRES      (1 << 11)       /* Secondary Resume Interrupt */
 329 #define GSR_PRIRES      (1 << 10)       /* Primary Resume Interrupt */
 330 #define GSR_SCR         (1 << 9)        /* Secondary Codec Ready */
 331 #define GSR_PCR         (1 << 8)        /*  Primary Codec Ready */
 332 #define GSR_MCINT       (1 << 7)        /* Mic In Interrupt */
 333 #define GSR_POINT       (1 << 6)        /* PCM Out Interrupt */
 334 #define GSR_PIINT       (1 << 5)        /* PCM In Interrupt */
 335 #define GSR_ACOFFD      (1 << 3)        /* AC-link Shut Off Done */
 336 #define GSR_MOINT       (1 << 2)        /* Modem Out Interrupt */
 337 #define GSR_MIINT       (1 << 1)        /* Modem In Interrupt */
 338 #define GSR_GSCI        (1 << 0)        /* Codec GPI Status Change Interrupt */
 339
 340 #define CAR             __REG(0x40500020)  /* CODEC Access Register */
 341 #define CAR_CAIP        (1 << 0)        /* Codec Access In Progress */
 342
 343 #define PCDR            __REG(0x40500040)  /* PCM FIFO Data Register */
 344 #define MCDR            __REG(0x40500060)  /* Mic-in FIFO Data Register */
 345
 346 #define MOCR            __REG(0x40500100)  /* Modem Out Control Register */
 347 #define MOCR_FEIE       (1 << 3)        /* FIFO Error */
 348 #define MOCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
 349
 350 #define MICR            __REG(0x40500108)  /* Modem In Control Register */
 351 #define MICR_FEIE       (1 << 3)        /* FIFO Error */
 352 #define MICR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
 353
 354 #define MOSR            __REG(0x40500110)  /* Modem Out Status Register */
 355 #define MOSR_FIFOE      (1 << 4)        /* FIFO error */
 356 #define MOSR_FSR        (1 << 2)        /* FIFO Service Request */
 357
 358 #define MISR            __REG(0x40500118)  /* Modem In Status Register */
 359 #define MISR_FIFOE      (1 << 4)        /* FIFO error */
 360 #define MISR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
 361 #define MISR_FSR        (1 << 2)        /* FIFO Service Request */
 362
 363 #define MODR            __REG(0x40500140)  /* Modem FIFO Data Register */
 364
 365 #define PAC_REG_BASE    __REG(0x40500200)  /* Primary Audio Codec */
 366 #define SAC_REG_BASE    __REG(0x40500300)  /* Secondary Audio Codec */
 367 #define PMC_REG_BASE    __REG(0x40500400)  /* Primary Modem Codec */
 368 #define SMC_REG_BASE    __REG(0x40500500)  /* Secondary Modem Codec */
 369
 370
 371 /*
 372  * Fast Infrared Communication Port - moved into drivers/net/irda/pxaficp_ir.c
 373  */
 374
 375 /*
 376  * Real Time Clock
 377  */
 378
 379 #define RCNR            __REG(0x40900000)  /* RTC Count Register */
 380 #define RTAR            __REG(0x40900004)  /* RTC Alarm Register */
 381 #define RTSR            __REG(0x40900008)  /* RTC Status Register */
 382 #define RTTR            __REG(0x4090000C)  /* RTC Timer Trim Register */
 383 #define PIAR            __REG(0x40900038)  /* Periodic Interrupt Alarm Register */
 384
 385 #define RTSR_PICE       (1 << 15)       /* Periodic interrupt count enable */
 386 #define RTSR_PIALE      (1 << 14)       /* Periodic interrupt Alarm enable */
 387 #define RTSR_HZE        (1 << 3)        /* HZ interrupt enable */
 388 #define RTSR_ALE        (1 << 2)        /* RTC alarm interrupt enable */
 389 #define RTSR_HZ         (1 << 1)        /* HZ rising-edge detected */
 390 #define RTSR_AL         (1 << 0)        /* RTC alarm detected */
 391
 392
 393 /*
 394  * OS Timer & Match Registers
 395  */
 396
 397 #define OSMR0           __REG(0x40A00000)  /* */
 398 #define OSMR1           __REG(0x40A00004)  /* */
 399 #define OSMR2           __REG(0x40A00008)  /* */
 400 #define OSMR3           __REG(0x40A0000C)  /* */
 401 #define OSMR4           __REG(0x40A00080)  /* */
 402 #define OSCR            __REG(0x40A00010)  /* OS Timer Counter Register */
 403 #define OSCR4           __REG(0x40A00040)  /* OS Timer Counter Register */
 404 #define OMCR4           __REG(0x40A000C0)  /* */
 405 #define OSSR            __REG(0x40A00014)  /* OS Timer Status Register */
 406 #define OWER            __REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
 407 #define OIER            __REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */
 408
 409 #define OSSR_M3         (1 << 3)        /* Match status channel 3 */
 410 #define OSSR_M2         (1 << 2)        /* Match status channel 2 */
 411 #define OSSR_M1         (1 << 1)        /* Match status channel 1 */
 412 #define OSSR_M0         (1 << 0)        /* Match status channel 0 */
 413
 414 #define OWER_WME        (1 << 0)        /* Watchdog Match Enable */
 415
 416 #define OIER_E3         (1 << 3)        /* Interrupt enable channel 3 */
 417 #define OIER_E2         (1 << 2)        /* Interrupt enable channel 2 */
 418 #define OIER_E1         (1 << 1)        /* Interrupt enable channel 1 */
 419 #define OIER_E0         (1 << 0)        /* Interrupt enable channel 0 */
 420
 421
 422 /*
 423  * Interrupt Controller
 424  */
 425
 426 #define ICIP            __REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
 427 #define ICMR            __REG(0x40D00004)  /* Interrupt Controller Mask Register */
 428 #define ICLR            __REG(0x40D00008)  /* Interrupt Controller Level Register */
 429 #define ICFP            __REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
 430 #define ICPR            __REG(0x40D00010)  /* Interrupt Controller Pending Register */
 431 #define ICCR            __REG(0x40D00014)  /* Interrupt Controller Control Register */
 432
 433 #define ICIP2           __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
 434 #define ICMR2           __REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
 435 #define ICLR2           __REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
 436 #define ICFP2           __REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
 437 #define ICPR2           __REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
 438
 439 /*
 440  * General Purpose I/O
 441  */
 442
 443 #define GPIO0_BASE      ((void __iomem *)io_p2v(0x40E00000))
 444 #define GPIO1_BASE      ((void __iomem *)io_p2v(0x40E00004))
 445 #define GPIO2_BASE      ((void __iomem *)io_p2v(0x40E00008))
 446 #define GPIO3_BASE      ((void __iomem *)io_p2v(0x40E00100))
 447
 448 #define GPLR_OFFSET     0x00
 449 #define GPDR_OFFSET     0x0C
 450 #define GPSR_OFFSET     0x18
 451 #define GPCR_OFFSET     0x24
 452 #define GRER_OFFSET     0x30
 453 #define GFER_OFFSET     0x3C
 454 #define GEDR_OFFSET     0x48
 455
 456 #define GPLR0           __REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
 457 #define GPLR1           __REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
 458 #define GPLR2           __REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */
 459
 460 #define GPDR0           __REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
 461 #define GPDR1           __REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
 462 #define GPDR2           __REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<80:64> */
 463
 464 #define GPSR0           __REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
 465 #define GPSR1           __REG(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
 466 #define GPSR2           __REG(0x40E00020)  /* GPIO Pin Output Set Register GPIO<80:64> */
 467
 468 #define GPCR0           __REG(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
 469 #define GPCR1           __REG(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
 470 #define GPCR2           __REG(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <80:64> */
 471
 472 #define GRER0           __REG(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
 473 #define GRER1           __REG(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
 474 #define GRER2           __REG(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<80:64> */
 475
 476 #define GFER0           __REG(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
 477 #define GFER1           __REG(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
 478 #define GFER2           __REG(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<80:64> */
 479
 480 #define GEDR0           __REG(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
 481 #define GEDR1           __REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
 482 #define GEDR2           __REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<80:64> */
 483
 484 #define GAFR0_L         __REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
 485 #define GAFR0_U         __REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
 486 #define GAFR1_L         __REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
 487 #define GAFR1_U         __REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
 488 #define GAFR2_L         __REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
 489 #define GAFR2_U         __REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO<95-80> */
 490 #define GAFR3_L         __REG(0x40E0006C)  /* GPIO Alternate Function Select Register GPIO<111:96> */
 491 #define GAFR3_U         __REG(0x40E00070)  /* GPIO Alternate Function Select Register GPIO<127:112> */
 492
 493 #define GPLR3           __REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<127:96> */
 494 #define GPDR3           __REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<127:96> */
 495 #define GPSR3           __REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<127:96> */
 496 #define GPCR3           __REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO<127:96> */
 497 #define GRER3           __REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
 498 #define GFER3           __REG(0x40E0013C)  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
 499 #define GEDR3           __REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<127:96> */
 500
 501 /* More handy macros.  The argument is a literal GPIO number. */
 502
 503 #define GPIO_bit(x)     (1 << ((x) & 0x1f))
 504
 505 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 506
 507 /* Interrupt Controller */
 508
 509 #define _GPLR(x)        __REG2(0x40E00000, ((x) & 0x60) >> 3)
 510 #define _GPDR(x)        __REG2(0x40E0000C, ((x) & 0x60) >> 3)
 511 #define _GPSR(x)        __REG2(0x40E00018, ((x) & 0x60) >> 3)
 512 #define _GPCR(x)        __REG2(0x40E00024, ((x) & 0x60) >> 3)
 513 #define _GRER(x)        __REG2(0x40E00030, ((x) & 0x60) >> 3)
 514 #define _GFER(x)        __REG2(0x40E0003C, ((x) & 0x60) >> 3)
 515 #define _GEDR(x)        __REG2(0x40E00048, ((x) & 0x60) >> 3)
 516 #define _GAFR(x)        __REG2(0x40E00054, ((x) & 0x70) >> 2)
 517
 518 #define GPLR(x)         (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
 519 #define GPDR(x)         (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
 520 #define GPSR(x)         (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
 521 #define GPCR(x)         (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
 522 #define GRER(x)         (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
 523 #define GFER(x)         (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
 524 #define GEDR(x)         (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
 525 #define GAFR(x)         (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
 526                          ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
 527 #else
 528
 529 #define GPLR(x)         __REG2(0x40E00000, ((x) & 0x60) >> 3)
 530 #define GPDR(x)         __REG2(0x40E0000C, ((x) & 0x60) >> 3)
 531 #define GPSR(x)         __REG2(0x40E00018, ((x) & 0x60) >> 3)
 532 #define GPCR(x)         __REG2(0x40E00024, ((x) & 0x60) >> 3)
 533 #define GRER(x)         __REG2(0x40E00030, ((x) & 0x60) >> 3)
 534 #define GFER(x)         __REG2(0x40E0003C, ((x) & 0x60) >> 3)
 535 #define GEDR(x)         __REG2(0x40E00048, ((x) & 0x60) >> 3)
 536 #define GAFR(x)         __REG2(0x40E00054, ((x) & 0x70) >> 2)
 537
 538 #endif
 539
 540 /*
 541  * Power Manager - see pxa2xx-regs.h
 542  */
 543
 544 /*
 545  * SSP Serial Port Registers - see arch/arm/mach-pxa/include/mach/regs-ssp.h
 546  */
 547
 548 /*
 549  * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
 550  */
 551
 552 /*
 553  * Core Clock - see arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
 554  */
 555
 556 #ifdef CONFIG_PXA27x
 557
 558 #define SRAM_SIZE               0x40000 /* 4x64K  */
 559
 560 #define SRAM_MEM_PHYS           0x5C000000
 561
 562 #define IMPMCR          __REG(0x58000000) /* IM Power Management Control Reg */
 563 #define IMPMSR          __REG(0x58000008) /* IM Power Management Status Reg */
 564
 565 #define IMPMCR_PC3              (0x3 << 22) /* Bank 3 Power Control */
 566 #define IMPMCR_PC3_RUN_MODE     (0x0 << 22) /*   Run mode */
 567 #define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /*   Standby mode */
 568 #define IMPMCR_PC3_AUTO_MODE    (0x3 << 22) /*   Automatically controlled */
 569
 570 #define IMPMCR_PC2              (0x3 << 20) /* Bank 2 Power Control */
 571 #define IMPMCR_PC2_RUN_MODE     (0x0 << 20) /*   Run mode */
 572 #define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /*   Standby mode */
 573 #define IMPMCR_PC2_AUTO_MODE    (0x3 << 20) /*   Automatically controlled */
 574
 575 #define IMPMCR_PC1              (0x3 << 18) /* Bank 1 Power Control */
 576 #define IMPMCR_PC1_RUN_MODE     (0x0 << 18) /*   Run mode */
 577 #define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /*   Standby mode */
 578 #define IMPMCR_PC1_AUTO_MODE    (0x3 << 18) /*   Automatically controlled */
 579
 580 #define IMPMCR_PC0              (0x3 << 16) /* Bank 0 Power Control */
 581 #define IMPMCR_PC0_RUN_MODE     (0x0 << 16) /*   Run mode */
 582 #define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /*   Standby mode */
 583 #define IMPMCR_PC0_AUTO_MODE    (0x3 << 16) /*   Automatically controlled */
 584
 585 #define IMPMCR_AW3              (1 << 11) /* Bank 3 Automatic Wake-up enable */
 586 #define IMPMCR_AW2              (1 << 10) /* Bank 2 Automatic Wake-up enable */
 587 #define IMPMCR_AW1              (1 << 9)  /* Bank 1 Automatic Wake-up enable */
 588 #define IMPMCR_AW0              (1 << 8)  /* Bank 0 Automatic Wake-up enable */
 589
 590 #define IMPMCR_DST              (0xFF << 0) /* Delay Standby Time, ms */
 591
 592 #define IMPMSR_PS3              (0x3 << 6) /* Bank 3 Power Status: */
 593 #define IMPMSR_PS3_RUN_MODE     (0x0 << 6) /*    Run mode */
 594 #define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /*    Standby mode */
 595
 596 #define IMPMSR_PS2              (0x3 << 4) /* Bank 2 Power Status: */
 597 #define IMPMSR_PS2_RUN_MODE     (0x0 << 4) /*    Run mode */
 598 #define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /*    Standby mode */
 599
 600 #define IMPMSR_PS1              (0x3 << 2) /* Bank 1 Power Status: */
 601 #define IMPMSR_PS1_RUN_MODE     (0x0 << 2) /*    Run mode */
 602 #define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /*    Standby mode */
 603
 604 #define IMPMSR_PS0              (0x3 << 0) /* Bank 0 Power Status: */
 605 #define IMPMSR_PS0_RUN_MODE     (0x0 << 0) /*    Run mode */
 606 #define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /*    Standby mode */
 607
 608 #endif
 609
 610 /* PWRMODE register M field values */
 611
 612 #define PWRMODE_IDLE            0x1
 613 #define PWRMODE_STANDBY         0x2
 614 #define PWRMODE_SLEEP           0x3
 615 #define PWRMODE_DEEPSLEEP       0x7
 616
 617 #endif