2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
16 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
31 #include <asm/virtext.h>
33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
35 MODULE_AUTHOR("Qumranet");
36 MODULE_LICENSE("GPL");
38 #define IOPM_ALLOC_ORDER 2
39 #define MSRPM_ALLOC_ORDER 1
41 #define DR7_GD_MASK (1 << 13)
42 #define DR6_BD_MASK (1 << 13)
44 #define SEG_TYPE_LDT 2
45 #define SEG_TYPE_BUSY_TSS16 3
47 #define SVM_FEATURE_NPT (1 << 0)
48 #define SVM_FEATURE_LBRV (1 << 1)
49 #define SVM_FEATURE_SVML (1 << 2)
51 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
53 /* Turn on to get debugging output*/
54 /* #define NESTED_DEBUG */
57 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
59 #define nsvm_printk(fmt, args...) do {} while(0)
62 /* enable NPT for AMD64 and X86 with PAE */
63 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
64 static bool npt_enabled
= true;
66 static bool npt_enabled
= false;
70 module_param(npt
, int, S_IRUGO
);
72 static int nested
= 0;
73 module_param(nested
, int, S_IRUGO
);
75 static void kvm_reput_irq(struct vcpu_svm
*svm
);
76 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
78 static int nested_svm_exit_handled(struct vcpu_svm
*svm
, bool kvm_override
);
79 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
80 static int nested_svm_vmsave(struct vcpu_svm
*svm
, void *nested_vmcb
,
81 void *arg2
, void *opaque
);
82 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
83 bool has_error_code
, u32 error_code
);
85 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
87 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
90 static inline bool is_nested(struct vcpu_svm
*svm
)
92 return svm
->nested_vmcb
;
95 static unsigned long iopm_base
;
97 struct kvm_ldttss_desc
{
100 unsigned base1
: 8, type
: 5, dpl
: 2, p
: 1;
101 unsigned limit1
: 4, zero0
: 3, g
: 1, base2
: 8;
104 } __attribute__((packed
));
106 struct svm_cpu_data
{
112 struct kvm_ldttss_desc
*tss_desc
;
114 struct page
*save_area
;
117 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
118 static uint32_t svm_features
;
120 struct svm_init_data
{
125 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
127 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
128 #define MSRS_RANGE_SIZE 2048
129 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
131 #define MAX_INST_SIZE 15
133 static inline u32
svm_has(u32 feat
)
135 return svm_features
& feat
;
138 static inline u8
pop_irq(struct kvm_vcpu
*vcpu
)
140 int word_index
= __ffs(vcpu
->arch
.irq_summary
);
141 int bit_index
= __ffs(vcpu
->arch
.irq_pending
[word_index
]);
142 int irq
= word_index
* BITS_PER_LONG
+ bit_index
;
144 clear_bit(bit_index
, &vcpu
->arch
.irq_pending
[word_index
]);
145 if (!vcpu
->arch
.irq_pending
[word_index
])
146 clear_bit(word_index
, &vcpu
->arch
.irq_summary
);
150 static inline void push_irq(struct kvm_vcpu
*vcpu
, u8 irq
)
152 set_bit(irq
, vcpu
->arch
.irq_pending
);
153 set_bit(irq
/ BITS_PER_LONG
, &vcpu
->arch
.irq_summary
);
156 static inline void clgi(void)
158 asm volatile (__ex(SVM_CLGI
));
161 static inline void stgi(void)
163 asm volatile (__ex(SVM_STGI
));
166 static inline void invlpga(unsigned long addr
, u32 asid
)
168 asm volatile (__ex(SVM_INVLPGA
) :: "a"(addr
), "c"(asid
));
171 static inline unsigned long kvm_read_cr2(void)
175 asm volatile ("mov %%cr2, %0" : "=r" (cr2
));
179 static inline void kvm_write_cr2(unsigned long val
)
181 asm volatile ("mov %0, %%cr2" :: "r" (val
));
184 static inline unsigned long read_dr6(void)
188 asm volatile ("mov %%dr6, %0" : "=r" (dr6
));
192 static inline void write_dr6(unsigned long val
)
194 asm volatile ("mov %0, %%dr6" :: "r" (val
));
197 static inline unsigned long read_dr7(void)
201 asm volatile ("mov %%dr7, %0" : "=r" (dr7
));
205 static inline void write_dr7(unsigned long val
)
207 asm volatile ("mov %0, %%dr7" :: "r" (val
));
210 static inline void force_new_asid(struct kvm_vcpu
*vcpu
)
212 to_svm(vcpu
)->asid_generation
--;
215 static inline void flush_guest_tlb(struct kvm_vcpu
*vcpu
)
217 force_new_asid(vcpu
);
220 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
222 if (!npt_enabled
&& !(efer
& EFER_LMA
))
225 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
226 vcpu
->arch
.shadow_efer
= efer
;
229 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
230 bool has_error_code
, u32 error_code
)
232 struct vcpu_svm
*svm
= to_svm(vcpu
);
234 /* If we are within a nested VM we'd better #VMEXIT and let the
235 guest handle the exception */
236 if (nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
239 svm
->vmcb
->control
.event_inj
= nr
241 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
242 | SVM_EVTINJ_TYPE_EXEPT
;
243 svm
->vmcb
->control
.event_inj_err
= error_code
;
246 static bool svm_exception_injected(struct kvm_vcpu
*vcpu
)
248 struct vcpu_svm
*svm
= to_svm(vcpu
);
250 return !(svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
);
253 static int is_external_interrupt(u32 info
)
255 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
256 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
259 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
261 struct vcpu_svm
*svm
= to_svm(vcpu
);
263 if (!svm
->next_rip
) {
264 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
267 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
268 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
269 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
271 kvm_rip_write(vcpu
, svm
->next_rip
);
272 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
274 vcpu
->arch
.interrupt_window_open
= (svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
277 static int has_svm(void)
281 if (!cpu_has_svm(&msg
)) {
282 printk(KERN_INFO
"has_svn: %s\n", msg
);
289 static void svm_hardware_disable(void *garbage
)
294 static void svm_hardware_enable(void *garbage
)
297 struct svm_cpu_data
*svm_data
;
299 struct desc_ptr gdt_descr
;
300 struct desc_struct
*gdt
;
301 int me
= raw_smp_processor_id();
304 printk(KERN_ERR
"svm_cpu_init: err EOPNOTSUPP on %d\n", me
);
307 svm_data
= per_cpu(svm_data
, me
);
310 printk(KERN_ERR
"svm_cpu_init: svm_data is NULL on %d\n",
315 svm_data
->asid_generation
= 1;
316 svm_data
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
317 svm_data
->next_asid
= svm_data
->max_asid
+ 1;
319 asm volatile ("sgdt %0" : "=m"(gdt_descr
));
320 gdt
= (struct desc_struct
*)gdt_descr
.address
;
321 svm_data
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
323 rdmsrl(MSR_EFER
, efer
);
324 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
326 wrmsrl(MSR_VM_HSAVE_PA
,
327 page_to_pfn(svm_data
->save_area
) << PAGE_SHIFT
);
330 static void svm_cpu_uninit(int cpu
)
332 struct svm_cpu_data
*svm_data
333 = per_cpu(svm_data
, raw_smp_processor_id());
338 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
339 __free_page(svm_data
->save_area
);
343 static int svm_cpu_init(int cpu
)
345 struct svm_cpu_data
*svm_data
;
348 svm_data
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
352 svm_data
->save_area
= alloc_page(GFP_KERNEL
);
354 if (!svm_data
->save_area
)
357 per_cpu(svm_data
, cpu
) = svm_data
;
367 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
372 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
373 if (msr
>= msrpm_ranges
[i
] &&
374 msr
< msrpm_ranges
[i
] + MSRS_IN_RANGE
) {
375 u32 msr_offset
= (i
* MSRS_IN_RANGE
+ msr
-
376 msrpm_ranges
[i
]) * 2;
378 u32
*base
= msrpm
+ (msr_offset
/ 32);
379 u32 msr_shift
= msr_offset
% 32;
380 u32 mask
= ((write
) ? 0 : 2) | ((read
) ? 0 : 1);
381 *base
= (*base
& ~(0x3 << msr_shift
)) |
389 static void svm_vcpu_init_msrpm(u32
*msrpm
)
391 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
394 set_msr_interception(msrpm
, MSR_GS_BASE
, 1, 1);
395 set_msr_interception(msrpm
, MSR_FS_BASE
, 1, 1);
396 set_msr_interception(msrpm
, MSR_KERNEL_GS_BASE
, 1, 1);
397 set_msr_interception(msrpm
, MSR_LSTAR
, 1, 1);
398 set_msr_interception(msrpm
, MSR_CSTAR
, 1, 1);
399 set_msr_interception(msrpm
, MSR_SYSCALL_MASK
, 1, 1);
401 set_msr_interception(msrpm
, MSR_K6_STAR
, 1, 1);
402 set_msr_interception(msrpm
, MSR_IA32_SYSENTER_CS
, 1, 1);
403 set_msr_interception(msrpm
, MSR_IA32_SYSENTER_ESP
, 1, 1);
404 set_msr_interception(msrpm
, MSR_IA32_SYSENTER_EIP
, 1, 1);
407 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
409 u32
*msrpm
= svm
->msrpm
;
411 svm
->vmcb
->control
.lbr_ctl
= 1;
412 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
413 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
414 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
415 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
418 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
420 u32
*msrpm
= svm
->msrpm
;
422 svm
->vmcb
->control
.lbr_ctl
= 0;
423 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
424 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
425 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
426 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
429 static __init
int svm_hardware_setup(void)
432 struct page
*iopm_pages
;
436 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
441 iopm_va
= page_address(iopm_pages
);
442 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
443 clear_bit(0x80, iopm_va
); /* allow direct access to PC debug port */
444 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
446 if (boot_cpu_has(X86_FEATURE_NX
))
447 kvm_enable_efer_bits(EFER_NX
);
450 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
451 kvm_enable_efer_bits(EFER_SVME
);
454 for_each_online_cpu(cpu
) {
455 r
= svm_cpu_init(cpu
);
460 svm_features
= cpuid_edx(SVM_CPUID_FUNC
);
462 if (!svm_has(SVM_FEATURE_NPT
))
465 if (npt_enabled
&& !npt
) {
466 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
471 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
479 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
484 static __exit
void svm_hardware_unsetup(void)
488 for_each_online_cpu(cpu
)
491 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
495 static void init_seg(struct vmcb_seg
*seg
)
498 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
499 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
504 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
507 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
512 static void init_vmcb(struct vcpu_svm
*svm
)
514 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
515 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
517 control
->intercept_cr_read
= INTERCEPT_CR0_MASK
|
521 control
->intercept_cr_write
= INTERCEPT_CR0_MASK
|
526 control
->intercept_dr_read
= INTERCEPT_DR0_MASK
|
531 control
->intercept_dr_write
= INTERCEPT_DR0_MASK
|
538 control
->intercept_exceptions
= (1 << PF_VECTOR
) |
543 control
->intercept
= (1ULL << INTERCEPT_INTR
) |
544 (1ULL << INTERCEPT_NMI
) |
545 (1ULL << INTERCEPT_SMI
) |
546 (1ULL << INTERCEPT_CPUID
) |
547 (1ULL << INTERCEPT_INVD
) |
548 (1ULL << INTERCEPT_HLT
) |
549 (1ULL << INTERCEPT_INVLPG
) |
550 (1ULL << INTERCEPT_INVLPGA
) |
551 (1ULL << INTERCEPT_IOIO_PROT
) |
552 (1ULL << INTERCEPT_MSR_PROT
) |
553 (1ULL << INTERCEPT_TASK_SWITCH
) |
554 (1ULL << INTERCEPT_SHUTDOWN
) |
555 (1ULL << INTERCEPT_VMRUN
) |
556 (1ULL << INTERCEPT_VMMCALL
) |
557 (1ULL << INTERCEPT_VMLOAD
) |
558 (1ULL << INTERCEPT_VMSAVE
) |
559 (1ULL << INTERCEPT_STGI
) |
560 (1ULL << INTERCEPT_CLGI
) |
561 (1ULL << INTERCEPT_SKINIT
) |
562 (1ULL << INTERCEPT_WBINVD
) |
563 (1ULL << INTERCEPT_MONITOR
) |
564 (1ULL << INTERCEPT_MWAIT
);
566 control
->iopm_base_pa
= iopm_base
;
567 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
568 control
->tsc_offset
= 0;
569 control
->int_ctl
= V_INTR_MASKING_MASK
;
577 save
->cs
.selector
= 0xf000;
578 /* Executable/Readable Code Segment */
579 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
580 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
581 save
->cs
.limit
= 0xffff;
583 * cs.base should really be 0xffff0000, but vmx can't handle that, so
584 * be consistent with it.
586 * Replace when we have real mode working for vmx.
588 save
->cs
.base
= 0xf0000;
590 save
->gdtr
.limit
= 0xffff;
591 save
->idtr
.limit
= 0xffff;
593 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
594 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
596 save
->efer
= EFER_SVME
;
597 save
->dr6
= 0xffff0ff0;
600 save
->rip
= 0x0000fff0;
601 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
604 * cr0 val on cpu init should be 0x60000010, we enable cpu
605 * cache by default. the orderly way is to enable cache in bios.
607 save
->cr0
= 0x00000010 | X86_CR0_PG
| X86_CR0_WP
;
608 save
->cr4
= X86_CR4_PAE
;
612 /* Setup VMCB for Nested Paging */
613 control
->nested_ctl
= 1;
614 control
->intercept
&= ~((1ULL << INTERCEPT_TASK_SWITCH
) |
615 (1ULL << INTERCEPT_INVLPG
));
616 control
->intercept_exceptions
&= ~(1 << PF_VECTOR
);
617 control
->intercept_cr_read
&= ~(INTERCEPT_CR0_MASK
|
619 control
->intercept_cr_write
&= ~(INTERCEPT_CR0_MASK
|
621 save
->g_pat
= 0x0007040600070406ULL
;
622 /* enable caching because the QEMU Bios doesn't enable it */
623 save
->cr0
= X86_CR0_ET
;
627 force_new_asid(&svm
->vcpu
);
629 svm
->nested_vmcb
= 0;
630 svm
->vcpu
.arch
.hflags
= HF_GIF_MASK
;
633 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
635 struct vcpu_svm
*svm
= to_svm(vcpu
);
639 if (vcpu
->vcpu_id
!= 0) {
640 kvm_rip_write(vcpu
, 0);
641 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
642 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
644 vcpu
->arch
.regs_avail
= ~0;
645 vcpu
->arch
.regs_dirty
= ~0;
650 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
652 struct vcpu_svm
*svm
;
654 struct page
*msrpm_pages
;
655 struct page
*hsave_page
;
656 struct page
*nested_msrpm_pages
;
659 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
665 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
669 page
= alloc_page(GFP_KERNEL
);
676 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
680 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
681 if (!nested_msrpm_pages
)
684 svm
->msrpm
= page_address(msrpm_pages
);
685 svm_vcpu_init_msrpm(svm
->msrpm
);
687 hsave_page
= alloc_page(GFP_KERNEL
);
690 svm
->hsave
= page_address(hsave_page
);
692 svm
->nested_msrpm
= page_address(nested_msrpm_pages
);
694 svm
->vmcb
= page_address(page
);
695 clear_page(svm
->vmcb
);
696 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
697 svm
->asid_generation
= 0;
698 memset(svm
->db_regs
, 0, sizeof(svm
->db_regs
));
702 svm
->vcpu
.fpu_active
= 1;
703 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
704 if (svm
->vcpu
.vcpu_id
== 0)
705 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
710 kvm_vcpu_uninit(&svm
->vcpu
);
712 kmem_cache_free(kvm_vcpu_cache
, svm
);
717 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
719 struct vcpu_svm
*svm
= to_svm(vcpu
);
721 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
722 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
723 __free_page(virt_to_page(svm
->hsave
));
724 __free_pages(virt_to_page(svm
->nested_msrpm
), MSRPM_ALLOC_ORDER
);
725 kvm_vcpu_uninit(vcpu
);
726 kmem_cache_free(kvm_vcpu_cache
, svm
);
729 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
731 struct vcpu_svm
*svm
= to_svm(vcpu
);
734 if (unlikely(cpu
!= vcpu
->cpu
)) {
738 * Make sure that the guest sees a monotonically
742 delta
= vcpu
->arch
.host_tsc
- tsc_this
;
743 svm
->vmcb
->control
.tsc_offset
+= delta
;
745 kvm_migrate_timers(vcpu
);
748 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
749 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
752 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
754 struct vcpu_svm
*svm
= to_svm(vcpu
);
757 ++vcpu
->stat
.host_state_reload
;
758 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
759 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
761 rdtscll(vcpu
->arch
.host_tsc
);
764 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
766 return to_svm(vcpu
)->vmcb
->save
.rflags
;
769 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
771 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
774 static void svm_set_vintr(struct vcpu_svm
*svm
)
776 svm
->vmcb
->control
.intercept
|= 1ULL << INTERCEPT_VINTR
;
779 static void svm_clear_vintr(struct vcpu_svm
*svm
)
781 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_VINTR
);
784 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
786 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
789 case VCPU_SREG_CS
: return &save
->cs
;
790 case VCPU_SREG_DS
: return &save
->ds
;
791 case VCPU_SREG_ES
: return &save
->es
;
792 case VCPU_SREG_FS
: return &save
->fs
;
793 case VCPU_SREG_GS
: return &save
->gs
;
794 case VCPU_SREG_SS
: return &save
->ss
;
795 case VCPU_SREG_TR
: return &save
->tr
;
796 case VCPU_SREG_LDTR
: return &save
->ldtr
;
802 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
804 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
809 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
810 struct kvm_segment
*var
, int seg
)
812 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
815 var
->limit
= s
->limit
;
816 var
->selector
= s
->selector
;
817 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
818 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
819 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
820 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
821 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
822 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
823 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
824 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
827 * SVM always stores 0 for the 'G' bit in the CS selector in
828 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
829 * Intel's VMENTRY has a check on the 'G' bit.
831 if (seg
== VCPU_SREG_CS
)
832 var
->g
= s
->limit
> 0xfffff;
835 * Work around a bug where the busy flag in the tr selector
838 if (seg
== VCPU_SREG_TR
)
841 var
->unusable
= !var
->present
;
844 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
846 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
851 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
853 struct vcpu_svm
*svm
= to_svm(vcpu
);
855 dt
->limit
= svm
->vmcb
->save
.idtr
.limit
;
856 dt
->base
= svm
->vmcb
->save
.idtr
.base
;
859 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
861 struct vcpu_svm
*svm
= to_svm(vcpu
);
863 svm
->vmcb
->save
.idtr
.limit
= dt
->limit
;
864 svm
->vmcb
->save
.idtr
.base
= dt
->base
;
867 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
869 struct vcpu_svm
*svm
= to_svm(vcpu
);
871 dt
->limit
= svm
->vmcb
->save
.gdtr
.limit
;
872 dt
->base
= svm
->vmcb
->save
.gdtr
.base
;
875 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
877 struct vcpu_svm
*svm
= to_svm(vcpu
);
879 svm
->vmcb
->save
.gdtr
.limit
= dt
->limit
;
880 svm
->vmcb
->save
.gdtr
.base
= dt
->base
;
883 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
887 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
889 struct vcpu_svm
*svm
= to_svm(vcpu
);
892 if (vcpu
->arch
.shadow_efer
& EFER_LME
) {
893 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
894 vcpu
->arch
.shadow_efer
|= EFER_LMA
;
895 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
898 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
899 vcpu
->arch
.shadow_efer
&= ~EFER_LMA
;
900 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
907 if ((vcpu
->arch
.cr0
& X86_CR0_TS
) && !(cr0
& X86_CR0_TS
)) {
908 svm
->vmcb
->control
.intercept_exceptions
&= ~(1 << NM_VECTOR
);
909 vcpu
->fpu_active
= 1;
912 vcpu
->arch
.cr0
= cr0
;
913 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
914 if (!vcpu
->fpu_active
) {
915 svm
->vmcb
->control
.intercept_exceptions
|= (1 << NM_VECTOR
);
920 * re-enable caching here because the QEMU bios
921 * does not do it - this results in some delay at
924 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
925 svm
->vmcb
->save
.cr0
= cr0
;
928 static void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
930 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
931 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
933 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
934 force_new_asid(vcpu
);
936 vcpu
->arch
.cr4
= cr4
;
940 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
943 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
944 struct kvm_segment
*var
, int seg
)
946 struct vcpu_svm
*svm
= to_svm(vcpu
);
947 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
950 s
->limit
= var
->limit
;
951 s
->selector
= var
->selector
;
955 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
956 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
957 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
958 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
959 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
960 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
961 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
962 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
964 if (seg
== VCPU_SREG_CS
)
966 = (svm
->vmcb
->save
.cs
.attrib
967 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
971 static int svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
973 int old_debug
= vcpu
->guest_debug
;
974 struct vcpu_svm
*svm
= to_svm(vcpu
);
976 vcpu
->guest_debug
= dbg
->control
;
978 svm
->vmcb
->control
.intercept_exceptions
&=
979 ~((1 << DB_VECTOR
) | (1 << BP_VECTOR
));
980 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
981 if (vcpu
->guest_debug
&
982 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
983 svm
->vmcb
->control
.intercept_exceptions
|=
985 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
986 svm
->vmcb
->control
.intercept_exceptions
|=
989 vcpu
->guest_debug
= 0;
991 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
992 svm
->vmcb
->save
.rflags
|= X86_EFLAGS_TF
| X86_EFLAGS_RF
;
993 else if (old_debug
& KVM_GUESTDBG_SINGLESTEP
)
994 svm
->vmcb
->save
.rflags
&= ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
999 static int svm_get_irq(struct kvm_vcpu
*vcpu
)
1001 struct vcpu_svm
*svm
= to_svm(vcpu
);
1002 u32 exit_int_info
= svm
->vmcb
->control
.exit_int_info
;
1004 if (is_external_interrupt(exit_int_info
))
1005 return exit_int_info
& SVM_EVTINJ_VEC_MASK
;
1009 static void load_host_msrs(struct kvm_vcpu
*vcpu
)
1011 #ifdef CONFIG_X86_64
1012 wrmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1016 static void save_host_msrs(struct kvm_vcpu
*vcpu
)
1018 #ifdef CONFIG_X86_64
1019 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1023 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*svm_data
)
1025 if (svm_data
->next_asid
> svm_data
->max_asid
) {
1026 ++svm_data
->asid_generation
;
1027 svm_data
->next_asid
= 1;
1028 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1031 svm
->vcpu
.cpu
= svm_data
->cpu
;
1032 svm
->asid_generation
= svm_data
->asid_generation
;
1033 svm
->vmcb
->control
.asid
= svm_data
->next_asid
++;
1036 static unsigned long svm_get_dr(struct kvm_vcpu
*vcpu
, int dr
)
1038 unsigned long val
= to_svm(vcpu
)->db_regs
[dr
];
1039 KVMTRACE_2D(DR_READ
, vcpu
, (u32
)dr
, (u32
)val
, handler
);
1043 static void svm_set_dr(struct kvm_vcpu
*vcpu
, int dr
, unsigned long value
,
1046 struct vcpu_svm
*svm
= to_svm(vcpu
);
1050 if (svm
->vmcb
->save
.dr7
& DR7_GD_MASK
) {
1051 svm
->vmcb
->save
.dr7
&= ~DR7_GD_MASK
;
1052 svm
->vmcb
->save
.dr6
|= DR6_BD_MASK
;
1053 *exception
= DB_VECTOR
;
1059 svm
->db_regs
[dr
] = value
;
1062 if (vcpu
->arch
.cr4
& X86_CR4_DE
) {
1063 *exception
= UD_VECTOR
;
1067 if (value
& ~((1ULL << 32) - 1)) {
1068 *exception
= GP_VECTOR
;
1071 svm
->vmcb
->save
.dr7
= value
;
1075 printk(KERN_DEBUG
"%s: unexpected dr %u\n",
1077 *exception
= UD_VECTOR
;
1082 static int pf_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1084 u32 exit_int_info
= svm
->vmcb
->control
.exit_int_info
;
1085 struct kvm
*kvm
= svm
->vcpu
.kvm
;
1088 bool event_injection
= false;
1090 if (!irqchip_in_kernel(kvm
) &&
1091 is_external_interrupt(exit_int_info
)) {
1092 event_injection
= true;
1093 push_irq(&svm
->vcpu
, exit_int_info
& SVM_EVTINJ_VEC_MASK
);
1096 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1097 error_code
= svm
->vmcb
->control
.exit_info_1
;
1100 KVMTRACE_3D(PAGE_FAULT
, &svm
->vcpu
, error_code
,
1101 (u32
)fault_address
, (u32
)(fault_address
>> 32),
1104 KVMTRACE_3D(TDP_FAULT
, &svm
->vcpu
, error_code
,
1105 (u32
)fault_address
, (u32
)(fault_address
>> 32),
1108 * FIXME: Tis shouldn't be necessary here, but there is a flush
1109 * missing in the MMU code. Until we find this bug, flush the
1110 * complete TLB here on an NPF
1113 svm_flush_tlb(&svm
->vcpu
);
1115 if (!npt_enabled
&& event_injection
)
1116 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1117 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
);
1120 static int db_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1122 if (!(svm
->vcpu
.guest_debug
&
1123 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
1124 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1127 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1128 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1129 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1133 static int bp_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1135 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1136 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1137 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1141 static int ud_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1145 er
= emulate_instruction(&svm
->vcpu
, kvm_run
, 0, 0, EMULTYPE_TRAP_UD
);
1146 if (er
!= EMULATE_DONE
)
1147 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1151 static int nm_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1153 svm
->vmcb
->control
.intercept_exceptions
&= ~(1 << NM_VECTOR
);
1154 if (!(svm
->vcpu
.arch
.cr0
& X86_CR0_TS
))
1155 svm
->vmcb
->save
.cr0
&= ~X86_CR0_TS
;
1156 svm
->vcpu
.fpu_active
= 1;
1161 static int mc_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1164 * On an #MC intercept the MCE handler is not called automatically in
1165 * the host. So do it by hand here.
1169 /* not sure if we ever come back to this point */
1174 static int shutdown_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1177 * VMCB is undefined after a SHUTDOWN intercept
1178 * so reinitialize it.
1180 clear_page(svm
->vmcb
);
1183 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1187 static int io_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1189 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1190 int size
, down
, in
, string
, rep
;
1193 ++svm
->vcpu
.stat
.io_exits
;
1195 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1197 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1200 if (emulate_instruction(&svm
->vcpu
,
1201 kvm_run
, 0, 0, 0) == EMULATE_DO_MMIO
)
1206 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1207 port
= io_info
>> 16;
1208 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1209 rep
= (io_info
& SVM_IOIO_REP_MASK
) != 0;
1210 down
= (svm
->vmcb
->save
.rflags
& X86_EFLAGS_DF
) != 0;
1212 skip_emulated_instruction(&svm
->vcpu
);
1213 return kvm_emulate_pio(&svm
->vcpu
, kvm_run
, in
, size
, port
);
1216 static int nmi_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1218 KVMTRACE_0D(NMI
, &svm
->vcpu
, handler
);
1222 static int intr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1224 ++svm
->vcpu
.stat
.irq_exits
;
1225 KVMTRACE_0D(INTR
, &svm
->vcpu
, handler
);
1229 static int nop_on_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1234 static int halt_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1236 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1237 skip_emulated_instruction(&svm
->vcpu
);
1238 return kvm_emulate_halt(&svm
->vcpu
);
1241 static int vmmcall_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1243 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1244 skip_emulated_instruction(&svm
->vcpu
);
1245 kvm_emulate_hypercall(&svm
->vcpu
);
1249 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1251 if (!(svm
->vcpu
.arch
.shadow_efer
& EFER_SVME
)
1252 || !is_paging(&svm
->vcpu
)) {
1253 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1257 if (svm
->vmcb
->save
.cpl
) {
1258 kvm_inject_gp(&svm
->vcpu
, 0);
1265 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1266 bool has_error_code
, u32 error_code
)
1268 if (is_nested(svm
)) {
1269 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1270 svm
->vmcb
->control
.exit_code_hi
= 0;
1271 svm
->vmcb
->control
.exit_info_1
= error_code
;
1272 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1273 if (nested_svm_exit_handled(svm
, false)) {
1274 nsvm_printk("VMexit -> EXCP 0x%x\n", nr
);
1276 nested_svm_vmexit(svm
);
1284 static inline int nested_svm_intr(struct vcpu_svm
*svm
)
1286 if (is_nested(svm
)) {
1287 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1290 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
1293 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
1295 if (nested_svm_exit_handled(svm
, false)) {
1296 nsvm_printk("VMexit -> INTR\n");
1297 nested_svm_vmexit(svm
);
1305 static struct page
*nested_svm_get_page(struct vcpu_svm
*svm
, u64 gpa
)
1309 down_read(¤t
->mm
->mmap_sem
);
1310 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
1311 up_read(¤t
->mm
->mmap_sem
);
1313 if (is_error_page(page
)) {
1314 printk(KERN_INFO
"%s: could not find page at 0x%llx\n",
1316 kvm_release_page_clean(page
);
1317 kvm_inject_gp(&svm
->vcpu
, 0);
1323 static int nested_svm_do(struct vcpu_svm
*svm
,
1324 u64 arg1_gpa
, u64 arg2_gpa
, void *opaque
,
1325 int (*handler
)(struct vcpu_svm
*svm
,
1330 struct page
*arg1_page
;
1331 struct page
*arg2_page
= NULL
;
1336 arg1_page
= nested_svm_get_page(svm
, arg1_gpa
);
1337 if(arg1_page
== NULL
)
1341 arg2_page
= nested_svm_get_page(svm
, arg2_gpa
);
1342 if(arg2_page
== NULL
) {
1343 kvm_release_page_clean(arg1_page
);
1348 arg1
= kmap_atomic(arg1_page
, KM_USER0
);
1350 arg2
= kmap_atomic(arg2_page
, KM_USER1
);
1352 retval
= handler(svm
, arg1
, arg2
, opaque
);
1354 kunmap_atomic(arg1
, KM_USER0
);
1356 kunmap_atomic(arg2
, KM_USER1
);
1358 kvm_release_page_dirty(arg1_page
);
1360 kvm_release_page_dirty(arg2_page
);
1365 static int nested_svm_exit_handled_real(struct vcpu_svm
*svm
,
1370 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1371 bool kvm_overrides
= *(bool *)opaque
;
1372 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1374 if (kvm_overrides
) {
1375 switch (exit_code
) {
1379 /* For now we are always handling NPFs when using them */
1384 /* When we're shadowing, trap PFs */
1385 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
1394 switch (exit_code
) {
1395 case SVM_EXIT_READ_CR0
... SVM_EXIT_READ_CR8
: {
1396 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_READ_CR0
);
1397 if (nested_vmcb
->control
.intercept_cr_read
& cr_bits
)
1401 case SVM_EXIT_WRITE_CR0
... SVM_EXIT_WRITE_CR8
: {
1402 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_CR0
);
1403 if (nested_vmcb
->control
.intercept_cr_write
& cr_bits
)
1407 case SVM_EXIT_READ_DR0
... SVM_EXIT_READ_DR7
: {
1408 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_READ_DR0
);
1409 if (nested_vmcb
->control
.intercept_dr_read
& dr_bits
)
1413 case SVM_EXIT_WRITE_DR0
... SVM_EXIT_WRITE_DR7
: {
1414 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_DR0
);
1415 if (nested_vmcb
->control
.intercept_dr_write
& dr_bits
)
1419 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
1420 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
1421 if (nested_vmcb
->control
.intercept_exceptions
& excp_bits
)
1426 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
1427 nsvm_printk("exit code: 0x%x\n", exit_code
);
1428 if (nested_vmcb
->control
.intercept
& exit_bits
)
1436 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
,
1437 void *arg1
, void *arg2
,
1440 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1441 u8
*msrpm
= (u8
*)arg2
;
1443 u32 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1444 u32 param
= svm
->vmcb
->control
.exit_info_1
& 1;
1446 if (!(nested_vmcb
->control
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1454 case 0xc0000000 ... 0xc0001fff:
1455 t0
= (8192 + msr
- 0xc0000000) * 2;
1459 case 0xc0010000 ... 0xc0011fff:
1460 t0
= (16384 + msr
- 0xc0010000) * 2;
1468 if (msrpm
[t1
] & ((1 << param
) << t0
))
1474 static int nested_svm_exit_handled(struct vcpu_svm
*svm
, bool kvm_override
)
1476 bool k
= kvm_override
;
1478 switch (svm
->vmcb
->control
.exit_code
) {
1480 return nested_svm_do(svm
, svm
->nested_vmcb
,
1481 svm
->nested_vmcb_msrpm
, NULL
,
1482 nested_svm_exit_handled_msr
);
1486 return nested_svm_do(svm
, svm
->nested_vmcb
, 0, &k
,
1487 nested_svm_exit_handled_real
);
1490 static int nested_svm_vmexit_real(struct vcpu_svm
*svm
, void *arg1
,
1491 void *arg2
, void *opaque
)
1493 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1494 struct vmcb
*hsave
= svm
->hsave
;
1495 u64 nested_save
[] = { nested_vmcb
->save
.cr0
,
1496 nested_vmcb
->save
.cr3
,
1497 nested_vmcb
->save
.cr4
,
1498 nested_vmcb
->save
.efer
,
1499 nested_vmcb
->control
.intercept_cr_read
,
1500 nested_vmcb
->control
.intercept_cr_write
,
1501 nested_vmcb
->control
.intercept_dr_read
,
1502 nested_vmcb
->control
.intercept_dr_write
,
1503 nested_vmcb
->control
.intercept_exceptions
,
1504 nested_vmcb
->control
.intercept
,
1505 nested_vmcb
->control
.msrpm_base_pa
,
1506 nested_vmcb
->control
.iopm_base_pa
,
1507 nested_vmcb
->control
.tsc_offset
};
1509 /* Give the current vmcb to the guest */
1510 memcpy(nested_vmcb
, svm
->vmcb
, sizeof(struct vmcb
));
1511 nested_vmcb
->save
.cr0
= nested_save
[0];
1513 nested_vmcb
->save
.cr3
= nested_save
[1];
1514 nested_vmcb
->save
.cr4
= nested_save
[2];
1515 nested_vmcb
->save
.efer
= nested_save
[3];
1516 nested_vmcb
->control
.intercept_cr_read
= nested_save
[4];
1517 nested_vmcb
->control
.intercept_cr_write
= nested_save
[5];
1518 nested_vmcb
->control
.intercept_dr_read
= nested_save
[6];
1519 nested_vmcb
->control
.intercept_dr_write
= nested_save
[7];
1520 nested_vmcb
->control
.intercept_exceptions
= nested_save
[8];
1521 nested_vmcb
->control
.intercept
= nested_save
[9];
1522 nested_vmcb
->control
.msrpm_base_pa
= nested_save
[10];
1523 nested_vmcb
->control
.iopm_base_pa
= nested_save
[11];
1524 nested_vmcb
->control
.tsc_offset
= nested_save
[12];
1526 /* We always set V_INTR_MASKING and remember the old value in hflags */
1527 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1528 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
1530 if ((nested_vmcb
->control
.int_ctl
& V_IRQ_MASK
) &&
1531 (nested_vmcb
->control
.int_vector
)) {
1532 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1533 nested_vmcb
->control
.int_vector
);
1536 /* Restore the original control entries */
1537 svm
->vmcb
->control
= hsave
->control
;
1539 /* Kill any pending exceptions */
1540 if (svm
->vcpu
.arch
.exception
.pending
== true)
1541 nsvm_printk("WARNING: Pending Exception\n");
1542 svm
->vcpu
.arch
.exception
.pending
= false;
1544 /* Restore selected save entries */
1545 svm
->vmcb
->save
.es
= hsave
->save
.es
;
1546 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
1547 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
1548 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
1549 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
1550 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
1551 svm
->vmcb
->save
.rflags
= hsave
->save
.rflags
;
1552 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
1553 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
1554 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
1556 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
1557 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
1559 kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
1561 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
1562 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
1563 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
1564 svm
->vmcb
->save
.dr7
= 0;
1565 svm
->vmcb
->save
.cpl
= 0;
1566 svm
->vmcb
->control
.exit_int_info
= 0;
1568 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
1569 /* Exit nested SVM mode */
1570 svm
->nested_vmcb
= 0;
1575 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
1577 nsvm_printk("VMexit\n");
1578 if (nested_svm_do(svm
, svm
->nested_vmcb
, 0,
1579 NULL
, nested_svm_vmexit_real
))
1582 kvm_mmu_reset_context(&svm
->vcpu
);
1583 kvm_mmu_load(&svm
->vcpu
);
1588 static int nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
, void *arg1
,
1589 void *arg2
, void *opaque
)
1592 u32
*nested_msrpm
= (u32
*)arg1
;
1593 for (i
=0; i
< PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
) / 4; i
++)
1594 svm
->nested_msrpm
[i
] = svm
->msrpm
[i
] | nested_msrpm
[i
];
1595 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested_msrpm
);
1600 static int nested_svm_vmrun(struct vcpu_svm
*svm
, void *arg1
,
1601 void *arg2
, void *opaque
)
1603 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1604 struct vmcb
*hsave
= svm
->hsave
;
1606 /* nested_vmcb is our indicator if nested SVM is activated */
1607 svm
->nested_vmcb
= svm
->vmcb
->save
.rax
;
1609 /* Clear internal status */
1610 svm
->vcpu
.arch
.exception
.pending
= false;
1612 /* Save the old vmcb, so we don't need to pick what we save, but
1613 can restore everything when a VMEXIT occurs */
1614 memcpy(hsave
, svm
->vmcb
, sizeof(struct vmcb
));
1615 /* We need to remember the original CR3 in the SPT case */
1617 hsave
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
1618 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
1619 hsave
->save
.rip
= svm
->next_rip
;
1621 if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
)
1622 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
1624 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
1626 /* Load the nested guest state */
1627 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
1628 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
1629 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
1630 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
1631 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
1632 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
1633 svm
->vmcb
->save
.rflags
= nested_vmcb
->save
.rflags
;
1634 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
1635 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
1636 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
1638 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
1639 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
1641 kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
1642 kvm_mmu_reset_context(&svm
->vcpu
);
1644 svm
->vmcb
->save
.cr2
= nested_vmcb
->save
.cr2
;
1645 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
1646 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
1647 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
1648 /* In case we don't even reach vcpu_run, the fields are not updated */
1649 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
1650 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
1651 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
1652 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
1653 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
1654 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
1656 /* We don't want a nested guest to be more powerful than the guest,
1657 so all intercepts are ORed */
1658 svm
->vmcb
->control
.intercept_cr_read
|=
1659 nested_vmcb
->control
.intercept_cr_read
;
1660 svm
->vmcb
->control
.intercept_cr_write
|=
1661 nested_vmcb
->control
.intercept_cr_write
;
1662 svm
->vmcb
->control
.intercept_dr_read
|=
1663 nested_vmcb
->control
.intercept_dr_read
;
1664 svm
->vmcb
->control
.intercept_dr_write
|=
1665 nested_vmcb
->control
.intercept_dr_write
;
1666 svm
->vmcb
->control
.intercept_exceptions
|=
1667 nested_vmcb
->control
.intercept_exceptions
;
1669 svm
->vmcb
->control
.intercept
|= nested_vmcb
->control
.intercept
;
1671 svm
->nested_vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
;
1673 force_new_asid(&svm
->vcpu
);
1674 svm
->vmcb
->control
.exit_int_info
= nested_vmcb
->control
.exit_int_info
;
1675 svm
->vmcb
->control
.exit_int_info_err
= nested_vmcb
->control
.exit_int_info_err
;
1676 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
1677 if (nested_vmcb
->control
.int_ctl
& V_IRQ_MASK
) {
1678 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1679 nested_vmcb
->control
.int_ctl
);
1681 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
1682 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
1684 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
1686 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1687 nested_vmcb
->control
.exit_int_info
,
1688 nested_vmcb
->control
.int_state
);
1690 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
1691 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
1692 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
1693 if (nested_vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
)
1694 nsvm_printk("Injecting Event: 0x%x\n",
1695 nested_vmcb
->control
.event_inj
);
1696 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
1697 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
1699 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
1704 static int nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
1706 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
1707 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
1708 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
1709 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
1710 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
1711 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
1712 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
1713 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
1714 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
1715 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
1716 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
1717 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
1722 static int nested_svm_vmload(struct vcpu_svm
*svm
, void *nested_vmcb
,
1723 void *arg2
, void *opaque
)
1725 return nested_svm_vmloadsave((struct vmcb
*)nested_vmcb
, svm
->vmcb
);
1728 static int nested_svm_vmsave(struct vcpu_svm
*svm
, void *nested_vmcb
,
1729 void *arg2
, void *opaque
)
1731 return nested_svm_vmloadsave(svm
->vmcb
, (struct vmcb
*)nested_vmcb
);
1734 static int vmload_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1736 if (nested_svm_check_permissions(svm
))
1739 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1740 skip_emulated_instruction(&svm
->vcpu
);
1742 nested_svm_do(svm
, svm
->vmcb
->save
.rax
, 0, NULL
, nested_svm_vmload
);
1747 static int vmsave_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1749 if (nested_svm_check_permissions(svm
))
1752 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1753 skip_emulated_instruction(&svm
->vcpu
);
1755 nested_svm_do(svm
, svm
->vmcb
->save
.rax
, 0, NULL
, nested_svm_vmsave
);
1760 static int vmrun_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1762 nsvm_printk("VMrun\n");
1763 if (nested_svm_check_permissions(svm
))
1766 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1767 skip_emulated_instruction(&svm
->vcpu
);
1769 if (nested_svm_do(svm
, svm
->vmcb
->save
.rax
, 0,
1770 NULL
, nested_svm_vmrun
))
1773 if (nested_svm_do(svm
, svm
->nested_vmcb_msrpm
, 0,
1774 NULL
, nested_svm_vmrun_msrpm
))
1780 static int stgi_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1782 if (nested_svm_check_permissions(svm
))
1785 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1786 skip_emulated_instruction(&svm
->vcpu
);
1788 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
1793 static int clgi_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1795 if (nested_svm_check_permissions(svm
))
1798 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1799 skip_emulated_instruction(&svm
->vcpu
);
1801 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
1803 /* After a CLGI no interrupts should come */
1804 svm_clear_vintr(svm
);
1805 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
1810 static int invalid_op_interception(struct vcpu_svm
*svm
,
1811 struct kvm_run
*kvm_run
)
1813 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1817 static int task_switch_interception(struct vcpu_svm
*svm
,
1818 struct kvm_run
*kvm_run
)
1822 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
1823 if (svm
->vmcb
->control
.exit_info_2
&
1824 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
1825 return kvm_task_switch(&svm
->vcpu
, tss_selector
,
1827 if (svm
->vmcb
->control
.exit_info_2
&
1828 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
1829 return kvm_task_switch(&svm
->vcpu
, tss_selector
,
1831 return kvm_task_switch(&svm
->vcpu
, tss_selector
, TASK_SWITCH_CALL
);
1834 static int cpuid_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1836 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
1837 kvm_emulate_cpuid(&svm
->vcpu
);
1841 static int invlpg_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1843 if (emulate_instruction(&svm
->vcpu
, kvm_run
, 0, 0, 0) != EMULATE_DONE
)
1844 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
1848 static int emulate_on_interception(struct vcpu_svm
*svm
,
1849 struct kvm_run
*kvm_run
)
1851 if (emulate_instruction(&svm
->vcpu
, NULL
, 0, 0, 0) != EMULATE_DONE
)
1852 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
1856 static int cr8_write_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1858 emulate_instruction(&svm
->vcpu
, NULL
, 0, 0, 0);
1859 if (irqchip_in_kernel(svm
->vcpu
.kvm
))
1861 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
1865 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
1867 struct vcpu_svm
*svm
= to_svm(vcpu
);
1870 case MSR_IA32_TIME_STAMP_COUNTER
: {
1874 *data
= svm
->vmcb
->control
.tsc_offset
+ tsc
;
1878 *data
= svm
->vmcb
->save
.star
;
1880 #ifdef CONFIG_X86_64
1882 *data
= svm
->vmcb
->save
.lstar
;
1885 *data
= svm
->vmcb
->save
.cstar
;
1887 case MSR_KERNEL_GS_BASE
:
1888 *data
= svm
->vmcb
->save
.kernel_gs_base
;
1890 case MSR_SYSCALL_MASK
:
1891 *data
= svm
->vmcb
->save
.sfmask
;
1894 case MSR_IA32_SYSENTER_CS
:
1895 *data
= svm
->vmcb
->save
.sysenter_cs
;
1897 case MSR_IA32_SYSENTER_EIP
:
1898 *data
= svm
->vmcb
->save
.sysenter_eip
;
1900 case MSR_IA32_SYSENTER_ESP
:
1901 *data
= svm
->vmcb
->save
.sysenter_esp
;
1903 /* Nobody will change the following 5 values in the VMCB so
1904 we can safely return them on rdmsr. They will always be 0
1905 until LBRV is implemented. */
1906 case MSR_IA32_DEBUGCTLMSR
:
1907 *data
= svm
->vmcb
->save
.dbgctl
;
1909 case MSR_IA32_LASTBRANCHFROMIP
:
1910 *data
= svm
->vmcb
->save
.br_from
;
1912 case MSR_IA32_LASTBRANCHTOIP
:
1913 *data
= svm
->vmcb
->save
.br_to
;
1915 case MSR_IA32_LASTINTFROMIP
:
1916 *data
= svm
->vmcb
->save
.last_excp_from
;
1918 case MSR_IA32_LASTINTTOIP
:
1919 *data
= svm
->vmcb
->save
.last_excp_to
;
1921 case MSR_VM_HSAVE_PA
:
1922 *data
= svm
->hsave_msr
;
1928 return kvm_get_msr_common(vcpu
, ecx
, data
);
1933 static int rdmsr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1935 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1938 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
))
1939 kvm_inject_gp(&svm
->vcpu
, 0);
1941 KVMTRACE_3D(MSR_READ
, &svm
->vcpu
, ecx
, (u32
)data
,
1942 (u32
)(data
>> 32), handler
);
1944 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
1945 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
1946 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
1947 skip_emulated_instruction(&svm
->vcpu
);
1952 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
1954 struct vcpu_svm
*svm
= to_svm(vcpu
);
1957 case MSR_IA32_TIME_STAMP_COUNTER
: {
1961 svm
->vmcb
->control
.tsc_offset
= data
- tsc
;
1965 svm
->vmcb
->save
.star
= data
;
1967 #ifdef CONFIG_X86_64
1969 svm
->vmcb
->save
.lstar
= data
;
1972 svm
->vmcb
->save
.cstar
= data
;
1974 case MSR_KERNEL_GS_BASE
:
1975 svm
->vmcb
->save
.kernel_gs_base
= data
;
1977 case MSR_SYSCALL_MASK
:
1978 svm
->vmcb
->save
.sfmask
= data
;
1981 case MSR_IA32_SYSENTER_CS
:
1982 svm
->vmcb
->save
.sysenter_cs
= data
;
1984 case MSR_IA32_SYSENTER_EIP
:
1985 svm
->vmcb
->save
.sysenter_eip
= data
;
1987 case MSR_IA32_SYSENTER_ESP
:
1988 svm
->vmcb
->save
.sysenter_esp
= data
;
1990 case MSR_IA32_DEBUGCTLMSR
:
1991 if (!svm_has(SVM_FEATURE_LBRV
)) {
1992 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1996 if (data
& DEBUGCTL_RESERVED_BITS
)
1999 svm
->vmcb
->save
.dbgctl
= data
;
2000 if (data
& (1ULL<<0))
2001 svm_enable_lbrv(svm
);
2003 svm_disable_lbrv(svm
);
2005 case MSR_K7_EVNTSEL0
:
2006 case MSR_K7_EVNTSEL1
:
2007 case MSR_K7_EVNTSEL2
:
2008 case MSR_K7_EVNTSEL3
:
2009 case MSR_K7_PERFCTR0
:
2010 case MSR_K7_PERFCTR1
:
2011 case MSR_K7_PERFCTR2
:
2012 case MSR_K7_PERFCTR3
:
2014 * Just discard all writes to the performance counters; this
2015 * should keep both older linux and windows 64-bit guests
2018 pr_unimpl(vcpu
, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2021 case MSR_VM_HSAVE_PA
:
2022 svm
->hsave_msr
= data
;
2025 return kvm_set_msr_common(vcpu
, ecx
, data
);
2030 static int wrmsr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
2032 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2033 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
2034 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2036 KVMTRACE_3D(MSR_WRITE
, &svm
->vcpu
, ecx
, (u32
)data
, (u32
)(data
>> 32),
2039 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2040 if (svm_set_msr(&svm
->vcpu
, ecx
, data
))
2041 kvm_inject_gp(&svm
->vcpu
, 0);
2043 skip_emulated_instruction(&svm
->vcpu
);
2047 static int msr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
2049 if (svm
->vmcb
->control
.exit_info_1
)
2050 return wrmsr_interception(svm
, kvm_run
);
2052 return rdmsr_interception(svm
, kvm_run
);
2055 static int interrupt_window_interception(struct vcpu_svm
*svm
,
2056 struct kvm_run
*kvm_run
)
2058 KVMTRACE_0D(PEND_INTR
, &svm
->vcpu
, handler
);
2060 svm_clear_vintr(svm
);
2061 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2063 * If the user space waits to inject interrupts, exit as soon as
2066 if (kvm_run
->request_interrupt_window
&&
2067 !svm
->vcpu
.arch
.irq_summary
) {
2068 ++svm
->vcpu
.stat
.irq_window_exits
;
2069 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2076 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
,
2077 struct kvm_run
*kvm_run
) = {
2078 [SVM_EXIT_READ_CR0
] = emulate_on_interception
,
2079 [SVM_EXIT_READ_CR3
] = emulate_on_interception
,
2080 [SVM_EXIT_READ_CR4
] = emulate_on_interception
,
2081 [SVM_EXIT_READ_CR8
] = emulate_on_interception
,
2083 [SVM_EXIT_WRITE_CR0
] = emulate_on_interception
,
2084 [SVM_EXIT_WRITE_CR3
] = emulate_on_interception
,
2085 [SVM_EXIT_WRITE_CR4
] = emulate_on_interception
,
2086 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
2087 [SVM_EXIT_READ_DR0
] = emulate_on_interception
,
2088 [SVM_EXIT_READ_DR1
] = emulate_on_interception
,
2089 [SVM_EXIT_READ_DR2
] = emulate_on_interception
,
2090 [SVM_EXIT_READ_DR3
] = emulate_on_interception
,
2091 [SVM_EXIT_WRITE_DR0
] = emulate_on_interception
,
2092 [SVM_EXIT_WRITE_DR1
] = emulate_on_interception
,
2093 [SVM_EXIT_WRITE_DR2
] = emulate_on_interception
,
2094 [SVM_EXIT_WRITE_DR3
] = emulate_on_interception
,
2095 [SVM_EXIT_WRITE_DR5
] = emulate_on_interception
,
2096 [SVM_EXIT_WRITE_DR7
] = emulate_on_interception
,
2097 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
2098 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
2099 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
2100 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
2101 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
2102 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
2103 [SVM_EXIT_INTR
] = intr_interception
,
2104 [SVM_EXIT_NMI
] = nmi_interception
,
2105 [SVM_EXIT_SMI
] = nop_on_interception
,
2106 [SVM_EXIT_INIT
] = nop_on_interception
,
2107 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
2108 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2109 [SVM_EXIT_CPUID
] = cpuid_interception
,
2110 [SVM_EXIT_INVD
] = emulate_on_interception
,
2111 [SVM_EXIT_HLT
] = halt_interception
,
2112 [SVM_EXIT_INVLPG
] = invlpg_interception
,
2113 [SVM_EXIT_INVLPGA
] = invalid_op_interception
,
2114 [SVM_EXIT_IOIO
] = io_interception
,
2115 [SVM_EXIT_MSR
] = msr_interception
,
2116 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
2117 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
2118 [SVM_EXIT_VMRUN
] = vmrun_interception
,
2119 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
2120 [SVM_EXIT_VMLOAD
] = vmload_interception
,
2121 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
2122 [SVM_EXIT_STGI
] = stgi_interception
,
2123 [SVM_EXIT_CLGI
] = clgi_interception
,
2124 [SVM_EXIT_SKINIT
] = invalid_op_interception
,
2125 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
2126 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
2127 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
2128 [SVM_EXIT_NPF
] = pf_interception
,
2131 static int handle_exit(struct kvm_run
*kvm_run
, struct kvm_vcpu
*vcpu
)
2133 struct vcpu_svm
*svm
= to_svm(vcpu
);
2134 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2136 KVMTRACE_3D(VMEXIT
, vcpu
, exit_code
, (u32
)svm
->vmcb
->save
.rip
,
2137 (u32
)((u64
)svm
->vmcb
->save
.rip
>> 32), entryexit
);
2139 if (is_nested(svm
)) {
2140 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2141 exit_code
, svm
->vmcb
->control
.exit_info_1
,
2142 svm
->vmcb
->control
.exit_info_2
, svm
->vmcb
->save
.rip
);
2143 if (nested_svm_exit_handled(svm
, true)) {
2144 nested_svm_vmexit(svm
);
2145 nsvm_printk("-> #VMEXIT\n");
2152 if ((vcpu
->arch
.cr0
^ svm
->vmcb
->save
.cr0
) & X86_CR0_PG
) {
2153 svm_set_cr0(vcpu
, svm
->vmcb
->save
.cr0
);
2156 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
2157 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
2158 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2159 if (!load_pdptrs(vcpu
, vcpu
->arch
.cr3
)) {
2160 kvm_inject_gp(vcpu
, 0);
2165 kvm_mmu_reset_context(vcpu
);
2172 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
2173 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
2174 kvm_run
->fail_entry
.hardware_entry_failure_reason
2175 = svm
->vmcb
->control
.exit_code
;
2179 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
2180 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
2181 exit_code
!= SVM_EXIT_NPF
)
2182 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
2184 __func__
, svm
->vmcb
->control
.exit_int_info
,
2187 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
2188 || !svm_exit_handlers
[exit_code
]) {
2189 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
2190 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
2194 return svm_exit_handlers
[exit_code
](svm
, kvm_run
);
2197 static void reload_tss(struct kvm_vcpu
*vcpu
)
2199 int cpu
= raw_smp_processor_id();
2201 struct svm_cpu_data
*svm_data
= per_cpu(svm_data
, cpu
);
2202 svm_data
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
2206 static void pre_svm_run(struct vcpu_svm
*svm
)
2208 int cpu
= raw_smp_processor_id();
2210 struct svm_cpu_data
*svm_data
= per_cpu(svm_data
, cpu
);
2212 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
2213 if (svm
->vcpu
.cpu
!= cpu
||
2214 svm
->asid_generation
!= svm_data
->asid_generation
)
2215 new_asid(svm
, svm_data
);
2219 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
2221 struct vmcb_control_area
*control
;
2223 KVMTRACE_1D(INJ_VIRQ
, &svm
->vcpu
, (u32
)irq
, handler
);
2225 ++svm
->vcpu
.stat
.irq_injections
;
2226 control
= &svm
->vmcb
->control
;
2227 control
->int_vector
= irq
;
2228 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
2229 control
->int_ctl
|= V_IRQ_MASK
|
2230 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
2233 static void svm_set_irq(struct kvm_vcpu
*vcpu
, int irq
)
2235 struct vcpu_svm
*svm
= to_svm(vcpu
);
2237 nested_svm_intr(svm
);
2239 svm_inject_irq(svm
, irq
);
2242 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
)
2244 struct vcpu_svm
*svm
= to_svm(vcpu
);
2245 struct vmcb
*vmcb
= svm
->vmcb
;
2248 if (!irqchip_in_kernel(vcpu
->kvm
) || vcpu
->arch
.apic
->vapic_addr
)
2251 vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
2253 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
2257 tpr
= kvm_lapic_get_cr8(vcpu
) << 4;
2259 if (tpr
>= (max_irr
& 0xf0))
2260 vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR8_MASK
;
2263 static void svm_intr_assist(struct kvm_vcpu
*vcpu
)
2265 struct vcpu_svm
*svm
= to_svm(vcpu
);
2266 struct vmcb
*vmcb
= svm
->vmcb
;
2267 int intr_vector
= -1;
2269 if ((vmcb
->control
.exit_int_info
& SVM_EVTINJ_VALID
) &&
2270 ((vmcb
->control
.exit_int_info
& SVM_EVTINJ_TYPE_MASK
) == 0)) {
2271 intr_vector
= vmcb
->control
.exit_int_info
&
2272 SVM_EVTINJ_VEC_MASK
;
2273 vmcb
->control
.exit_int_info
= 0;
2274 svm_inject_irq(svm
, intr_vector
);
2278 if (vmcb
->control
.int_ctl
& V_IRQ_MASK
)
2281 if (!kvm_cpu_has_interrupt(vcpu
))
2284 if (nested_svm_intr(svm
))
2287 if (!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
))
2290 if (!(vmcb
->save
.rflags
& X86_EFLAGS_IF
) ||
2291 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) ||
2292 (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
)) {
2293 /* unable to deliver irq, set pending irq */
2295 svm_inject_irq(svm
, 0x0);
2298 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
2299 intr_vector
= kvm_cpu_get_interrupt(vcpu
);
2300 svm_inject_irq(svm
, intr_vector
);
2302 update_cr8_intercept(vcpu
);
2305 static void kvm_reput_irq(struct vcpu_svm
*svm
)
2307 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
2309 if ((control
->int_ctl
& V_IRQ_MASK
)
2310 && !irqchip_in_kernel(svm
->vcpu
.kvm
)) {
2311 control
->int_ctl
&= ~V_IRQ_MASK
;
2312 push_irq(&svm
->vcpu
, control
->int_vector
);
2315 svm
->vcpu
.arch
.interrupt_window_open
=
2316 !(control
->int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
2317 (svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
2320 static void svm_do_inject_vector(struct vcpu_svm
*svm
)
2322 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2323 int word_index
= __ffs(vcpu
->arch
.irq_summary
);
2324 int bit_index
= __ffs(vcpu
->arch
.irq_pending
[word_index
]);
2325 int irq
= word_index
* BITS_PER_LONG
+ bit_index
;
2327 clear_bit(bit_index
, &vcpu
->arch
.irq_pending
[word_index
]);
2328 if (!vcpu
->arch
.irq_pending
[word_index
])
2329 clear_bit(word_index
, &vcpu
->arch
.irq_summary
);
2330 svm_inject_irq(svm
, irq
);
2333 static void do_interrupt_requests(struct kvm_vcpu
*vcpu
,
2334 struct kvm_run
*kvm_run
)
2336 struct vcpu_svm
*svm
= to_svm(vcpu
);
2337 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
2339 if (nested_svm_intr(svm
))
2342 svm
->vcpu
.arch
.interrupt_window_open
=
2343 (!(control
->int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
2344 (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
) &&
2345 (svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
));
2347 if (svm
->vcpu
.arch
.interrupt_window_open
&& svm
->vcpu
.arch
.irq_summary
)
2349 * If interrupts enabled, and not blocked by sti or mov ss. Good.
2351 svm_do_inject_vector(svm
);
2354 * Interrupts blocked. Wait for unblock.
2356 if (!svm
->vcpu
.arch
.interrupt_window_open
&&
2357 (svm
->vcpu
.arch
.irq_summary
|| kvm_run
->request_interrupt_window
))
2360 svm_clear_vintr(svm
);
2363 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2368 static void save_db_regs(unsigned long *db_regs
)
2370 asm volatile ("mov %%dr0, %0" : "=r"(db_regs
[0]));
2371 asm volatile ("mov %%dr1, %0" : "=r"(db_regs
[1]));
2372 asm volatile ("mov %%dr2, %0" : "=r"(db_regs
[2]));
2373 asm volatile ("mov %%dr3, %0" : "=r"(db_regs
[3]));
2376 static void load_db_regs(unsigned long *db_regs
)
2378 asm volatile ("mov %0, %%dr0" : : "r"(db_regs
[0]));
2379 asm volatile ("mov %0, %%dr1" : : "r"(db_regs
[1]));
2380 asm volatile ("mov %0, %%dr2" : : "r"(db_regs
[2]));
2381 asm volatile ("mov %0, %%dr3" : : "r"(db_regs
[3]));
2384 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
2386 force_new_asid(vcpu
);
2389 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
2393 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
2395 struct vcpu_svm
*svm
= to_svm(vcpu
);
2397 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR8_MASK
)) {
2398 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
2399 kvm_lapic_set_tpr(vcpu
, cr8
);
2403 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
2405 struct vcpu_svm
*svm
= to_svm(vcpu
);
2408 if (!irqchip_in_kernel(vcpu
->kvm
))
2411 cr8
= kvm_get_cr8(vcpu
);
2412 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
2413 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
2416 #ifdef CONFIG_X86_64
2422 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2424 struct vcpu_svm
*svm
= to_svm(vcpu
);
2429 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
2430 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
2431 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
2435 sync_lapic_to_cr8(vcpu
);
2437 save_host_msrs(vcpu
);
2438 fs_selector
= kvm_read_fs();
2439 gs_selector
= kvm_read_gs();
2440 ldt_selector
= kvm_read_ldt();
2441 svm
->host_cr2
= kvm_read_cr2();
2442 svm
->host_dr6
= read_dr6();
2443 svm
->host_dr7
= read_dr7();
2444 if (!is_nested(svm
))
2445 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
2446 /* required for live migration with NPT */
2448 svm
->vmcb
->save
.cr3
= vcpu
->arch
.cr3
;
2450 if (svm
->vmcb
->save
.dr7
& 0xff) {
2452 save_db_regs(svm
->host_db_regs
);
2453 load_db_regs(svm
->db_regs
);
2461 "push %%"R
"bp; \n\t"
2462 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
2463 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
2464 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
2465 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
2466 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
2467 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
2468 #ifdef CONFIG_X86_64
2469 "mov %c[r8](%[svm]), %%r8 \n\t"
2470 "mov %c[r9](%[svm]), %%r9 \n\t"
2471 "mov %c[r10](%[svm]), %%r10 \n\t"
2472 "mov %c[r11](%[svm]), %%r11 \n\t"
2473 "mov %c[r12](%[svm]), %%r12 \n\t"
2474 "mov %c[r13](%[svm]), %%r13 \n\t"
2475 "mov %c[r14](%[svm]), %%r14 \n\t"
2476 "mov %c[r15](%[svm]), %%r15 \n\t"
2479 /* Enter guest mode */
2481 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
2482 __ex(SVM_VMLOAD
) "\n\t"
2483 __ex(SVM_VMRUN
) "\n\t"
2484 __ex(SVM_VMSAVE
) "\n\t"
2487 /* Save guest registers, load host registers */
2488 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
2489 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
2490 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
2491 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
2492 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
2493 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
2494 #ifdef CONFIG_X86_64
2495 "mov %%r8, %c[r8](%[svm]) \n\t"
2496 "mov %%r9, %c[r9](%[svm]) \n\t"
2497 "mov %%r10, %c[r10](%[svm]) \n\t"
2498 "mov %%r11, %c[r11](%[svm]) \n\t"
2499 "mov %%r12, %c[r12](%[svm]) \n\t"
2500 "mov %%r13, %c[r13](%[svm]) \n\t"
2501 "mov %%r14, %c[r14](%[svm]) \n\t"
2502 "mov %%r15, %c[r15](%[svm]) \n\t"
2507 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
2508 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
2509 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
2510 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
2511 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
2512 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
2513 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
2514 #ifdef CONFIG_X86_64
2515 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
2516 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
2517 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
2518 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
2519 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
2520 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
2521 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
2522 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
2525 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
2526 #ifdef CONFIG_X86_64
2527 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2531 if ((svm
->vmcb
->save
.dr7
& 0xff))
2532 load_db_regs(svm
->host_db_regs
);
2534 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
2535 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
2536 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
2537 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
2539 write_dr6(svm
->host_dr6
);
2540 write_dr7(svm
->host_dr7
);
2541 kvm_write_cr2(svm
->host_cr2
);
2543 kvm_load_fs(fs_selector
);
2544 kvm_load_gs(gs_selector
);
2545 kvm_load_ldt(ldt_selector
);
2546 load_host_msrs(vcpu
);
2550 local_irq_disable();
2554 sync_cr8_to_lapic(vcpu
);
2561 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
2563 struct vcpu_svm
*svm
= to_svm(vcpu
);
2566 svm
->vmcb
->control
.nested_cr3
= root
;
2567 force_new_asid(vcpu
);
2571 svm
->vmcb
->save
.cr3
= root
;
2572 force_new_asid(vcpu
);
2574 if (vcpu
->fpu_active
) {
2575 svm
->vmcb
->control
.intercept_exceptions
|= (1 << NM_VECTOR
);
2576 svm
->vmcb
->save
.cr0
|= X86_CR0_TS
;
2577 vcpu
->fpu_active
= 0;
2581 static int is_disabled(void)
2585 rdmsrl(MSR_VM_CR
, vm_cr
);
2586 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
2593 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
2596 * Patch in the VMMCALL instruction:
2598 hypercall
[0] = 0x0f;
2599 hypercall
[1] = 0x01;
2600 hypercall
[2] = 0xd9;
2603 static void svm_check_processor_compat(void *rtn
)
2608 static bool svm_cpu_has_accelerated_tpr(void)
2613 static int get_npt_level(void)
2615 #ifdef CONFIG_X86_64
2616 return PT64_ROOT_LEVEL
;
2618 return PT32E_ROOT_LEVEL
;
2622 static int svm_get_mt_mask_shift(void)
2627 static struct kvm_x86_ops svm_x86_ops
= {
2628 .cpu_has_kvm_support
= has_svm
,
2629 .disabled_by_bios
= is_disabled
,
2630 .hardware_setup
= svm_hardware_setup
,
2631 .hardware_unsetup
= svm_hardware_unsetup
,
2632 .check_processor_compatibility
= svm_check_processor_compat
,
2633 .hardware_enable
= svm_hardware_enable
,
2634 .hardware_disable
= svm_hardware_disable
,
2635 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
2637 .vcpu_create
= svm_create_vcpu
,
2638 .vcpu_free
= svm_free_vcpu
,
2639 .vcpu_reset
= svm_vcpu_reset
,
2641 .prepare_guest_switch
= svm_prepare_guest_switch
,
2642 .vcpu_load
= svm_vcpu_load
,
2643 .vcpu_put
= svm_vcpu_put
,
2645 .set_guest_debug
= svm_guest_debug
,
2646 .get_msr
= svm_get_msr
,
2647 .set_msr
= svm_set_msr
,
2648 .get_segment_base
= svm_get_segment_base
,
2649 .get_segment
= svm_get_segment
,
2650 .set_segment
= svm_set_segment
,
2651 .get_cpl
= svm_get_cpl
,
2652 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
2653 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
2654 .set_cr0
= svm_set_cr0
,
2655 .set_cr3
= svm_set_cr3
,
2656 .set_cr4
= svm_set_cr4
,
2657 .set_efer
= svm_set_efer
,
2658 .get_idt
= svm_get_idt
,
2659 .set_idt
= svm_set_idt
,
2660 .get_gdt
= svm_get_gdt
,
2661 .set_gdt
= svm_set_gdt
,
2662 .get_dr
= svm_get_dr
,
2663 .set_dr
= svm_set_dr
,
2664 .get_rflags
= svm_get_rflags
,
2665 .set_rflags
= svm_set_rflags
,
2667 .tlb_flush
= svm_flush_tlb
,
2669 .run
= svm_vcpu_run
,
2670 .handle_exit
= handle_exit
,
2671 .skip_emulated_instruction
= skip_emulated_instruction
,
2672 .patch_hypercall
= svm_patch_hypercall
,
2673 .get_irq
= svm_get_irq
,
2674 .set_irq
= svm_set_irq
,
2675 .queue_exception
= svm_queue_exception
,
2676 .exception_injected
= svm_exception_injected
,
2677 .inject_pending_irq
= svm_intr_assist
,
2678 .inject_pending_vectors
= do_interrupt_requests
,
2680 .set_tss_addr
= svm_set_tss_addr
,
2681 .get_tdp_level
= get_npt_level
,
2682 .get_mt_mask_shift
= svm_get_mt_mask_shift
,
2685 static int __init
svm_init(void)
2687 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
2691 static void __exit
svm_exit(void)
2696 module_init(svm_init
)
2697 module_exit(svm_exit
)