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skge: receive flush logic
[linux-2.6/mini2440.git] / drivers / net / skge.c
blob82edf44b9e2a9df0c792b8d9b4d91fb2eb63cdb9
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/in.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/if_vlan.h>
35 #include <linux/ip.h>
36 #include <linux/delay.h>
37 #include <linux/crc32.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/debugfs.h>
40 #include <linux/seq_file.h>
41 #include <linux/mii.h>
42 #include <asm/irq.h>
43
44 #include "skge.h"
45
46 #define DRV_NAME "skge"
47 #define DRV_VERSION "1.12"
48 #define PFX DRV_NAME " "
49
50 #define DEFAULT_TX_RING_SIZE 128
51 #define DEFAULT_RX_RING_SIZE 512
52 #define MAX_TX_RING_SIZE 1024
53 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
54 #define MAX_RX_RING_SIZE 4096
55 #define RX_COPY_THRESHOLD 128
56 #define RX_BUF_SIZE 1536
57 #define PHY_RETRIES 1000
58 #define ETH_JUMBO_MTU 9000
59 #define TX_WATCHDOG (5 * HZ)
60 #define NAPI_WEIGHT 64
61 #define BLINK_MS 250
62 #define LINK_HZ HZ
63
64 #define SKGE_EEPROM_MAGIC 0x9933aabb
65
66
67 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
68 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
69 MODULE_LICENSE("GPL");
70 MODULE_VERSION(DRV_VERSION);
71
72 static const u32 default_msg
73 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
74 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
75
76 static int debug = -1; /* defaults above */
77 module_param(debug, int, 0);
78 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
79
80 static const struct pci_device_id skge_id_table[] = {
81 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
82 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
83 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
84 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
85 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
86 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
87 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
88 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
89 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
90 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
91 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
92 { 0 }
93 };
94 MODULE_DEVICE_TABLE(pci, skge_id_table);
95
96 static int skge_up(struct net_device *dev);
97 static int skge_down(struct net_device *dev);
98 static void skge_phy_reset(struct skge_port *skge);
99 static void skge_tx_clean(struct net_device *dev);
100 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
101 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
102 static void genesis_get_stats(struct skge_port *skge, u64 *data);
103 static void yukon_get_stats(struct skge_port *skge, u64 *data);
104 static void yukon_init(struct skge_hw *hw, int port);
105 static void genesis_mac_init(struct skge_hw *hw, int port);
106 static void genesis_link_up(struct skge_port *skge);
107
108 /* Avoid conditionals by using array */
109 static const int txqaddr[] = { Q_XA1, Q_XA2 };
110 static const int rxqaddr[] = { Q_R1, Q_R2 };
111 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
112 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
113 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
114 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
115
116 static int skge_get_regs_len(struct net_device *dev)
117 {
118 return 0x4000;
119 }
120
121 /*
122 * Returns copy of whole control register region
123 * Note: skip RAM address register because accessing it will
124 * cause bus hangs!
125 */
126 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
127 void *p)
128 {
129 const struct skge_port *skge = netdev_priv(dev);
130 const void __iomem *io = skge->hw->regs;
131
132 regs->version = 1;
133 memset(p, 0, regs->len);
134 memcpy_fromio(p, io, B3_RAM_ADDR);
135
136 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
137 regs->len - B3_RI_WTO_R1);
138 }
139
140 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
141 static u32 wol_supported(const struct skge_hw *hw)
142 {
143 if (hw->chip_id == CHIP_ID_GENESIS)
144 return 0;
145
146 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
147 return 0;
148
149 return WAKE_MAGIC | WAKE_PHY;
150 }
151
152 static u32 pci_wake_enabled(struct pci_dev *dev)
153 {
154 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
155 u16 value;
156
157 /* If device doesn't support PM Capabilities, but request is to disable
158 * wake events, it's a nop; otherwise fail */
159 if (!pm)
160 return 0;
161
162 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
163
164 value &= PCI_PM_CAP_PME_MASK;
165 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
166
167 return value != 0;
168 }
169
170 static void skge_wol_init(struct skge_port *skge)
171 {
172 struct skge_hw *hw = skge->hw;
173 int port = skge->port;
174 u16 ctrl;
175
176 skge_write16(hw, B0_CTST, CS_RST_CLR);
177 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
178
179 /* Turn on Vaux */
180 skge_write8(hw, B0_POWER_CTRL,
181 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
182
183 /* WA code for COMA mode -- clear PHY reset */
184 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
185 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
186 u32 reg = skge_read32(hw, B2_GP_IO);
187 reg |= GP_DIR_9;
188 reg &= ~GP_IO_9;
189 skge_write32(hw, B2_GP_IO, reg);
190 }
191
192 skge_write32(hw, SK_REG(port, GPHY_CTRL),
193 GPC_DIS_SLEEP |
194 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
195 GPC_ANEG_1 | GPC_RST_SET);
196
197 skge_write32(hw, SK_REG(port, GPHY_CTRL),
198 GPC_DIS_SLEEP |
199 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
200 GPC_ANEG_1 | GPC_RST_CLR);
201
202 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
203
204 /* Force to 10/100 skge_reset will re-enable on resume */
205 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
206 PHY_AN_100FULL | PHY_AN_100HALF |
207 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
208 /* no 1000 HD/FD */
209 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
210 gm_phy_write(hw, port, PHY_MARV_CTRL,
211 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
212 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
213
214
215 /* Set GMAC to no flow control and auto update for speed/duplex */
216 gma_write16(hw, port, GM_GP_CTRL,
217 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
218 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
219
220 /* Set WOL address */
221 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
222 skge->netdev->dev_addr, ETH_ALEN);
223
224 /* Turn on appropriate WOL control bits */
225 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
226 ctrl = 0;
227 if (skge->wol & WAKE_PHY)
228 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
229 else
230 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
231
232 if (skge->wol & WAKE_MAGIC)
233 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
234 else
235 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
236
237 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
238 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
239
240 /* block receiver */
241 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
242 }
243
244 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
245 {
246 struct skge_port *skge = netdev_priv(dev);
247
248 wol->supported = wol_supported(skge->hw);
249 wol->wolopts = skge->wol;
250 }
251
252 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
253 {
254 struct skge_port *skge = netdev_priv(dev);
255 struct skge_hw *hw = skge->hw;
256
257 if (wol->wolopts & ~wol_supported(hw))
258 return -EOPNOTSUPP;
259
260 skge->wol = wol->wolopts;
261 return 0;
262 }
263
264 /* Determine supported/advertised modes based on hardware.
265 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
266 */
267 static u32 skge_supported_modes(const struct skge_hw *hw)
268 {
269 u32 supported;
270
271 if (hw->copper) {
272 supported = SUPPORTED_10baseT_Half
273 | SUPPORTED_10baseT_Full
274 | SUPPORTED_100baseT_Half
275 | SUPPORTED_100baseT_Full
276 | SUPPORTED_1000baseT_Half
277 | SUPPORTED_1000baseT_Full
278 | SUPPORTED_Autoneg| SUPPORTED_TP;
279
280 if (hw->chip_id == CHIP_ID_GENESIS)
281 supported &= ~(SUPPORTED_10baseT_Half
282 | SUPPORTED_10baseT_Full
283 | SUPPORTED_100baseT_Half
284 | SUPPORTED_100baseT_Full);
285
286 else if (hw->chip_id == CHIP_ID_YUKON)
287 supported &= ~SUPPORTED_1000baseT_Half;
288 } else
289 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
290 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
291
292 return supported;
293 }
294
295 static int skge_get_settings(struct net_device *dev,
296 struct ethtool_cmd *ecmd)
297 {
298 struct skge_port *skge = netdev_priv(dev);
299 struct skge_hw *hw = skge->hw;
300
301 ecmd->transceiver = XCVR_INTERNAL;
302 ecmd->supported = skge_supported_modes(hw);
303
304 if (hw->copper) {
305 ecmd->port = PORT_TP;
306 ecmd->phy_address = hw->phy_addr;
307 } else
308 ecmd->port = PORT_FIBRE;
309
310 ecmd->advertising = skge->advertising;
311 ecmd->autoneg = skge->autoneg;
312 ecmd->speed = skge->speed;
313 ecmd->duplex = skge->duplex;
314 return 0;
315 }
316
317 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
318 {
319 struct skge_port *skge = netdev_priv(dev);
320 const struct skge_hw *hw = skge->hw;
321 u32 supported = skge_supported_modes(hw);
322
323 if (ecmd->autoneg == AUTONEG_ENABLE) {
324 ecmd->advertising = supported;
325 skge->duplex = -1;
326 skge->speed = -1;
327 } else {
328 u32 setting;
329
330 switch (ecmd->speed) {
331 case SPEED_1000:
332 if (ecmd->duplex == DUPLEX_FULL)
333 setting = SUPPORTED_1000baseT_Full;
334 else if (ecmd->duplex == DUPLEX_HALF)
335 setting = SUPPORTED_1000baseT_Half;
336 else
337 return -EINVAL;
338 break;
339 case SPEED_100:
340 if (ecmd->duplex == DUPLEX_FULL)
341 setting = SUPPORTED_100baseT_Full;
342 else if (ecmd->duplex == DUPLEX_HALF)
343 setting = SUPPORTED_100baseT_Half;
344 else
345 return -EINVAL;
346 break;
347
348 case SPEED_10:
349 if (ecmd->duplex == DUPLEX_FULL)
350 setting = SUPPORTED_10baseT_Full;
351 else if (ecmd->duplex == DUPLEX_HALF)
352 setting = SUPPORTED_10baseT_Half;
353 else
354 return -EINVAL;
355 break;
356 default:
357 return -EINVAL;
358 }
359
360 if ((setting & supported) == 0)
361 return -EINVAL;
362
363 skge->speed = ecmd->speed;
364 skge->duplex = ecmd->duplex;
365 }
366
367 skge->autoneg = ecmd->autoneg;
368 skge->advertising = ecmd->advertising;
369
370 if (netif_running(dev))
371 skge_phy_reset(skge);
372
373 return (0);
374 }
375
376 static void skge_get_drvinfo(struct net_device *dev,
377 struct ethtool_drvinfo *info)
378 {
379 struct skge_port *skge = netdev_priv(dev);
380
381 strcpy(info->driver, DRV_NAME);
382 strcpy(info->version, DRV_VERSION);
383 strcpy(info->fw_version, "N/A");
384 strcpy(info->bus_info, pci_name(skge->hw->pdev));
385 }
386
387 static const struct skge_stat {
388 char name[ETH_GSTRING_LEN];
389 u16 xmac_offset;
390 u16 gma_offset;
391 } skge_stats[] = {
392 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
393 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
394
395 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
396 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
397 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
398 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
399 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
400 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
401 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
402 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
403
404 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
405 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
406 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
407 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
408 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
409 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
410
411 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
412 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
413 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
414 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
415 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
416 };
417
418 static int skge_get_sset_count(struct net_device *dev, int sset)
419 {
420 switch (sset) {
421 case ETH_SS_STATS:
422 return ARRAY_SIZE(skge_stats);
423 default:
424 return -EOPNOTSUPP;
425 }
426 }
427
428 static void skge_get_ethtool_stats(struct net_device *dev,
429 struct ethtool_stats *stats, u64 *data)
430 {
431 struct skge_port *skge = netdev_priv(dev);
432
433 if (skge->hw->chip_id == CHIP_ID_GENESIS)
434 genesis_get_stats(skge, data);
435 else
436 yukon_get_stats(skge, data);
437 }
438
439 /* Use hardware MIB variables for critical path statistics and
440 * transmit feedback not reported at interrupt.
441 * Other errors are accounted for in interrupt handler.
442 */
443 static struct net_device_stats *skge_get_stats(struct net_device *dev)
444 {
445 struct skge_port *skge = netdev_priv(dev);
446 u64 data[ARRAY_SIZE(skge_stats)];
447
448 if (skge->hw->chip_id == CHIP_ID_GENESIS)
449 genesis_get_stats(skge, data);
450 else
451 yukon_get_stats(skge, data);
452
453 dev->stats.tx_bytes = data[0];
454 dev->stats.rx_bytes = data[1];
455 dev->stats.tx_packets = data[2] + data[4] + data[6];
456 dev->stats.rx_packets = data[3] + data[5] + data[7];
457 dev->stats.multicast = data[3] + data[5];
458 dev->stats.collisions = data[10];
459 dev->stats.tx_aborted_errors = data[12];
460
461 return &dev->stats;
462 }
463
464 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
465 {
466 int i;
467
468 switch (stringset) {
469 case ETH_SS_STATS:
470 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
471 memcpy(data + i * ETH_GSTRING_LEN,
472 skge_stats[i].name, ETH_GSTRING_LEN);
473 break;
474 }
475 }
476
477 static void skge_get_ring_param(struct net_device *dev,
478 struct ethtool_ringparam *p)
479 {
480 struct skge_port *skge = netdev_priv(dev);
481
482 p->rx_max_pending = MAX_RX_RING_SIZE;
483 p->tx_max_pending = MAX_TX_RING_SIZE;
484 p->rx_mini_max_pending = 0;
485 p->rx_jumbo_max_pending = 0;
486
487 p->rx_pending = skge->rx_ring.count;
488 p->tx_pending = skge->tx_ring.count;
489 p->rx_mini_pending = 0;
490 p->rx_jumbo_pending = 0;
491 }
492
493 static int skge_set_ring_param(struct net_device *dev,
494 struct ethtool_ringparam *p)
495 {
496 struct skge_port *skge = netdev_priv(dev);
497 int err;
498
499 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
500 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
501 return -EINVAL;
502
503 skge->rx_ring.count = p->rx_pending;
504 skge->tx_ring.count = p->tx_pending;
505
506 if (netif_running(dev)) {
507 skge_down(dev);
508 err = skge_up(dev);
509 if (err)
510 dev_close(dev);
511 }
512
513 return 0;
514 }
515
516 static u32 skge_get_msglevel(struct net_device *netdev)
517 {
518 struct skge_port *skge = netdev_priv(netdev);
519 return skge->msg_enable;
520 }
521
522 static void skge_set_msglevel(struct net_device *netdev, u32 value)
523 {
524 struct skge_port *skge = netdev_priv(netdev);
525 skge->msg_enable = value;
526 }
527
528 static int skge_nway_reset(struct net_device *dev)
529 {
530 struct skge_port *skge = netdev_priv(dev);
531
532 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
533 return -EINVAL;
534
535 skge_phy_reset(skge);
536 return 0;
537 }
538
539 static int skge_set_sg(struct net_device *dev, u32 data)
540 {
541 struct skge_port *skge = netdev_priv(dev);
542 struct skge_hw *hw = skge->hw;
543
544 if (hw->chip_id == CHIP_ID_GENESIS && data)
545 return -EOPNOTSUPP;
546 return ethtool_op_set_sg(dev, data);
547 }
548
549 static int skge_set_tx_csum(struct net_device *dev, u32 data)
550 {
551 struct skge_port *skge = netdev_priv(dev);
552 struct skge_hw *hw = skge->hw;
553
554 if (hw->chip_id == CHIP_ID_GENESIS && data)
555 return -EOPNOTSUPP;
556
557 return ethtool_op_set_tx_csum(dev, data);
558 }
559
560 static u32 skge_get_rx_csum(struct net_device *dev)
561 {
562 struct skge_port *skge = netdev_priv(dev);
563
564 return skge->rx_csum;
565 }
566
567 /* Only Yukon supports checksum offload. */
568 static int skge_set_rx_csum(struct net_device *dev, u32 data)
569 {
570 struct skge_port *skge = netdev_priv(dev);
571
572 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
573 return -EOPNOTSUPP;
574
575 skge->rx_csum = data;
576 return 0;
577 }
578
579 static void skge_get_pauseparam(struct net_device *dev,
580 struct ethtool_pauseparam *ecmd)
581 {
582 struct skge_port *skge = netdev_priv(dev);
583
584 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
585 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
586 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
587
588 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
589 }
590
591 static int skge_set_pauseparam(struct net_device *dev,
592 struct ethtool_pauseparam *ecmd)
593 {
594 struct skge_port *skge = netdev_priv(dev);
595 struct ethtool_pauseparam old;
596
597 skge_get_pauseparam(dev, &old);
598
599 if (ecmd->autoneg != old.autoneg)
600 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
601 else {
602 if (ecmd->rx_pause && ecmd->tx_pause)
603 skge->flow_control = FLOW_MODE_SYMMETRIC;
604 else if (ecmd->rx_pause && !ecmd->tx_pause)
605 skge->flow_control = FLOW_MODE_SYM_OR_REM;
606 else if (!ecmd->rx_pause && ecmd->tx_pause)
607 skge->flow_control = FLOW_MODE_LOC_SEND;
608 else
609 skge->flow_control = FLOW_MODE_NONE;
610 }
611
612 if (netif_running(dev))
613 skge_phy_reset(skge);
614
615 return 0;
616 }
617
618 /* Chip internal frequency for clock calculations */
619 static inline u32 hwkhz(const struct skge_hw *hw)
620 {
621 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
622 }
623
624 /* Chip HZ to microseconds */
625 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
626 {
627 return (ticks * 1000) / hwkhz(hw);
628 }
629
630 /* Microseconds to chip HZ */
631 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
632 {
633 return hwkhz(hw) * usec / 1000;
634 }
635
636 static int skge_get_coalesce(struct net_device *dev,
637 struct ethtool_coalesce *ecmd)
638 {
639 struct skge_port *skge = netdev_priv(dev);
640 struct skge_hw *hw = skge->hw;
641 int port = skge->port;
642
643 ecmd->rx_coalesce_usecs = 0;
644 ecmd->tx_coalesce_usecs = 0;
645
646 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
647 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
648 u32 msk = skge_read32(hw, B2_IRQM_MSK);
649
650 if (msk & rxirqmask[port])
651 ecmd->rx_coalesce_usecs = delay;
652 if (msk & txirqmask[port])
653 ecmd->tx_coalesce_usecs = delay;
654 }
655
656 return 0;
657 }
658
659 /* Note: interrupt timer is per board, but can turn on/off per port */
660 static int skge_set_coalesce(struct net_device *dev,
661 struct ethtool_coalesce *ecmd)
662 {
663 struct skge_port *skge = netdev_priv(dev);
664 struct skge_hw *hw = skge->hw;
665 int port = skge->port;
666 u32 msk = skge_read32(hw, B2_IRQM_MSK);
667 u32 delay = 25;
668
669 if (ecmd->rx_coalesce_usecs == 0)
670 msk &= ~rxirqmask[port];
671 else if (ecmd->rx_coalesce_usecs < 25 ||
672 ecmd->rx_coalesce_usecs > 33333)
673 return -EINVAL;
674 else {
675 msk |= rxirqmask[port];
676 delay = ecmd->rx_coalesce_usecs;
677 }
678
679 if (ecmd->tx_coalesce_usecs == 0)
680 msk &= ~txirqmask[port];
681 else if (ecmd->tx_coalesce_usecs < 25 ||
682 ecmd->tx_coalesce_usecs > 33333)
683 return -EINVAL;
684 else {
685 msk |= txirqmask[port];
686 delay = min(delay, ecmd->rx_coalesce_usecs);
687 }
688
689 skge_write32(hw, B2_IRQM_MSK, msk);
690 if (msk == 0)
691 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
692 else {
693 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
694 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
695 }
696 return 0;
697 }
698
699 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
700 static void skge_led(struct skge_port *skge, enum led_mode mode)
701 {
702 struct skge_hw *hw = skge->hw;
703 int port = skge->port;
704
705 spin_lock_bh(&hw->phy_lock);
706 if (hw->chip_id == CHIP_ID_GENESIS) {
707 switch (mode) {
708 case LED_MODE_OFF:
709 if (hw->phy_type == SK_PHY_BCOM)
710 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
711 else {
712 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
713 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
714 }
715 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
716 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
717 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
718 break;
719
720 case LED_MODE_ON:
721 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
722 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
723
724 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
725 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
726
727 break;
728
729 case LED_MODE_TST:
730 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
731 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
732 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
733
734 if (hw->phy_type == SK_PHY_BCOM)
735 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
736 else {
737 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
738 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
739 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
740 }
741
742 }
743 } else {
744 switch (mode) {
745 case LED_MODE_OFF:
746 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
747 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
748 PHY_M_LED_MO_DUP(MO_LED_OFF) |
749 PHY_M_LED_MO_10(MO_LED_OFF) |
750 PHY_M_LED_MO_100(MO_LED_OFF) |
751 PHY_M_LED_MO_1000(MO_LED_OFF) |
752 PHY_M_LED_MO_RX(MO_LED_OFF));
753 break;
754 case LED_MODE_ON:
755 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
756 PHY_M_LED_PULS_DUR(PULS_170MS) |
757 PHY_M_LED_BLINK_RT(BLINK_84MS) |
758 PHY_M_LEDC_TX_CTRL |
759 PHY_M_LEDC_DP_CTRL);
760
761 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
762 PHY_M_LED_MO_RX(MO_LED_OFF) |
763 (skge->speed == SPEED_100 ?
764 PHY_M_LED_MO_100(MO_LED_ON) : 0));
765 break;
766 case LED_MODE_TST:
767 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
768 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
769 PHY_M_LED_MO_DUP(MO_LED_ON) |
770 PHY_M_LED_MO_10(MO_LED_ON) |
771 PHY_M_LED_MO_100(MO_LED_ON) |
772 PHY_M_LED_MO_1000(MO_LED_ON) |
773 PHY_M_LED_MO_RX(MO_LED_ON));
774 }
775 }
776 spin_unlock_bh(&hw->phy_lock);
777 }
778
779 /* blink LED's for finding board */
780 static int skge_phys_id(struct net_device *dev, u32 data)
781 {
782 struct skge_port *skge = netdev_priv(dev);
783 unsigned long ms;
784 enum led_mode mode = LED_MODE_TST;
785
786 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
787 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
788 else
789 ms = data * 1000;
790
791 while (ms > 0) {
792 skge_led(skge, mode);
793 mode ^= LED_MODE_TST;
794
795 if (msleep_interruptible(BLINK_MS))
796 break;
797 ms -= BLINK_MS;
798 }
799
800 /* back to regular LED state */
801 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
802
803 return 0;
804 }
805
806 static int skge_get_eeprom_len(struct net_device *dev)
807 {
808 struct skge_port *skge = netdev_priv(dev);
809 u32 reg2;
810
811 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
812 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
813 }
814
815 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
816 {
817 u32 val;
818
819 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
820
821 do {
822 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
823 } while (!(offset & PCI_VPD_ADDR_F));
824
825 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
826 return val;
827 }
828
829 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
830 {
831 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
832 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
833 offset | PCI_VPD_ADDR_F);
834
835 do {
836 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
837 } while (offset & PCI_VPD_ADDR_F);
838 }
839
840 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
841 u8 *data)
842 {
843 struct skge_port *skge = netdev_priv(dev);
844 struct pci_dev *pdev = skge->hw->pdev;
845 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
846 int length = eeprom->len;
847 u16 offset = eeprom->offset;
848
849 if (!cap)
850 return -EINVAL;
851
852 eeprom->magic = SKGE_EEPROM_MAGIC;
853
854 while (length > 0) {
855 u32 val = skge_vpd_read(pdev, cap, offset);
856 int n = min_t(int, length, sizeof(val));
857
858 memcpy(data, &val, n);
859 length -= n;
860 data += n;
861 offset += n;
862 }
863 return 0;
864 }
865
866 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
867 u8 *data)
868 {
869 struct skge_port *skge = netdev_priv(dev);
870 struct pci_dev *pdev = skge->hw->pdev;
871 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
872 int length = eeprom->len;
873 u16 offset = eeprom->offset;
874
875 if (!cap)
876 return -EINVAL;
877
878 if (eeprom->magic != SKGE_EEPROM_MAGIC)
879 return -EINVAL;
880
881 while (length > 0) {
882 u32 val;
883 int n = min_t(int, length, sizeof(val));
884
885 if (n < sizeof(val))
886 val = skge_vpd_read(pdev, cap, offset);
887 memcpy(&val, data, n);
888
889 skge_vpd_write(pdev, cap, offset, val);
890
891 length -= n;
892 data += n;
893 offset += n;
894 }
895 return 0;
896 }
897
898 static const struct ethtool_ops skge_ethtool_ops = {
899 .get_settings = skge_get_settings,
900 .set_settings = skge_set_settings,
901 .get_drvinfo = skge_get_drvinfo,
902 .get_regs_len = skge_get_regs_len,
903 .get_regs = skge_get_regs,
904 .get_wol = skge_get_wol,
905 .set_wol = skge_set_wol,
906 .get_msglevel = skge_get_msglevel,
907 .set_msglevel = skge_set_msglevel,
908 .nway_reset = skge_nway_reset,
909 .get_link = ethtool_op_get_link,
910 .get_eeprom_len = skge_get_eeprom_len,
911 .get_eeprom = skge_get_eeprom,
912 .set_eeprom = skge_set_eeprom,
913 .get_ringparam = skge_get_ring_param,
914 .set_ringparam = skge_set_ring_param,
915 .get_pauseparam = skge_get_pauseparam,
916 .set_pauseparam = skge_set_pauseparam,
917 .get_coalesce = skge_get_coalesce,
918 .set_coalesce = skge_set_coalesce,
919 .set_sg = skge_set_sg,
920 .set_tx_csum = skge_set_tx_csum,
921 .get_rx_csum = skge_get_rx_csum,
922 .set_rx_csum = skge_set_rx_csum,
923 .get_strings = skge_get_strings,
924 .phys_id = skge_phys_id,
925 .get_sset_count = skge_get_sset_count,
926 .get_ethtool_stats = skge_get_ethtool_stats,
927 };
928
929 /*
930 * Allocate ring elements and chain them together
931 * One-to-one association of board descriptors with ring elements
932 */
933 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
934 {
935 struct skge_tx_desc *d;
936 struct skge_element *e;
937 int i;
938
939 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
940 if (!ring->start)
941 return -ENOMEM;
942
943 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
944 e->desc = d;
945 if (i == ring->count - 1) {
946 e->next = ring->start;
947 d->next_offset = base;
948 } else {
949 e->next = e + 1;
950 d->next_offset = base + (i+1) * sizeof(*d);
951 }
952 }
953 ring->to_use = ring->to_clean = ring->start;
954
955 return 0;
956 }
957
958 /* Allocate and setup a new buffer for receiving */
959 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
960 struct sk_buff *skb, unsigned int bufsize)
961 {
962 struct skge_rx_desc *rd = e->desc;
963 u64 map;
964
965 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
966 PCI_DMA_FROMDEVICE);
967
968 rd->dma_lo = map;
969 rd->dma_hi = map >> 32;
970 e->skb = skb;
971 rd->csum1_start = ETH_HLEN;
972 rd->csum2_start = ETH_HLEN;
973 rd->csum1 = 0;
974 rd->csum2 = 0;
975
976 wmb();
977
978 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
979 pci_unmap_addr_set(e, mapaddr, map);
980 pci_unmap_len_set(e, maplen, bufsize);
981 }
982
983 /* Resume receiving using existing skb,
984 * Note: DMA address is not changed by chip.
985 * MTU not changed while receiver active.
986 */
987 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
988 {
989 struct skge_rx_desc *rd = e->desc;
990
991 rd->csum2 = 0;
992 rd->csum2_start = ETH_HLEN;
993
994 wmb();
995
996 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
997 }
998
999
1000 /* Free all buffers in receive ring, assumes receiver stopped */
1001 static void skge_rx_clean(struct skge_port *skge)
1002 {
1003 struct skge_hw *hw = skge->hw;
1004 struct skge_ring *ring = &skge->rx_ring;
1005 struct skge_element *e;
1006
1007 e = ring->start;
1008 do {
1009 struct skge_rx_desc *rd = e->desc;
1010 rd->control = 0;
1011 if (e->skb) {
1012 pci_unmap_single(hw->pdev,
1013 pci_unmap_addr(e, mapaddr),
1014 pci_unmap_len(e, maplen),
1015 PCI_DMA_FROMDEVICE);
1016 dev_kfree_skb(e->skb);
1017 e->skb = NULL;
1018 }
1019 } while ((e = e->next) != ring->start);
1020 }
1021
1022
1023 /* Allocate buffers for receive ring
1024 * For receive: to_clean is next received frame.
1025 */
1026 static int skge_rx_fill(struct net_device *dev)
1027 {
1028 struct skge_port *skge = netdev_priv(dev);
1029 struct skge_ring *ring = &skge->rx_ring;
1030 struct skge_element *e;
1031
1032 e = ring->start;
1033 do {
1034 struct sk_buff *skb;
1035
1036 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1037 GFP_KERNEL);
1038 if (!skb)
1039 return -ENOMEM;
1040
1041 skb_reserve(skb, NET_IP_ALIGN);
1042 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
1043 } while ( (e = e->next) != ring->start);
1044
1045 ring->to_clean = ring->start;
1046 return 0;
1047 }
1048
1049 static const char *skge_pause(enum pause_status status)
1050 {
1051 switch(status) {
1052 case FLOW_STAT_NONE:
1053 return "none";
1054 case FLOW_STAT_REM_SEND:
1055 return "rx only";
1056 case FLOW_STAT_LOC_SEND:
1057 return "tx_only";
1058 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1059 return "both";
1060 default:
1061 return "indeterminated";
1062 }
1063 }
1064
1065
1066 static void skge_link_up(struct skge_port *skge)
1067 {
1068 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1069 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1070
1071 netif_carrier_on(skge->netdev);
1072 netif_wake_queue(skge->netdev);
1073
1074 if (netif_msg_link(skge)) {
1075 printk(KERN_INFO PFX
1076 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1077 skge->netdev->name, skge->speed,
1078 skge->duplex == DUPLEX_FULL ? "full" : "half",
1079 skge_pause(skge->flow_status));
1080 }
1081 }
1082
1083 static void skge_link_down(struct skge_port *skge)
1084 {
1085 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
1086 netif_carrier_off(skge->netdev);
1087 netif_stop_queue(skge->netdev);
1088
1089 if (netif_msg_link(skge))
1090 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
1091 }
1092
1093
1094 static void xm_link_down(struct skge_hw *hw, int port)
1095 {
1096 struct net_device *dev = hw->dev[port];
1097 struct skge_port *skge = netdev_priv(dev);
1098 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1099
1100 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1101
1102 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1103 xm_write16(hw, port, XM_MMU_CMD, cmd);
1104
1105 /* dummy read to ensure writing */
1106 xm_read16(hw, port, XM_MMU_CMD);
1107
1108 if (netif_carrier_ok(dev))
1109 skge_link_down(skge);
1110 }
1111
1112 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1113 {
1114 int i;
1115
1116 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1117 *val = xm_read16(hw, port, XM_PHY_DATA);
1118
1119 if (hw->phy_type == SK_PHY_XMAC)
1120 goto ready;
1121
1122 for (i = 0; i < PHY_RETRIES; i++) {
1123 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1124 goto ready;
1125 udelay(1);
1126 }
1127
1128 return -ETIMEDOUT;
1129 ready:
1130 *val = xm_read16(hw, port, XM_PHY_DATA);
1131
1132 return 0;
1133 }
1134
1135 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1136 {
1137 u16 v = 0;
1138 if (__xm_phy_read(hw, port, reg, &v))
1139 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1140 hw->dev[port]->name);
1141 return v;
1142 }
1143
1144 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1145 {
1146 int i;
1147
1148 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1149 for (i = 0; i < PHY_RETRIES; i++) {
1150 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1151 goto ready;
1152 udelay(1);
1153 }
1154 return -EIO;
1155
1156 ready:
1157 xm_write16(hw, port, XM_PHY_DATA, val);
1158 for (i = 0; i < PHY_RETRIES; i++) {
1159 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1160 return 0;
1161 udelay(1);
1162 }
1163 return -ETIMEDOUT;
1164 }
1165
1166 static void genesis_init(struct skge_hw *hw)
1167 {
1168 /* set blink source counter */
1169 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1170 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1171
1172 /* configure mac arbiter */
1173 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1174
1175 /* configure mac arbiter timeout values */
1176 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1177 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1178 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1179 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1180
1181 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1182 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1183 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1184 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1185
1186 /* configure packet arbiter timeout */
1187 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1188 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1189 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1190 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1191 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1192 }
1193
1194 static void genesis_reset(struct skge_hw *hw, int port)
1195 {
1196 const u8 zero[8] = { 0 };
1197
1198 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1199
1200 /* reset the statistics module */
1201 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1202 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1203 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1204 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1205 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1206
1207 /* disable Broadcom PHY IRQ */
1208 if (hw->phy_type == SK_PHY_BCOM)
1209 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1210
1211 xm_outhash(hw, port, XM_HSM, zero);
1212 }
1213
1214
1215 /* Convert mode to MII values */
1216 static const u16 phy_pause_map[] = {
1217 [FLOW_MODE_NONE] = 0,
1218 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1219 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1220 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1221 };
1222
1223 /* special defines for FIBER (88E1011S only) */
1224 static const u16 fiber_pause_map[] = {
1225 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1226 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1227 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1228 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1229 };
1230
1231
1232 /* Check status of Broadcom phy link */
1233 static void bcom_check_link(struct skge_hw *hw, int port)
1234 {
1235 struct net_device *dev = hw->dev[port];
1236 struct skge_port *skge = netdev_priv(dev);
1237 u16 status;
1238
1239 /* read twice because of latch */
1240 xm_phy_read(hw, port, PHY_BCOM_STAT);
1241 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1242
1243 if ((status & PHY_ST_LSYNC) == 0) {
1244 xm_link_down(hw, port);
1245 return;
1246 }
1247
1248 if (skge->autoneg == AUTONEG_ENABLE) {
1249 u16 lpa, aux;
1250
1251 if (!(status & PHY_ST_AN_OVER))
1252 return;
1253
1254 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1255 if (lpa & PHY_B_AN_RF) {
1256 printk(KERN_NOTICE PFX "%s: remote fault\n",
1257 dev->name);
1258 return;
1259 }
1260
1261 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1262
1263 /* Check Duplex mismatch */
1264 switch (aux & PHY_B_AS_AN_RES_MSK) {
1265 case PHY_B_RES_1000FD:
1266 skge->duplex = DUPLEX_FULL;
1267 break;
1268 case PHY_B_RES_1000HD:
1269 skge->duplex = DUPLEX_HALF;
1270 break;
1271 default:
1272 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1273 dev->name);
1274 return;
1275 }
1276
1277 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1278 switch (aux & PHY_B_AS_PAUSE_MSK) {
1279 case PHY_B_AS_PAUSE_MSK:
1280 skge->flow_status = FLOW_STAT_SYMMETRIC;
1281 break;
1282 case PHY_B_AS_PRR:
1283 skge->flow_status = FLOW_STAT_REM_SEND;
1284 break;
1285 case PHY_B_AS_PRT:
1286 skge->flow_status = FLOW_STAT_LOC_SEND;
1287 break;
1288 default:
1289 skge->flow_status = FLOW_STAT_NONE;
1290 }
1291 skge->speed = SPEED_1000;
1292 }
1293
1294 if (!netif_carrier_ok(dev))
1295 genesis_link_up(skge);
1296 }
1297
1298 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1299 * Phy on for 100 or 10Mbit operation
1300 */
1301 static void bcom_phy_init(struct skge_port *skge)
1302 {
1303 struct skge_hw *hw = skge->hw;
1304 int port = skge->port;
1305 int i;
1306 u16 id1, r, ext, ctl;
1307
1308 /* magic workaround patterns for Broadcom */
1309 static const struct {
1310 u16 reg;
1311 u16 val;
1312 } A1hack[] = {
1313 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1314 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1315 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1316 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1317 }, C0hack[] = {
1318 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1319 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1320 };
1321
1322 /* read Id from external PHY (all have the same address) */
1323 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1324
1325 /* Optimize MDIO transfer by suppressing preamble. */
1326 r = xm_read16(hw, port, XM_MMU_CMD);
1327 r |= XM_MMU_NO_PRE;
1328 xm_write16(hw, port, XM_MMU_CMD,r);
1329
1330 switch (id1) {
1331 case PHY_BCOM_ID1_C0:
1332 /*
1333 * Workaround BCOM Errata for the C0 type.
1334 * Write magic patterns to reserved registers.
1335 */
1336 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1337 xm_phy_write(hw, port,
1338 C0hack[i].reg, C0hack[i].val);
1339
1340 break;
1341 case PHY_BCOM_ID1_A1:
1342 /*
1343 * Workaround BCOM Errata for the A1 type.
1344 * Write magic patterns to reserved registers.
1345 */
1346 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1347 xm_phy_write(hw, port,
1348 A1hack[i].reg, A1hack[i].val);
1349 break;
1350 }
1351
1352 /*
1353 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1354 * Disable Power Management after reset.
1355 */
1356 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1357 r |= PHY_B_AC_DIS_PM;
1358 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1359
1360 /* Dummy read */
1361 xm_read16(hw, port, XM_ISRC);
1362
1363 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1364 ctl = PHY_CT_SP1000; /* always 1000mbit */
1365
1366 if (skge->autoneg == AUTONEG_ENABLE) {
1367 /*
1368 * Workaround BCOM Errata #1 for the C5 type.
1369 * 1000Base-T Link Acquisition Failure in Slave Mode
1370 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1371 */
1372 u16 adv = PHY_B_1000C_RD;
1373 if (skge->advertising & ADVERTISED_1000baseT_Half)
1374 adv |= PHY_B_1000C_AHD;
1375 if (skge->advertising & ADVERTISED_1000baseT_Full)
1376 adv |= PHY_B_1000C_AFD;
1377 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1378
1379 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1380 } else {
1381 if (skge->duplex == DUPLEX_FULL)
1382 ctl |= PHY_CT_DUP_MD;
1383 /* Force to slave */
1384 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1385 }
1386
1387 /* Set autonegotiation pause parameters */
1388 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1389 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1390
1391 /* Handle Jumbo frames */
1392 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1393 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1394 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1395
1396 ext |= PHY_B_PEC_HIGH_LA;
1397
1398 }
1399
1400 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1401 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1402
1403 /* Use link status change interrupt */
1404 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1405 }
1406
1407 static void xm_phy_init(struct skge_port *skge)
1408 {
1409 struct skge_hw *hw = skge->hw;
1410 int port = skge->port;
1411 u16 ctrl = 0;
1412
1413 if (skge->autoneg == AUTONEG_ENABLE) {
1414 if (skge->advertising & ADVERTISED_1000baseT_Half)
1415 ctrl |= PHY_X_AN_HD;
1416 if (skge->advertising & ADVERTISED_1000baseT_Full)
1417 ctrl |= PHY_X_AN_FD;
1418
1419 ctrl |= fiber_pause_map[skge->flow_control];
1420
1421 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1422
1423 /* Restart Auto-negotiation */
1424 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1425 } else {
1426 /* Set DuplexMode in Config register */
1427 if (skge->duplex == DUPLEX_FULL)
1428 ctrl |= PHY_CT_DUP_MD;
1429 /*
1430 * Do NOT enable Auto-negotiation here. This would hold
1431 * the link down because no IDLEs are transmitted
1432 */
1433 }
1434
1435 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1436
1437 /* Poll PHY for status changes */
1438 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1439 }
1440
1441 static int xm_check_link(struct net_device *dev)
1442 {
1443 struct skge_port *skge = netdev_priv(dev);
1444 struct skge_hw *hw = skge->hw;
1445 int port = skge->port;
1446 u16 status;
1447
1448 /* read twice because of latch */
1449 xm_phy_read(hw, port, PHY_XMAC_STAT);
1450 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1451
1452 if ((status & PHY_ST_LSYNC) == 0) {
1453 xm_link_down(hw, port);
1454 return 0;
1455 }
1456
1457 if (skge->autoneg == AUTONEG_ENABLE) {
1458 u16 lpa, res;
1459
1460 if (!(status & PHY_ST_AN_OVER))
1461 return 0;
1462
1463 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1464 if (lpa & PHY_B_AN_RF) {
1465 printk(KERN_NOTICE PFX "%s: remote fault\n",
1466 dev->name);
1467 return 0;
1468 }
1469
1470 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1471
1472 /* Check Duplex mismatch */
1473 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1474 case PHY_X_RS_FD:
1475 skge->duplex = DUPLEX_FULL;
1476 break;
1477 case PHY_X_RS_HD:
1478 skge->duplex = DUPLEX_HALF;
1479 break;
1480 default:
1481 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1482 dev->name);
1483 return 0;
1484 }
1485
1486 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1487 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1488 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1489 (lpa & PHY_X_P_SYM_MD))
1490 skge->flow_status = FLOW_STAT_SYMMETRIC;
1491 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1492 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1493 /* Enable PAUSE receive, disable PAUSE transmit */
1494 skge->flow_status = FLOW_STAT_REM_SEND;
1495 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1496 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1497 /* Disable PAUSE receive, enable PAUSE transmit */
1498 skge->flow_status = FLOW_STAT_LOC_SEND;
1499 else
1500 skge->flow_status = FLOW_STAT_NONE;
1501
1502 skge->speed = SPEED_1000;
1503 }
1504
1505 if (!netif_carrier_ok(dev))
1506 genesis_link_up(skge);
1507 return 1;
1508 }
1509
1510 /* Poll to check for link coming up.
1511 *
1512 * Since internal PHY is wired to a level triggered pin, can't
1513 * get an interrupt when carrier is detected, need to poll for
1514 * link coming up.
1515 */
1516 static void xm_link_timer(unsigned long arg)
1517 {
1518 struct skge_port *skge = (struct skge_port *) arg;
1519 struct net_device *dev = skge->netdev;
1520 struct skge_hw *hw = skge->hw;
1521 int port = skge->port;
1522 int i;
1523 unsigned long flags;
1524
1525 if (!netif_running(dev))
1526 return;
1527
1528 spin_lock_irqsave(&hw->phy_lock, flags);
1529
1530 /*
1531 * Verify that the link by checking GPIO register three times.
1532 * This pin has the signal from the link_sync pin connected to it.
1533 */
1534 for (i = 0; i < 3; i++) {
1535 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1536 goto link_down;
1537 }
1538
1539 /* Re-enable interrupt to detect link down */
1540 if (xm_check_link(dev)) {
1541 u16 msk = xm_read16(hw, port, XM_IMSK);
1542 msk &= ~XM_IS_INP_ASS;
1543 xm_write16(hw, port, XM_IMSK, msk);
1544 xm_read16(hw, port, XM_ISRC);
1545 } else {
1546 link_down:
1547 mod_timer(&skge->link_timer,
1548 round_jiffies(jiffies + LINK_HZ));
1549 }
1550 spin_unlock_irqrestore(&hw->phy_lock, flags);
1551 }
1552
1553 static void genesis_mac_init(struct skge_hw *hw, int port)
1554 {
1555 struct net_device *dev = hw->dev[port];
1556 struct skge_port *skge = netdev_priv(dev);
1557 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1558 int i;
1559 u32 r;
1560 const u8 zero[6] = { 0 };
1561
1562 for (i = 0; i < 10; i++) {
1563 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1564 MFF_SET_MAC_RST);
1565 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1566 goto reset_ok;
1567 udelay(1);
1568 }
1569
1570 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1571
1572 reset_ok:
1573 /* Unreset the XMAC. */
1574 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1575
1576 /*
1577 * Perform additional initialization for external PHYs,
1578 * namely for the 1000baseTX cards that use the XMAC's
1579 * GMII mode.
1580 */
1581 if (hw->phy_type != SK_PHY_XMAC) {
1582 /* Take external Phy out of reset */
1583 r = skge_read32(hw, B2_GP_IO);
1584 if (port == 0)
1585 r |= GP_DIR_0|GP_IO_0;
1586 else
1587 r |= GP_DIR_2|GP_IO_2;
1588
1589 skge_write32(hw, B2_GP_IO, r);
1590
1591 /* Enable GMII interface */
1592 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1593 }
1594
1595
1596 switch(hw->phy_type) {
1597 case SK_PHY_XMAC:
1598 xm_phy_init(skge);
1599 break;
1600 case SK_PHY_BCOM:
1601 bcom_phy_init(skge);
1602 bcom_check_link(hw, port);
1603 }
1604
1605 /* Set Station Address */
1606 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1607
1608 /* We don't use match addresses so clear */
1609 for (i = 1; i < 16; i++)
1610 xm_outaddr(hw, port, XM_EXM(i), zero);
1611
1612 /* Clear MIB counters */
1613 xm_write16(hw, port, XM_STAT_CMD,
1614 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1615 /* Clear two times according to Errata #3 */
1616 xm_write16(hw, port, XM_STAT_CMD,
1617 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1618
1619 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1620 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1621
1622 /* We don't need the FCS appended to the packet. */
1623 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1624 if (jumbo)
1625 r |= XM_RX_BIG_PK_OK;
1626
1627 if (skge->duplex == DUPLEX_HALF) {
1628 /*
1629 * If in manual half duplex mode the other side might be in
1630 * full duplex mode, so ignore if a carrier extension is not seen
1631 * on frames received
1632 */
1633 r |= XM_RX_DIS_CEXT;
1634 }
1635 xm_write16(hw, port, XM_RX_CMD, r);
1636
1637
1638 /* We want short frames padded to 60 bytes. */
1639 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1640
1641 /*
1642 * Bump up the transmit threshold. This helps hold off transmit
1643 * underruns when we're blasting traffic from both ports at once.
1644 */
1645 xm_write16(hw, port, XM_TX_THR, 512);
1646
1647 /*
1648 * Enable the reception of all error frames. This is is
1649 * a necessary evil due to the design of the XMAC. The
1650 * XMAC's receive FIFO is only 8K in size, however jumbo
1651 * frames can be up to 9000 bytes in length. When bad
1652 * frame filtering is enabled, the XMAC's RX FIFO operates
1653 * in 'store and forward' mode. For this to work, the
1654 * entire frame has to fit into the FIFO, but that means
1655 * that jumbo frames larger than 8192 bytes will be
1656 * truncated. Disabling all bad frame filtering causes
1657 * the RX FIFO to operate in streaming mode, in which
1658 * case the XMAC will start transferring frames out of the
1659 * RX FIFO as soon as the FIFO threshold is reached.
1660 */
1661 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1662
1663
1664 /*
1665 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1666 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1667 * and 'Octets Rx OK Hi Cnt Ov'.
1668 */
1669 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1670
1671 /*
1672 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1673 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1674 * and 'Octets Tx OK Hi Cnt Ov'.
1675 */
1676 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1677
1678 /* Configure MAC arbiter */
1679 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1680
1681 /* configure timeout values */
1682 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1683 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1684 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1685 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1686
1687 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1688 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1689 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1690 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1691
1692 /* Configure Rx MAC FIFO */
1693 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1694 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1695 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1696
1697 /* Configure Tx MAC FIFO */
1698 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1699 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1700 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1701
1702 if (jumbo) {
1703 /* Enable frame flushing if jumbo frames used */
1704 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1705 } else {
1706 /* enable timeout timers if normal frames */
1707 skge_write16(hw, B3_PA_CTRL,
1708 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1709 }
1710 }
1711
1712 static void genesis_stop(struct skge_port *skge)
1713 {
1714 struct skge_hw *hw = skge->hw;
1715 int port = skge->port;
1716 u32 reg;
1717
1718 genesis_reset(hw, port);
1719
1720 /* Clear Tx packet arbiter timeout IRQ */
1721 skge_write16(hw, B3_PA_CTRL,
1722 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1723
1724 /*
1725 * If the transfer sticks at the MAC the STOP command will not
1726 * terminate if we don't flush the XMAC's transmit FIFO !
1727 */
1728 xm_write32(hw, port, XM_MODE,
1729 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1730
1731
1732 /* Reset the MAC */
1733 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1734
1735 /* For external PHYs there must be special handling */
1736 if (hw->phy_type != SK_PHY_XMAC) {
1737 reg = skge_read32(hw, B2_GP_IO);
1738 if (port == 0) {
1739 reg |= GP_DIR_0;
1740 reg &= ~GP_IO_0;
1741 } else {
1742 reg |= GP_DIR_2;
1743 reg &= ~GP_IO_2;
1744 }
1745 skge_write32(hw, B2_GP_IO, reg);
1746 skge_read32(hw, B2_GP_IO);
1747 }
1748
1749 xm_write16(hw, port, XM_MMU_CMD,
1750 xm_read16(hw, port, XM_MMU_CMD)
1751 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1752
1753 xm_read16(hw, port, XM_MMU_CMD);
1754 }
1755
1756
1757 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1758 {
1759 struct skge_hw *hw = skge->hw;
1760 int port = skge->port;
1761 int i;
1762 unsigned long timeout = jiffies + HZ;
1763
1764 xm_write16(hw, port,
1765 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1766
1767 /* wait for update to complete */
1768 while (xm_read16(hw, port, XM_STAT_CMD)
1769 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1770 if (time_after(jiffies, timeout))
1771 break;
1772 udelay(10);
1773 }
1774
1775 /* special case for 64 bit octet counter */
1776 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1777 | xm_read32(hw, port, XM_TXO_OK_LO);
1778 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1779 | xm_read32(hw, port, XM_RXO_OK_LO);
1780
1781 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1782 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1783 }
1784
1785 static void genesis_mac_intr(struct skge_hw *hw, int port)
1786 {
1787 struct net_device *dev = hw->dev[port];
1788 struct skge_port *skge = netdev_priv(dev);
1789 u16 status = xm_read16(hw, port, XM_ISRC);
1790
1791 if (netif_msg_intr(skge))
1792 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1793 dev->name, status);
1794
1795 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1796 xm_link_down(hw, port);
1797 mod_timer(&skge->link_timer, jiffies + 1);
1798 }
1799
1800 if (status & XM_IS_TXF_UR) {
1801 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1802 ++dev->stats.tx_fifo_errors;
1803 }
1804 }
1805
1806 static void genesis_link_up(struct skge_port *skge)
1807 {
1808 struct skge_hw *hw = skge->hw;
1809 int port = skge->port;
1810 u16 cmd, msk;
1811 u32 mode;
1812
1813 cmd = xm_read16(hw, port, XM_MMU_CMD);
1814
1815 /*
1816 * enabling pause frame reception is required for 1000BT
1817 * because the XMAC is not reset if the link is going down
1818 */
1819 if (skge->flow_status == FLOW_STAT_NONE ||
1820 skge->flow_status == FLOW_STAT_LOC_SEND)
1821 /* Disable Pause Frame Reception */
1822 cmd |= XM_MMU_IGN_PF;
1823 else
1824 /* Enable Pause Frame Reception */
1825 cmd &= ~XM_MMU_IGN_PF;
1826
1827 xm_write16(hw, port, XM_MMU_CMD, cmd);
1828
1829 mode = xm_read32(hw, port, XM_MODE);
1830 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1831 skge->flow_status == FLOW_STAT_LOC_SEND) {
1832 /*
1833 * Configure Pause Frame Generation
1834 * Use internal and external Pause Frame Generation.
1835 * Sending pause frames is edge triggered.
1836 * Send a Pause frame with the maximum pause time if
1837 * internal oder external FIFO full condition occurs.
1838 * Send a zero pause time frame to re-start transmission.
1839 */
1840 /* XM_PAUSE_DA = '010000C28001' (default) */
1841 /* XM_MAC_PTIME = 0xffff (maximum) */
1842 /* remember this value is defined in big endian (!) */
1843 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1844
1845 mode |= XM_PAUSE_MODE;
1846 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1847 } else {
1848 /*
1849 * disable pause frame generation is required for 1000BT
1850 * because the XMAC is not reset if the link is going down
1851 */
1852 /* Disable Pause Mode in Mode Register */
1853 mode &= ~XM_PAUSE_MODE;
1854
1855 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1856 }
1857
1858 xm_write32(hw, port, XM_MODE, mode);
1859
1860 /* Turn on detection of Tx underrun */
1861 msk = xm_read16(hw, port, XM_IMSK);
1862 msk &= ~XM_IS_TXF_UR;
1863 xm_write16(hw, port, XM_IMSK, msk);
1864
1865 xm_read16(hw, port, XM_ISRC);
1866
1867 /* get MMU Command Reg. */
1868 cmd = xm_read16(hw, port, XM_MMU_CMD);
1869 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1870 cmd |= XM_MMU_GMII_FD;
1871
1872 /*
1873 * Workaround BCOM Errata (#10523) for all BCom Phys
1874 * Enable Power Management after link up
1875 */
1876 if (hw->phy_type == SK_PHY_BCOM) {
1877 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1878 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1879 & ~PHY_B_AC_DIS_PM);
1880 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1881 }
1882
1883 /* enable Rx/Tx */
1884 xm_write16(hw, port, XM_MMU_CMD,
1885 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1886 skge_link_up(skge);
1887 }
1888
1889
1890 static inline void bcom_phy_intr(struct skge_port *skge)
1891 {
1892 struct skge_hw *hw = skge->hw;
1893 int port = skge->port;
1894 u16 isrc;
1895
1896 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1897 if (netif_msg_intr(skge))
1898 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1899 skge->netdev->name, isrc);
1900
1901 if (isrc & PHY_B_IS_PSE)
1902 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1903 hw->dev[port]->name);
1904
1905 /* Workaround BCom Errata:
1906 * enable and disable loopback mode if "NO HCD" occurs.
1907 */
1908 if (isrc & PHY_B_IS_NO_HDCL) {
1909 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1910 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1911 ctrl | PHY_CT_LOOP);
1912 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1913 ctrl & ~PHY_CT_LOOP);
1914 }
1915
1916 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1917 bcom_check_link(hw, port);
1918
1919 }
1920
1921 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1922 {
1923 int i;
1924
1925 gma_write16(hw, port, GM_SMI_DATA, val);
1926 gma_write16(hw, port, GM_SMI_CTRL,
1927 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1928 for (i = 0; i < PHY_RETRIES; i++) {
1929 udelay(1);
1930
1931 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1932 return 0;
1933 }
1934
1935 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1936 hw->dev[port]->name);
1937 return -EIO;
1938 }
1939
1940 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1941 {
1942 int i;
1943
1944 gma_write16(hw, port, GM_SMI_CTRL,
1945 GM_SMI_CT_PHY_AD(hw->phy_addr)
1946 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1947
1948 for (i = 0; i < PHY_RETRIES; i++) {
1949 udelay(1);
1950 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1951 goto ready;
1952 }
1953
1954 return -ETIMEDOUT;
1955 ready:
1956 *val = gma_read16(hw, port, GM_SMI_DATA);
1957 return 0;
1958 }
1959
1960 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1961 {
1962 u16 v = 0;
1963 if (__gm_phy_read(hw, port, reg, &v))
1964 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1965 hw->dev[port]->name);
1966 return v;
1967 }
1968
1969 /* Marvell Phy Initialization */
1970 static void yukon_init(struct skge_hw *hw, int port)
1971 {
1972 struct skge_port *skge = netdev_priv(hw->dev[port]);
1973 u16 ctrl, ct1000, adv;
1974
1975 if (skge->autoneg == AUTONEG_ENABLE) {
1976 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1977
1978 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1979 PHY_M_EC_MAC_S_MSK);
1980 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1981
1982 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1983
1984 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1985 }
1986
1987 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1988 if (skge->autoneg == AUTONEG_DISABLE)
1989 ctrl &= ~PHY_CT_ANE;
1990
1991 ctrl |= PHY_CT_RESET;
1992 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1993
1994 ctrl = 0;
1995 ct1000 = 0;
1996 adv = PHY_AN_CSMA;
1997
1998 if (skge->autoneg == AUTONEG_ENABLE) {
1999 if (hw->copper) {
2000 if (skge->advertising & ADVERTISED_1000baseT_Full)
2001 ct1000 |= PHY_M_1000C_AFD;
2002 if (skge->advertising & ADVERTISED_1000baseT_Half)
2003 ct1000 |= PHY_M_1000C_AHD;
2004 if (skge->advertising & ADVERTISED_100baseT_Full)
2005 adv |= PHY_M_AN_100_FD;
2006 if (skge->advertising & ADVERTISED_100baseT_Half)
2007 adv |= PHY_M_AN_100_HD;
2008 if (skge->advertising & ADVERTISED_10baseT_Full)
2009 adv |= PHY_M_AN_10_FD;
2010 if (skge->advertising & ADVERTISED_10baseT_Half)
2011 adv |= PHY_M_AN_10_HD;
2012
2013 /* Set Flow-control capabilities */
2014 adv |= phy_pause_map[skge->flow_control];
2015 } else {
2016 if (skge->advertising & ADVERTISED_1000baseT_Full)
2017 adv |= PHY_M_AN_1000X_AFD;
2018 if (skge->advertising & ADVERTISED_1000baseT_Half)
2019 adv |= PHY_M_AN_1000X_AHD;
2020
2021 adv |= fiber_pause_map[skge->flow_control];
2022 }
2023
2024 /* Restart Auto-negotiation */
2025 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2026 } else {
2027 /* forced speed/duplex settings */
2028 ct1000 = PHY_M_1000C_MSE;
2029
2030 if (skge->duplex == DUPLEX_FULL)
2031 ctrl |= PHY_CT_DUP_MD;
2032
2033 switch (skge->speed) {
2034 case SPEED_1000:
2035 ctrl |= PHY_CT_SP1000;
2036 break;
2037 case SPEED_100:
2038 ctrl |= PHY_CT_SP100;
2039 break;
2040 }
2041
2042 ctrl |= PHY_CT_RESET;
2043 }
2044
2045 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2046
2047 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2048 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2049
2050 /* Enable phy interrupt on autonegotiation complete (or link up) */
2051 if (skge->autoneg == AUTONEG_ENABLE)
2052 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2053 else
2054 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2055 }
2056
2057 static void yukon_reset(struct skge_hw *hw, int port)
2058 {
2059 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2060 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2061 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2062 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2063 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2064
2065 gma_write16(hw, port, GM_RX_CTRL,
2066 gma_read16(hw, port, GM_RX_CTRL)
2067 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2068 }
2069
2070 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2071 static int is_yukon_lite_a0(struct skge_hw *hw)
2072 {
2073 u32 reg;
2074 int ret;
2075
2076 if (hw->chip_id != CHIP_ID_YUKON)
2077 return 0;
2078
2079 reg = skge_read32(hw, B2_FAR);
2080 skge_write8(hw, B2_FAR + 3, 0xff);
2081 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2082 skge_write32(hw, B2_FAR, reg);
2083 return ret;
2084 }
2085
2086 static void yukon_mac_init(struct skge_hw *hw, int port)
2087 {
2088 struct skge_port *skge = netdev_priv(hw->dev[port]);
2089 int i;
2090 u32 reg;
2091 const u8 *addr = hw->dev[port]->dev_addr;
2092
2093 /* WA code for COMA mode -- set PHY reset */
2094 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2095 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2096 reg = skge_read32(hw, B2_GP_IO);
2097 reg |= GP_DIR_9 | GP_IO_9;
2098 skge_write32(hw, B2_GP_IO, reg);
2099 }
2100
2101 /* hard reset */
2102 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2103 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2104
2105 /* WA code for COMA mode -- clear PHY reset */
2106 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2107 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2108 reg = skge_read32(hw, B2_GP_IO);
2109 reg |= GP_DIR_9;
2110 reg &= ~GP_IO_9;
2111 skge_write32(hw, B2_GP_IO, reg);
2112 }
2113
2114 /* Set hardware config mode */
2115 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2116 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2117 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2118
2119 /* Clear GMC reset */
2120 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2121 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2122 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2123
2124 if (skge->autoneg == AUTONEG_DISABLE) {
2125 reg = GM_GPCR_AU_ALL_DIS;
2126 gma_write16(hw, port, GM_GP_CTRL,
2127 gma_read16(hw, port, GM_GP_CTRL) | reg);
2128
2129 switch (skge->speed) {
2130 case SPEED_1000:
2131 reg &= ~GM_GPCR_SPEED_100;
2132 reg |= GM_GPCR_SPEED_1000;
2133 break;
2134 case SPEED_100:
2135 reg &= ~GM_GPCR_SPEED_1000;
2136 reg |= GM_GPCR_SPEED_100;
2137 break;
2138 case SPEED_10:
2139 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2140 break;
2141 }
2142
2143 if (skge->duplex == DUPLEX_FULL)
2144 reg |= GM_GPCR_DUP_FULL;
2145 } else
2146 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2147
2148 switch (skge->flow_control) {
2149 case FLOW_MODE_NONE:
2150 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2151 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2152 break;
2153 case FLOW_MODE_LOC_SEND:
2154 /* disable Rx flow-control */
2155 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2156 break;
2157 case FLOW_MODE_SYMMETRIC:
2158 case FLOW_MODE_SYM_OR_REM:
2159 /* enable Tx & Rx flow-control */
2160 break;
2161 }
2162
2163 gma_write16(hw, port, GM_GP_CTRL, reg);
2164 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2165
2166 yukon_init(hw, port);
2167
2168 /* MIB clear */
2169 reg = gma_read16(hw, port, GM_PHY_ADDR);
2170 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2171
2172 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2173 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2174 gma_write16(hw, port, GM_PHY_ADDR, reg);
2175
2176 /* transmit control */
2177 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2178
2179 /* receive control reg: unicast + multicast + no FCS */
2180 gma_write16(hw, port, GM_RX_CTRL,
2181 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2182
2183 /* transmit flow control */
2184 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2185
2186 /* transmit parameter */
2187 gma_write16(hw, port, GM_TX_PARAM,
2188 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2189 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2190 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2191
2192 /* serial mode register */
2193 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2194 if (hw->dev[port]->mtu > 1500)
2195 reg |= GM_SMOD_JUMBO_ENA;
2196
2197 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2198
2199 /* physical address: used for pause frames */
2200 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2201 /* virtual address for data */
2202 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2203
2204 /* enable interrupt mask for counter overflows */
2205 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2206 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2207 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2208
2209 /* Initialize Mac Fifo */
2210
2211 /* Configure Rx MAC FIFO */
2212 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2213 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2214
2215 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2216 if (is_yukon_lite_a0(hw))
2217 reg &= ~GMF_RX_F_FL_ON;
2218
2219 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2220 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2221 /*
2222 * because Pause Packet Truncation in GMAC is not working
2223 * we have to increase the Flush Threshold to 64 bytes
2224 * in order to flush pause packets in Rx FIFO on Yukon-1
2225 */
2226 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2227
2228 /* Configure Tx MAC FIFO */
2229 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2230 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2231 }
2232
2233 /* Go into power down mode */
2234 static void yukon_suspend(struct skge_hw *hw, int port)
2235 {
2236 u16 ctrl;
2237
2238 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2239 ctrl |= PHY_M_PC_POL_R_DIS;
2240 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2241
2242 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2243 ctrl |= PHY_CT_RESET;
2244 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2245
2246 /* switch IEEE compatible power down mode on */
2247 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2248 ctrl |= PHY_CT_PDOWN;
2249 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2250 }
2251
2252 static void yukon_stop(struct skge_port *skge)
2253 {
2254 struct skge_hw *hw = skge->hw;
2255 int port = skge->port;
2256
2257 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2258 yukon_reset(hw, port);
2259
2260 gma_write16(hw, port, GM_GP_CTRL,
2261 gma_read16(hw, port, GM_GP_CTRL)
2262 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2263 gma_read16(hw, port, GM_GP_CTRL);
2264
2265 yukon_suspend(hw, port);
2266
2267 /* set GPHY Control reset */
2268 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2269 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2270 }
2271
2272 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2273 {
2274 struct skge_hw *hw = skge->hw;
2275 int port = skge->port;
2276 int i;
2277
2278 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2279 | gma_read32(hw, port, GM_TXO_OK_LO);
2280 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2281 | gma_read32(hw, port, GM_RXO_OK_LO);
2282
2283 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2284 data[i] = gma_read32(hw, port,
2285 skge_stats[i].gma_offset);
2286 }
2287
2288 static void yukon_mac_intr(struct skge_hw *hw, int port)
2289 {
2290 struct net_device *dev = hw->dev[port];
2291 struct skge_port *skge = netdev_priv(dev);
2292 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2293
2294 if (netif_msg_intr(skge))
2295 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2296 dev->name, status);
2297
2298 if (status & GM_IS_RX_FF_OR) {
2299 ++dev->stats.rx_fifo_errors;
2300 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2301 }
2302
2303 if (status & GM_IS_TX_FF_UR) {
2304 ++dev->stats.tx_fifo_errors;
2305 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2306 }
2307
2308 }
2309
2310 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2311 {
2312 switch (aux & PHY_M_PS_SPEED_MSK) {
2313 case PHY_M_PS_SPEED_1000:
2314 return SPEED_1000;
2315 case PHY_M_PS_SPEED_100:
2316 return SPEED_100;
2317 default:
2318 return SPEED_10;
2319 }
2320 }
2321
2322 static void yukon_link_up(struct skge_port *skge)
2323 {
2324 struct skge_hw *hw = skge->hw;
2325 int port = skge->port;
2326 u16 reg;
2327
2328 /* Enable Transmit FIFO Underrun */
2329 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2330
2331 reg = gma_read16(hw, port, GM_GP_CTRL);
2332 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2333 reg |= GM_GPCR_DUP_FULL;
2334
2335 /* enable Rx/Tx */
2336 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2337 gma_write16(hw, port, GM_GP_CTRL, reg);
2338
2339 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2340 skge_link_up(skge);
2341 }
2342
2343 static void yukon_link_down(struct skge_port *skge)
2344 {
2345 struct skge_hw *hw = skge->hw;
2346 int port = skge->port;
2347 u16 ctrl;
2348
2349 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2350 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2351 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2352
2353 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2354 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2355 ctrl |= PHY_M_AN_ASP;
2356 /* restore Asymmetric Pause bit */
2357 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2358 }
2359
2360 skge_link_down(skge);
2361
2362 yukon_init(hw, port);
2363 }
2364
2365 static void yukon_phy_intr(struct skge_port *skge)
2366 {
2367 struct skge_hw *hw = skge->hw;
2368 int port = skge->port;
2369 const char *reason = NULL;
2370 u16 istatus, phystat;
2371
2372 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2373 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2374
2375 if (netif_msg_intr(skge))
2376 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2377 skge->netdev->name, istatus, phystat);
2378
2379 if (istatus & PHY_M_IS_AN_COMPL) {
2380 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2381 & PHY_M_AN_RF) {
2382 reason = "remote fault";
2383 goto failed;
2384 }
2385
2386 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2387 reason = "master/slave fault";
2388 goto failed;
2389 }
2390
2391 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2392 reason = "speed/duplex";
2393 goto failed;
2394 }
2395
2396 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2397 ? DUPLEX_FULL : DUPLEX_HALF;
2398 skge->speed = yukon_speed(hw, phystat);
2399
2400 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2401 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2402 case PHY_M_PS_PAUSE_MSK:
2403 skge->flow_status = FLOW_STAT_SYMMETRIC;
2404 break;
2405 case PHY_M_PS_RX_P_EN:
2406 skge->flow_status = FLOW_STAT_REM_SEND;
2407 break;
2408 case PHY_M_PS_TX_P_EN:
2409 skge->flow_status = FLOW_STAT_LOC_SEND;
2410 break;
2411 default:
2412 skge->flow_status = FLOW_STAT_NONE;
2413 }
2414
2415 if (skge->flow_status == FLOW_STAT_NONE ||
2416 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2417 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2418 else
2419 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2420 yukon_link_up(skge);
2421 return;
2422 }
2423
2424 if (istatus & PHY_M_IS_LSP_CHANGE)
2425 skge->speed = yukon_speed(hw, phystat);
2426
2427 if (istatus & PHY_M_IS_DUP_CHANGE)
2428 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2429 if (istatus & PHY_M_IS_LST_CHANGE) {
2430 if (phystat & PHY_M_PS_LINK_UP)
2431 yukon_link_up(skge);
2432 else
2433 yukon_link_down(skge);
2434 }
2435 return;
2436 failed:
2437 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2438 skge->netdev->name, reason);
2439
2440 /* XXX restart autonegotiation? */
2441 }
2442
2443 static void skge_phy_reset(struct skge_port *skge)
2444 {
2445 struct skge_hw *hw = skge->hw;
2446 int port = skge->port;
2447 struct net_device *dev = hw->dev[port];
2448
2449 netif_stop_queue(skge->netdev);
2450 netif_carrier_off(skge->netdev);
2451
2452 spin_lock_bh(&hw->phy_lock);
2453 if (hw->chip_id == CHIP_ID_GENESIS) {
2454 genesis_reset(hw, port);
2455 genesis_mac_init(hw, port);
2456 } else {
2457 yukon_reset(hw, port);
2458 yukon_init(hw, port);
2459 }
2460 spin_unlock_bh(&hw->phy_lock);
2461
2462 dev->set_multicast_list(dev);
2463 }
2464
2465 /* Basic MII support */
2466 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2467 {
2468 struct mii_ioctl_data *data = if_mii(ifr);
2469 struct skge_port *skge = netdev_priv(dev);
2470 struct skge_hw *hw = skge->hw;
2471 int err = -EOPNOTSUPP;
2472
2473 if (!netif_running(dev))
2474 return -ENODEV; /* Phy still in reset */
2475
2476 switch(cmd) {
2477 case SIOCGMIIPHY:
2478 data->phy_id = hw->phy_addr;
2479
2480 /* fallthru */
2481 case SIOCGMIIREG: {
2482 u16 val = 0;
2483 spin_lock_bh(&hw->phy_lock);
2484 if (hw->chip_id == CHIP_ID_GENESIS)
2485 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2486 else
2487 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2488 spin_unlock_bh(&hw->phy_lock);
2489 data->val_out = val;
2490 break;
2491 }
2492
2493 case SIOCSMIIREG:
2494 if (!capable(CAP_NET_ADMIN))
2495 return -EPERM;
2496
2497 spin_lock_bh(&hw->phy_lock);
2498 if (hw->chip_id == CHIP_ID_GENESIS)
2499 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2500 data->val_in);
2501 else
2502 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2503 data->val_in);
2504 spin_unlock_bh(&hw->phy_lock);
2505 break;
2506 }
2507 return err;
2508 }
2509
2510 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2511 {
2512 u32 end;
2513
2514 start /= 8;
2515 len /= 8;
2516 end = start + len - 1;
2517
2518 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2519 skge_write32(hw, RB_ADDR(q, RB_START), start);
2520 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2521 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2522 skge_write32(hw, RB_ADDR(q, RB_END), end);
2523
2524 if (q == Q_R1 || q == Q_R2) {
2525 /* Set thresholds on receive queue's */
2526 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2527 start + (2*len)/3);
2528 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2529 start + (len/3));
2530 } else {
2531 /* Enable store & forward on Tx queue's because
2532 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2533 */
2534 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2535 }
2536
2537 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2538 }
2539
2540 /* Setup Bus Memory Interface */
2541 static void skge_qset(struct skge_port *skge, u16 q,
2542 const struct skge_element *e)
2543 {
2544 struct skge_hw *hw = skge->hw;
2545 u32 watermark = 0x600;
2546 u64 base = skge->dma + (e->desc - skge->mem);
2547
2548 /* optimization to reduce window on 32bit/33mhz */
2549 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2550 watermark /= 2;
2551
2552 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2553 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2554 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2555 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2556 }
2557
2558 static int skge_up(struct net_device *dev)
2559 {
2560 struct skge_port *skge = netdev_priv(dev);
2561 struct skge_hw *hw = skge->hw;
2562 int port = skge->port;
2563 u32 chunk, ram_addr;
2564 size_t rx_size, tx_size;
2565 int err;
2566
2567 if (!is_valid_ether_addr(dev->dev_addr))
2568 return -EINVAL;
2569
2570 if (netif_msg_ifup(skge))
2571 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2572
2573 if (dev->mtu > RX_BUF_SIZE)
2574 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2575 else
2576 skge->rx_buf_size = RX_BUF_SIZE;
2577
2578
2579 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2580 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2581 skge->mem_size = tx_size + rx_size;
2582 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2583 if (!skge->mem)
2584 return -ENOMEM;
2585
2586 BUG_ON(skge->dma & 7);
2587
2588 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2589 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2590 err = -EINVAL;
2591 goto free_pci_mem;
2592 }
2593
2594 memset(skge->mem, 0, skge->mem_size);
2595
2596 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2597 if (err)
2598 goto free_pci_mem;
2599
2600 err = skge_rx_fill(dev);
2601 if (err)
2602 goto free_rx_ring;
2603
2604 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2605 skge->dma + rx_size);
2606 if (err)
2607 goto free_rx_ring;
2608
2609 /* Initialize MAC */
2610 spin_lock_bh(&hw->phy_lock);
2611 if (hw->chip_id == CHIP_ID_GENESIS)
2612 genesis_mac_init(hw, port);
2613 else
2614 yukon_mac_init(hw, port);
2615 spin_unlock_bh(&hw->phy_lock);
2616
2617 /* Configure RAMbuffers - equally between ports and tx/rx */
2618 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2619 ram_addr = hw->ram_offset + 2 * chunk * port;
2620
2621 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2622 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2623
2624 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2625 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2626 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2627
2628 /* Start receiver BMU */
2629 wmb();
2630 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2631 skge_led(skge, LED_MODE_ON);
2632
2633 spin_lock_irq(&hw->hw_lock);
2634 hw->intr_mask |= portmask[port];
2635 skge_write32(hw, B0_IMSK, hw->intr_mask);
2636 spin_unlock_irq(&hw->hw_lock);
2637
2638 napi_enable(&skge->napi);
2639 return 0;
2640
2641 free_rx_ring:
2642 skge_rx_clean(skge);
2643 kfree(skge->rx_ring.start);
2644 free_pci_mem:
2645 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2646 skge->mem = NULL;
2647
2648 return err;
2649 }
2650
2651 /* stop receiver */
2652 static void skge_rx_stop(struct skge_hw *hw, int port)
2653 {
2654 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2655 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2656 RB_RST_SET|RB_DIS_OP_MD);
2657 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2658 }
2659
2660 static int skge_down(struct net_device *dev)
2661 {
2662 struct skge_port *skge = netdev_priv(dev);
2663 struct skge_hw *hw = skge->hw;
2664 int port = skge->port;
2665
2666 if (skge->mem == NULL)
2667 return 0;
2668
2669 if (netif_msg_ifdown(skge))
2670 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2671
2672 netif_stop_queue(dev);
2673
2674 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2675 del_timer_sync(&skge->link_timer);
2676
2677 napi_disable(&skge->napi);
2678 netif_carrier_off(dev);
2679
2680 spin_lock_irq(&hw->hw_lock);
2681 hw->intr_mask &= ~portmask[port];
2682 skge_write32(hw, B0_IMSK, hw->intr_mask);
2683 spin_unlock_irq(&hw->hw_lock);
2684
2685 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2686 if (hw->chip_id == CHIP_ID_GENESIS)
2687 genesis_stop(skge);
2688 else
2689 yukon_stop(skge);
2690
2691 /* Stop transmitter */
2692 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2693 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2694 RB_RST_SET|RB_DIS_OP_MD);
2695
2696
2697 /* Disable Force Sync bit and Enable Alloc bit */
2698 skge_write8(hw, SK_REG(port, TXA_CTRL),
2699 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2700
2701 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2702 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2703 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2704
2705 /* Reset PCI FIFO */
2706 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2707 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2708
2709 /* Reset the RAM Buffer async Tx queue */
2710 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2711
2712 skge_rx_stop(hw, port);
2713
2714 if (hw->chip_id == CHIP_ID_GENESIS) {
2715 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2716 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2717 } else {
2718 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2719 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2720 }
2721
2722 skge_led(skge, LED_MODE_OFF);
2723
2724 netif_tx_lock_bh(dev);
2725 skge_tx_clean(dev);
2726 netif_tx_unlock_bh(dev);
2727
2728 skge_rx_clean(skge);
2729
2730 kfree(skge->rx_ring.start);
2731 kfree(skge->tx_ring.start);
2732 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2733 skge->mem = NULL;
2734 return 0;
2735 }
2736
2737 static inline int skge_avail(const struct skge_ring *ring)
2738 {
2739 smp_mb();
2740 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2741 + (ring->to_clean - ring->to_use) - 1;
2742 }
2743
2744 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2745 {
2746 struct skge_port *skge = netdev_priv(dev);
2747 struct skge_hw *hw = skge->hw;
2748 struct skge_element *e;
2749 struct skge_tx_desc *td;
2750 int i;
2751 u32 control, len;
2752 u64 map;
2753
2754 if (skb_padto(skb, ETH_ZLEN))
2755 return NETDEV_TX_OK;
2756
2757 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2758 return NETDEV_TX_BUSY;
2759
2760 e = skge->tx_ring.to_use;
2761 td = e->desc;
2762 BUG_ON(td->control & BMU_OWN);
2763 e->skb = skb;
2764 len = skb_headlen(skb);
2765 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2766 pci_unmap_addr_set(e, mapaddr, map);
2767 pci_unmap_len_set(e, maplen, len);
2768
2769 td->dma_lo = map;
2770 td->dma_hi = map >> 32;
2771
2772 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2773 const int offset = skb_transport_offset(skb);
2774
2775 /* This seems backwards, but it is what the sk98lin
2776 * does. Looks like hardware is wrong?
2777 */
2778 if (ipip_hdr(skb)->protocol == IPPROTO_UDP
2779 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2780 control = BMU_TCP_CHECK;
2781 else
2782 control = BMU_UDP_CHECK;
2783
2784 td->csum_offs = 0;
2785 td->csum_start = offset;
2786 td->csum_write = offset + skb->csum_offset;
2787 } else
2788 control = BMU_CHECK;
2789
2790 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2791 control |= BMU_EOF| BMU_IRQ_EOF;
2792 else {
2793 struct skge_tx_desc *tf = td;
2794
2795 control |= BMU_STFWD;
2796 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2797 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2798
2799 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2800 frag->size, PCI_DMA_TODEVICE);
2801
2802 e = e->next;
2803 e->skb = skb;
2804 tf = e->desc;
2805 BUG_ON(tf->control & BMU_OWN);
2806
2807 tf->dma_lo = map;
2808 tf->dma_hi = (u64) map >> 32;
2809 pci_unmap_addr_set(e, mapaddr, map);
2810 pci_unmap_len_set(e, maplen, frag->size);
2811
2812 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2813 }
2814 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2815 }
2816 /* Make sure all the descriptors written */
2817 wmb();
2818 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2819 wmb();
2820
2821 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2822
2823 if (unlikely(netif_msg_tx_queued(skge)))
2824 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2825 dev->name, e - skge->tx_ring.start, skb->len);
2826
2827 skge->tx_ring.to_use = e->next;
2828 smp_wmb();
2829
2830 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2831 pr_debug("%s: transmit queue full\n", dev->name);
2832 netif_stop_queue(dev);
2833 }
2834
2835 dev->trans_start = jiffies;
2836
2837 return NETDEV_TX_OK;
2838 }
2839
2840
2841 /* Free resources associated with this reing element */
2842 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2843 u32 control)
2844 {
2845 struct pci_dev *pdev = skge->hw->pdev;
2846
2847 /* skb header vs. fragment */
2848 if (control & BMU_STF)
2849 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2850 pci_unmap_len(e, maplen),
2851 PCI_DMA_TODEVICE);
2852 else
2853 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2854 pci_unmap_len(e, maplen),
2855 PCI_DMA_TODEVICE);
2856
2857 if (control & BMU_EOF) {
2858 if (unlikely(netif_msg_tx_done(skge)))
2859 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2860 skge->netdev->name, e - skge->tx_ring.start);
2861
2862 dev_kfree_skb(e->skb);
2863 }
2864 }
2865
2866 /* Free all buffers in transmit ring */
2867 static void skge_tx_clean(struct net_device *dev)
2868 {
2869 struct skge_port *skge = netdev_priv(dev);
2870 struct skge_element *e;
2871
2872 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2873 struct skge_tx_desc *td = e->desc;
2874 skge_tx_free(skge, e, td->control);
2875 td->control = 0;
2876 }
2877
2878 skge->tx_ring.to_clean = e;
2879 netif_wake_queue(dev);
2880 }
2881
2882 static void skge_tx_timeout(struct net_device *dev)
2883 {
2884 struct skge_port *skge = netdev_priv(dev);
2885
2886 if (netif_msg_timer(skge))
2887 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2888
2889 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2890 skge_tx_clean(dev);
2891 }
2892
2893 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2894 {
2895 struct skge_port *skge = netdev_priv(dev);
2896 struct skge_hw *hw = skge->hw;
2897 int port = skge->port;
2898 int err;
2899 u16 ctl, reg;
2900
2901 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2902 return -EINVAL;
2903
2904 if (!netif_running(dev)) {
2905 dev->mtu = new_mtu;
2906 return 0;
2907 }
2908
2909 skge_write32(hw, B0_IMSK, 0);
2910 dev->trans_start = jiffies; /* prevent tx timeout */
2911 netif_stop_queue(dev);
2912 napi_disable(&skge->napi);
2913
2914 ctl = gma_read16(hw, port, GM_GP_CTRL);
2915 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2916
2917 skge_rx_clean(skge);
2918 skge_rx_stop(hw, port);
2919
2920 dev->mtu = new_mtu;
2921
2922 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2923 if (new_mtu > 1500)
2924 reg |= GM_SMOD_JUMBO_ENA;
2925 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2926
2927 skge_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2928
2929 err = skge_rx_fill(dev);
2930 wmb();
2931 if (!err)
2932 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2933 skge_write32(hw, B0_IMSK, hw->intr_mask);
2934
2935 if (err)
2936 dev_close(dev);
2937 else {
2938 gma_write16(hw, port, GM_GP_CTRL, ctl);
2939
2940 napi_enable(&skge->napi);
2941 netif_wake_queue(dev);
2942 }
2943
2944 return err;
2945 }
2946
2947 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2948
2949 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2950 {
2951 u32 crc, bit;
2952
2953 crc = ether_crc_le(ETH_ALEN, addr);
2954 bit = ~crc & 0x3f;
2955 filter[bit/8] |= 1 << (bit%8);
2956 }
2957
2958 static void genesis_set_multicast(struct net_device *dev)
2959 {
2960 struct skge_port *skge = netdev_priv(dev);
2961 struct skge_hw *hw = skge->hw;
2962 int port = skge->port;
2963 int i, count = dev->mc_count;
2964 struct dev_mc_list *list = dev->mc_list;
2965 u32 mode;
2966 u8 filter[8];
2967
2968 mode = xm_read32(hw, port, XM_MODE);
2969 mode |= XM_MD_ENA_HASH;
2970 if (dev->flags & IFF_PROMISC)
2971 mode |= XM_MD_ENA_PROM;
2972 else
2973 mode &= ~XM_MD_ENA_PROM;
2974
2975 if (dev->flags & IFF_ALLMULTI)
2976 memset(filter, 0xff, sizeof(filter));
2977 else {
2978 memset(filter, 0, sizeof(filter));
2979
2980 if (skge->flow_status == FLOW_STAT_REM_SEND
2981 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2982 genesis_add_filter(filter, pause_mc_addr);
2983
2984 for (i = 0; list && i < count; i++, list = list->next)
2985 genesis_add_filter(filter, list->dmi_addr);
2986 }
2987
2988 xm_write32(hw, port, XM_MODE, mode);
2989 xm_outhash(hw, port, XM_HSM, filter);
2990 }
2991
2992 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2993 {
2994 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2995 filter[bit/8] |= 1 << (bit%8);
2996 }
2997
2998 static void yukon_set_multicast(struct net_device *dev)
2999 {
3000 struct skge_port *skge = netdev_priv(dev);
3001 struct skge_hw *hw = skge->hw;
3002 int port = skge->port;
3003 struct dev_mc_list *list = dev->mc_list;
3004 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
3005 || skge->flow_status == FLOW_STAT_SYMMETRIC);
3006 u16 reg;
3007 u8 filter[8];
3008
3009 memset(filter, 0, sizeof(filter));
3010
3011 reg = gma_read16(hw, port, GM_RX_CTRL);
3012 reg |= GM_RXCR_UCF_ENA;
3013
3014 if (dev->flags & IFF_PROMISC) /* promiscuous */
3015 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3016 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
3017 memset(filter, 0xff, sizeof(filter));
3018 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
3019 reg &= ~GM_RXCR_MCF_ENA;
3020 else {
3021 int i;
3022 reg |= GM_RXCR_MCF_ENA;
3023
3024 if (rx_pause)
3025 yukon_add_filter(filter, pause_mc_addr);
3026
3027 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3028 yukon_add_filter(filter, list->dmi_addr);
3029 }
3030
3031
3032 gma_write16(hw, port, GM_MC_ADDR_H1,
3033 (u16)filter[0] | ((u16)filter[1] << 8));
3034 gma_write16(hw, port, GM_MC_ADDR_H2,
3035 (u16)filter[2] | ((u16)filter[3] << 8));
3036 gma_write16(hw, port, GM_MC_ADDR_H3,
3037 (u16)filter[4] | ((u16)filter[5] << 8));
3038 gma_write16(hw, port, GM_MC_ADDR_H4,
3039 (u16)filter[6] | ((u16)filter[7] << 8));
3040
3041 gma_write16(hw, port, GM_RX_CTRL, reg);
3042 }
3043
3044 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3045 {
3046 if (hw->chip_id == CHIP_ID_GENESIS)
3047 return status >> XMR_FS_LEN_SHIFT;
3048 else
3049 return status >> GMR_FS_LEN_SHIFT;
3050 }
3051
3052 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3053 {
3054 if (hw->chip_id == CHIP_ID_GENESIS)
3055 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3056 else
3057 return (status & GMR_FS_ANY_ERR) ||
3058 (status & GMR_FS_RX_OK) == 0;
3059 }
3060
3061
3062 /* Get receive buffer from descriptor.
3063 * Handles copy of small buffers and reallocation failures
3064 */
3065 static struct sk_buff *skge_rx_get(struct net_device *dev,
3066 struct skge_element *e,
3067 u32 control, u32 status, u16 csum)
3068 {
3069 struct skge_port *skge = netdev_priv(dev);
3070 struct sk_buff *skb;
3071 u16 len = control & BMU_BBC;
3072
3073 if (unlikely(netif_msg_rx_status(skge)))
3074 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
3075 dev->name, e - skge->rx_ring.start,
3076 status, len);
3077
3078 if (len > skge->rx_buf_size)
3079 goto error;
3080
3081 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3082 goto error;
3083
3084 if (bad_phy_status(skge->hw, status))
3085 goto error;
3086
3087 if (phy_length(skge->hw, status) != len)
3088 goto error;
3089
3090 if (len < RX_COPY_THRESHOLD) {
3091 skb = netdev_alloc_skb(dev, len + 2);
3092 if (!skb)
3093 goto resubmit;
3094
3095 skb_reserve(skb, 2);
3096 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3097 pci_unmap_addr(e, mapaddr),
3098 len, PCI_DMA_FROMDEVICE);
3099 skb_copy_from_linear_data(e->skb, skb->data, len);
3100 pci_dma_sync_single_for_device(skge->hw->pdev,
3101 pci_unmap_addr(e, mapaddr),
3102 len, PCI_DMA_FROMDEVICE);
3103 skge_rx_reuse(e, skge->rx_buf_size);
3104 } else {
3105 struct sk_buff *nskb;
3106 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
3107 if (!nskb)
3108 goto resubmit;
3109
3110 skb_reserve(nskb, NET_IP_ALIGN);
3111 pci_unmap_single(skge->hw->pdev,
3112 pci_unmap_addr(e, mapaddr),
3113 pci_unmap_len(e, maplen),
3114 PCI_DMA_FROMDEVICE);
3115 skb = e->skb;
3116 prefetch(skb->data);
3117 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
3118 }
3119
3120 skb_put(skb, len);
3121 if (skge->rx_csum) {
3122 skb->csum = csum;
3123 skb->ip_summed = CHECKSUM_COMPLETE;
3124 }
3125
3126 skb->protocol = eth_type_trans(skb, dev);
3127
3128 return skb;
3129 error:
3130
3131 if (netif_msg_rx_err(skge))
3132 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
3133 dev->name, e - skge->rx_ring.start,
3134 control, status);
3135
3136 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3137 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3138 dev->stats.rx_length_errors++;
3139 if (status & XMR_FS_FRA_ERR)
3140 dev->stats.rx_frame_errors++;
3141 if (status & XMR_FS_FCS_ERR)
3142 dev->stats.rx_crc_errors++;
3143 } else {
3144 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3145 dev->stats.rx_length_errors++;
3146 if (status & GMR_FS_FRAGMENT)
3147 dev->stats.rx_frame_errors++;
3148 if (status & GMR_FS_CRC_ERR)
3149 dev->stats.rx_crc_errors++;
3150 }
3151
3152 resubmit:
3153 skge_rx_reuse(e, skge->rx_buf_size);
3154 return NULL;
3155 }
3156
3157 /* Free all buffers in Tx ring which are no longer owned by device */
3158 static void skge_tx_done(struct net_device *dev)
3159 {
3160 struct skge_port *skge = netdev_priv(dev);
3161 struct skge_ring *ring = &skge->tx_ring;
3162 struct skge_element *e;
3163
3164 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3165
3166 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3167 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3168
3169 if (control & BMU_OWN)
3170 break;
3171
3172 skge_tx_free(skge, e, control);
3173 }
3174 skge->tx_ring.to_clean = e;
3175
3176 /* Can run lockless until we need to synchronize to restart queue. */
3177 smp_mb();
3178
3179 if (unlikely(netif_queue_stopped(dev) &&
3180 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3181 netif_tx_lock(dev);
3182 if (unlikely(netif_queue_stopped(dev) &&
3183 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3184 netif_wake_queue(dev);
3185
3186 }
3187 netif_tx_unlock(dev);
3188 }
3189 }
3190
3191 static int skge_poll(struct napi_struct *napi, int to_do)
3192 {
3193 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3194 struct net_device *dev = skge->netdev;
3195 struct skge_hw *hw = skge->hw;
3196 struct skge_ring *ring = &skge->rx_ring;
3197 struct skge_element *e;
3198 int work_done = 0;
3199
3200 skge_tx_done(dev);
3201
3202 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3203
3204 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3205 struct skge_rx_desc *rd = e->desc;
3206 struct sk_buff *skb;
3207 u32 control;
3208
3209 rmb();
3210 control = rd->control;
3211 if (control & BMU_OWN)
3212 break;
3213
3214 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3215 if (likely(skb)) {
3216 dev->last_rx = jiffies;
3217 netif_receive_skb(skb);
3218
3219 ++work_done;
3220 }
3221 }
3222 ring->to_clean = e;
3223
3224 /* restart receiver */
3225 wmb();
3226 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3227
3228 if (work_done < to_do) {
3229 spin_lock_irq(&hw->hw_lock);
3230 __netif_rx_complete(dev, napi);
3231 hw->intr_mask |= napimask[skge->port];
3232 skge_write32(hw, B0_IMSK, hw->intr_mask);
3233 skge_read32(hw, B0_IMSK);
3234 spin_unlock_irq(&hw->hw_lock);
3235 }
3236
3237 return work_done;
3238 }
3239
3240 /* Parity errors seem to happen when Genesis is connected to a switch
3241 * with no other ports present. Heartbeat error??
3242 */
3243 static void skge_mac_parity(struct skge_hw *hw, int port)
3244 {
3245 struct net_device *dev = hw->dev[port];
3246
3247 ++dev->stats.tx_heartbeat_errors;
3248
3249 if (hw->chip_id == CHIP_ID_GENESIS)
3250 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3251 MFF_CLR_PERR);
3252 else
3253 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3254 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3255 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3256 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3257 }
3258
3259 static void skge_mac_intr(struct skge_hw *hw, int port)
3260 {
3261 if (hw->chip_id == CHIP_ID_GENESIS)
3262 genesis_mac_intr(hw, port);
3263 else
3264 yukon_mac_intr(hw, port);
3265 }
3266
3267 /* Handle device specific framing and timeout interrupts */
3268 static void skge_error_irq(struct skge_hw *hw)
3269 {
3270 struct pci_dev *pdev = hw->pdev;
3271 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3272
3273 if (hw->chip_id == CHIP_ID_GENESIS) {
3274 /* clear xmac errors */
3275 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3276 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3277 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3278 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3279 } else {
3280 /* Timestamp (unused) overflow */
3281 if (hwstatus & IS_IRQ_TIST_OV)
3282 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3283 }
3284
3285 if (hwstatus & IS_RAM_RD_PAR) {
3286 dev_err(&pdev->dev, "Ram read data parity error\n");
3287 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3288 }
3289
3290 if (hwstatus & IS_RAM_WR_PAR) {
3291 dev_err(&pdev->dev, "Ram write data parity error\n");
3292 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3293 }
3294
3295 if (hwstatus & IS_M1_PAR_ERR)
3296 skge_mac_parity(hw, 0);
3297
3298 if (hwstatus & IS_M2_PAR_ERR)
3299 skge_mac_parity(hw, 1);
3300
3301 if (hwstatus & IS_R1_PAR_ERR) {
3302 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3303 hw->dev[0]->name);
3304 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3305 }
3306
3307 if (hwstatus & IS_R2_PAR_ERR) {
3308 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3309 hw->dev[1]->name);
3310 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3311 }
3312
3313 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3314 u16 pci_status, pci_cmd;
3315
3316 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3317 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3318
3319 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3320 pci_cmd, pci_status);
3321
3322 /* Write the error bits back to clear them. */
3323 pci_status &= PCI_STATUS_ERROR_BITS;
3324 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3325 pci_write_config_word(pdev, PCI_COMMAND,
3326 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3327 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3328 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3329
3330 /* if error still set then just ignore it */
3331 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3332 if (hwstatus & IS_IRQ_STAT) {
3333 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3334 hw->intr_mask &= ~IS_HW_ERR;
3335 }
3336 }
3337 }
3338
3339 /*
3340 * Interrupt from PHY are handled in tasklet (softirq)
3341 * because accessing phy registers requires spin wait which might
3342 * cause excess interrupt latency.
3343 */
3344 static void skge_extirq(unsigned long arg)
3345 {
3346 struct skge_hw *hw = (struct skge_hw *) arg;
3347 int port;
3348
3349 for (port = 0; port < hw->ports; port++) {
3350 struct net_device *dev = hw->dev[port];
3351
3352 if (netif_running(dev)) {
3353 struct skge_port *skge = netdev_priv(dev);
3354
3355 spin_lock(&hw->phy_lock);
3356 if (hw->chip_id != CHIP_ID_GENESIS)
3357 yukon_phy_intr(skge);
3358 else if (hw->phy_type == SK_PHY_BCOM)
3359 bcom_phy_intr(skge);
3360 spin_unlock(&hw->phy_lock);
3361 }
3362 }
3363
3364 spin_lock_irq(&hw->hw_lock);
3365 hw->intr_mask |= IS_EXT_REG;
3366 skge_write32(hw, B0_IMSK, hw->intr_mask);
3367 skge_read32(hw, B0_IMSK);
3368 spin_unlock_irq(&hw->hw_lock);
3369 }
3370
3371 static irqreturn_t skge_intr(int irq, void *dev_id)
3372 {
3373 struct skge_hw *hw = dev_id;
3374 u32 status;
3375 int handled = 0;
3376
3377 spin_lock(&hw->hw_lock);
3378 /* Reading this register masks IRQ */
3379 status = skge_read32(hw, B0_SP_ISRC);
3380 if (status == 0 || status == ~0)
3381 goto out;
3382
3383 handled = 1;
3384 status &= hw->intr_mask;
3385 if (status & IS_EXT_REG) {
3386 hw->intr_mask &= ~IS_EXT_REG;
3387 tasklet_schedule(&hw->phy_task);
3388 }
3389
3390 if (status & (IS_XA1_F|IS_R1_F)) {
3391 struct skge_port *skge = netdev_priv(hw->dev[0]);
3392 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3393 netif_rx_schedule(hw->dev[0], &skge->napi);
3394 }
3395
3396 if (status & IS_PA_TO_TX1)
3397 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3398
3399 if (status & IS_PA_TO_RX1) {
3400 ++hw->dev[0]->stats.rx_over_errors;
3401 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3402 }
3403
3404
3405 if (status & IS_MAC1)
3406 skge_mac_intr(hw, 0);
3407
3408 if (hw->dev[1]) {
3409 struct skge_port *skge = netdev_priv(hw->dev[1]);
3410
3411 if (status & (IS_XA2_F|IS_R2_F)) {
3412 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3413 netif_rx_schedule(hw->dev[1], &skge->napi);
3414 }
3415
3416 if (status & IS_PA_TO_RX2) {
3417 ++hw->dev[1]->stats.rx_over_errors;
3418 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3419 }
3420
3421 if (status & IS_PA_TO_TX2)
3422 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3423
3424 if (status & IS_MAC2)
3425 skge_mac_intr(hw, 1);
3426 }
3427
3428 if (status & IS_HW_ERR)
3429 skge_error_irq(hw);
3430
3431 skge_write32(hw, B0_IMSK, hw->intr_mask);
3432 skge_read32(hw, B0_IMSK);
3433 out:
3434 spin_unlock(&hw->hw_lock);
3435
3436 return IRQ_RETVAL(handled);
3437 }
3438
3439 #ifdef CONFIG_NET_POLL_CONTROLLER
3440 static void skge_netpoll(struct net_device *dev)
3441 {
3442 struct skge_port *skge = netdev_priv(dev);
3443
3444 disable_irq(dev->irq);
3445 skge_intr(dev->irq, skge->hw);
3446 enable_irq(dev->irq);
3447 }
3448 #endif
3449
3450 static int skge_set_mac_address(struct net_device *dev, void *p)
3451 {
3452 struct skge_port *skge = netdev_priv(dev);
3453 struct skge_hw *hw = skge->hw;
3454 unsigned port = skge->port;
3455 const struct sockaddr *addr = p;
3456 u16 ctrl;
3457
3458 if (!is_valid_ether_addr(addr->sa_data))
3459 return -EADDRNOTAVAIL;
3460
3461 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3462
3463 if (!netif_running(dev)) {
3464 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3465 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3466 } else {
3467 /* disable Rx */
3468 spin_lock_bh(&hw->phy_lock);
3469 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3470 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3471
3472 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3473 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3474
3475 if (hw->chip_id == CHIP_ID_GENESIS)
3476 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3477 else {
3478 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3479 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3480 }
3481
3482 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3483 spin_unlock_bh(&hw->phy_lock);
3484 }
3485
3486 return 0;
3487 }
3488
3489 static const struct {
3490 u8 id;
3491 const char *name;
3492 } skge_chips[] = {
3493 { CHIP_ID_GENESIS, "Genesis" },
3494 { CHIP_ID_YUKON, "Yukon" },
3495 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3496 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3497 };
3498
3499 static const char *skge_board_name(const struct skge_hw *hw)
3500 {
3501 int i;
3502 static char buf[16];
3503
3504 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3505 if (skge_chips[i].id == hw->chip_id)
3506 return skge_chips[i].name;
3507
3508 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3509 return buf;
3510 }
3511
3512
3513 /*
3514 * Setup the board data structure, but don't bring up
3515 * the port(s)
3516 */
3517 static int skge_reset(struct skge_hw *hw)
3518 {
3519 u32 reg;
3520 u16 ctst, pci_status;
3521 u8 t8, mac_cfg, pmd_type;
3522 int i;
3523
3524 ctst = skge_read16(hw, B0_CTST);
3525
3526 /* do a SW reset */
3527 skge_write8(hw, B0_CTST, CS_RST_SET);
3528 skge_write8(hw, B0_CTST, CS_RST_CLR);
3529
3530 /* clear PCI errors, if any */
3531 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3532 skge_write8(hw, B2_TST_CTRL2, 0);
3533
3534 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3535 pci_write_config_word(hw->pdev, PCI_STATUS,
3536 pci_status | PCI_STATUS_ERROR_BITS);
3537 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3538 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3539
3540 /* restore CLK_RUN bits (for Yukon-Lite) */
3541 skge_write16(hw, B0_CTST,
3542 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3543
3544 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3545 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3546 pmd_type = skge_read8(hw, B2_PMD_TYP);
3547 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3548
3549 switch (hw->chip_id) {
3550 case CHIP_ID_GENESIS:
3551 switch (hw->phy_type) {
3552 case SK_PHY_XMAC:
3553 hw->phy_addr = PHY_ADDR_XMAC;
3554 break;
3555 case SK_PHY_BCOM:
3556 hw->phy_addr = PHY_ADDR_BCOM;
3557 break;
3558 default:
3559 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3560 hw->phy_type);
3561 return -EOPNOTSUPP;
3562 }
3563 break;
3564
3565 case CHIP_ID_YUKON:
3566 case CHIP_ID_YUKON_LITE:
3567 case CHIP_ID_YUKON_LP:
3568 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3569 hw->copper = 1;
3570
3571 hw->phy_addr = PHY_ADDR_MARV;
3572 break;
3573
3574 default:
3575 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3576 hw->chip_id);
3577 return -EOPNOTSUPP;
3578 }
3579
3580 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3581 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3582 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3583
3584 /* read the adapters RAM size */
3585 t8 = skge_read8(hw, B2_E_0);
3586 if (hw->chip_id == CHIP_ID_GENESIS) {
3587 if (t8 == 3) {
3588 /* special case: 4 x 64k x 36, offset = 0x80000 */
3589 hw->ram_size = 0x100000;
3590 hw->ram_offset = 0x80000;
3591 } else
3592 hw->ram_size = t8 * 512;
3593 }
3594 else if (t8 == 0)
3595 hw->ram_size = 0x20000;
3596 else
3597 hw->ram_size = t8 * 4096;
3598
3599 hw->intr_mask = IS_HW_ERR;
3600
3601 /* Use PHY IRQ for all but fiber based Genesis board */
3602 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3603 hw->intr_mask |= IS_EXT_REG;
3604
3605 if (hw->chip_id == CHIP_ID_GENESIS)
3606 genesis_init(hw);
3607 else {
3608 /* switch power to VCC (WA for VAUX problem) */
3609 skge_write8(hw, B0_POWER_CTRL,
3610 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3611
3612 /* avoid boards with stuck Hardware error bits */
3613 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3614 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3615 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3616 hw->intr_mask &= ~IS_HW_ERR;
3617 }
3618
3619 /* Clear PHY COMA */
3620 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3621 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3622 reg &= ~PCI_PHY_COMA;
3623 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3624 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3625
3626
3627 for (i = 0; i < hw->ports; i++) {
3628 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3629 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3630 }
3631 }
3632
3633 /* turn off hardware timer (unused) */
3634 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3635 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3636 skge_write8(hw, B0_LED, LED_STAT_ON);
3637
3638 /* enable the Tx Arbiters */
3639 for (i = 0; i < hw->ports; i++)
3640 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3641
3642 /* Initialize ram interface */
3643 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3644
3645 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3646 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3647 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3648 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3649 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3650 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3651 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3652 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3653 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3654 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3655 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3656 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3657
3658 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3659
3660 /* Set interrupt moderation for Transmit only
3661 * Receive interrupts avoided by NAPI
3662 */
3663 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3664 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3665 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3666
3667 skge_write32(hw, B0_IMSK, hw->intr_mask);
3668
3669 for (i = 0; i < hw->ports; i++) {
3670 if (hw->chip_id == CHIP_ID_GENESIS)
3671 genesis_reset(hw, i);
3672 else
3673 yukon_reset(hw, i);
3674 }
3675
3676 return 0;
3677 }
3678
3679
3680 #ifdef CONFIG_SKGE_DEBUG
3681
3682 static struct dentry *skge_debug;
3683
3684 static int skge_debug_show(struct seq_file *seq, void *v)
3685 {
3686 struct net_device *dev = seq->private;
3687 const struct skge_port *skge = netdev_priv(dev);
3688 const struct skge_hw *hw = skge->hw;
3689 const struct skge_element *e;
3690
3691 if (!netif_running(dev))
3692 return -ENETDOWN;
3693
3694 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3695 skge_read32(hw, B0_IMSK));
3696
3697 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3698 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3699 const struct skge_tx_desc *t = e->desc;
3700 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3701 t->control, t->dma_hi, t->dma_lo, t->status,
3702 t->csum_offs, t->csum_write, t->csum_start);
3703 }
3704
3705 seq_printf(seq, "\nRx Ring: \n");
3706 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3707 const struct skge_rx_desc *r = e->desc;
3708
3709 if (r->control & BMU_OWN)
3710 break;
3711
3712 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3713 r->control, r->dma_hi, r->dma_lo, r->status,
3714 r->timestamp, r->csum1, r->csum1_start);
3715 }
3716
3717 return 0;
3718 }
3719
3720 static int skge_debug_open(struct inode *inode, struct file *file)
3721 {
3722 return single_open(file, skge_debug_show, inode->i_private);
3723 }
3724
3725 static const struct file_operations skge_debug_fops = {
3726 .owner = THIS_MODULE,
3727 .open = skge_debug_open,
3728 .read = seq_read,
3729 .llseek = seq_lseek,
3730 .release = single_release,
3731 };
3732
3733 /*
3734 * Use network device events to create/remove/rename
3735 * debugfs file entries
3736 */
3737 static int skge_device_event(struct notifier_block *unused,
3738 unsigned long event, void *ptr)
3739 {
3740 struct net_device *dev = ptr;
3741 struct skge_port *skge;
3742 struct dentry *d;
3743
3744 if (dev->open != &skge_up || !skge_debug)
3745 goto done;
3746
3747 skge = netdev_priv(dev);
3748 switch(event) {
3749 case NETDEV_CHANGENAME:
3750 if (skge->debugfs) {
3751 d = debugfs_rename(skge_debug, skge->debugfs,
3752 skge_debug, dev->name);
3753 if (d)
3754 skge->debugfs = d;
3755 else {
3756 pr_info(PFX "%s: rename failed\n", dev->name);
3757 debugfs_remove(skge->debugfs);
3758 }
3759 }
3760 break;
3761
3762 case NETDEV_GOING_DOWN:
3763 if (skge->debugfs) {
3764 debugfs_remove(skge->debugfs);
3765 skge->debugfs = NULL;
3766 }
3767 break;
3768
3769 case NETDEV_UP:
3770 d = debugfs_create_file(dev->name, S_IRUGO,
3771 skge_debug, dev,
3772 &skge_debug_fops);
3773 if (!d || IS_ERR(d))
3774 pr_info(PFX "%s: debugfs create failed\n",
3775 dev->name);
3776 else
3777 skge->debugfs = d;
3778 break;
3779 }
3780
3781 done:
3782 return NOTIFY_DONE;
3783 }
3784
3785 static struct notifier_block skge_notifier = {
3786 .notifier_call = skge_device_event,
3787 };
3788
3789
3790 static __init void skge_debug_init(void)
3791 {
3792 struct dentry *ent;
3793
3794 ent = debugfs_create_dir("skge", NULL);
3795 if (!ent || IS_ERR(ent)) {
3796 pr_info(PFX "debugfs create directory failed\n");
3797 return;
3798 }
3799
3800 skge_debug = ent;
3801 register_netdevice_notifier(&skge_notifier);
3802 }
3803
3804 static __exit void skge_debug_cleanup(void)
3805 {
3806 if (skge_debug) {
3807 unregister_netdevice_notifier(&skge_notifier);
3808 debugfs_remove(skge_debug);
3809 skge_debug = NULL;
3810 }
3811 }
3812
3813 #else
3814 #define skge_debug_init()
3815 #define skge_debug_cleanup()
3816 #endif
3817
3818 /* Initialize network device */
3819 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3820 int highmem)
3821 {
3822 struct skge_port *skge;
3823 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3824
3825 if (!dev) {
3826 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3827 return NULL;
3828 }
3829
3830 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3831 dev->open = skge_up;
3832 dev->stop = skge_down;
3833 dev->do_ioctl = skge_ioctl;
3834 dev->hard_start_xmit = skge_xmit_frame;
3835 dev->get_stats = skge_get_stats;
3836 if (hw->chip_id == CHIP_ID_GENESIS)
3837 dev->set_multicast_list = genesis_set_multicast;
3838 else
3839 dev->set_multicast_list = yukon_set_multicast;
3840
3841 dev->set_mac_address = skge_set_mac_address;
3842 dev->change_mtu = skge_change_mtu;
3843 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3844 dev->tx_timeout = skge_tx_timeout;
3845 dev->watchdog_timeo = TX_WATCHDOG;
3846 #ifdef CONFIG_NET_POLL_CONTROLLER
3847 dev->poll_controller = skge_netpoll;
3848 #endif
3849 dev->irq = hw->pdev->irq;
3850
3851 if (highmem)
3852 dev->features |= NETIF_F_HIGHDMA;
3853
3854 skge = netdev_priv(dev);
3855 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3856 skge->netdev = dev;
3857 skge->hw = hw;
3858 skge->msg_enable = netif_msg_init(debug, default_msg);
3859
3860 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3861 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3862
3863 /* Auto speed and flow control */
3864 skge->autoneg = AUTONEG_ENABLE;
3865 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3866 skge->duplex = -1;
3867 skge->speed = -1;
3868 skge->advertising = skge_supported_modes(hw);
3869
3870 if (pci_wake_enabled(hw->pdev))
3871 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3872
3873 hw->dev[port] = dev;
3874
3875 skge->port = port;
3876
3877 /* Only used for Genesis XMAC */
3878 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3879
3880 if (hw->chip_id != CHIP_ID_GENESIS) {
3881 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3882 skge->rx_csum = 1;
3883 }
3884
3885 /* read the mac address */
3886 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3887 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3888
3889 /* device is off until link detection */
3890 netif_carrier_off(dev);
3891 netif_stop_queue(dev);
3892
3893 return dev;
3894 }
3895
3896 static void __devinit skge_show_addr(struct net_device *dev)
3897 {
3898 const struct skge_port *skge = netdev_priv(dev);
3899 DECLARE_MAC_BUF(mac);
3900
3901 if (netif_msg_probe(skge))
3902 printk(KERN_INFO PFX "%s: addr %s\n",
3903 dev->name, print_mac(mac, dev->dev_addr));
3904 }
3905
3906 static int __devinit skge_probe(struct pci_dev *pdev,
3907 const struct pci_device_id *ent)
3908 {
3909 struct net_device *dev, *dev1;
3910 struct skge_hw *hw;
3911 int err, using_dac = 0;
3912
3913 err = pci_enable_device(pdev);
3914 if (err) {
3915 dev_err(&pdev->dev, "cannot enable PCI device\n");
3916 goto err_out;
3917 }
3918
3919 err = pci_request_regions(pdev, DRV_NAME);
3920 if (err) {
3921 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3922 goto err_out_disable_pdev;
3923 }
3924
3925 pci_set_master(pdev);
3926
3927 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3928 using_dac = 1;
3929 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3930 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3931 using_dac = 0;
3932 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3933 }
3934
3935 if (err) {
3936 dev_err(&pdev->dev, "no usable DMA configuration\n");
3937 goto err_out_free_regions;
3938 }
3939
3940 #ifdef __BIG_ENDIAN
3941 /* byte swap descriptors in hardware */
3942 {
3943 u32 reg;
3944
3945 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3946 reg |= PCI_REV_DESC;
3947 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3948 }
3949 #endif
3950
3951 err = -ENOMEM;
3952 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3953 if (!hw) {
3954 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3955 goto err_out_free_regions;
3956 }
3957
3958 hw->pdev = pdev;
3959 spin_lock_init(&hw->hw_lock);
3960 spin_lock_init(&hw->phy_lock);
3961 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
3962
3963 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3964 if (!hw->regs) {
3965 dev_err(&pdev->dev, "cannot map device registers\n");
3966 goto err_out_free_hw;
3967 }
3968
3969 err = skge_reset(hw);
3970 if (err)
3971 goto err_out_iounmap;
3972
3973 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3974 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3975 skge_board_name(hw), hw->chip_rev);
3976
3977 dev = skge_devinit(hw, 0, using_dac);
3978 if (!dev)
3979 goto err_out_led_off;
3980
3981 /* Some motherboards are broken and has zero in ROM. */
3982 if (!is_valid_ether_addr(dev->dev_addr))
3983 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3984
3985 err = register_netdev(dev);
3986 if (err) {
3987 dev_err(&pdev->dev, "cannot register net device\n");
3988 goto err_out_free_netdev;
3989 }
3990
3991 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3992 if (err) {
3993 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
3994 dev->name, pdev->irq);
3995 goto err_out_unregister;
3996 }
3997 skge_show_addr(dev);
3998
3999 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
4000 if (register_netdev(dev1) == 0)
4001 skge_show_addr(dev1);
4002 else {
4003 /* Failure to register second port need not be fatal */
4004 dev_warn(&pdev->dev, "register of second port failed\n");
4005 hw->dev[1] = NULL;
4006 free_netdev(dev1);
4007 }
4008 }
4009 pci_set_drvdata(pdev, hw);
4010
4011 return 0;
4012
4013 err_out_unregister:
4014 unregister_netdev(dev);
4015 err_out_free_netdev:
4016 free_netdev(dev);
4017 err_out_led_off:
4018 skge_write16(hw, B0_LED, LED_STAT_OFF);
4019 err_out_iounmap:
4020 iounmap(hw->regs);
4021 err_out_free_hw:
4022 kfree(hw);
4023 err_out_free_regions:
4024 pci_release_regions(pdev);
4025 err_out_disable_pdev:
4026 pci_disable_device(pdev);
4027 pci_set_drvdata(pdev, NULL);
4028 err_out:
4029 return err;
4030 }
4031
4032 static void __devexit skge_remove(struct pci_dev *pdev)
4033 {
4034 struct skge_hw *hw = pci_get_drvdata(pdev);
4035 struct net_device *dev0, *dev1;
4036
4037 if (!hw)
4038 return;
4039
4040 flush_scheduled_work();
4041
4042 if ((dev1 = hw->dev[1]))
4043 unregister_netdev(dev1);
4044 dev0 = hw->dev[0];
4045 unregister_netdev(dev0);
4046
4047 tasklet_disable(&hw->phy_task);
4048
4049 spin_lock_irq(&hw->hw_lock);
4050 hw->intr_mask = 0;
4051 skge_write32(hw, B0_IMSK, 0);
4052 skge_read32(hw, B0_IMSK);
4053 spin_unlock_irq(&hw->hw_lock);
4054
4055 skge_write16(hw, B0_LED, LED_STAT_OFF);
4056 skge_write8(hw, B0_CTST, CS_RST_SET);
4057
4058 free_irq(pdev->irq, hw);
4059 pci_release_regions(pdev);
4060 pci_disable_device(pdev);
4061 if (dev1)
4062 free_netdev(dev1);
4063 free_netdev(dev0);
4064
4065 iounmap(hw->regs);
4066 kfree(hw);
4067 pci_set_drvdata(pdev, NULL);
4068 }
4069
4070 #ifdef CONFIG_PM
4071 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
4072 {
4073 struct skge_hw *hw = pci_get_drvdata(pdev);
4074 int i, err, wol = 0;
4075
4076 if (!hw)
4077 return 0;
4078
4079 err = pci_save_state(pdev);
4080 if (err)
4081 return err;
4082
4083 for (i = 0; i < hw->ports; i++) {
4084 struct net_device *dev = hw->dev[i];
4085 struct skge_port *skge = netdev_priv(dev);
4086
4087 if (netif_running(dev))
4088 skge_down(dev);
4089 if (skge->wol)
4090 skge_wol_init(skge);
4091
4092 wol |= skge->wol;
4093 }
4094
4095 skge_write32(hw, B0_IMSK, 0);
4096 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4097 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4098
4099 return 0;
4100 }
4101
4102 static int skge_resume(struct pci_dev *pdev)
4103 {
4104 struct skge_hw *hw = pci_get_drvdata(pdev);
4105 int i, err;
4106
4107 if (!hw)
4108 return 0;
4109
4110 err = pci_set_power_state(pdev, PCI_D0);
4111 if (err)
4112 goto out;
4113
4114 err = pci_restore_state(pdev);
4115 if (err)
4116 goto out;
4117
4118 pci_enable_wake(pdev, PCI_D0, 0);
4119
4120 err = skge_reset(hw);
4121 if (err)
4122 goto out;
4123
4124 for (i = 0; i < hw->ports; i++) {
4125 struct net_device *dev = hw->dev[i];
4126
4127 if (netif_running(dev)) {
4128 err = skge_up(dev);
4129
4130 if (err) {
4131 printk(KERN_ERR PFX "%s: could not up: %d\n",
4132 dev->name, err);
4133 dev_close(dev);
4134 goto out;
4135 }
4136 }
4137 }
4138 out:
4139 return err;
4140 }
4141 #endif
4142
4143 static void skge_shutdown(struct pci_dev *pdev)
4144 {
4145 struct skge_hw *hw = pci_get_drvdata(pdev);
4146 int i, wol = 0;
4147
4148 if (!hw)
4149 return;
4150
4151 for (i = 0; i < hw->ports; i++) {
4152 struct net_device *dev = hw->dev[i];
4153 struct skge_port *skge = netdev_priv(dev);
4154
4155 if (skge->wol)
4156 skge_wol_init(skge);
4157 wol |= skge->wol;
4158 }
4159
4160 pci_enable_wake(pdev, PCI_D3hot, wol);
4161 pci_enable_wake(pdev, PCI_D3cold, wol);
4162
4163 pci_disable_device(pdev);
4164 pci_set_power_state(pdev, PCI_D3hot);
4165
4166 }
4167
4168 static struct pci_driver skge_driver = {
4169 .name = DRV_NAME,
4170 .id_table = skge_id_table,
4171 .probe = skge_probe,
4172 .remove = __devexit_p(skge_remove),
4173 #ifdef CONFIG_PM
4174 .suspend = skge_suspend,
4175 .resume = skge_resume,
4176 #endif
4177 .shutdown = skge_shutdown,
4178 };
4179
4180 static int __init skge_init_module(void)
4181 {
4182 skge_debug_init();
4183 return pci_register_driver(&skge_driver);
4184 }
4185
4186 static void __exit skge_cleanup_module(void)
4187 {
4188 pci_unregister_driver(&skge_driver);
4189 skge_debug_cleanup();
4190 }
4191
4192 module_init(skge_init_module);
4193 module_exit(skge_cleanup_module);
Support for the Chinese Samsung S3C2440 based development boards