?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[HIFN]: Fix data alignment checks
[linux-2.6/mini2440.git] / sound / pci / maestro3.c
bloba536c59fbea1e4faed5155ce579ac0ac800e572b
1 /*
2 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
3 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the hardware init stuffs are based on maestro3 driver for
7 * OSS/Free by Zach Brown. Many thanks to Zach!
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 *
24 * ChangeLog:
25 * Aug. 27, 2001
26 * - Fixed deadlock on capture
27 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
28 *
29 */
30
31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
32 #define DRIVER_NAME "Maestro3"
33
34 #include <asm/io.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/init.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/moduleparam.h>
43 #include <linux/firmware.h>
44 #include <sound/core.h>
45 #include <sound/info.h>
46 #include <sound/control.h>
47 #include <sound/pcm.h>
48 #include <sound/mpu401.h>
49 #include <sound/ac97_codec.h>
50 #include <sound/initval.h>
51 #include <asm/byteorder.h>
52
53 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
54 MODULE_DESCRIPTION("ESS Maestro3 PCI");
55 MODULE_LICENSE("GPL");
56 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
57 "{ESS,ES1988},"
58 "{ESS,Allegro PCI},"
59 "{ESS,Allegro-1 PCI},"
60 "{ESS,Canyon3D-2/LE PCI}}");
61 #ifndef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL
62 MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
63 MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
64 #endif
65
66 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
67 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
68 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
69 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
70 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
71
72 module_param_array(index, int, NULL, 0444);
73 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
74 module_param_array(id, charp, NULL, 0444);
75 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
76 module_param_array(enable, bool, NULL, 0444);
77 MODULE_PARM_DESC(enable, "Enable this soundcard.");
78 module_param_array(external_amp, bool, NULL, 0444);
79 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
80 module_param_array(amp_gpio, int, NULL, 0444);
81 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
82
83 #define MAX_PLAYBACKS 2
84 #define MAX_CAPTURES 1
85 #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
86
87
88 /*
89 * maestro3 registers
90 */
91
92 /* Allegro PCI configuration registers */
93 #define PCI_LEGACY_AUDIO_CTRL 0x40
94 #define SOUND_BLASTER_ENABLE 0x00000001
95 #define FM_SYNTHESIS_ENABLE 0x00000002
96 #define GAME_PORT_ENABLE 0x00000004
97 #define MPU401_IO_ENABLE 0x00000008
98 #define MPU401_IRQ_ENABLE 0x00000010
99 #define ALIAS_10BIT_IO 0x00000020
100 #define SB_DMA_MASK 0x000000C0
101 #define SB_DMA_0 0x00000040
102 #define SB_DMA_1 0x00000040
103 #define SB_DMA_R 0x00000080
104 #define SB_DMA_3 0x000000C0
105 #define SB_IRQ_MASK 0x00000700
106 #define SB_IRQ_5 0x00000000
107 #define SB_IRQ_7 0x00000100
108 #define SB_IRQ_9 0x00000200
109 #define SB_IRQ_10 0x00000300
110 #define MIDI_IRQ_MASK 0x00003800
111 #define SERIAL_IRQ_ENABLE 0x00004000
112 #define DISABLE_LEGACY 0x00008000
113
114 #define PCI_ALLEGRO_CONFIG 0x50
115 #define SB_ADDR_240 0x00000004
116 #define MPU_ADDR_MASK 0x00000018
117 #define MPU_ADDR_330 0x00000000
118 #define MPU_ADDR_300 0x00000008
119 #define MPU_ADDR_320 0x00000010
120 #define MPU_ADDR_340 0x00000018
121 #define USE_PCI_TIMING 0x00000040
122 #define POSTED_WRITE_ENABLE 0x00000080
123 #define DMA_POLICY_MASK 0x00000700
124 #define DMA_DDMA 0x00000000
125 #define DMA_TDMA 0x00000100
126 #define DMA_PCPCI 0x00000200
127 #define DMA_WBDMA16 0x00000400
128 #define DMA_WBDMA4 0x00000500
129 #define DMA_WBDMA2 0x00000600
130 #define DMA_WBDMA1 0x00000700
131 #define DMA_SAFE_GUARD 0x00000800
132 #define HI_PERF_GP_ENABLE 0x00001000
133 #define PIC_SNOOP_MODE_0 0x00002000
134 #define PIC_SNOOP_MODE_1 0x00004000
135 #define SOUNDBLASTER_IRQ_MASK 0x00008000
136 #define RING_IN_ENABLE 0x00010000
137 #define SPDIF_TEST_MODE 0x00020000
138 #define CLK_MULT_MODE_SELECT_2 0x00040000
139 #define EEPROM_WRITE_ENABLE 0x00080000
140 #define CODEC_DIR_IN 0x00100000
141 #define HV_BUTTON_FROM_GD 0x00200000
142 #define REDUCED_DEBOUNCE 0x00400000
143 #define HV_CTRL_ENABLE 0x00800000
144 #define SPDIF_ENABLE 0x01000000
145 #define CLK_DIV_SELECT 0x06000000
146 #define CLK_DIV_BY_48 0x00000000
147 #define CLK_DIV_BY_49 0x02000000
148 #define CLK_DIV_BY_50 0x04000000
149 #define CLK_DIV_RESERVED 0x06000000
150 #define PM_CTRL_ENABLE 0x08000000
151 #define CLK_MULT_MODE_SELECT 0x30000000
152 #define CLK_MULT_MODE_SHIFT 28
153 #define CLK_MULT_MODE_0 0x00000000
154 #define CLK_MULT_MODE_1 0x10000000
155 #define CLK_MULT_MODE_2 0x20000000
156 #define CLK_MULT_MODE_3 0x30000000
157 #define INT_CLK_SELECT 0x40000000
158 #define INT_CLK_MULT_RESET 0x80000000
159
160 /* M3 */
161 #define INT_CLK_SRC_NOT_PCI 0x00100000
162 #define INT_CLK_MULT_ENABLE 0x80000000
163
164 #define PCI_ACPI_CONTROL 0x54
165 #define PCI_ACPI_D0 0x00000000
166 #define PCI_ACPI_D1 0xB4F70000
167 #define PCI_ACPI_D2 0xB4F7B4F7
168
169 #define PCI_USER_CONFIG 0x58
170 #define EXT_PCI_MASTER_ENABLE 0x00000001
171 #define SPDIF_OUT_SELECT 0x00000002
172 #define TEST_PIN_DIR_CTRL 0x00000004
173 #define AC97_CODEC_TEST 0x00000020
174 #define TRI_STATE_BUFFER 0x00000080
175 #define IN_CLK_12MHZ_SELECT 0x00000100
176 #define MULTI_FUNC_DISABLE 0x00000200
177 #define EXT_MASTER_PAIR_SEL 0x00000400
178 #define PCI_MASTER_SUPPORT 0x00000800
179 #define STOP_CLOCK_ENABLE 0x00001000
180 #define EAPD_DRIVE_ENABLE 0x00002000
181 #define REQ_TRI_STATE_ENABLE 0x00004000
182 #define REQ_LOW_ENABLE 0x00008000
183 #define MIDI_1_ENABLE 0x00010000
184 #define MIDI_2_ENABLE 0x00020000
185 #define SB_AUDIO_SYNC 0x00040000
186 #define HV_CTRL_TEST 0x00100000
187 #define SOUNDBLASTER_TEST 0x00400000
188
189 #define PCI_USER_CONFIG_C 0x5C
190
191 #define PCI_DDMA_CTRL 0x60
192 #define DDMA_ENABLE 0x00000001
193
194
195 /* Allegro registers */
196 #define HOST_INT_CTRL 0x18
197 #define SB_INT_ENABLE 0x0001
198 #define MPU401_INT_ENABLE 0x0002
199 #define ASSP_INT_ENABLE 0x0010
200 #define RING_INT_ENABLE 0x0020
201 #define HV_INT_ENABLE 0x0040
202 #define CLKRUN_GEN_ENABLE 0x0100
203 #define HV_CTRL_TO_PME 0x0400
204 #define SOFTWARE_RESET_ENABLE 0x8000
205
206 /*
207 * should be using the above defines, probably.
208 */
209 #define REGB_ENABLE_RESET 0x01
210 #define REGB_STOP_CLOCK 0x10
211
212 #define HOST_INT_STATUS 0x1A
213 #define SB_INT_PENDING 0x01
214 #define MPU401_INT_PENDING 0x02
215 #define ASSP_INT_PENDING 0x10
216 #define RING_INT_PENDING 0x20
217 #define HV_INT_PENDING 0x40
218
219 #define HARDWARE_VOL_CTRL 0x1B
220 #define SHADOW_MIX_REG_VOICE 0x1C
221 #define HW_VOL_COUNTER_VOICE 0x1D
222 #define SHADOW_MIX_REG_MASTER 0x1E
223 #define HW_VOL_COUNTER_MASTER 0x1F
224
225 #define CODEC_COMMAND 0x30
226 #define CODEC_READ_B 0x80
227
228 #define CODEC_STATUS 0x30
229 #define CODEC_BUSY_B 0x01
230
231 #define CODEC_DATA 0x32
232
233 #define RING_BUS_CTRL_A 0x36
234 #define RAC_PME_ENABLE 0x0100
235 #define RAC_SDFS_ENABLE 0x0200
236 #define LAC_PME_ENABLE 0x0400
237 #define LAC_SDFS_ENABLE 0x0800
238 #define SERIAL_AC_LINK_ENABLE 0x1000
239 #define IO_SRAM_ENABLE 0x2000
240 #define IIS_INPUT_ENABLE 0x8000
241
242 #define RING_BUS_CTRL_B 0x38
243 #define SECOND_CODEC_ID_MASK 0x0003
244 #define SPDIF_FUNC_ENABLE 0x0010
245 #define SECOND_AC_ENABLE 0x0020
246 #define SB_MODULE_INTF_ENABLE 0x0040
247 #define SSPE_ENABLE 0x0040
248 #define M3I_DOCK_ENABLE 0x0080
249
250 #define SDO_OUT_DEST_CTRL 0x3A
251 #define COMMAND_ADDR_OUT 0x0003
252 #define PCM_LR_OUT_LOCAL 0x0000
253 #define PCM_LR_OUT_REMOTE 0x0004
254 #define PCM_LR_OUT_MUTE 0x0008
255 #define PCM_LR_OUT_BOTH 0x000C
256 #define LINE1_DAC_OUT_LOCAL 0x0000
257 #define LINE1_DAC_OUT_REMOTE 0x0010
258 #define LINE1_DAC_OUT_MUTE 0x0020
259 #define LINE1_DAC_OUT_BOTH 0x0030
260 #define PCM_CLS_OUT_LOCAL 0x0000
261 #define PCM_CLS_OUT_REMOTE 0x0040
262 #define PCM_CLS_OUT_MUTE 0x0080
263 #define PCM_CLS_OUT_BOTH 0x00C0
264 #define PCM_RLF_OUT_LOCAL 0x0000
265 #define PCM_RLF_OUT_REMOTE 0x0100
266 #define PCM_RLF_OUT_MUTE 0x0200
267 #define PCM_RLF_OUT_BOTH 0x0300
268 #define LINE2_DAC_OUT_LOCAL 0x0000
269 #define LINE2_DAC_OUT_REMOTE 0x0400
270 #define LINE2_DAC_OUT_MUTE 0x0800
271 #define LINE2_DAC_OUT_BOTH 0x0C00
272 #define HANDSET_OUT_LOCAL 0x0000
273 #define HANDSET_OUT_REMOTE 0x1000
274 #define HANDSET_OUT_MUTE 0x2000
275 #define HANDSET_OUT_BOTH 0x3000
276 #define IO_CTRL_OUT_LOCAL 0x0000
277 #define IO_CTRL_OUT_REMOTE 0x4000
278 #define IO_CTRL_OUT_MUTE 0x8000
279 #define IO_CTRL_OUT_BOTH 0xC000
280
281 #define SDO_IN_DEST_CTRL 0x3C
282 #define STATUS_ADDR_IN 0x0003
283 #define PCM_LR_IN_LOCAL 0x0000
284 #define PCM_LR_IN_REMOTE 0x0004
285 #define PCM_LR_RESERVED 0x0008
286 #define PCM_LR_IN_BOTH 0x000C
287 #define LINE1_ADC_IN_LOCAL 0x0000
288 #define LINE1_ADC_IN_REMOTE 0x0010
289 #define LINE1_ADC_IN_MUTE 0x0020
290 #define MIC_ADC_IN_LOCAL 0x0000
291 #define MIC_ADC_IN_REMOTE 0x0040
292 #define MIC_ADC_IN_MUTE 0x0080
293 #define LINE2_DAC_IN_LOCAL 0x0000
294 #define LINE2_DAC_IN_REMOTE 0x0400
295 #define LINE2_DAC_IN_MUTE 0x0800
296 #define HANDSET_IN_LOCAL 0x0000
297 #define HANDSET_IN_REMOTE 0x1000
298 #define HANDSET_IN_MUTE 0x2000
299 #define IO_STATUS_IN_LOCAL 0x0000
300 #define IO_STATUS_IN_REMOTE 0x4000
301
302 #define SPDIF_IN_CTRL 0x3E
303 #define SPDIF_IN_ENABLE 0x0001
304
305 #define GPIO_DATA 0x60
306 #define GPIO_DATA_MASK 0x0FFF
307 #define GPIO_HV_STATUS 0x3000
308 #define GPIO_PME_STATUS 0x4000
309
310 #define GPIO_MASK 0x64
311 #define GPIO_DIRECTION 0x68
312 #define GPO_PRIMARY_AC97 0x0001
313 #define GPI_LINEOUT_SENSE 0x0004
314 #define GPO_SECONDARY_AC97 0x0008
315 #define GPI_VOL_DOWN 0x0010
316 #define GPI_VOL_UP 0x0020
317 #define GPI_IIS_CLK 0x0040
318 #define GPI_IIS_LRCLK 0x0080
319 #define GPI_IIS_DATA 0x0100
320 #define GPI_DOCKING_STATUS 0x0100
321 #define GPI_HEADPHONE_SENSE 0x0200
322 #define GPO_EXT_AMP_SHUTDOWN 0x1000
323
324 #define GPO_EXT_AMP_M3 1 /* default m3 amp */
325 #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
326
327 /* M3 */
328 #define GPO_M3_EXT_AMP_SHUTDN 0x0002
329
330 #define ASSP_INDEX_PORT 0x80
331 #define ASSP_MEMORY_PORT 0x82
332 #define ASSP_DATA_PORT 0x84
333
334 #define MPU401_DATA_PORT 0x98
335 #define MPU401_STATUS_PORT 0x99
336
337 #define CLK_MULT_DATA_PORT 0x9C
338
339 #define ASSP_CONTROL_A 0xA2
340 #define ASSP_0_WS_ENABLE 0x01
341 #define ASSP_CTRL_A_RESERVED1 0x02
342 #define ASSP_CTRL_A_RESERVED2 0x04
343 #define ASSP_CLK_49MHZ_SELECT 0x08
344 #define FAST_PLU_ENABLE 0x10
345 #define ASSP_CTRL_A_RESERVED3 0x20
346 #define DSP_CLK_36MHZ_SELECT 0x40
347
348 #define ASSP_CONTROL_B 0xA4
349 #define RESET_ASSP 0x00
350 #define RUN_ASSP 0x01
351 #define ENABLE_ASSP_CLOCK 0x00
352 #define STOP_ASSP_CLOCK 0x10
353 #define RESET_TOGGLE 0x40
354
355 #define ASSP_CONTROL_C 0xA6
356 #define ASSP_HOST_INT_ENABLE 0x01
357 #define FM_ADDR_REMAP_DISABLE 0x02
358 #define HOST_WRITE_PORT_ENABLE 0x08
359
360 #define ASSP_HOST_INT_STATUS 0xAC
361 #define DSP2HOST_REQ_PIORECORD 0x01
362 #define DSP2HOST_REQ_I2SRATE 0x02
363 #define DSP2HOST_REQ_TIMER 0x04
364
365 /* AC97 registers */
366 /* XXX fix this crap up */
367 /*#define AC97_RESET 0x00*/
368
369 #define AC97_VOL_MUTE_B 0x8000
370 #define AC97_VOL_M 0x1F
371 #define AC97_LEFT_VOL_S 8
372
373 #define AC97_MASTER_VOL 0x02
374 #define AC97_LINE_LEVEL_VOL 0x04
375 #define AC97_MASTER_MONO_VOL 0x06
376 #define AC97_PC_BEEP_VOL 0x0A
377 #define AC97_PC_BEEP_VOL_M 0x0F
378 #define AC97_SROUND_MASTER_VOL 0x38
379 #define AC97_PC_BEEP_VOL_S 1
380
381 /*#define AC97_PHONE_VOL 0x0C
382 #define AC97_MIC_VOL 0x0E*/
383 #define AC97_MIC_20DB_ENABLE 0x40
384
385 /*#define AC97_LINEIN_VOL 0x10
386 #define AC97_CD_VOL 0x12
387 #define AC97_VIDEO_VOL 0x14
388 #define AC97_AUX_VOL 0x16*/
389 #define AC97_PCM_OUT_VOL 0x18
390 /*#define AC97_RECORD_SELECT 0x1A*/
391 #define AC97_RECORD_MIC 0x00
392 #define AC97_RECORD_CD 0x01
393 #define AC97_RECORD_VIDEO 0x02
394 #define AC97_RECORD_AUX 0x03
395 #define AC97_RECORD_MONO_MUX 0x02
396 #define AC97_RECORD_DIGITAL 0x03
397 #define AC97_RECORD_LINE 0x04
398 #define AC97_RECORD_STEREO 0x05
399 #define AC97_RECORD_MONO 0x06
400 #define AC97_RECORD_PHONE 0x07
401
402 /*#define AC97_RECORD_GAIN 0x1C*/
403 #define AC97_RECORD_VOL_M 0x0F
404
405 /*#define AC97_GENERAL_PURPOSE 0x20*/
406 #define AC97_POWER_DOWN_CTRL 0x26
407 #define AC97_ADC_READY 0x0001
408 #define AC97_DAC_READY 0x0002
409 #define AC97_ANALOG_READY 0x0004
410 #define AC97_VREF_ON 0x0008
411 #define AC97_PR0 0x0100
412 #define AC97_PR1 0x0200
413 #define AC97_PR2 0x0400
414 #define AC97_PR3 0x0800
415 #define AC97_PR4 0x1000
416
417 #define AC97_RESERVED1 0x28
418
419 #define AC97_VENDOR_TEST 0x5A
420
421 #define AC97_CLOCK_DELAY 0x5C
422 #define AC97_LINEOUT_MUX_SEL 0x0001
423 #define AC97_MONO_MUX_SEL 0x0002
424 #define AC97_CLOCK_DELAY_SEL 0x1F
425 #define AC97_DAC_CDS_SHIFT 6
426 #define AC97_ADC_CDS_SHIFT 11
427
428 #define AC97_MULTI_CHANNEL_SEL 0x74
429
430 /*#define AC97_VENDOR_ID1 0x7C
431 #define AC97_VENDOR_ID2 0x7E*/
432
433 /*
434 * ASSP control regs
435 */
436 #define DSP_PORT_TIMER_COUNT 0x06
437
438 #define DSP_PORT_MEMORY_INDEX 0x80
439
440 #define DSP_PORT_MEMORY_TYPE 0x82
441 #define MEMTYPE_INTERNAL_CODE 0x0002
442 #define MEMTYPE_INTERNAL_DATA 0x0003
443 #define MEMTYPE_MASK 0x0003
444
445 #define DSP_PORT_MEMORY_DATA 0x84
446
447 #define DSP_PORT_CONTROL_REG_A 0xA2
448 #define DSP_PORT_CONTROL_REG_B 0xA4
449 #define DSP_PORT_CONTROL_REG_C 0xA6
450
451 #define REV_A_CODE_MEMORY_BEGIN 0x0000
452 #define REV_A_CODE_MEMORY_END 0x0FFF
453 #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
454 #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
455
456 #define REV_B_CODE_MEMORY_BEGIN 0x0000
457 #define REV_B_CODE_MEMORY_END 0x0BFF
458 #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
459 #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
460
461 #define REV_A_DATA_MEMORY_BEGIN 0x1000
462 #define REV_A_DATA_MEMORY_END 0x2FFF
463 #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
464 #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
465
466 #define REV_B_DATA_MEMORY_BEGIN 0x1000
467 #define REV_B_DATA_MEMORY_END 0x2BFF
468 #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
469 #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
470
471
472 #define NUM_UNITS_KERNEL_CODE 16
473 #define NUM_UNITS_KERNEL_DATA 2
474
475 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
476 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
477
478 /*
479 * Kernel data layout
480 */
481
482 #define DP_SHIFT_COUNT 7
483
484 #define KDATA_BASE_ADDR 0x1000
485 #define KDATA_BASE_ADDR2 0x1080
486
487 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
488 #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
489 #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
490 #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
491 #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
492 #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
493 #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
494 #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
495 #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
496
497 #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
498 #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
499
500 #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
501 #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
502 #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
503 #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
504 #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
505 #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
506 #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
507 #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
508 #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
509 #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
510
511 #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
512 #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
513
514 #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
515 #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
516
517 #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
518 #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
519
520 #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
521 #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
522 #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
523
524 #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
525 #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
526 #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
527 #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
528 #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
529
530 #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
531 #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
532 #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
533
534 #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
535 #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
536 #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
537
538 #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
539 #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
540 #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
541 #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
542 #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
543 #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
544 #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
545 #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
546 #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
547 #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
548
549 #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
550 #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
551 #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
552
553 #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
554 #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
555
556 #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
557 #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
558 #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
559
560 #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
561 #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
562 #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
563 #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
564 #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
565 #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
566
567 #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
568 #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
569 #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
570 #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
571 #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
572 #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
573
574 #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
575 #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
576 #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
577 #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
578 #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
579 #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
580
581 #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
582 #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
583 #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
584 #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
585
586 #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
587 #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
588
589 #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
590 #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
591
592 #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
593 #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
594 #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
595 #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
596 #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
597
598 #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
599 #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
600
601 #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
602 #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
603 #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
604
605 #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
606 #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
607
608 #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
609
610 #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
611 #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
612 #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
613 #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
614 #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
615 #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
616 #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
617 #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
618 #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
619 #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
620 #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
621 #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
622
623 #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
624 #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
625 #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
626 #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
627
628 #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
629 #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
630
631 #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
632 #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
633 #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
634 #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
635
636 #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
637 #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
638 #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
639 #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
640 #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
641
642 /*
643 * second 'segment' (?) reserved for mixer
644 * buffers..
645 */
646
647 #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
648 #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
649 #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
650 #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
651 #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
652 #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
653 #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
654 #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
655 #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
656 #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
657 #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
658 #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
659 #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
660 #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
661 #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
662 #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
663
664 #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
665 #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
666 #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
667 #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
668 #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
669 #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
670 #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
671 #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
672 #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
673 #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
674 #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
675
676 #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
677 #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
678 #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
679 #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
680 #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
681 #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
682
683 #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
684 #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
685 #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
686 #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
687
688 /*
689 * client data area offsets
690 */
691 #define CDATA_INSTANCE_READY 0x00
692
693 #define CDATA_HOST_SRC_ADDRL 0x01
694 #define CDATA_HOST_SRC_ADDRH 0x02
695 #define CDATA_HOST_SRC_END_PLUS_1L 0x03
696 #define CDATA_HOST_SRC_END_PLUS_1H 0x04
697 #define CDATA_HOST_SRC_CURRENTL 0x05
698 #define CDATA_HOST_SRC_CURRENTH 0x06
699
700 #define CDATA_IN_BUF_CONNECT 0x07
701 #define CDATA_OUT_BUF_CONNECT 0x08
702
703 #define CDATA_IN_BUF_BEGIN 0x09
704 #define CDATA_IN_BUF_END_PLUS_1 0x0A
705 #define CDATA_IN_BUF_HEAD 0x0B
706 #define CDATA_IN_BUF_TAIL 0x0C
707 #define CDATA_OUT_BUF_BEGIN 0x0D
708 #define CDATA_OUT_BUF_END_PLUS_1 0x0E
709 #define CDATA_OUT_BUF_HEAD 0x0F
710 #define CDATA_OUT_BUF_TAIL 0x10
711
712 #define CDATA_DMA_CONTROL 0x11
713 #define CDATA_RESERVED 0x12
714
715 #define CDATA_FREQUENCY 0x13
716 #define CDATA_LEFT_VOLUME 0x14
717 #define CDATA_RIGHT_VOLUME 0x15
718 #define CDATA_LEFT_SUR_VOL 0x16
719 #define CDATA_RIGHT_SUR_VOL 0x17
720
721 #define CDATA_HEADER_LEN 0x18
722
723 #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
724 #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
725 #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
726 #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
727 #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
728 #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
729 #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
730 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
731
732 #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
733 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
734 #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
735 #define MINISRC_BIQUAD_STAGE 2
736 #define MINISRC_COEF_LOC 0x175
737
738 #define DMACONTROL_BLOCK_MASK 0x000F
739 #define DMAC_BLOCK0_SELECTOR 0x0000
740 #define DMAC_BLOCK1_SELECTOR 0x0001
741 #define DMAC_BLOCK2_SELECTOR 0x0002
742 #define DMAC_BLOCK3_SELECTOR 0x0003
743 #define DMAC_BLOCK4_SELECTOR 0x0004
744 #define DMAC_BLOCK5_SELECTOR 0x0005
745 #define DMAC_BLOCK6_SELECTOR 0x0006
746 #define DMAC_BLOCK7_SELECTOR 0x0007
747 #define DMAC_BLOCK8_SELECTOR 0x0008
748 #define DMAC_BLOCK9_SELECTOR 0x0009
749 #define DMAC_BLOCKA_SELECTOR 0x000A
750 #define DMAC_BLOCKB_SELECTOR 0x000B
751 #define DMAC_BLOCKC_SELECTOR 0x000C
752 #define DMAC_BLOCKD_SELECTOR 0x000D
753 #define DMAC_BLOCKE_SELECTOR 0x000E
754 #define DMAC_BLOCKF_SELECTOR 0x000F
755 #define DMACONTROL_PAGE_MASK 0x00F0
756 #define DMAC_PAGE0_SELECTOR 0x0030
757 #define DMAC_PAGE1_SELECTOR 0x0020
758 #define DMAC_PAGE2_SELECTOR 0x0010
759 #define DMAC_PAGE3_SELECTOR 0x0000
760 #define DMACONTROL_AUTOREPEAT 0x1000
761 #define DMACONTROL_STOPPED 0x2000
762 #define DMACONTROL_DIRECTION 0x0100
763
764 /*
765 * an arbitrary volume we set the internal
766 * volume settings to so that the ac97 volume
767 * range is a little less insane. 0x7fff is
768 * max.
769 */
770 #define ARB_VOLUME ( 0x6800 )
771
772 /*
773 */
774
775 struct m3_list {
776 int curlen;
777 int mem_addr;
778 int max;
779 };
780
781 struct m3_dma {
782
783 int number;
784 struct snd_pcm_substream *substream;
785
786 struct assp_instance {
787 unsigned short code, data;
788 } inst;
789
790 int running;
791 int opened;
792
793 unsigned long buffer_addr;
794 int dma_size;
795 int period_size;
796 unsigned int hwptr;
797 int count;
798
799 int index[3];
800 struct m3_list *index_list[3];
801
802 int in_lists;
803
804 struct list_head list;
805
806 };
807
808 struct snd_m3 {
809
810 struct snd_card *card;
811
812 unsigned long iobase;
813
814 int irq;
815 unsigned int allegro_flag : 1;
816
817 struct snd_ac97 *ac97;
818
819 struct snd_pcm *pcm;
820
821 struct pci_dev *pci;
822
823 int dacs_active;
824 int timer_users;
825
826 struct m3_list msrc_list;
827 struct m3_list mixer_list;
828 struct m3_list adc1_list;
829 struct m3_list dma_list;
830
831 /* for storing reset state..*/
832 u8 reset_state;
833
834 int external_amp;
835 int amp_gpio; /* gpio pin # for external amp, -1 = default */
836 unsigned int hv_config; /* hardware-volume config bits */
837 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
838 (e.g. for IrDA on Dell Inspirons) */
839 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
840
841 /* midi */
842 struct snd_rawmidi *rmidi;
843
844 /* pcm streams */
845 int num_substreams;
846 struct m3_dma *substreams;
847
848 spinlock_t reg_lock;
849 spinlock_t ac97_lock;
850
851 struct snd_kcontrol *master_switch;
852 struct snd_kcontrol *master_volume;
853 struct tasklet_struct hwvol_tq;
854
855 #ifdef CONFIG_PM
856 u16 *suspend_mem;
857 #endif
858
859 const struct firmware *assp_kernel_image;
860 const struct firmware *assp_minisrc_image;
861 };
862
863 /*
864 * pci ids
865 */
866 static struct pci_device_id snd_m3_ids[] = {
867 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
868 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
869 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
870 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
871 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
872 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
873 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
874 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
875 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
876 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
877 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
878 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
879 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
880 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
881 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
882 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
883 {0,},
884 };
885
886 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
887
888 static struct snd_pci_quirk m3_amp_quirk_list[] __devinitdata = {
889 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
890 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
891 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
892 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
893 { } /* END */
894 };
895
896 static struct snd_pci_quirk m3_irda_quirk_list[] __devinitdata = {
897 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
898 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
899 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
900 { } /* END */
901 };
902
903 /* hardware volume quirks */
904 static struct snd_pci_quirk m3_hv_quirk_list[] __devinitdata = {
905 /* Allegro chips */
906 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
907 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
908 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
909 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
910 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
911 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
912 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
913 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
914 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
915 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
916 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
917 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
918 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
919 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
920 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
921 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
922 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
923 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
924 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
925 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
926 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
927 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
928 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
929 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
930 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
931 SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
932 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
933 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
934 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
935 SND_PCI_QUIRK(0x107B, 0x340A, NULL,
936 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
937 SND_PCI_QUIRK(0x107B, 0x3450, NULL,
938 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
939 SND_PCI_QUIRK(0x109F, 0x3134, NULL,
940 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
941 SND_PCI_QUIRK(0x109F, 0x3161, NULL,
942 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
943 SND_PCI_QUIRK(0x144D, 0x3280, NULL,
944 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
945 SND_PCI_QUIRK(0x144D, 0x3281, NULL,
946 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
947 SND_PCI_QUIRK(0x144D, 0xC002, NULL,
948 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
949 SND_PCI_QUIRK(0x144D, 0xC003, NULL,
950 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
951 SND_PCI_QUIRK(0x1509, 0x1740, NULL,
952 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
953 SND_PCI_QUIRK(0x1610, 0x0010, NULL,
954 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
955 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
956 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
957 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
958 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
959 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
960 /* Maestro3 chips */
961 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
962 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
963 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
964 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
965 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
966 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
967 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
968 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
969 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
970 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
971 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
972 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
973 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
974 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
975 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
976 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
977 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
978 { } /* END */
979 };
980
981 /* HP Omnibook quirks */
982 static struct snd_pci_quirk m3_omnibook_quirk_list[] __devinitdata = {
983 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
984 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
985 { } /* END */
986 };
987
988 /*
989 * lowlevel functions
990 */
991
992 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
993 {
994 outw(value, chip->iobase + reg);
995 }
996
997 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
998 {
999 return inw(chip->iobase + reg);
1000 }
1001
1002 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
1003 {
1004 outb(value, chip->iobase + reg);
1005 }
1006
1007 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
1008 {
1009 return inb(chip->iobase + reg);
1010 }
1011
1012 /*
1013 * access 16bit words to the code or data regions of the dsp's memory.
1014 * index addresses 16bit words.
1015 */
1016 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
1017 {
1018 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1019 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1020 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1021 }
1022
1023 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
1024 {
1025 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1026 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1027 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1028 }
1029
1030 static void snd_m3_assp_halt(struct snd_m3 *chip)
1031 {
1032 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1033 msleep(10);
1034 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1035 }
1036
1037 static void snd_m3_assp_continue(struct snd_m3 *chip)
1038 {
1039 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1040 }
1041
1042
1043 /*
1044 * This makes me sad. the maestro3 has lists
1045 * internally that must be packed.. 0 terminates,
1046 * apparently, or maybe all unused entries have
1047 * to be 0, the lists have static lengths set
1048 * by the binary code images.
1049 */
1050
1051 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
1052 {
1053 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1054 list->mem_addr + list->curlen,
1055 val);
1056 return list->curlen++;
1057 }
1058
1059 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
1060 {
1061 u16 val;
1062 int lastindex = list->curlen - 1;
1063
1064 if (index != lastindex) {
1065 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1066 list->mem_addr + lastindex);
1067 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1068 list->mem_addr + index,
1069 val);
1070 }
1071
1072 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1073 list->mem_addr + lastindex,
1074 0);
1075
1076 list->curlen--;
1077 }
1078
1079 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1080 {
1081 chip->timer_users++;
1082 if (chip->timer_users != 1)
1083 return;
1084
1085 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1086 KDATA_TIMER_COUNT_RELOAD,
1087 240);
1088
1089 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1090 KDATA_TIMER_COUNT_CURRENT,
1091 240);
1092
1093 snd_m3_outw(chip,
1094 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1095 HOST_INT_CTRL);
1096 }
1097
1098 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1099 {
1100 chip->timer_users--;
1101 if (chip->timer_users > 0)
1102 return;
1103
1104 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1105 KDATA_TIMER_COUNT_RELOAD,
1106 0);
1107
1108 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1109 KDATA_TIMER_COUNT_CURRENT,
1110 0);
1111
1112 snd_m3_outw(chip,
1113 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1114 HOST_INT_CTRL);
1115 }
1116
1117 /*
1118 * start/stop
1119 */
1120
1121 /* spinlock held! */
1122 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1123 struct snd_pcm_substream *subs)
1124 {
1125 if (! s || ! subs)
1126 return -EINVAL;
1127
1128 snd_m3_inc_timer_users(chip);
1129 switch (subs->stream) {
1130 case SNDRV_PCM_STREAM_PLAYBACK:
1131 chip->dacs_active++;
1132 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1133 s->inst.data + CDATA_INSTANCE_READY, 1);
1134 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1135 KDATA_MIXER_TASK_NUMBER,
1136 chip->dacs_active);
1137 break;
1138 case SNDRV_PCM_STREAM_CAPTURE:
1139 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1140 KDATA_ADC1_REQUEST, 1);
1141 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1142 s->inst.data + CDATA_INSTANCE_READY, 1);
1143 break;
1144 }
1145 return 0;
1146 }
1147
1148 /* spinlock held! */
1149 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1150 struct snd_pcm_substream *subs)
1151 {
1152 if (! s || ! subs)
1153 return -EINVAL;
1154
1155 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1156 s->inst.data + CDATA_INSTANCE_READY, 0);
1157 snd_m3_dec_timer_users(chip);
1158 switch (subs->stream) {
1159 case SNDRV_PCM_STREAM_PLAYBACK:
1160 chip->dacs_active--;
1161 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1162 KDATA_MIXER_TASK_NUMBER,
1163 chip->dacs_active);
1164 break;
1165 case SNDRV_PCM_STREAM_CAPTURE:
1166 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1167 KDATA_ADC1_REQUEST, 0);
1168 break;
1169 }
1170 return 0;
1171 }
1172
1173 static int
1174 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1175 {
1176 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1177 struct m3_dma *s = subs->runtime->private_data;
1178 int err = -EINVAL;
1179
1180 snd_assert(s != NULL, return -ENXIO);
1181
1182 spin_lock(&chip->reg_lock);
1183 switch (cmd) {
1184 case SNDRV_PCM_TRIGGER_START:
1185 case SNDRV_PCM_TRIGGER_RESUME:
1186 if (s->running)
1187 err = -EBUSY;
1188 else {
1189 s->running = 1;
1190 err = snd_m3_pcm_start(chip, s, subs);
1191 }
1192 break;
1193 case SNDRV_PCM_TRIGGER_STOP:
1194 case SNDRV_PCM_TRIGGER_SUSPEND:
1195 if (! s->running)
1196 err = 0; /* should return error? */
1197 else {
1198 s->running = 0;
1199 err = snd_m3_pcm_stop(chip, s, subs);
1200 }
1201 break;
1202 }
1203 spin_unlock(&chip->reg_lock);
1204 return err;
1205 }
1206
1207 /*
1208 * setup
1209 */
1210 static void
1211 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1212 {
1213 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1214 struct snd_pcm_runtime *runtime = subs->runtime;
1215
1216 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1217 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1218 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1219 } else {
1220 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1221 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1222 }
1223 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1224 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1225
1226 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1227 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1228 s->hwptr = 0;
1229 s->count = 0;
1230
1231 #define LO(x) ((x) & 0xffff)
1232 #define HI(x) LO((x) >> 16)
1233
1234 /* host dma buffer pointers */
1235 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1236 s->inst.data + CDATA_HOST_SRC_ADDRL,
1237 LO(s->buffer_addr));
1238
1239 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1240 s->inst.data + CDATA_HOST_SRC_ADDRH,
1241 HI(s->buffer_addr));
1242
1243 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1244 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1245 LO(s->buffer_addr + s->dma_size));
1246
1247 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1248 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1249 HI(s->buffer_addr + s->dma_size));
1250
1251 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1252 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1253 LO(s->buffer_addr));
1254
1255 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1256 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1257 HI(s->buffer_addr));
1258 #undef LO
1259 #undef HI
1260
1261 /* dsp buffers */
1262
1263 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1264 s->inst.data + CDATA_IN_BUF_BEGIN,
1265 dsp_in_buffer);
1266
1267 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1268 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1269 dsp_in_buffer + (dsp_in_size / 2));
1270
1271 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1272 s->inst.data + CDATA_IN_BUF_HEAD,
1273 dsp_in_buffer);
1274
1275 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1276 s->inst.data + CDATA_IN_BUF_TAIL,
1277 dsp_in_buffer);
1278
1279 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1280 s->inst.data + CDATA_OUT_BUF_BEGIN,
1281 dsp_out_buffer);
1282
1283 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1284 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1285 dsp_out_buffer + (dsp_out_size / 2));
1286
1287 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1288 s->inst.data + CDATA_OUT_BUF_HEAD,
1289 dsp_out_buffer);
1290
1291 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1292 s->inst.data + CDATA_OUT_BUF_TAIL,
1293 dsp_out_buffer);
1294 }
1295
1296 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1297 struct snd_pcm_runtime *runtime)
1298 {
1299 u32 freq;
1300
1301 /*
1302 * put us in the lists if we're not already there
1303 */
1304 if (! s->in_lists) {
1305 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1306 s->inst.data >> DP_SHIFT_COUNT);
1307 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1308 s->inst.data >> DP_SHIFT_COUNT);
1309 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1310 s->inst.data >> DP_SHIFT_COUNT);
1311 s->in_lists = 1;
1312 }
1313
1314 /* write to 'mono' word */
1315 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1316 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1317 runtime->channels == 2 ? 0 : 1);
1318 /* write to '8bit' word */
1319 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1320 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1321 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1322
1323 /* set up dac/adc rate */
1324 freq = ((runtime->rate << 15) + 24000 ) / 48000;
1325 if (freq)
1326 freq--;
1327
1328 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1329 s->inst.data + CDATA_FREQUENCY,
1330 freq);
1331 }
1332
1333
1334 static const struct play_vals {
1335 u16 addr, val;
1336 } pv[] = {
1337 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1338 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1339 {SRC3_DIRECTION_OFFSET, 0} ,
1340 /* +1, +2 are stereo/16 bit */
1341 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1342 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1343 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1344 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1345 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1346 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1347 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1348 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1349 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1350 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1351 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1352 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1353 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1354 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1355 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1356 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1357 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1358 };
1359
1360
1361 /* the mode passed should be already shifted and masked */
1362 static void
1363 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1364 struct snd_pcm_substream *subs)
1365 {
1366 unsigned int i;
1367
1368 /*
1369 * some per client initializers
1370 */
1371
1372 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1373 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1374 s->inst.data + 40 + 8);
1375
1376 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1377 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1378 s->inst.code + MINISRC_COEF_LOC);
1379
1380 /* enable or disable low pass filter? */
1381 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1382 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1383 subs->runtime->rate > 45000 ? 0xff : 0);
1384
1385 /* tell it which way dma is going? */
1386 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1387 s->inst.data + CDATA_DMA_CONTROL,
1388 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1389
1390 /*
1391 * set an armload of static initializers
1392 */
1393 for (i = 0; i < ARRAY_SIZE(pv); i++)
1394 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1395 s->inst.data + pv[i].addr, pv[i].val);
1396 }
1397
1398 /*
1399 * Native record driver
1400 */
1401 static const struct rec_vals {
1402 u16 addr, val;
1403 } rv[] = {
1404 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1405 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1406 {SRC3_DIRECTION_OFFSET, 1} ,
1407 /* +1, +2 are stereo/16 bit */
1408 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1409 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1410 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1411 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1412 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1413 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1414 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1415 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1416 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1417 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1418 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1419 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1420 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1421 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1422 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1423 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1424 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1425 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1426 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1427 };
1428
1429 static void
1430 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1431 {
1432 unsigned int i;
1433
1434 /*
1435 * some per client initializers
1436 */
1437
1438 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1439 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1440 s->inst.data + 40 + 8);
1441
1442 /* tell it which way dma is going? */
1443 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1444 s->inst.data + CDATA_DMA_CONTROL,
1445 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1446 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1447
1448 /*
1449 * set an armload of static initializers
1450 */
1451 for (i = 0; i < ARRAY_SIZE(rv); i++)
1452 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1453 s->inst.data + rv[i].addr, rv[i].val);
1454 }
1455
1456 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1457 struct snd_pcm_hw_params *hw_params)
1458 {
1459 struct m3_dma *s = substream->runtime->private_data;
1460 int err;
1461
1462 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1463 return err;
1464 /* set buffer address */
1465 s->buffer_addr = substream->runtime->dma_addr;
1466 if (s->buffer_addr & 0x3) {
1467 snd_printk(KERN_ERR "oh my, not aligned\n");
1468 s->buffer_addr = s->buffer_addr & ~0x3;
1469 }
1470 return 0;
1471 }
1472
1473 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1474 {
1475 struct m3_dma *s;
1476
1477 if (substream->runtime->private_data == NULL)
1478 return 0;
1479 s = substream->runtime->private_data;
1480 snd_pcm_lib_free_pages(substream);
1481 s->buffer_addr = 0;
1482 return 0;
1483 }
1484
1485 static int
1486 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1487 {
1488 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1489 struct snd_pcm_runtime *runtime = subs->runtime;
1490 struct m3_dma *s = runtime->private_data;
1491
1492 snd_assert(s != NULL, return -ENXIO);
1493
1494 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1495 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1496 return -EINVAL;
1497 if (runtime->rate > 48000 ||
1498 runtime->rate < 8000)
1499 return -EINVAL;
1500
1501 spin_lock_irq(&chip->reg_lock);
1502
1503 snd_m3_pcm_setup1(chip, s, subs);
1504
1505 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1506 snd_m3_playback_setup(chip, s, subs);
1507 else
1508 snd_m3_capture_setup(chip, s, subs);
1509
1510 snd_m3_pcm_setup2(chip, s, runtime);
1511
1512 spin_unlock_irq(&chip->reg_lock);
1513
1514 return 0;
1515 }
1516
1517 /*
1518 * get current pointer
1519 */
1520 static unsigned int
1521 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1522 {
1523 u16 hi = 0, lo = 0;
1524 int retry = 10;
1525 u32 addr;
1526
1527 /*
1528 * try and get a valid answer
1529 */
1530 while (retry--) {
1531 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1532 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1533
1534 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1535 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1536
1537 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1538 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1539 break;
1540 }
1541 addr = lo | ((u32)hi<<16);
1542 return (unsigned int)(addr - s->buffer_addr);
1543 }
1544
1545 static snd_pcm_uframes_t
1546 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1547 {
1548 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1549 unsigned int ptr;
1550 struct m3_dma *s = subs->runtime->private_data;
1551 snd_assert(s != NULL, return 0);
1552
1553 spin_lock(&chip->reg_lock);
1554 ptr = snd_m3_get_pointer(chip, s, subs);
1555 spin_unlock(&chip->reg_lock);
1556 return bytes_to_frames(subs->runtime, ptr);
1557 }
1558
1559
1560 /* update pointer */
1561 /* spinlock held! */
1562 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1563 {
1564 struct snd_pcm_substream *subs = s->substream;
1565 unsigned int hwptr;
1566 int diff;
1567
1568 if (! s->running)
1569 return;
1570
1571 hwptr = snd_m3_get_pointer(chip, s, subs);
1572
1573 /* try to avoid expensive modulo divisions */
1574 if (hwptr >= s->dma_size)
1575 hwptr %= s->dma_size;
1576
1577 diff = s->dma_size + hwptr - s->hwptr;
1578 if (diff >= s->dma_size)
1579 diff %= s->dma_size;
1580
1581 s->hwptr = hwptr;
1582 s->count += diff;
1583
1584 if (s->count >= (signed)s->period_size) {
1585
1586 if (s->count < 2 * (signed)s->period_size)
1587 s->count -= (signed)s->period_size;
1588 else
1589 s->count %= s->period_size;
1590
1591 spin_unlock(&chip->reg_lock);
1592 snd_pcm_period_elapsed(subs);
1593 spin_lock(&chip->reg_lock);
1594 }
1595 }
1596
1597 static void snd_m3_update_hw_volume(unsigned long private_data)
1598 {
1599 struct snd_m3 *chip = (struct snd_m3 *) private_data;
1600 int x, val;
1601 unsigned long flags;
1602
1603 /* Figure out which volume control button was pushed,
1604 based on differences from the default register
1605 values. */
1606 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1607
1608 /* Reset the volume control registers. */
1609 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1610 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1611 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1612 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1613
1614 if (!chip->master_switch || !chip->master_volume)
1615 return;
1616
1617 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1618 spin_lock_irqsave(&chip->ac97_lock, flags);
1619
1620 val = chip->ac97->regs[AC97_MASTER_VOL];
1621 switch (x) {
1622 case 0x88:
1623 /* mute */
1624 val ^= 0x8000;
1625 chip->ac97->regs[AC97_MASTER_VOL] = val;
1626 outw(val, chip->iobase + CODEC_DATA);
1627 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1628 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1629 &chip->master_switch->id);
1630 break;
1631 case 0xaa:
1632 /* volume up */
1633 if ((val & 0x7f) > 0)
1634 val--;
1635 if ((val & 0x7f00) > 0)
1636 val -= 0x0100;
1637 chip->ac97->regs[AC97_MASTER_VOL] = val;
1638 outw(val, chip->iobase + CODEC_DATA);
1639 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1640 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1641 &chip->master_volume->id);
1642 break;
1643 case 0x66:
1644 /* volume down */
1645 if ((val & 0x7f) < 0x1f)
1646 val++;
1647 if ((val & 0x7f00) < 0x1f00)
1648 val += 0x0100;
1649 chip->ac97->regs[AC97_MASTER_VOL] = val;
1650 outw(val, chip->iobase + CODEC_DATA);
1651 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1652 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1653 &chip->master_volume->id);
1654 break;
1655 }
1656 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1657 }
1658
1659 static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1660 {
1661 struct snd_m3 *chip = dev_id;
1662 u8 status;
1663 int i;
1664
1665 status = inb(chip->iobase + HOST_INT_STATUS);
1666
1667 if (status == 0xff)
1668 return IRQ_NONE;
1669
1670 if (status & HV_INT_PENDING)
1671 tasklet_hi_schedule(&chip->hwvol_tq);
1672
1673 /*
1674 * ack an assp int if its running
1675 * and has an int pending
1676 */
1677 if (status & ASSP_INT_PENDING) {
1678 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1679 if (!(ctl & STOP_ASSP_CLOCK)) {
1680 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1681 if (ctl & DSP2HOST_REQ_TIMER) {
1682 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1683 /* update adc/dac info if it was a timer int */
1684 spin_lock(&chip->reg_lock);
1685 for (i = 0; i < chip->num_substreams; i++) {
1686 struct m3_dma *s = &chip->substreams[i];
1687 if (s->running)
1688 snd_m3_update_ptr(chip, s);
1689 }
1690 spin_unlock(&chip->reg_lock);
1691 }
1692 }
1693 }
1694
1695 #if 0 /* TODO: not supported yet */
1696 if ((status & MPU401_INT_PENDING) && chip->rmidi)
1697 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1698 #endif
1699
1700 /* ack ints */
1701 outb(status, chip->iobase + HOST_INT_STATUS);
1702
1703 return IRQ_HANDLED;
1704 }
1705
1706
1707 /*
1708 */
1709
1710 static struct snd_pcm_hardware snd_m3_playback =
1711 {
1712 .info = (SNDRV_PCM_INFO_MMAP |
1713 SNDRV_PCM_INFO_INTERLEAVED |
1714 SNDRV_PCM_INFO_MMAP_VALID |
1715 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1716 /*SNDRV_PCM_INFO_PAUSE |*/
1717 SNDRV_PCM_INFO_RESUME),
1718 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1719 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1720 .rate_min = 8000,
1721 .rate_max = 48000,
1722 .channels_min = 1,
1723 .channels_max = 2,
1724 .buffer_bytes_max = (512*1024),
1725 .period_bytes_min = 64,
1726 .period_bytes_max = (512*1024),
1727 .periods_min = 1,
1728 .periods_max = 1024,
1729 };
1730
1731 static struct snd_pcm_hardware snd_m3_capture =
1732 {
1733 .info = (SNDRV_PCM_INFO_MMAP |
1734 SNDRV_PCM_INFO_INTERLEAVED |
1735 SNDRV_PCM_INFO_MMAP_VALID |
1736 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1737 /*SNDRV_PCM_INFO_PAUSE |*/
1738 SNDRV_PCM_INFO_RESUME),
1739 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1740 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1741 .rate_min = 8000,
1742 .rate_max = 48000,
1743 .channels_min = 1,
1744 .channels_max = 2,
1745 .buffer_bytes_max = (512*1024),
1746 .period_bytes_min = 64,
1747 .period_bytes_max = (512*1024),
1748 .periods_min = 1,
1749 .periods_max = 1024,
1750 };
1751
1752
1753 /*
1754 */
1755
1756 static int
1757 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1758 {
1759 int i;
1760 struct m3_dma *s;
1761
1762 spin_lock_irq(&chip->reg_lock);
1763 for (i = 0; i < chip->num_substreams; i++) {
1764 s = &chip->substreams[i];
1765 if (! s->opened)
1766 goto __found;
1767 }
1768 spin_unlock_irq(&chip->reg_lock);
1769 return -ENOMEM;
1770 __found:
1771 s->opened = 1;
1772 s->running = 0;
1773 spin_unlock_irq(&chip->reg_lock);
1774
1775 subs->runtime->private_data = s;
1776 s->substream = subs;
1777
1778 /* set list owners */
1779 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1780 s->index_list[0] = &chip->mixer_list;
1781 } else
1782 s->index_list[0] = &chip->adc1_list;
1783 s->index_list[1] = &chip->msrc_list;
1784 s->index_list[2] = &chip->dma_list;
1785
1786 return 0;
1787 }
1788
1789 static void
1790 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1791 {
1792 struct m3_dma *s = subs->runtime->private_data;
1793
1794 if (s == NULL)
1795 return; /* not opened properly */
1796
1797 spin_lock_irq(&chip->reg_lock);
1798 if (s->substream && s->running)
1799 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1800 if (s->in_lists) {
1801 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1802 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1803 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1804 s->in_lists = 0;
1805 }
1806 s->running = 0;
1807 s->opened = 0;
1808 spin_unlock_irq(&chip->reg_lock);
1809 }
1810
1811 static int
1812 snd_m3_playback_open(struct snd_pcm_substream *subs)
1813 {
1814 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1815 struct snd_pcm_runtime *runtime = subs->runtime;
1816 int err;
1817
1818 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1819 return err;
1820
1821 runtime->hw = snd_m3_playback;
1822
1823 return 0;
1824 }
1825
1826 static int
1827 snd_m3_playback_close(struct snd_pcm_substream *subs)
1828 {
1829 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1830
1831 snd_m3_substream_close(chip, subs);
1832 return 0;
1833 }
1834
1835 static int
1836 snd_m3_capture_open(struct snd_pcm_substream *subs)
1837 {
1838 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1839 struct snd_pcm_runtime *runtime = subs->runtime;
1840 int err;
1841
1842 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1843 return err;
1844
1845 runtime->hw = snd_m3_capture;
1846
1847 return 0;
1848 }
1849
1850 static int
1851 snd_m3_capture_close(struct snd_pcm_substream *subs)
1852 {
1853 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1854
1855 snd_m3_substream_close(chip, subs);
1856 return 0;
1857 }
1858
1859 /*
1860 * create pcm instance
1861 */
1862
1863 static struct snd_pcm_ops snd_m3_playback_ops = {
1864 .open = snd_m3_playback_open,
1865 .close = snd_m3_playback_close,
1866 .ioctl = snd_pcm_lib_ioctl,
1867 .hw_params = snd_m3_pcm_hw_params,
1868 .hw_free = snd_m3_pcm_hw_free,
1869 .prepare = snd_m3_pcm_prepare,
1870 .trigger = snd_m3_pcm_trigger,
1871 .pointer = snd_m3_pcm_pointer,
1872 };
1873
1874 static struct snd_pcm_ops snd_m3_capture_ops = {
1875 .open = snd_m3_capture_open,
1876 .close = snd_m3_capture_close,
1877 .ioctl = snd_pcm_lib_ioctl,
1878 .hw_params = snd_m3_pcm_hw_params,
1879 .hw_free = snd_m3_pcm_hw_free,
1880 .prepare = snd_m3_pcm_prepare,
1881 .trigger = snd_m3_pcm_trigger,
1882 .pointer = snd_m3_pcm_pointer,
1883 };
1884
1885 static int __devinit
1886 snd_m3_pcm(struct snd_m3 * chip, int device)
1887 {
1888 struct snd_pcm *pcm;
1889 int err;
1890
1891 err = snd_pcm_new(chip->card, chip->card->driver, device,
1892 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1893 if (err < 0)
1894 return err;
1895
1896 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1897 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1898
1899 pcm->private_data = chip;
1900 pcm->info_flags = 0;
1901 strcpy(pcm->name, chip->card->driver);
1902 chip->pcm = pcm;
1903
1904 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1905 snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1906
1907 return 0;
1908 }
1909
1910
1911 /*
1912 * ac97 interface
1913 */
1914
1915 /*
1916 * Wait for the ac97 serial bus to be free.
1917 * return nonzero if the bus is still busy.
1918 */
1919 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1920 {
1921 int i = 10000;
1922
1923 do {
1924 if (! (snd_m3_inb(chip, 0x30) & 1))
1925 return 0;
1926 cpu_relax();
1927 } while (i-- > 0);
1928
1929 snd_printk(KERN_ERR "ac97 serial bus busy\n");
1930 return 1;
1931 }
1932
1933 static unsigned short
1934 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1935 {
1936 struct snd_m3 *chip = ac97->private_data;
1937 unsigned long flags;
1938 unsigned short data = 0xffff;
1939
1940 if (snd_m3_ac97_wait(chip))
1941 goto fail;
1942 spin_lock_irqsave(&chip->ac97_lock, flags);
1943 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1944 if (snd_m3_ac97_wait(chip))
1945 goto fail_unlock;
1946 data = snd_m3_inw(chip, CODEC_DATA);
1947 fail_unlock:
1948 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1949 fail:
1950 return data;
1951 }
1952
1953 static void
1954 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1955 {
1956 struct snd_m3 *chip = ac97->private_data;
1957 unsigned long flags;
1958
1959 if (snd_m3_ac97_wait(chip))
1960 return;
1961 spin_lock_irqsave(&chip->ac97_lock, flags);
1962 snd_m3_outw(chip, val, CODEC_DATA);
1963 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1964 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1965 }
1966
1967
1968 static void snd_m3_remote_codec_config(int io, int isremote)
1969 {
1970 isremote = isremote ? 1 : 0;
1971
1972 outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1973 io + RING_BUS_CTRL_B);
1974 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1975 io + SDO_OUT_DEST_CTRL);
1976 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1977 io + SDO_IN_DEST_CTRL);
1978 }
1979
1980 /*
1981 * hack, returns non zero on err
1982 */
1983 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
1984 {
1985 u16 ret;
1986
1987 if (snd_m3_ac97_wait(chip))
1988 return 1;
1989
1990 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1991
1992 if (snd_m3_ac97_wait(chip))
1993 return 1;
1994
1995 ret = snd_m3_inw(chip, 0x32);
1996
1997 return (ret == 0) || (ret == 0xffff);
1998 }
1999
2000 static void snd_m3_ac97_reset(struct snd_m3 *chip)
2001 {
2002 u16 dir;
2003 int delay1 = 0, delay2 = 0, i;
2004 int io = chip->iobase;
2005
2006 if (chip->allegro_flag) {
2007 /*
2008 * the onboard codec on the allegro seems
2009 * to want to wait a very long time before
2010 * coming back to life
2011 */
2012 delay1 = 50;
2013 delay2 = 800;
2014 } else {
2015 /* maestro3 */
2016 delay1 = 20;
2017 delay2 = 500;
2018 }
2019
2020 for (i = 0; i < 5; i++) {
2021 dir = inw(io + GPIO_DIRECTION);
2022 if (!chip->irda_workaround)
2023 dir |= 0x10; /* assuming pci bus master? */
2024
2025 snd_m3_remote_codec_config(io, 0);
2026
2027 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2028 udelay(20);
2029
2030 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2031 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2032 outw(0, io + GPIO_DATA);
2033 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2034
2035 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2036
2037 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2038 udelay(5);
2039 /* ok, bring back the ac-link */
2040 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2041 outw(~0, io + GPIO_MASK);
2042
2043 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2044
2045 if (! snd_m3_try_read_vendor(chip))
2046 break;
2047
2048 delay1 += 10;
2049 delay2 += 100;
2050
2051 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2052 delay1, delay2);
2053 }
2054
2055 #if 0
2056 /* more gung-ho reset that doesn't
2057 * seem to work anywhere :)
2058 */
2059 tmp = inw(io + RING_BUS_CTRL_A);
2060 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2061 msleep(20);
2062 outw(tmp, io + RING_BUS_CTRL_A);
2063 msleep(50);
2064 #endif
2065 }
2066
2067 static int __devinit snd_m3_mixer(struct snd_m3 *chip)
2068 {
2069 struct snd_ac97_bus *pbus;
2070 struct snd_ac97_template ac97;
2071 struct snd_ctl_elem_id elem_id;
2072 int err;
2073 static struct snd_ac97_bus_ops ops = {
2074 .write = snd_m3_ac97_write,
2075 .read = snd_m3_ac97_read,
2076 };
2077
2078 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2079 return err;
2080
2081 memset(&ac97, 0, sizeof(ac97));
2082 ac97.private_data = chip;
2083 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2084 return err;
2085
2086 /* seems ac97 PCM needs initialization.. hack hack.. */
2087 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2088 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2089 snd_ac97_write(chip->ac97, AC97_PCM, 0);
2090
2091 memset(&elem_id, 0, sizeof(elem_id));
2092 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2093 strcpy(elem_id.name, "Master Playback Switch");
2094 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2095 memset(&elem_id, 0, sizeof(elem_id));
2096 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2097 strcpy(elem_id.name, "Master Playback Volume");
2098 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2099
2100 return 0;
2101 }
2102
2103
2104 #ifdef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL
2105
2106 /*
2107 * DSP Code images
2108 */
2109
2110 static const u16 assp_kernel_image[] = {
2111 0x7980, 0x0030, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x00FB, 0x7980, 0x00DD, 0x7980, 0x03B4,
2112 0x7980, 0x0332, 0x7980, 0x0287, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2113 0x7980, 0x031A, 0x7980, 0x03B4, 0x7980, 0x022F, 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x03B4,
2114 0x7980, 0x03B4, 0x7980, 0x03B4, 0x7980, 0x0063, 0x7980, 0x006B, 0x7980, 0x03B4, 0x7980, 0x03B4,
2115 0xBF80, 0x2C7C, 0x8806, 0x8804, 0xBE40, 0xBC20, 0xAE09, 0x1000, 0xAE0A, 0x0001, 0x6938, 0xEB08,
2116 0x0053, 0x695A, 0xEB08, 0x00D6, 0x0009, 0x8B88, 0x6980, 0xE388, 0x0036, 0xBE30, 0xBC20, 0x6909,
2117 0xB801, 0x9009, 0xBE41, 0xBE41, 0x6928, 0xEB88, 0x0078, 0xBE41, 0xBE40, 0x7980, 0x0038, 0xBE41,
2118 0xBE41, 0x903A, 0x6938, 0xE308, 0x0056, 0x903A, 0xBE41, 0xBE40, 0xEF00, 0x903A, 0x6939, 0xE308,
2119 0x005E, 0x903A, 0xEF00, 0x690B, 0x660C, 0xEF8C, 0x690A, 0x660C, 0x620B, 0x6609, 0xEF00, 0x6910,
2120 0x660F, 0xEF04, 0xE388, 0x0075, 0x690E, 0x660F, 0x6210, 0x660D, 0xEF00, 0x690E, 0x660D, 0xEF00,
2121 0xAE70, 0x0001, 0xBC20, 0xAE27, 0x0001, 0x6939, 0xEB08, 0x005D, 0x6926, 0xB801, 0x9026, 0x0026,
2122 0x8B88, 0x6980, 0xE388, 0x00CB, 0x9028, 0x0D28, 0x4211, 0xE100, 0x007A, 0x4711, 0xE100, 0x00A0,
2123 0x7A80, 0x0063, 0xB811, 0x660A, 0x6209, 0xE304, 0x007A, 0x0C0B, 0x4005, 0x100A, 0xBA01, 0x9012,
2124 0x0C12, 0x4002, 0x7980, 0x00AF, 0x7A80, 0x006B, 0xBE02, 0x620E, 0x660D, 0xBA10, 0xE344, 0x007A,
2125 0x0C10, 0x4005, 0x100E, 0xBA01, 0x9012, 0x0C12, 0x4002, 0x1003, 0xBA02, 0x9012, 0x0C12, 0x4000,
2126 0x1003, 0xE388, 0x00BA, 0x1004, 0x7980, 0x00BC, 0x1004, 0xBA01, 0x9012, 0x0C12, 0x4001, 0x0C05,
2127 0x4003, 0x0C06, 0x4004, 0x1011, 0xBFB0, 0x01FF, 0x9012, 0x0C12, 0x4006, 0xBC20, 0xEF00, 0xAE26,
2128 0x1028, 0x6970, 0xBFD0, 0x0001, 0x9070, 0xE388, 0x007A, 0xAE28, 0x0000, 0xEF00, 0xAE70, 0x0300,
2129 0x0C70, 0xB00C, 0xAE5A, 0x0000, 0xEF00, 0x7A80, 0x038A, 0x697F, 0xB801, 0x907F, 0x0056, 0x8B88,
2130 0x0CA0, 0xB008, 0xAF71, 0xB000, 0x4E71, 0xE200, 0x00F3, 0xAE56, 0x1057, 0x0056, 0x0CA0, 0xB008,
2131 0x8056, 0x7980, 0x03A1, 0x0810, 0xBFA0, 0x1059, 0xE304, 0x03A1, 0x8056, 0x7980, 0x03A1, 0x7A80,
2132 0x038A, 0xBF01, 0xBE43, 0xBE59, 0x907C, 0x6937, 0xE388, 0x010D, 0xBA01, 0xE308, 0x010C, 0xAE71,
2133 0x0004, 0x0C71, 0x5000, 0x6936, 0x9037, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80, 0xBF0A,
2134 0x0560, 0xF500, 0xBF0A, 0x0520, 0xB900, 0xBB17, 0x90A0, 0x6917, 0xE388, 0x0148, 0x0D17, 0xE100,
2135 0x0127, 0xBF0C, 0x0578, 0xBF0D, 0x057C, 0x7980, 0x012B, 0xBF0C, 0x0538, 0xBF0D, 0x053C, 0x6900,
2136 0xE308, 0x0135, 0x8B8C, 0xBE59, 0xBB07, 0x90A0, 0xBC20, 0x7980, 0x0157, 0x030C, 0x8B8B, 0xB903,
2137 0x8809, 0xBEC6, 0x013E, 0x69AC, 0x90AB, 0x69AD, 0x90AB, 0x0813, 0x660A, 0xE344, 0x0144, 0x0309,
2138 0x830C, 0xBC20, 0x7980, 0x0157, 0x6955, 0xE388, 0x0157, 0x7C38, 0xBF0B, 0x0578, 0xF500, 0xBF0B,
2139 0x0538, 0xB907, 0x8809, 0xBEC6, 0x0156, 0x10AB, 0x90AA, 0x6974, 0xE388, 0x0163, 0xAE72, 0x0540,
2140 0xF500, 0xAE72, 0x0500, 0xAE61, 0x103B, 0x7A80, 0x02F6, 0x6978, 0xE388, 0x0182, 0x8B8C, 0xBF0C,
2141 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA20, 0x8812, 0x733D, 0x7A80, 0x0380, 0x733E, 0x7A80, 0x0380,
2142 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA2C, 0x8812, 0x733F, 0x7A80, 0x0380, 0x7340,
2143 0x7A80, 0x0380, 0x6975, 0xE388, 0x018E, 0xAE72, 0x0548, 0xF500, 0xAE72, 0x0508, 0xAE61, 0x1041,
2144 0x7A80, 0x02F6, 0x6979, 0xE388, 0x01AD, 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA18,
2145 0x8812, 0x7343, 0x7A80, 0x0380, 0x7344, 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40,
2146 0x0814, 0xBA24, 0x8812, 0x7345, 0x7A80, 0x0380, 0x7346, 0x7A80, 0x0380, 0x6976, 0xE388, 0x01B9,
2147 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x1047, 0x7A80, 0x02F6, 0x697A, 0xE388, 0x01D8,
2148 0x8B8C, 0xBF0C, 0x0560, 0xE500, 0x7C40, 0x0814, 0xBA08, 0x8812, 0x7349, 0x7A80, 0x0380, 0x734A,
2149 0x7A80, 0x0380, 0x8B8C, 0xBF0C, 0x056C, 0xE500, 0x7C40, 0x0814, 0xBA14, 0x8812, 0x734B, 0x7A80,
2150 0x0380, 0x734C, 0x7A80, 0x0380, 0xBC21, 0xAE1C, 0x1090, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40,
2151 0x0812, 0xB804, 0x8813, 0x8B8D, 0xBF0D, 0x056C, 0xE500, 0x7C40, 0x0815, 0xB804, 0x8811, 0x7A80,
2152 0x034A, 0x8B8A, 0xBF0A, 0x0560, 0xE500, 0x7C40, 0x731F, 0xB903, 0x8809, 0xBEC6, 0x01F9, 0x548A,
2153 0xBE03, 0x98A0, 0x7320, 0xB903, 0x8809, 0xBEC6, 0x0201, 0x548A, 0xBE03, 0x98A0, 0x1F20, 0x2F1F,
2154 0x9826, 0xBC20, 0x6935, 0xE388, 0x03A1, 0x6933, 0xB801, 0x9033, 0xBFA0, 0x02EE, 0xE308, 0x03A1,
2155 0x9033, 0xBF00, 0x6951, 0xE388, 0x021F, 0x7334, 0xBE80, 0x5760, 0xBE03, 0x9F7E, 0xBE59, 0x9034,
2156 0x697E, 0x0D51, 0x9013, 0xBC20, 0x695C, 0xE388, 0x03A1, 0x735E, 0xBE80, 0x5760, 0xBE03, 0x9F7E,
2157 0xBE59, 0x905E, 0x697E, 0x0D5C, 0x9013, 0x7980, 0x03A1, 0x7A80, 0x038A, 0xBF01, 0xBE43, 0x6977,
2158 0xE388, 0x024E, 0xAE61, 0x104D, 0x0061, 0x8B88, 0x6980, 0xE388, 0x024E, 0x9071, 0x0D71, 0x000B,
2159 0xAFA0, 0x8010, 0xAFA0, 0x8010, 0x0810, 0x660A, 0xE308, 0x0249, 0x0009, 0x0810, 0x660C, 0xE388,
2160 0x024E, 0x800B, 0xBC20, 0x697B, 0xE388, 0x03A1, 0xBF0A, 0x109E, 0x8B8A, 0xAF80, 0x8014, 0x4C80,
2161 0xE100, 0x0266, 0x697C, 0xBF90, 0x0560, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0564, 0x9073, 0x0473,
2162 0x7980, 0x0270, 0x697C, 0xBF90, 0x0520, 0x9072, 0x0372, 0x697C, 0xBF90, 0x0524, 0x9073, 0x0473,
2163 0x697C, 0xB801, 0x907C, 0xBF0A, 0x10FD, 0x8B8A, 0xAF80, 0x8010, 0x734F, 0x548A, 0xBE03, 0x9880,
2164 0xBC21, 0x7326, 0x548B, 0xBE03, 0x618B, 0x988C, 0xBE03, 0x6180, 0x9880, 0x7980, 0x03A1, 0x7A80,
2165 0x038A, 0x0D28, 0x4711, 0xE100, 0x02BE, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388, 0x02B6,
2166 0xBFA0, 0x0800, 0xE388, 0x02B2, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02A3, 0x6909,
2167 0x900B, 0x7980, 0x02A5, 0xAF0B, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100, 0x02ED,
2168 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x6909, 0x900B, 0x7980, 0x02B8, 0xAF0B, 0x4005,
2169 0xAF05, 0x4003, 0xAF06, 0x4004, 0x7980, 0x02ED, 0xAF12, 0x4006, 0x6912, 0xBFB0, 0x0C00, 0xE388,
2170 0x02E7, 0xBFA0, 0x0800, 0xE388, 0x02E3, 0x6912, 0xBFB0, 0x0C00, 0xBFA0, 0x0400, 0xE388, 0x02D4,
2171 0x690D, 0x9010, 0x7980, 0x02D6, 0xAF10, 0x4005, 0x6901, 0x9005, 0x6902, 0x9006, 0x4311, 0xE100,
2172 0x02ED, 0x6911, 0xBFC0, 0x2000, 0x9011, 0x7980, 0x02ED, 0x690D, 0x9010, 0x7980, 0x02E9, 0xAF10,
2173 0x4005, 0xAF05, 0x4003, 0xAF06, 0x4004, 0xBC20, 0x6970, 0x9071, 0x7A80, 0x0078, 0x6971, 0x9070,
2174 0x7980, 0x03A1, 0xBC20, 0x0361, 0x8B8B, 0x6980, 0xEF88, 0x0272, 0x0372, 0x7804, 0x9071, 0x0D71,
2175 0x8B8A, 0x000B, 0xB903, 0x8809, 0xBEC6, 0x0309, 0x69A8, 0x90AB, 0x69A8, 0x90AA, 0x0810, 0x660A,
2176 0xE344, 0x030F, 0x0009, 0x0810, 0x660C, 0xE388, 0x0314, 0x800B, 0xBC20, 0x6961, 0xB801, 0x9061,
2177 0x7980, 0x02F7, 0x7A80, 0x038A, 0x5D35, 0x0001, 0x6934, 0xB801, 0x9034, 0xBF0A, 0x109E, 0x8B8A,
2178 0xAF80, 0x8014, 0x4880, 0xAE72, 0x0550, 0xF500, 0xAE72, 0x0510, 0xAE61, 0x1051, 0x7A80, 0x02F6,
2179 0x7980, 0x03A1, 0x7A80, 0x038A, 0x5D35, 0x0002, 0x695E, 0xB801, 0x905E, 0xBF0A, 0x109E, 0x8B8A,
2180 0xAF80, 0x8014, 0x4780, 0xAE72, 0x0558, 0xF500, 0xAE72, 0x0518, 0xAE61, 0x105C, 0x7A80, 0x02F6,
2181 0x7980, 0x03A1, 0x001C, 0x8B88, 0x6980, 0xEF88, 0x901D, 0x0D1D, 0x100F, 0x6610, 0xE38C, 0x0358,
2182 0x690E, 0x6610, 0x620F, 0x660D, 0xBA0F, 0xE301, 0x037A, 0x0410, 0x8B8A, 0xB903, 0x8809, 0xBEC6,
2183 0x036C, 0x6A8C, 0x61AA, 0x98AB, 0x6A8C, 0x61AB, 0x98AD, 0x6A8C, 0x61AD, 0x98A9, 0x6A8C, 0x61A9,
2184 0x98AA, 0x7C04, 0x8B8B, 0x7C04, 0x8B8D, 0x7C04, 0x8B89, 0x7C04, 0x0814, 0x660E, 0xE308, 0x0379,
2185 0x040D, 0x8410, 0xBC21, 0x691C, 0xB801, 0x901C, 0x7980, 0x034A, 0xB903, 0x8809, 0x8B8A, 0xBEC6,
2186 0x0388, 0x54AC, 0xBE03, 0x618C, 0x98AA, 0xEF00, 0xBC20, 0xBE46, 0x0809, 0x906B, 0x080A, 0x906C,
2187 0x080B, 0x906D, 0x081A, 0x9062, 0x081B, 0x9063, 0x081E, 0x9064, 0xBE59, 0x881E, 0x8065, 0x8166,
2188 0x8267, 0x8368, 0x8469, 0x856A, 0xEF00, 0xBC20, 0x696B, 0x8809, 0x696C, 0x880A, 0x696D, 0x880B,
2189 0x6962, 0x881A, 0x6963, 0x881B, 0x6964, 0x881E, 0x0065, 0x0166, 0x0267, 0x0368, 0x0469, 0x056A,
2190 0xBE3A,
2191 };
2192
2193 /*
2194 * Mini sample rate converter code image
2195 * that is to be loaded at 0x400 on the DSP.
2196 */
2197 static const u16 assp_minisrc_image[] = {
2198
2199 0xBF80, 0x101E, 0x906E, 0x006E, 0x8B88, 0x6980, 0xEF88, 0x906F, 0x0D6F, 0x6900, 0xEB08, 0x0412,
2200 0xBC20, 0x696E, 0xB801, 0x906E, 0x7980, 0x0403, 0xB90E, 0x8807, 0xBE43, 0xBF01, 0xBE47, 0xBE41,
2201 0x7A80, 0x002A, 0xBE40, 0x3029, 0xEFCC, 0xBE41, 0x7A80, 0x0028, 0xBE40, 0x3028, 0xEFCC, 0x6907,
2202 0xE308, 0x042A, 0x6909, 0x902C, 0x7980, 0x042C, 0x690D, 0x902C, 0x1009, 0x881A, 0x100A, 0xBA01,
2203 0x881B, 0x100D, 0x881C, 0x100E, 0xBA01, 0x881D, 0xBF80, 0x00ED, 0x881E, 0x050C, 0x0124, 0xB904,
2204 0x9027, 0x6918, 0xE308, 0x04B3, 0x902D, 0x6913, 0xBFA0, 0x7598, 0xF704, 0xAE2D, 0x00FF, 0x8B8D,
2205 0x6919, 0xE308, 0x0463, 0x691A, 0xE308, 0x0456, 0xB907, 0x8809, 0xBEC6, 0x0453, 0x10A9, 0x90AD,
2206 0x7980, 0x047C, 0xB903, 0x8809, 0xBEC6, 0x0460, 0x1889, 0x6C22, 0x90AD, 0x10A9, 0x6E23, 0x6C22,
2207 0x90AD, 0x7980, 0x047C, 0x101A, 0xE308, 0x046F, 0xB903, 0x8809, 0xBEC6, 0x046C, 0x10A9, 0x90A0,
2208 0x90AD, 0x7980, 0x047C, 0xB901, 0x8809, 0xBEC6, 0x047B, 0x1889, 0x6C22, 0x90A0, 0x90AD, 0x10A9,
2209 0x6E23, 0x6C22, 0x90A0, 0x90AD, 0x692D, 0xE308, 0x049C, 0x0124, 0xB703, 0xB902, 0x8818, 0x8B89,
2210 0x022C, 0x108A, 0x7C04, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99A0,
2211 0x108A, 0x90A0, 0x692B, 0x881F, 0x7E80, 0x055B, 0x692A, 0x8809, 0x8B89, 0x99AF, 0x7B99, 0x0484,
2212 0x0124, 0x060F, 0x101B, 0x2013, 0x901B, 0xBFA0, 0x7FFF, 0xE344, 0x04AC, 0x901B, 0x8B89, 0x7A80,
2213 0x051A, 0x6927, 0xBA01, 0x9027, 0x7A80, 0x0523, 0x6927, 0xE308, 0x049E, 0x7980, 0x050F, 0x0624,
2214 0x1026, 0x2013, 0x9026, 0xBFA0, 0x7FFF, 0xE304, 0x04C0, 0x8B8D, 0x7A80, 0x051A, 0x7980, 0x04B4,
2215 0x9026, 0x1013, 0x3026, 0x901B, 0x8B8D, 0x7A80, 0x051A, 0x7A80, 0x0523, 0x1027, 0xBA01, 0x9027,
2216 0xE308, 0x04B4, 0x0124, 0x060F, 0x8B89, 0x691A, 0xE308, 0x04EA, 0x6919, 0xE388, 0x04E0, 0xB903,
2217 0x8809, 0xBEC6, 0x04DD, 0x1FA0, 0x2FAE, 0x98A9, 0x7980, 0x050F, 0xB901, 0x8818, 0xB907, 0x8809,
2218 0xBEC6, 0x04E7, 0x10EE, 0x90A9, 0x7980, 0x050F, 0x6919, 0xE308, 0x04FE, 0xB903, 0x8809, 0xBE46,
2219 0xBEC6, 0x04FA, 0x17A0, 0xBE1E, 0x1FAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0xBE47,
2220 0x7980, 0x050F, 0xB901, 0x8809, 0xBEC6, 0x050E, 0x16A0, 0x26A0, 0xBFB7, 0xFF00, 0xBE1E, 0x1EA0,
2221 0x2EAE, 0xBFBF, 0xFF00, 0xBE13, 0xBFDF, 0x8080, 0x99A9, 0x850C, 0x860F, 0x6907, 0xE388, 0x0516,
2222 0x0D07, 0x8510, 0xBE59, 0x881E, 0xBE4A, 0xEF00, 0x101E, 0x901C, 0x101F, 0x901D, 0x10A0, 0x901E,
2223 0x10A0, 0x901F, 0xEF00, 0x101E, 0x301C, 0x9020, 0x731B, 0x5420, 0xBE03, 0x9825, 0x1025, 0x201C,
2224 0x9025, 0x7325, 0x5414, 0xBE03, 0x8B8E, 0x9880, 0x692F, 0xE388, 0x0539, 0xBE59, 0xBB07, 0x6180,
2225 0x9880, 0x8BA0, 0x101F, 0x301D, 0x9021, 0x731B, 0x5421, 0xBE03, 0x982E, 0x102E, 0x201D, 0x902E,
2226 0x732E, 0x5415, 0xBE03, 0x9880, 0x692F, 0xE388, 0x054F, 0xBE59, 0xBB07, 0x6180, 0x9880, 0x8BA0,
2227 0x6918, 0xEF08, 0x7325, 0x5416, 0xBE03, 0x98A0, 0x732E, 0x5417, 0xBE03, 0x98A0, 0xEF00, 0x8BA0,
2228 0xBEC6, 0x056B, 0xBE59, 0xBB04, 0xAA90, 0xBE04, 0xBE1E, 0x99E0, 0x8BE0, 0x69A0, 0x90D0, 0x69A0,
2229 0x90D0, 0x081F, 0xB805, 0x881F, 0x8B90, 0x69A0, 0x90D0, 0x69A0, 0x9090, 0x8BD0, 0x8BD8, 0xBE1F,
2230 0xEF00, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2231 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
2232 };
2233
2234 static const struct firmware assp_kernel = {
2235 .data = (u8 *)assp_kernel_image,
2236 .size = sizeof assp_kernel_image
2237 };
2238 static const struct firmware assp_minisrc = {
2239 .data = (u8 *)assp_minisrc_image,
2240 .size = sizeof assp_minisrc_image
2241 };
2242
2243 #else /* CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL */
2244
2245 #ifdef __LITTLE_ENDIAN
2246 static inline void snd_m3_convert_from_le(const struct firmware *fw) { }
2247 #else
2248 static void snd_m3_convert_from_le(const struct firmware *fw)
2249 {
2250 int i;
2251 u16 *data = (u16 *)fw->data;
2252
2253 for (i = 0; i < fw->size / 2; ++i)
2254 le16_to_cpus(&data[i]);
2255 }
2256 #endif
2257
2258 #endif /* CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL */
2259
2260
2261 /*
2262 * initialize ASSP
2263 */
2264
2265 #define MINISRC_LPF_LEN 10
2266 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2267 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2268 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2269 };
2270
2271 static void snd_m3_assp_init(struct snd_m3 *chip)
2272 {
2273 unsigned int i;
2274 u16 *data;
2275
2276 /* zero kernel data */
2277 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2278 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2279 KDATA_BASE_ADDR + i, 0);
2280
2281 /* zero mixer data? */
2282 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2283 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2284 KDATA_BASE_ADDR2 + i, 0);
2285
2286 /* init dma pointer */
2287 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2288 KDATA_CURRENT_DMA,
2289 KDATA_DMA_XFER0);
2290
2291 /* write kernel into code memory.. */
2292 data = (u16 *)chip->assp_kernel_image->data;
2293 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2294 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2295 REV_B_CODE_MEMORY_BEGIN + i, data[i]);
2296 }
2297
2298 /*
2299 * We only have this one client and we know that 0x400
2300 * is free in our kernel's mem map, so lets just
2301 * drop it there. It seems that the minisrc doesn't
2302 * need vectors, so we won't bother with them..
2303 */
2304 data = (u16 *)chip->assp_minisrc_image->data;
2305 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2306 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2307 0x400 + i, data[i]);
2308 }
2309
2310 /*
2311 * write the coefficients for the low pass filter?
2312 */
2313 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2314 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2315 0x400 + MINISRC_COEF_LOC + i,
2316 minisrc_lpf[i]);
2317 }
2318
2319 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2320 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2321 0x8000);
2322
2323 /*
2324 * the minisrc is the only thing on
2325 * our task list..
2326 */
2327 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2328 KDATA_TASK0,
2329 0x400);
2330
2331 /*
2332 * init the mixer number..
2333 */
2334
2335 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2336 KDATA_MIXER_TASK_NUMBER,0);
2337
2338 /*
2339 * EXTREME KERNEL MASTER VOLUME
2340 */
2341 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2342 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2343 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2344 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2345
2346 chip->mixer_list.curlen = 0;
2347 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2348 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2349 chip->adc1_list.curlen = 0;
2350 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2351 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2352 chip->dma_list.curlen = 0;
2353 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2354 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2355 chip->msrc_list.curlen = 0;
2356 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2357 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2358 }
2359
2360
2361 static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2362 {
2363 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2364 MINISRC_IN_BUFFER_SIZE / 2 +
2365 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2366 int address, i;
2367
2368 /*
2369 * the revb memory map has 0x1100 through 0x1c00
2370 * free.
2371 */
2372
2373 /*
2374 * align instance address to 256 bytes so that its
2375 * shifted list address is aligned.
2376 * list address = (mem address >> 1) >> 7;
2377 */
2378 data_bytes = ALIGN(data_bytes, 256);
2379 address = 0x1100 + ((data_bytes/2) * index);
2380
2381 if ((address + (data_bytes/2)) >= 0x1c00) {
2382 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
2383 data_bytes, index, address);
2384 return -ENOMEM;
2385 }
2386
2387 s->number = index;
2388 s->inst.code = 0x400;
2389 s->inst.data = address;
2390
2391 for (i = data_bytes / 2; i > 0; address++, i--) {
2392 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2393 address, 0);
2394 }
2395
2396 return 0;
2397 }
2398
2399
2400 /*
2401 * this works for the reference board, have to find
2402 * out about others
2403 *
2404 * this needs more magic for 4 speaker, but..
2405 */
2406 static void
2407 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2408 {
2409 int io = chip->iobase;
2410 u16 gpo, polarity;
2411
2412 if (! chip->external_amp)
2413 return;
2414
2415 polarity = enable ? 0 : 1;
2416 polarity = polarity << chip->amp_gpio;
2417 gpo = 1 << chip->amp_gpio;
2418
2419 outw(~gpo, io + GPIO_MASK);
2420
2421 outw(inw(io + GPIO_DIRECTION) | gpo,
2422 io + GPIO_DIRECTION);
2423
2424 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2425 io + GPIO_DATA);
2426
2427 outw(0xffff, io + GPIO_MASK);
2428 }
2429
2430 static int
2431 snd_m3_chip_init(struct snd_m3 *chip)
2432 {
2433 struct pci_dev *pcidev = chip->pci;
2434 unsigned long io = chip->iobase;
2435 u32 n;
2436 u16 w;
2437 u8 t; /* makes as much sense as 'n', no? */
2438
2439 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2440 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2441 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2442 DISABLE_LEGACY);
2443 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2444
2445 if (chip->is_omnibook) {
2446 /*
2447 * Volume buttons on some HP OmniBook laptops don't work
2448 * correctly. This makes them work for the most part.
2449 *
2450 * Volume up and down buttons on the laptop side work.
2451 * Fn+cursor_up (volme up) works.
2452 * Fn+cursor_down (volume down) doesn't work.
2453 * Fn+F7 (mute) works acts as volume up.
2454 */
2455 outw(~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_MASK);
2456 outw(inw(io + GPIO_DIRECTION) & ~(GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DIRECTION);
2457 outw((GPI_VOL_DOWN|GPI_VOL_UP), io + GPIO_DATA);
2458 outw(0xffff, io + GPIO_MASK);
2459 }
2460 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2461 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2462 n |= chip->hv_config;
2463 /* For some reason we must always use reduced debounce. */
2464 n |= REDUCED_DEBOUNCE;
2465 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2466 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2467
2468 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2469 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2470 n &= ~INT_CLK_SELECT;
2471 if (!chip->allegro_flag) {
2472 n &= ~INT_CLK_MULT_ENABLE;
2473 n |= INT_CLK_SRC_NOT_PCI;
2474 }
2475 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2476 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2477
2478 if (chip->allegro_flag) {
2479 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2480 n |= IN_CLK_12MHZ_SELECT;
2481 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2482 }
2483
2484 t = inb(chip->iobase + ASSP_CONTROL_A);
2485 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2486 t |= ASSP_CLK_49MHZ_SELECT;
2487 t |= ASSP_0_WS_ENABLE;
2488 outb(t, chip->iobase + ASSP_CONTROL_A);
2489
2490 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2491 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2492
2493 outb(0x00, io + HARDWARE_VOL_CTRL);
2494 outb(0x88, io + SHADOW_MIX_REG_VOICE);
2495 outb(0x88, io + HW_VOL_COUNTER_VOICE);
2496 outb(0x88, io + SHADOW_MIX_REG_MASTER);
2497 outb(0x88, io + HW_VOL_COUNTER_MASTER);
2498
2499 return 0;
2500 }
2501
2502 static void
2503 snd_m3_enable_ints(struct snd_m3 *chip)
2504 {
2505 unsigned long io = chip->iobase;
2506 unsigned short val;
2507
2508 /* TODO: MPU401 not supported yet */
2509 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2510 if (chip->hv_config & HV_CTRL_ENABLE)
2511 val |= HV_INT_ENABLE;
2512 outw(val, io + HOST_INT_CTRL);
2513 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2514 io + ASSP_CONTROL_C);
2515 }
2516
2517
2518 /*
2519 */
2520
2521 static int snd_m3_free(struct snd_m3 *chip)
2522 {
2523 struct m3_dma *s;
2524 int i;
2525
2526 if (chip->substreams) {
2527 spin_lock_irq(&chip->reg_lock);
2528 for (i = 0; i < chip->num_substreams; i++) {
2529 s = &chip->substreams[i];
2530 /* check surviving pcms; this should not happen though.. */
2531 if (s->substream && s->running)
2532 snd_m3_pcm_stop(chip, s, s->substream);
2533 }
2534 spin_unlock_irq(&chip->reg_lock);
2535 kfree(chip->substreams);
2536 }
2537 if (chip->iobase) {
2538 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2539 }
2540
2541 #ifdef CONFIG_PM
2542 vfree(chip->suspend_mem);
2543 #endif
2544
2545 if (chip->irq >= 0)
2546 free_irq(chip->irq, chip);
2547
2548 if (chip->iobase)
2549 pci_release_regions(chip->pci);
2550
2551 #ifndef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL
2552 release_firmware(chip->assp_kernel_image);
2553 release_firmware(chip->assp_minisrc_image);
2554 #endif
2555
2556 pci_disable_device(chip->pci);
2557 kfree(chip);
2558 return 0;
2559 }
2560
2561
2562 /*
2563 * APM support
2564 */
2565 #ifdef CONFIG_PM
2566 static int m3_suspend(struct pci_dev *pci, pm_message_t state)
2567 {
2568 struct snd_card *card = pci_get_drvdata(pci);
2569 struct snd_m3 *chip = card->private_data;
2570 int i, dsp_index;
2571
2572 if (chip->suspend_mem == NULL)
2573 return 0;
2574
2575 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2576 snd_pcm_suspend_all(chip->pcm);
2577 snd_ac97_suspend(chip->ac97);
2578
2579 msleep(10); /* give the assp a chance to idle.. */
2580
2581 snd_m3_assp_halt(chip);
2582
2583 /* save dsp image */
2584 dsp_index = 0;
2585 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2586 chip->suspend_mem[dsp_index++] =
2587 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2588 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2589 chip->suspend_mem[dsp_index++] =
2590 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2591
2592 pci_disable_device(pci);
2593 pci_save_state(pci);
2594 pci_set_power_state(pci, pci_choose_state(pci, state));
2595 return 0;
2596 }
2597
2598 static int m3_resume(struct pci_dev *pci)
2599 {
2600 struct snd_card *card = pci_get_drvdata(pci);
2601 struct snd_m3 *chip = card->private_data;
2602 int i, dsp_index;
2603
2604 if (chip->suspend_mem == NULL)
2605 return 0;
2606
2607 pci_set_power_state(pci, PCI_D0);
2608 pci_restore_state(pci);
2609 if (pci_enable_device(pci) < 0) {
2610 printk(KERN_ERR "maestor3: pci_enable_device failed, "
2611 "disabling device\n");
2612 snd_card_disconnect(card);
2613 return -EIO;
2614 }
2615 pci_set_master(pci);
2616
2617 /* first lets just bring everything back. .*/
2618 snd_m3_outw(chip, 0, 0x54);
2619 snd_m3_outw(chip, 0, 0x56);
2620
2621 snd_m3_chip_init(chip);
2622 snd_m3_assp_halt(chip);
2623 snd_m3_ac97_reset(chip);
2624
2625 /* restore dsp image */
2626 dsp_index = 0;
2627 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2628 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2629 chip->suspend_mem[dsp_index++]);
2630 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2631 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2632 chip->suspend_mem[dsp_index++]);
2633
2634 /* tell the dma engine to restart itself */
2635 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2636 KDATA_DMA_ACTIVE, 0);
2637
2638 /* restore ac97 registers */
2639 snd_ac97_resume(chip->ac97);
2640
2641 snd_m3_assp_continue(chip);
2642 snd_m3_enable_ints(chip);
2643 snd_m3_amp_enable(chip, 1);
2644
2645 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2646 return 0;
2647 }
2648 #endif /* CONFIG_PM */
2649
2650
2651 /*
2652 */
2653
2654 static int snd_m3_dev_free(struct snd_device *device)
2655 {
2656 struct snd_m3 *chip = device->device_data;
2657 return snd_m3_free(chip);
2658 }
2659
2660 static int __devinit
2661 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2662 int enable_amp,
2663 int amp_gpio,
2664 struct snd_m3 **chip_ret)
2665 {
2666 struct snd_m3 *chip;
2667 int i, err;
2668 const struct snd_pci_quirk *quirk;
2669 static struct snd_device_ops ops = {
2670 .dev_free = snd_m3_dev_free,
2671 };
2672
2673 *chip_ret = NULL;
2674
2675 if (pci_enable_device(pci))
2676 return -EIO;
2677
2678 /* check, if we can restrict PCI DMA transfers to 28 bits */
2679 if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
2680 pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
2681 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2682 pci_disable_device(pci);
2683 return -ENXIO;
2684 }
2685
2686 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2687 if (chip == NULL) {
2688 pci_disable_device(pci);
2689 return -ENOMEM;
2690 }
2691
2692 spin_lock_init(&chip->reg_lock);
2693 spin_lock_init(&chip->ac97_lock);
2694
2695 switch (pci->device) {
2696 case PCI_DEVICE_ID_ESS_ALLEGRO:
2697 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2698 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2699 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2700 chip->allegro_flag = 1;
2701 break;
2702 }
2703
2704 chip->card = card;
2705 chip->pci = pci;
2706 chip->irq = -1;
2707
2708 chip->external_amp = enable_amp;
2709 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2710 chip->amp_gpio = amp_gpio;
2711 else {
2712 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2713 if (quirk) {
2714 snd_printdd(KERN_INFO "maestro3: set amp-gpio "
2715 "for '%s'\n", quirk->name);
2716 chip->amp_gpio = quirk->value;
2717 } else if (chip->allegro_flag)
2718 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2719 else /* presumably this is for all 'maestro3's.. */
2720 chip->amp_gpio = GPO_EXT_AMP_M3;
2721 }
2722
2723 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2724 if (quirk) {
2725 snd_printdd(KERN_INFO "maestro3: enabled irda workaround "
2726 "for '%s'\n", quirk->name);
2727 chip->irda_workaround = 1;
2728 }
2729 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2730 if (quirk)
2731 chip->hv_config = quirk->value;
2732 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2733 chip->is_omnibook = 1;
2734
2735 chip->num_substreams = NR_DSPS;
2736 chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2737 GFP_KERNEL);
2738 if (chip->substreams == NULL) {
2739 kfree(chip);
2740 pci_disable_device(pci);
2741 return -ENOMEM;
2742 }
2743
2744 #ifdef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL
2745 chip->assp_kernel_image = &assp_kernel;
2746 #else
2747 err = request_firmware(&chip->assp_kernel_image,
2748 "ess/maestro3_assp_kernel.fw", &pci->dev);
2749 if (err < 0) {
2750 snd_m3_free(chip);
2751 return err;
2752 } else
2753 snd_m3_convert_from_le(chip->assp_kernel_image);
2754 #endif
2755
2756 #ifdef CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL
2757 chip->assp_minisrc_image = &assp_minisrc;
2758 #else
2759 err = request_firmware(&chip->assp_minisrc_image,
2760 "ess/maestro3_assp_minisrc.fw", &pci->dev);
2761 if (err < 0) {
2762 snd_m3_free(chip);
2763 return err;
2764 } else
2765 snd_m3_convert_from_le(chip->assp_minisrc_image);
2766 #endif
2767
2768 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2769 snd_m3_free(chip);
2770 return err;
2771 }
2772 chip->iobase = pci_resource_start(pci, 0);
2773
2774 /* just to be sure */
2775 pci_set_master(pci);
2776
2777 snd_m3_chip_init(chip);
2778 snd_m3_assp_halt(chip);
2779
2780 snd_m3_ac97_reset(chip);
2781
2782 snd_m3_amp_enable(chip, 1);
2783
2784 tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2785
2786 if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2787 card->driver, chip)) {
2788 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2789 snd_m3_free(chip);
2790 return -ENOMEM;
2791 }
2792 chip->irq = pci->irq;
2793
2794 #ifdef CONFIG_PM
2795 chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2796 if (chip->suspend_mem == NULL)
2797 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2798 #endif
2799
2800 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2801 snd_m3_free(chip);
2802 return err;
2803 }
2804
2805 if ((err = snd_m3_mixer(chip)) < 0)
2806 return err;
2807
2808 for (i = 0; i < chip->num_substreams; i++) {
2809 struct m3_dma *s = &chip->substreams[i];
2810 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2811 return err;
2812 }
2813
2814 if ((err = snd_m3_pcm(chip, 0)) < 0)
2815 return err;
2816
2817 snd_m3_enable_ints(chip);
2818 snd_m3_assp_continue(chip);
2819
2820 snd_card_set_dev(card, &pci->dev);
2821
2822 *chip_ret = chip;
2823
2824 return 0;
2825 }
2826
2827 /*
2828 */
2829 static int __devinit
2830 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2831 {
2832 static int dev;
2833 struct snd_card *card;
2834 struct snd_m3 *chip;
2835 int err;
2836
2837 /* don't pick up modems */
2838 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2839 return -ENODEV;
2840
2841 if (dev >= SNDRV_CARDS)
2842 return -ENODEV;
2843 if (!enable[dev]) {
2844 dev++;
2845 return -ENOENT;
2846 }
2847
2848 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2849 if (card == NULL)
2850 return -ENOMEM;
2851
2852 switch (pci->device) {
2853 case PCI_DEVICE_ID_ESS_ALLEGRO:
2854 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2855 strcpy(card->driver, "Allegro");
2856 break;
2857 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2858 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2859 strcpy(card->driver, "Canyon3D-2");
2860 break;
2861 default:
2862 strcpy(card->driver, "Maestro3");
2863 break;
2864 }
2865
2866 if ((err = snd_m3_create(card, pci,
2867 external_amp[dev],
2868 amp_gpio[dev],
2869 &chip)) < 0) {
2870 snd_card_free(card);
2871 return err;
2872 }
2873 card->private_data = chip;
2874
2875 sprintf(card->shortname, "ESS %s PCI", card->driver);
2876 sprintf(card->longname, "%s at 0x%lx, irq %d",
2877 card->shortname, chip->iobase, chip->irq);
2878
2879 if ((err = snd_card_register(card)) < 0) {
2880 snd_card_free(card);
2881 return err;
2882 }
2883
2884 #if 0 /* TODO: not supported yet */
2885 /* TODO enable MIDI IRQ and I/O */
2886 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2887 chip->iobase + MPU401_DATA_PORT,
2888 MPU401_INFO_INTEGRATED,
2889 chip->irq, 0, &chip->rmidi);
2890 if (err < 0)
2891 printk(KERN_WARNING "maestro3: no MIDI support.\n");
2892 #endif
2893
2894 pci_set_drvdata(pci, card);
2895 dev++;
2896 return 0;
2897 }
2898
2899 static void __devexit snd_m3_remove(struct pci_dev *pci)
2900 {
2901 snd_card_free(pci_get_drvdata(pci));
2902 pci_set_drvdata(pci, NULL);
2903 }
2904
2905 static struct pci_driver driver = {
2906 .name = "Maestro3",
2907 .id_table = snd_m3_ids,
2908 .probe = snd_m3_probe,
2909 .remove = __devexit_p(snd_m3_remove),
2910 #ifdef CONFIG_PM
2911 .suspend = m3_suspend,
2912 .resume = m3_resume,
2913 #endif
2914 };
2915
2916 static int __init alsa_card_m3_init(void)
2917 {
2918 return pci_register_driver(&driver);
2919 }
2920
2921 static void __exit alsa_card_m3_exit(void)
2922 {
2923 pci_unregister_driver(&driver);
2924 }
2925
2926 module_init(alsa_card_m3_init)
2927 module_exit(alsa_card_m3_exit)
Support for the Chinese Samsung S3C2440 based development boards