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Merge branch 'misc' into release
[linux-2.6/mini2440.git] / arch / x86 / kernel / amd_iommu.c
blob0a60d60ed036b264e6d4c05174dfc3b464574852
1 /*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/scatterlist.h>
24 #include <linux/iommu-helper.h>
25 #include <asm/proto.h>
26 #include <asm/iommu.h>
27 #include <asm/amd_iommu_types.h>
28 #include <asm/amd_iommu.h>
29
30 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
31
32 #define EXIT_LOOP_COUNT 10000000
33
34 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
35
36 /* A list of preallocated protection domains */
37 static LIST_HEAD(iommu_pd_list);
38 static DEFINE_SPINLOCK(iommu_pd_list_lock);
39
40 /*
41 * general struct to manage commands send to an IOMMU
42 */
43 struct iommu_cmd {
44 u32 data[4];
45 };
46
47 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
48 struct unity_map_entry *e);
49
50 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
51 static int iommu_has_npcache(struct amd_iommu *iommu)
52 {
53 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
54 }
55
56 /****************************************************************************
57 *
58 * Interrupt handling functions
59 *
60 ****************************************************************************/
61
62 static void iommu_print_event(void *__evt)
63 {
64 u32 *event = __evt;
65 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
66 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
67 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
68 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
69 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
70
71 printk(KERN_ERR "AMD IOMMU: Event logged [");
72
73 switch (type) {
74 case EVENT_TYPE_ILL_DEV:
75 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
76 "address=0x%016llx flags=0x%04x]\n",
77 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
78 address, flags);
79 break;
80 case EVENT_TYPE_IO_FAULT:
81 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
82 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
83 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
84 domid, address, flags);
85 break;
86 case EVENT_TYPE_DEV_TAB_ERR:
87 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
88 "address=0x%016llx flags=0x%04x]\n",
89 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90 address, flags);
91 break;
92 case EVENT_TYPE_PAGE_TAB_ERR:
93 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
94 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
95 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
96 domid, address, flags);
97 break;
98 case EVENT_TYPE_ILL_CMD:
99 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
100 break;
101 case EVENT_TYPE_CMD_HARD_ERR:
102 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
103 "flags=0x%04x]\n", address, flags);
104 break;
105 case EVENT_TYPE_IOTLB_INV_TO:
106 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
107 "address=0x%016llx]\n",
108 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
109 address);
110 break;
111 case EVENT_TYPE_INV_DEV_REQ:
112 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
113 "address=0x%016llx flags=0x%04x]\n",
114 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
115 address, flags);
116 break;
117 default:
118 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
119 }
120 }
121
122 static void iommu_poll_events(struct amd_iommu *iommu)
123 {
124 u32 head, tail;
125 unsigned long flags;
126
127 spin_lock_irqsave(&iommu->lock, flags);
128
129 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
130 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
131
132 while (head != tail) {
133 iommu_print_event(iommu->evt_buf + head);
134 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
135 }
136
137 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
138
139 spin_unlock_irqrestore(&iommu->lock, flags);
140 }
141
142 irqreturn_t amd_iommu_int_handler(int irq, void *data)
143 {
144 struct amd_iommu *iommu;
145
146 list_for_each_entry(iommu, &amd_iommu_list, list)
147 iommu_poll_events(iommu);
148
149 return IRQ_HANDLED;
150 }
151
152 /****************************************************************************
153 *
154 * IOMMU command queuing functions
155 *
156 ****************************************************************************/
157
158 /*
159 * Writes the command to the IOMMUs command buffer and informs the
160 * hardware about the new command. Must be called with iommu->lock held.
161 */
162 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
163 {
164 u32 tail, head;
165 u8 *target;
166
167 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
168 target = iommu->cmd_buf + tail;
169 memcpy_toio(target, cmd, sizeof(*cmd));
170 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
171 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
172 if (tail == head)
173 return -ENOMEM;
174 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
175
176 return 0;
177 }
178
179 /*
180 * General queuing function for commands. Takes iommu->lock and calls
181 * __iommu_queue_command().
182 */
183 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
184 {
185 unsigned long flags;
186 int ret;
187
188 spin_lock_irqsave(&iommu->lock, flags);
189 ret = __iommu_queue_command(iommu, cmd);
190 if (!ret)
191 iommu->need_sync = 1;
192 spin_unlock_irqrestore(&iommu->lock, flags);
193
194 return ret;
195 }
196
197 /*
198 * This function is called whenever we need to ensure that the IOMMU has
199 * completed execution of all commands we sent. It sends a
200 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
201 * us about that by writing a value to a physical address we pass with
202 * the command.
203 */
204 static int iommu_completion_wait(struct amd_iommu *iommu)
205 {
206 int ret = 0, ready = 0;
207 unsigned status = 0;
208 struct iommu_cmd cmd;
209 unsigned long flags, i = 0;
210
211 memset(&cmd, 0, sizeof(cmd));
212 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
213 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
214
215 spin_lock_irqsave(&iommu->lock, flags);
216
217 if (!iommu->need_sync)
218 goto out;
219
220 iommu->need_sync = 0;
221
222 ret = __iommu_queue_command(iommu, &cmd);
223
224 if (ret)
225 goto out;
226
227 while (!ready && (i < EXIT_LOOP_COUNT)) {
228 ++i;
229 /* wait for the bit to become one */
230 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
231 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
232 }
233
234 /* set bit back to zero */
235 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
236 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
237
238 if (unlikely(i == EXIT_LOOP_COUNT))
239 panic("AMD IOMMU: Completion wait loop failed\n");
240
241 out:
242 spin_unlock_irqrestore(&iommu->lock, flags);
243
244 return 0;
245 }
246
247 /*
248 * Command send function for invalidating a device table entry
249 */
250 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
251 {
252 struct iommu_cmd cmd;
253 int ret;
254
255 BUG_ON(iommu == NULL);
256
257 memset(&cmd, 0, sizeof(cmd));
258 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
259 cmd.data[0] = devid;
260
261 ret = iommu_queue_command(iommu, &cmd);
262
263 return ret;
264 }
265
266 /*
267 * Generic command send function for invalidaing TLB entries
268 */
269 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
270 u64 address, u16 domid, int pde, int s)
271 {
272 struct iommu_cmd cmd;
273 int ret;
274
275 memset(&cmd, 0, sizeof(cmd));
276 address &= PAGE_MASK;
277 CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES);
278 cmd.data[1] |= domid;
279 cmd.data[2] = lower_32_bits(address);
280 cmd.data[3] = upper_32_bits(address);
281 if (s) /* size bit - we flush more than one 4kb page */
282 cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
283 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
284 cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
285
286 ret = iommu_queue_command(iommu, &cmd);
287
288 return ret;
289 }
290
291 /*
292 * TLB invalidation function which is called from the mapping functions.
293 * It invalidates a single PTE if the range to flush is within a single
294 * page. Otherwise it flushes the whole TLB of the IOMMU.
295 */
296 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
297 u64 address, size_t size)
298 {
299 int s = 0;
300 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
301
302 address &= PAGE_MASK;
303
304 if (pages > 1) {
305 /*
306 * If we have to flush more than one page, flush all
307 * TLB entries for this domain
308 */
309 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
310 s = 1;
311 }
312
313 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
314
315 return 0;
316 }
317
318 /* Flush the whole IO/TLB for a given protection domain */
319 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
320 {
321 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
322
323 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
324 }
325
326 /****************************************************************************
327 *
328 * The functions below are used the create the page table mappings for
329 * unity mapped regions.
330 *
331 ****************************************************************************/
332
333 /*
334 * Generic mapping functions. It maps a physical address into a DMA
335 * address space. It allocates the page table pages if necessary.
336 * In the future it can be extended to a generic mapping function
337 * supporting all features of AMD IOMMU page tables like level skipping
338 * and full 64 bit address spaces.
339 */
340 static int iommu_map(struct protection_domain *dom,
341 unsigned long bus_addr,
342 unsigned long phys_addr,
343 int prot)
344 {
345 u64 __pte, *pte, *page;
346
347 bus_addr = PAGE_ALIGN(bus_addr);
348 phys_addr = PAGE_ALIGN(phys_addr);
349
350 /* only support 512GB address spaces for now */
351 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
352 return -EINVAL;
353
354 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
355
356 if (!IOMMU_PTE_PRESENT(*pte)) {
357 page = (u64 *)get_zeroed_page(GFP_KERNEL);
358 if (!page)
359 return -ENOMEM;
360 *pte = IOMMU_L2_PDE(virt_to_phys(page));
361 }
362
363 pte = IOMMU_PTE_PAGE(*pte);
364 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
365
366 if (!IOMMU_PTE_PRESENT(*pte)) {
367 page = (u64 *)get_zeroed_page(GFP_KERNEL);
368 if (!page)
369 return -ENOMEM;
370 *pte = IOMMU_L1_PDE(virt_to_phys(page));
371 }
372
373 pte = IOMMU_PTE_PAGE(*pte);
374 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
375
376 if (IOMMU_PTE_PRESENT(*pte))
377 return -EBUSY;
378
379 __pte = phys_addr | IOMMU_PTE_P;
380 if (prot & IOMMU_PROT_IR)
381 __pte |= IOMMU_PTE_IR;
382 if (prot & IOMMU_PROT_IW)
383 __pte |= IOMMU_PTE_IW;
384
385 *pte = __pte;
386
387 return 0;
388 }
389
390 /*
391 * This function checks if a specific unity mapping entry is needed for
392 * this specific IOMMU.
393 */
394 static int iommu_for_unity_map(struct amd_iommu *iommu,
395 struct unity_map_entry *entry)
396 {
397 u16 bdf, i;
398
399 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
400 bdf = amd_iommu_alias_table[i];
401 if (amd_iommu_rlookup_table[bdf] == iommu)
402 return 1;
403 }
404
405 return 0;
406 }
407
408 /*
409 * Init the unity mappings for a specific IOMMU in the system
410 *
411 * Basically iterates over all unity mapping entries and applies them to
412 * the default domain DMA of that IOMMU if necessary.
413 */
414 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
415 {
416 struct unity_map_entry *entry;
417 int ret;
418
419 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
420 if (!iommu_for_unity_map(iommu, entry))
421 continue;
422 ret = dma_ops_unity_map(iommu->default_dom, entry);
423 if (ret)
424 return ret;
425 }
426
427 return 0;
428 }
429
430 /*
431 * This function actually applies the mapping to the page table of the
432 * dma_ops domain.
433 */
434 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
435 struct unity_map_entry *e)
436 {
437 u64 addr;
438 int ret;
439
440 for (addr = e->address_start; addr < e->address_end;
441 addr += PAGE_SIZE) {
442 ret = iommu_map(&dma_dom->domain, addr, addr, e->prot);
443 if (ret)
444 return ret;
445 /*
446 * if unity mapping is in aperture range mark the page
447 * as allocated in the aperture
448 */
449 if (addr < dma_dom->aperture_size)
450 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
451 }
452
453 return 0;
454 }
455
456 /*
457 * Inits the unity mappings required for a specific device
458 */
459 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
460 u16 devid)
461 {
462 struct unity_map_entry *e;
463 int ret;
464
465 list_for_each_entry(e, &amd_iommu_unity_map, list) {
466 if (!(devid >= e->devid_start && devid <= e->devid_end))
467 continue;
468 ret = dma_ops_unity_map(dma_dom, e);
469 if (ret)
470 return ret;
471 }
472
473 return 0;
474 }
475
476 /****************************************************************************
477 *
478 * The next functions belong to the address allocator for the dma_ops
479 * interface functions. They work like the allocators in the other IOMMU
480 * drivers. Its basically a bitmap which marks the allocated pages in
481 * the aperture. Maybe it could be enhanced in the future to a more
482 * efficient allocator.
483 *
484 ****************************************************************************/
485
486 /*
487 * The address allocator core function.
488 *
489 * called with domain->lock held
490 */
491 static unsigned long dma_ops_alloc_addresses(struct device *dev,
492 struct dma_ops_domain *dom,
493 unsigned int pages,
494 unsigned long align_mask,
495 u64 dma_mask)
496 {
497 unsigned long limit;
498 unsigned long address;
499 unsigned long boundary_size;
500
501 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
502 PAGE_SIZE) >> PAGE_SHIFT;
503 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
504 dma_mask >> PAGE_SHIFT);
505
506 if (dom->next_bit >= limit) {
507 dom->next_bit = 0;
508 dom->need_flush = true;
509 }
510
511 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
512 0 , boundary_size, align_mask);
513 if (address == -1) {
514 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
515 0, boundary_size, align_mask);
516 dom->need_flush = true;
517 }
518
519 if (likely(address != -1)) {
520 dom->next_bit = address + pages;
521 address <<= PAGE_SHIFT;
522 } else
523 address = bad_dma_address;
524
525 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
526
527 return address;
528 }
529
530 /*
531 * The address free function.
532 *
533 * called with domain->lock held
534 */
535 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
536 unsigned long address,
537 unsigned int pages)
538 {
539 address >>= PAGE_SHIFT;
540 iommu_area_free(dom->bitmap, address, pages);
541
542 if (address >= dom->next_bit)
543 dom->need_flush = true;
544 }
545
546 /****************************************************************************
547 *
548 * The next functions belong to the domain allocation. A domain is
549 * allocated for every IOMMU as the default domain. If device isolation
550 * is enabled, every device get its own domain. The most important thing
551 * about domains is the page table mapping the DMA address space they
552 * contain.
553 *
554 ****************************************************************************/
555
556 static u16 domain_id_alloc(void)
557 {
558 unsigned long flags;
559 int id;
560
561 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
562 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
563 BUG_ON(id == 0);
564 if (id > 0 && id < MAX_DOMAIN_ID)
565 __set_bit(id, amd_iommu_pd_alloc_bitmap);
566 else
567 id = 0;
568 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
569
570 return id;
571 }
572
573 /*
574 * Used to reserve address ranges in the aperture (e.g. for exclusion
575 * ranges.
576 */
577 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
578 unsigned long start_page,
579 unsigned int pages)
580 {
581 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
582
583 if (start_page + pages > last_page)
584 pages = last_page - start_page;
585
586 iommu_area_reserve(dom->bitmap, start_page, pages);
587 }
588
589 static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom)
590 {
591 int i, j;
592 u64 *p1, *p2, *p3;
593
594 p1 = dma_dom->domain.pt_root;
595
596 if (!p1)
597 return;
598
599 for (i = 0; i < 512; ++i) {
600 if (!IOMMU_PTE_PRESENT(p1[i]))
601 continue;
602
603 p2 = IOMMU_PTE_PAGE(p1[i]);
604 for (j = 0; j < 512; ++j) {
605 if (!IOMMU_PTE_PRESENT(p2[j]))
606 continue;
607 p3 = IOMMU_PTE_PAGE(p2[j]);
608 free_page((unsigned long)p3);
609 }
610
611 free_page((unsigned long)p2);
612 }
613
614 free_page((unsigned long)p1);
615 }
616
617 /*
618 * Free a domain, only used if something went wrong in the
619 * allocation path and we need to free an already allocated page table
620 */
621 static void dma_ops_domain_free(struct dma_ops_domain *dom)
622 {
623 if (!dom)
624 return;
625
626 dma_ops_free_pagetable(dom);
627
628 kfree(dom->pte_pages);
629
630 kfree(dom->bitmap);
631
632 kfree(dom);
633 }
634
635 /*
636 * Allocates a new protection domain usable for the dma_ops functions.
637 * It also intializes the page table and the address allocator data
638 * structures required for the dma_ops interface
639 */
640 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
641 unsigned order)
642 {
643 struct dma_ops_domain *dma_dom;
644 unsigned i, num_pte_pages;
645 u64 *l2_pde;
646 u64 address;
647
648 /*
649 * Currently the DMA aperture must be between 32 MB and 1GB in size
650 */
651 if ((order < 25) || (order > 30))
652 return NULL;
653
654 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
655 if (!dma_dom)
656 return NULL;
657
658 spin_lock_init(&dma_dom->domain.lock);
659
660 dma_dom->domain.id = domain_id_alloc();
661 if (dma_dom->domain.id == 0)
662 goto free_dma_dom;
663 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
664 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
665 dma_dom->domain.priv = dma_dom;
666 if (!dma_dom->domain.pt_root)
667 goto free_dma_dom;
668 dma_dom->aperture_size = (1ULL << order);
669 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
670 GFP_KERNEL);
671 if (!dma_dom->bitmap)
672 goto free_dma_dom;
673 /*
674 * mark the first page as allocated so we never return 0 as
675 * a valid dma-address. So we can use 0 as error value
676 */
677 dma_dom->bitmap[0] = 1;
678 dma_dom->next_bit = 0;
679
680 dma_dom->need_flush = false;
681 dma_dom->target_dev = 0xffff;
682
683 /* Intialize the exclusion range if necessary */
684 if (iommu->exclusion_start &&
685 iommu->exclusion_start < dma_dom->aperture_size) {
686 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
687 int pages = iommu_num_pages(iommu->exclusion_start,
688 iommu->exclusion_length,
689 PAGE_SIZE);
690 dma_ops_reserve_addresses(dma_dom, startpage, pages);
691 }
692
693 /*
694 * At the last step, build the page tables so we don't need to
695 * allocate page table pages in the dma_ops mapping/unmapping
696 * path.
697 */
698 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
699 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
700 GFP_KERNEL);
701 if (!dma_dom->pte_pages)
702 goto free_dma_dom;
703
704 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
705 if (l2_pde == NULL)
706 goto free_dma_dom;
707
708 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
709
710 for (i = 0; i < num_pte_pages; ++i) {
711 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
712 if (!dma_dom->pte_pages[i])
713 goto free_dma_dom;
714 address = virt_to_phys(dma_dom->pte_pages[i]);
715 l2_pde[i] = IOMMU_L1_PDE(address);
716 }
717
718 return dma_dom;
719
720 free_dma_dom:
721 dma_ops_domain_free(dma_dom);
722
723 return NULL;
724 }
725
726 /*
727 * Find out the protection domain structure for a given PCI device. This
728 * will give us the pointer to the page table root for example.
729 */
730 static struct protection_domain *domain_for_device(u16 devid)
731 {
732 struct protection_domain *dom;
733 unsigned long flags;
734
735 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
736 dom = amd_iommu_pd_table[devid];
737 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
738
739 return dom;
740 }
741
742 /*
743 * If a device is not yet associated with a domain, this function does
744 * assigns it visible for the hardware
745 */
746 static void set_device_domain(struct amd_iommu *iommu,
747 struct protection_domain *domain,
748 u16 devid)
749 {
750 unsigned long flags;
751
752 u64 pte_root = virt_to_phys(domain->pt_root);
753
754 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
755 << DEV_ENTRY_MODE_SHIFT;
756 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
757
758 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
759 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
760 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
761 amd_iommu_dev_table[devid].data[2] = domain->id;
762
763 amd_iommu_pd_table[devid] = domain;
764 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
765
766 iommu_queue_inv_dev_entry(iommu, devid);
767 }
768
769 /*****************************************************************************
770 *
771 * The next functions belong to the dma_ops mapping/unmapping code.
772 *
773 *****************************************************************************/
774
775 /*
776 * This function checks if the driver got a valid device from the caller to
777 * avoid dereferencing invalid pointers.
778 */
779 static bool check_device(struct device *dev)
780 {
781 if (!dev || !dev->dma_mask)
782 return false;
783
784 return true;
785 }
786
787 /*
788 * In this function the list of preallocated protection domains is traversed to
789 * find the domain for a specific device
790 */
791 static struct dma_ops_domain *find_protection_domain(u16 devid)
792 {
793 struct dma_ops_domain *entry, *ret = NULL;
794 unsigned long flags;
795
796 if (list_empty(&iommu_pd_list))
797 return NULL;
798
799 spin_lock_irqsave(&iommu_pd_list_lock, flags);
800
801 list_for_each_entry(entry, &iommu_pd_list, list) {
802 if (entry->target_dev == devid) {
803 ret = entry;
804 list_del(&ret->list);
805 break;
806 }
807 }
808
809 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
810
811 return ret;
812 }
813
814 /*
815 * In the dma_ops path we only have the struct device. This function
816 * finds the corresponding IOMMU, the protection domain and the
817 * requestor id for a given device.
818 * If the device is not yet associated with a domain this is also done
819 * in this function.
820 */
821 static int get_device_resources(struct device *dev,
822 struct amd_iommu **iommu,
823 struct protection_domain **domain,
824 u16 *bdf)
825 {
826 struct dma_ops_domain *dma_dom;
827 struct pci_dev *pcidev;
828 u16 _bdf;
829
830 *iommu = NULL;
831 *domain = NULL;
832 *bdf = 0xffff;
833
834 if (dev->bus != &pci_bus_type)
835 return 0;
836
837 pcidev = to_pci_dev(dev);
838 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
839
840 /* device not translated by any IOMMU in the system? */
841 if (_bdf > amd_iommu_last_bdf)
842 return 0;
843
844 *bdf = amd_iommu_alias_table[_bdf];
845
846 *iommu = amd_iommu_rlookup_table[*bdf];
847 if (*iommu == NULL)
848 return 0;
849 *domain = domain_for_device(*bdf);
850 if (*domain == NULL) {
851 dma_dom = find_protection_domain(*bdf);
852 if (!dma_dom)
853 dma_dom = (*iommu)->default_dom;
854 *domain = &dma_dom->domain;
855 set_device_domain(*iommu, *domain, *bdf);
856 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
857 "device ", (*domain)->id);
858 print_devid(_bdf, 1);
859 }
860
861 if (domain_for_device(_bdf) == NULL)
862 set_device_domain(*iommu, *domain, _bdf);
863
864 return 1;
865 }
866
867 /*
868 * This is the generic map function. It maps one 4kb page at paddr to
869 * the given address in the DMA address space for the domain.
870 */
871 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
872 struct dma_ops_domain *dom,
873 unsigned long address,
874 phys_addr_t paddr,
875 int direction)
876 {
877 u64 *pte, __pte;
878
879 WARN_ON(address > dom->aperture_size);
880
881 paddr &= PAGE_MASK;
882
883 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
884 pte += IOMMU_PTE_L0_INDEX(address);
885
886 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
887
888 if (direction == DMA_TO_DEVICE)
889 __pte |= IOMMU_PTE_IR;
890 else if (direction == DMA_FROM_DEVICE)
891 __pte |= IOMMU_PTE_IW;
892 else if (direction == DMA_BIDIRECTIONAL)
893 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
894
895 WARN_ON(*pte);
896
897 *pte = __pte;
898
899 return (dma_addr_t)address;
900 }
901
902 /*
903 * The generic unmapping function for on page in the DMA address space.
904 */
905 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
906 struct dma_ops_domain *dom,
907 unsigned long address)
908 {
909 u64 *pte;
910
911 if (address >= dom->aperture_size)
912 return;
913
914 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
915
916 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
917 pte += IOMMU_PTE_L0_INDEX(address);
918
919 WARN_ON(!*pte);
920
921 *pte = 0ULL;
922 }
923
924 /*
925 * This function contains common code for mapping of a physically
926 * contiguous memory region into DMA address space. It is used by all
927 * mapping functions provided with this IOMMU driver.
928 * Must be called with the domain lock held.
929 */
930 static dma_addr_t __map_single(struct device *dev,
931 struct amd_iommu *iommu,
932 struct dma_ops_domain *dma_dom,
933 phys_addr_t paddr,
934 size_t size,
935 int dir,
936 bool align,
937 u64 dma_mask)
938 {
939 dma_addr_t offset = paddr & ~PAGE_MASK;
940 dma_addr_t address, start;
941 unsigned int pages;
942 unsigned long align_mask = 0;
943 int i;
944
945 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
946 paddr &= PAGE_MASK;
947
948 if (align)
949 align_mask = (1UL << get_order(size)) - 1;
950
951 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
952 dma_mask);
953 if (unlikely(address == bad_dma_address))
954 goto out;
955
956 start = address;
957 for (i = 0; i < pages; ++i) {
958 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
959 paddr += PAGE_SIZE;
960 start += PAGE_SIZE;
961 }
962 address += offset;
963
964 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
965 iommu_flush_tlb(iommu, dma_dom->domain.id);
966 dma_dom->need_flush = false;
967 } else if (unlikely(iommu_has_npcache(iommu)))
968 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
969
970 out:
971 return address;
972 }
973
974 /*
975 * Does the reverse of the __map_single function. Must be called with
976 * the domain lock held too
977 */
978 static void __unmap_single(struct amd_iommu *iommu,
979 struct dma_ops_domain *dma_dom,
980 dma_addr_t dma_addr,
981 size_t size,
982 int dir)
983 {
984 dma_addr_t i, start;
985 unsigned int pages;
986
987 if ((dma_addr == bad_dma_address) ||
988 (dma_addr + size > dma_dom->aperture_size))
989 return;
990
991 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
992 dma_addr &= PAGE_MASK;
993 start = dma_addr;
994
995 for (i = 0; i < pages; ++i) {
996 dma_ops_domain_unmap(iommu, dma_dom, start);
997 start += PAGE_SIZE;
998 }
999
1000 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1001
1002 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1003 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1004 dma_dom->need_flush = false;
1005 }
1006 }
1007
1008 /*
1009 * The exported map_single function for dma_ops.
1010 */
1011 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1012 size_t size, int dir)
1013 {
1014 unsigned long flags;
1015 struct amd_iommu *iommu;
1016 struct protection_domain *domain;
1017 u16 devid;
1018 dma_addr_t addr;
1019 u64 dma_mask;
1020
1021 if (!check_device(dev))
1022 return bad_dma_address;
1023
1024 dma_mask = *dev->dma_mask;
1025
1026 get_device_resources(dev, &iommu, &domain, &devid);
1027
1028 if (iommu == NULL || domain == NULL)
1029 /* device not handled by any AMD IOMMU */
1030 return (dma_addr_t)paddr;
1031
1032 spin_lock_irqsave(&domain->lock, flags);
1033 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1034 dma_mask);
1035 if (addr == bad_dma_address)
1036 goto out;
1037
1038 iommu_completion_wait(iommu);
1039
1040 out:
1041 spin_unlock_irqrestore(&domain->lock, flags);
1042
1043 return addr;
1044 }
1045
1046 /*
1047 * The exported unmap_single function for dma_ops.
1048 */
1049 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1050 size_t size, int dir)
1051 {
1052 unsigned long flags;
1053 struct amd_iommu *iommu;
1054 struct protection_domain *domain;
1055 u16 devid;
1056
1057 if (!check_device(dev) ||
1058 !get_device_resources(dev, &iommu, &domain, &devid))
1059 /* device not handled by any AMD IOMMU */
1060 return;
1061
1062 spin_lock_irqsave(&domain->lock, flags);
1063
1064 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1065
1066 iommu_completion_wait(iommu);
1067
1068 spin_unlock_irqrestore(&domain->lock, flags);
1069 }
1070
1071 /*
1072 * This is a special map_sg function which is used if we should map a
1073 * device which is not handled by an AMD IOMMU in the system.
1074 */
1075 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1076 int nelems, int dir)
1077 {
1078 struct scatterlist *s;
1079 int i;
1080
1081 for_each_sg(sglist, s, nelems, i) {
1082 s->dma_address = (dma_addr_t)sg_phys(s);
1083 s->dma_length = s->length;
1084 }
1085
1086 return nelems;
1087 }
1088
1089 /*
1090 * The exported map_sg function for dma_ops (handles scatter-gather
1091 * lists).
1092 */
1093 static int map_sg(struct device *dev, struct scatterlist *sglist,
1094 int nelems, int dir)
1095 {
1096 unsigned long flags;
1097 struct amd_iommu *iommu;
1098 struct protection_domain *domain;
1099 u16 devid;
1100 int i;
1101 struct scatterlist *s;
1102 phys_addr_t paddr;
1103 int mapped_elems = 0;
1104 u64 dma_mask;
1105
1106 if (!check_device(dev))
1107 return 0;
1108
1109 dma_mask = *dev->dma_mask;
1110
1111 get_device_resources(dev, &iommu, &domain, &devid);
1112
1113 if (!iommu || !domain)
1114 return map_sg_no_iommu(dev, sglist, nelems, dir);
1115
1116 spin_lock_irqsave(&domain->lock, flags);
1117
1118 for_each_sg(sglist, s, nelems, i) {
1119 paddr = sg_phys(s);
1120
1121 s->dma_address = __map_single(dev, iommu, domain->priv,
1122 paddr, s->length, dir, false,
1123 dma_mask);
1124
1125 if (s->dma_address) {
1126 s->dma_length = s->length;
1127 mapped_elems++;
1128 } else
1129 goto unmap;
1130 }
1131
1132 iommu_completion_wait(iommu);
1133
1134 out:
1135 spin_unlock_irqrestore(&domain->lock, flags);
1136
1137 return mapped_elems;
1138 unmap:
1139 for_each_sg(sglist, s, mapped_elems, i) {
1140 if (s->dma_address)
1141 __unmap_single(iommu, domain->priv, s->dma_address,
1142 s->dma_length, dir);
1143 s->dma_address = s->dma_length = 0;
1144 }
1145
1146 mapped_elems = 0;
1147
1148 goto out;
1149 }
1150
1151 /*
1152 * The exported map_sg function for dma_ops (handles scatter-gather
1153 * lists).
1154 */
1155 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1156 int nelems, int dir)
1157 {
1158 unsigned long flags;
1159 struct amd_iommu *iommu;
1160 struct protection_domain *domain;
1161 struct scatterlist *s;
1162 u16 devid;
1163 int i;
1164
1165 if (!check_device(dev) ||
1166 !get_device_resources(dev, &iommu, &domain, &devid))
1167 return;
1168
1169 spin_lock_irqsave(&domain->lock, flags);
1170
1171 for_each_sg(sglist, s, nelems, i) {
1172 __unmap_single(iommu, domain->priv, s->dma_address,
1173 s->dma_length, dir);
1174 s->dma_address = s->dma_length = 0;
1175 }
1176
1177 iommu_completion_wait(iommu);
1178
1179 spin_unlock_irqrestore(&domain->lock, flags);
1180 }
1181
1182 /*
1183 * The exported alloc_coherent function for dma_ops.
1184 */
1185 static void *alloc_coherent(struct device *dev, size_t size,
1186 dma_addr_t *dma_addr, gfp_t flag)
1187 {
1188 unsigned long flags;
1189 void *virt_addr;
1190 struct amd_iommu *iommu;
1191 struct protection_domain *domain;
1192 u16 devid;
1193 phys_addr_t paddr;
1194 u64 dma_mask = dev->coherent_dma_mask;
1195
1196 if (!check_device(dev))
1197 return NULL;
1198
1199 if (!get_device_resources(dev, &iommu, &domain, &devid))
1200 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1201
1202 flag |= __GFP_ZERO;
1203 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1204 if (!virt_addr)
1205 return 0;
1206
1207 paddr = virt_to_phys(virt_addr);
1208
1209 if (!iommu || !domain) {
1210 *dma_addr = (dma_addr_t)paddr;
1211 return virt_addr;
1212 }
1213
1214 if (!dma_mask)
1215 dma_mask = *dev->dma_mask;
1216
1217 spin_lock_irqsave(&domain->lock, flags);
1218
1219 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1220 size, DMA_BIDIRECTIONAL, true, dma_mask);
1221
1222 if (*dma_addr == bad_dma_address) {
1223 free_pages((unsigned long)virt_addr, get_order(size));
1224 virt_addr = NULL;
1225 goto out;
1226 }
1227
1228 iommu_completion_wait(iommu);
1229
1230 out:
1231 spin_unlock_irqrestore(&domain->lock, flags);
1232
1233 return virt_addr;
1234 }
1235
1236 /*
1237 * The exported free_coherent function for dma_ops.
1238 */
1239 static void free_coherent(struct device *dev, size_t size,
1240 void *virt_addr, dma_addr_t dma_addr)
1241 {
1242 unsigned long flags;
1243 struct amd_iommu *iommu;
1244 struct protection_domain *domain;
1245 u16 devid;
1246
1247 if (!check_device(dev))
1248 return;
1249
1250 get_device_resources(dev, &iommu, &domain, &devid);
1251
1252 if (!iommu || !domain)
1253 goto free_mem;
1254
1255 spin_lock_irqsave(&domain->lock, flags);
1256
1257 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1258
1259 iommu_completion_wait(iommu);
1260
1261 spin_unlock_irqrestore(&domain->lock, flags);
1262
1263 free_mem:
1264 free_pages((unsigned long)virt_addr, get_order(size));
1265 }
1266
1267 /*
1268 * This function is called by the DMA layer to find out if we can handle a
1269 * particular device. It is part of the dma_ops.
1270 */
1271 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1272 {
1273 u16 bdf;
1274 struct pci_dev *pcidev;
1275
1276 /* No device or no PCI device */
1277 if (!dev || dev->bus != &pci_bus_type)
1278 return 0;
1279
1280 pcidev = to_pci_dev(dev);
1281
1282 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1283
1284 /* Out of our scope? */
1285 if (bdf > amd_iommu_last_bdf)
1286 return 0;
1287
1288 return 1;
1289 }
1290
1291 /*
1292 * The function for pre-allocating protection domains.
1293 *
1294 * If the driver core informs the DMA layer if a driver grabs a device
1295 * we don't need to preallocate the protection domains anymore.
1296 * For now we have to.
1297 */
1298 void prealloc_protection_domains(void)
1299 {
1300 struct pci_dev *dev = NULL;
1301 struct dma_ops_domain *dma_dom;
1302 struct amd_iommu *iommu;
1303 int order = amd_iommu_aperture_order;
1304 u16 devid;
1305
1306 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1307 devid = (dev->bus->number << 8) | dev->devfn;
1308 if (devid > amd_iommu_last_bdf)
1309 continue;
1310 devid = amd_iommu_alias_table[devid];
1311 if (domain_for_device(devid))
1312 continue;
1313 iommu = amd_iommu_rlookup_table[devid];
1314 if (!iommu)
1315 continue;
1316 dma_dom = dma_ops_domain_alloc(iommu, order);
1317 if (!dma_dom)
1318 continue;
1319 init_unity_mappings_for_device(dma_dom, devid);
1320 dma_dom->target_dev = devid;
1321
1322 list_add_tail(&dma_dom->list, &iommu_pd_list);
1323 }
1324 }
1325
1326 static struct dma_mapping_ops amd_iommu_dma_ops = {
1327 .alloc_coherent = alloc_coherent,
1328 .free_coherent = free_coherent,
1329 .map_single = map_single,
1330 .unmap_single = unmap_single,
1331 .map_sg = map_sg,
1332 .unmap_sg = unmap_sg,
1333 .dma_supported = amd_iommu_dma_supported,
1334 };
1335
1336 /*
1337 * The function which clues the AMD IOMMU driver into dma_ops.
1338 */
1339 int __init amd_iommu_init_dma_ops(void)
1340 {
1341 struct amd_iommu *iommu;
1342 int order = amd_iommu_aperture_order;
1343 int ret;
1344
1345 /*
1346 * first allocate a default protection domain for every IOMMU we
1347 * found in the system. Devices not assigned to any other
1348 * protection domain will be assigned to the default one.
1349 */
1350 list_for_each_entry(iommu, &amd_iommu_list, list) {
1351 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1352 if (iommu->default_dom == NULL)
1353 return -ENOMEM;
1354 ret = iommu_init_unity_mappings(iommu);
1355 if (ret)
1356 goto free_domains;
1357 }
1358
1359 /*
1360 * If device isolation is enabled, pre-allocate the protection
1361 * domains for each device.
1362 */
1363 if (amd_iommu_isolate)
1364 prealloc_protection_domains();
1365
1366 iommu_detected = 1;
1367 force_iommu = 1;
1368 bad_dma_address = 0;
1369 #ifdef CONFIG_GART_IOMMU
1370 gart_iommu_aperture_disabled = 1;
1371 gart_iommu_aperture = 0;
1372 #endif
1373
1374 /* Make the driver finally visible to the drivers */
1375 dma_ops = &amd_iommu_dma_ops;
1376
1377 return 0;
1378
1379 free_domains:
1380
1381 list_for_each_entry(iommu, &amd_iommu_list, list) {
1382 if (iommu->default_dom)
1383 dma_ops_domain_free(iommu->default_dom);
1384 }
1385
1386 return ret;
1387 }
Support for the Chinese Samsung S3C2440 based development boards