arch/ppc/syslib/open_pic_defs.h

   1 /*
   2  *  arch/ppc/kernel/open_pic_defs.h -- OpenPIC definitions
   3  *
   4  *  Copyright (C) 1997 Geert Uytterhoeven
   5  *
   6  *  This file is based on the following documentation:
   7  *
   8  *      The Open Programmable Interrupt Controller (PIC)
   9  *      Register Interface Specification Revision 1.2
  10  *
  11  *      Issue Date: October 1995
  12  *
  13  *      Issued jointly by Advanced Micro Devices and Cyrix Corporation
  14  *
  15  *      AMD is a registered trademark of Advanced Micro Devices, Inc.
  16  *      Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc.
  17  *      All Rights Reserved.
  18  *
  19  *  To receive a copy of this documentation, send an email to openpic@amd.com.
  20  *
  21  *  This file is subject to the terms and conditions of the GNU General Public
  22  *  License.  See the file COPYING in the main directory of this archive
  23  *  for more details.
  24  */
  25
  26 #ifndef _LINUX_OPENPIC_H
  27 #define _LINUX_OPENPIC_H
  28
  29 #ifdef __KERNEL__
  30
  31     /*
  32      *  OpenPIC supports up to 2048 interrupt sources and up to 32 processors
  33      */
  34
  35 #define OPENPIC_MAX_SOURCES     2048
  36 #define OPENPIC_MAX_PROCESSORS  32
  37 #define OPENPIC_MAX_ISU         16
  38
  39 #define OPENPIC_NUM_TIMERS      4
  40 #define OPENPIC_NUM_IPI         4
  41 #define OPENPIC_NUM_PRI         16
  42 #define OPENPIC_NUM_VECTORS     256
  43
  44
  45
  46     /*
  47      *  OpenPIC Registers are 32 bits and aligned on 128 bit boundaries
  48      */
  49
  50 typedef struct _OpenPIC_Reg {
  51     u_int Reg;                                  /* Little endian! */
  52     char Pad[0xc];
  53 } OpenPIC_Reg;
  54
  55
  56     /*
  57      *  Per Processor Registers
  58      */
  59
  60 typedef struct _OpenPIC_Processor {
  61     /*
  62      *  Private Shadow Registers (for SLiC backwards compatibility)
  63      */
  64     u_int IPI0_Dispatch_Shadow;                 /* Write Only */
  65     char Pad1[0x4];
  66     u_int IPI0_Vector_Priority_Shadow;          /* Read/Write */
  67     char Pad2[0x34];
  68     /*
  69      *  Interprocessor Interrupt Command Ports
  70      */
  71     OpenPIC_Reg _IPI_Dispatch[OPENPIC_NUM_IPI]; /* Write Only */
  72     /*
  73      *  Current Task Priority Register
  74      */
  75     OpenPIC_Reg _Current_Task_Priority;         /* Read/Write */
  76     char Pad3[0x10];
  77     /*
  78      *  Interrupt Acknowledge Register
  79      */
  80     OpenPIC_Reg _Interrupt_Acknowledge;         /* Read Only */
  81     /*
  82      *  End of Interrupt (EOI) Register
  83      */
  84     OpenPIC_Reg _EOI;                           /* Read/Write */
  85     char Pad5[0xf40];
  86 } OpenPIC_Processor;
  87
  88
  89     /*
  90      *  Timer Registers
  91      */
  92
  93 typedef struct _OpenPIC_Timer {
  94     OpenPIC_Reg _Current_Count;                 /* Read Only */
  95     OpenPIC_Reg _Base_Count;                    /* Read/Write */
  96     OpenPIC_Reg _Vector_Priority;               /* Read/Write */
  97     OpenPIC_Reg _Destination;                   /* Read/Write */
  98 } OpenPIC_Timer;
  99
 100
 101     /*
 102      *  Global Registers
 103      */
 104
 105 typedef struct _OpenPIC_Global {
 106     /*
 107      *  Feature Reporting Registers
 108      */
 109     OpenPIC_Reg _Feature_Reporting0;            /* Read Only */
 110     OpenPIC_Reg _Feature_Reporting1;            /* Future Expansion */
 111     /*
 112      *  Global Configuration Registers
 113      */
 114     OpenPIC_Reg _Global_Configuration0;         /* Read/Write */
 115     OpenPIC_Reg _Global_Configuration1;         /* Future Expansion */
 116     /*
 117      *  Vendor Specific Registers
 118      */
 119     OpenPIC_Reg _Vendor_Specific[4];
 120     /*
 121      *  Vendor Identification Register
 122      */
 123     OpenPIC_Reg _Vendor_Identification;         /* Read Only */
 124     /*
 125      *  Processor Initialization Register
 126      */
 127     OpenPIC_Reg _Processor_Initialization;      /* Read/Write */
 128     /*
 129      *  IPI Vector/Priority Registers
 130      */
 131     OpenPIC_Reg _IPI_Vector_Priority[OPENPIC_NUM_IPI];  /* Read/Write */
 132     /*
 133      *  Spurious Vector Register
 134      */
 135     OpenPIC_Reg _Spurious_Vector;               /* Read/Write */
 136     /*
 137      *  Global Timer Registers
 138      */
 139     OpenPIC_Reg _Timer_Frequency;               /* Read/Write */
 140     OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS];
 141     char Pad1[0xee00];
 142 } OpenPIC_Global;
 143
 144
 145     /*
 146      *  Interrupt Source Registers
 147      */
 148
 149 typedef struct _OpenPIC_Source {
 150     OpenPIC_Reg _Vector_Priority;               /* Read/Write */
 151     OpenPIC_Reg _Destination;                   /* Read/Write */
 152 } OpenPIC_Source, *OpenPIC_SourcePtr;
 153
 154
 155     /*
 156      *  OpenPIC Register Map
 157      */
 158
 159 struct OpenPIC {
 160     char Pad1[0x1000];
 161     /*
 162      *  Global Registers
 163      */
 164     OpenPIC_Global Global;
 165     /*
 166      *  Interrupt Source Configuration Registers
 167      */
 168     OpenPIC_Source Source[OPENPIC_MAX_SOURCES];
 169     /*
 170      *  Per Processor Registers
 171      */
 172     OpenPIC_Processor Processor[OPENPIC_MAX_PROCESSORS];
 173 };
 174
 175     /*
 176      *  Current Task Priority Register
 177      */
 178
 179 #define OPENPIC_CURRENT_TASK_PRIORITY_MASK      0x0000000f
 180
 181     /*
 182      *  Who Am I Register
 183      */
 184
 185 #define OPENPIC_WHO_AM_I_ID_MASK                0x0000001f
 186
 187     /*
 188      *  Feature Reporting Register 0
 189      */
 190
 191 #define OPENPIC_FEATURE_LAST_SOURCE_MASK        0x07ff0000
 192 #define OPENPIC_FEATURE_LAST_SOURCE_SHIFT       16
 193 #define OPENPIC_FEATURE_LAST_PROCESSOR_MASK     0x00001f00
 194 #define OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT    8
 195 #define OPENPIC_FEATURE_VERSION_MASK            0x000000ff
 196
 197     /*
 198      *  Global Configuration Register 0
 199      */
 200
 201 #define OPENPIC_CONFIG_RESET                    0x80000000
 202 #define OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE 0x20000000
 203 #define OPENPIC_CONFIG_BASE_MASK                0x000fffff
 204
 205     /*
 206      *  Global Configuration Register 1
 207      *  This is the EICR on EPICs.
 208      */
 209
 210 #define OPENPIC_EICR_S_CLK_MASK                 0x70000000
 211 #define OPENPIC_EICR_SIE                        0x08000000
 212
 213     /*
 214      *  Vendor Identification Register
 215      */
 216
 217 #define OPENPIC_VENDOR_ID_STEPPING_MASK         0x00ff0000
 218 #define OPENPIC_VENDOR_ID_STEPPING_SHIFT        16
 219 #define OPENPIC_VENDOR_ID_DEVICE_ID_MASK        0x0000ff00
 220 #define OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT       8
 221 #define OPENPIC_VENDOR_ID_VENDOR_ID_MASK        0x000000ff
 222
 223     /*
 224      *  Vector/Priority Registers
 225      */
 226
 227 #define OPENPIC_MASK                            0x80000000
 228 #define OPENPIC_ACTIVITY                        0x40000000      /* Read Only */
 229 #define OPENPIC_PRIORITY_MASK                   0x000f0000
 230 #define OPENPIC_PRIORITY_SHIFT                  16
 231 #define OPENPIC_VECTOR_MASK                     0x000000ff
 232
 233
 234     /*
 235      *  Interrupt Source Registers
 236      */
 237
 238 #define OPENPIC_POLARITY_POSITIVE               0x00800000
 239 #define OPENPIC_POLARITY_NEGATIVE               0x00000000
 240 #define OPENPIC_POLARITY_MASK                   0x00800000
 241 #define OPENPIC_SENSE_LEVEL                     0x00400000
 242 #define OPENPIC_SENSE_EDGE                      0x00000000
 243 #define OPENPIC_SENSE_MASK                      0x00400000
 244
 245
 246     /*
 247      *  Timer Registers
 248      */
 249
 250 #define OPENPIC_COUNT_MASK                      0x7fffffff
 251 #define OPENPIC_TIMER_TOGGLE                    0x80000000
 252 #define OPENPIC_TIMER_COUNT_INHIBIT             0x80000000
 253
 254
 255     /*
 256      *  Aliases to make life simpler
 257      */
 258
 259 /* Per Processor Registers */
 260 #define IPI_Dispatch(i)                 _IPI_Dispatch[i].Reg
 261 #define Current_Task_Priority           _Current_Task_Priority.Reg
 262 #define Interrupt_Acknowledge           _Interrupt_Acknowledge.Reg
 263 #define EOI                             _EOI.Reg
 264
 265 /* Global Registers */
 266 #define Feature_Reporting0              _Feature_Reporting0.Reg
 267 #define Feature_Reporting1              _Feature_Reporting1.Reg
 268 #define Global_Configuration0           _Global_Configuration0.Reg
 269 #define Global_Configuration1           _Global_Configuration1.Reg
 270 #define Vendor_Specific(i)              _Vendor_Specific[i].Reg
 271 #define Vendor_Identification           _Vendor_Identification.Reg
 272 #define Processor_Initialization        _Processor_Initialization.Reg
 273 #define IPI_Vector_Priority(i)          _IPI_Vector_Priority[i].Reg
 274 #define Spurious_Vector                 _Spurious_Vector.Reg
 275 #define Timer_Frequency                 _Timer_Frequency.Reg
 276
 277 /* Timer Registers */
 278 #define Current_Count                   _Current_Count.Reg
 279 #define Base_Count                      _Base_Count.Reg
 280 #define Vector_Priority                 _Vector_Priority.Reg
 281 #define Destination                     _Destination.Reg
 282
 283 /* Interrupt Source Registers */
 284 #define Vector_Priority                 _Vector_Priority.Reg
 285 #define Destination                     _Destination.Reg
 286
 287 #endif /* __KERNEL__ */
 288
 289 #endif /* _LINUX_OPENPIC_H */