arch/ppc/syslib/m8xx_setup.c

   1 /*
   2  *  arch/ppc/kernel/setup.c
   3  *
   4  *  Copyright (C) 1995  Linus Torvalds
   5  *  Adapted from 'alpha' version by Gary Thomas
   6  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   7  *  Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
   8  *  Further modified for generic 8xx by Dan.
   9  */
  10
  11 /*
  12  * bootup setup stuff..
  13  */
  14
  15 #include <linux/config.h>
  16 #include <linux/errno.h>
  17 #include <linux/sched.h>
  18 #include <linux/kernel.h>
  19 #include <linux/mm.h>
  20 #include <linux/stddef.h>
  21 #include <linux/unistd.h>
  22 #include <linux/ptrace.h>
  23 #include <linux/slab.h>
  24 #include <linux/user.h>
  25 #include <linux/a.out.h>
  26 #include <linux/tty.h>
  27 #include <linux/major.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/reboot.h>
  30 #include <linux/init.h>
  31 #include <linux/initrd.h>
  32 #include <linux/ioport.h>
  33 #include <linux/bootmem.h>
  34 #include <linux/seq_file.h>
  35 #include <linux/root_dev.h>
  36
  37 #include <asm/mmu.h>
  38 #include <asm/reg.h>
  39 #include <asm/residual.h>
  40 #include <asm/io.h>
  41 #include <asm/pgtable.h>
  42 #include <asm/mpc8xx.h>
  43 #include <asm/8xx_immap.h>
  44 #include <asm/machdep.h>
  45 #include <asm/bootinfo.h>
  46 #include <asm/time.h>
  47 #include <asm/xmon.h>
  48
  49 #include "ppc8xx_pic.h"
  50
  51 static int m8xx_set_rtc_time(unsigned long time);
  52 static unsigned long m8xx_get_rtc_time(void);
  53 void m8xx_calibrate_decr(void);
  54
  55 unsigned char __res[sizeof(bd_t)];
  56
  57 extern void m8xx_ide_init(void);
  58
  59 extern unsigned long find_available_memory(void);
  60 extern void m8xx_cpm_reset(void);
  61 extern void m8xx_wdt_handler_install(bd_t *bp);
  62 extern void rpxfb_alloc_pages(void);
  63 extern void cpm_interrupt_init(void);
  64
  65 void __attribute__ ((weak))
  66 board_init(void)
  67 {
  68 }
  69
  70 void __init
  71 m8xx_setup_arch(void)
  72 {
  73         /* Reset the Communication Processor Module.
  74         */
  75         m8xx_cpm_reset();
  76
  77 #ifdef CONFIG_FB_RPX
  78         rpxfb_alloc_pages();
  79 #endif
  80
  81 #ifdef notdef
  82         ROOT_DEV = Root_HDA1; /* hda1 */
  83 #endif
  84
  85 #ifdef CONFIG_BLK_DEV_INITRD
  86 #if 0
  87         ROOT_DEV = Root_FD0; /* floppy */
  88         rd_prompt = 1;
  89         rd_doload = 1;
  90         rd_image_start = 0;
  91 #endif
  92 #if 0   /* XXX this may need to be updated for the new bootmem stuff,
  93            or possibly just deleted (see set_phys_avail() in init.c).
  94            - paulus. */
  95         /* initrd_start and size are setup by boot/head.S and kernel/head.S */
  96         if ( initrd_start )
  97         {
  98                 if (initrd_end > *memory_end_p)
  99                 {
 100                         printk("initrd extends beyond end of memory "
 101                                "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
 102                                initrd_end,*memory_end_p);
 103                         initrd_start = 0;
 104                 }
 105         }
 106 #endif
 107 #endif
 108         board_init();
 109 }
 110
 111 void
 112 abort(void)
 113 {
 114 #ifdef CONFIG_XMON
 115         xmon(0);
 116 #endif
 117         machine_restart(NULL);
 118
 119         /* not reached */
 120         for (;;);
 121 }
 122
 123 /* A place holder for time base interrupts, if they are ever enabled. */
 124 irqreturn_t timebase_interrupt(int irq, void * dev, struct pt_regs * regs)
 125 {
 126         printk ("timebase_interrupt()\n");
 127
 128         return IRQ_HANDLED;
 129 }
 130
 131 static struct irqaction tbint_irqaction = {
 132         .handler = timebase_interrupt,
 133         .mask = CPU_MASK_NONE,
 134         .name = "tbint",
 135 };
 136
 137 /* The decrementer counts at the system (internal) clock frequency divided by
 138  * sixteen, or external oscillator divided by four.  We force the processor
 139  * to use system clock divided by sixteen.
 140  */
 141 void __init m8xx_calibrate_decr(void)
 142 {
 143         bd_t    *binfo = (bd_t *)__res;
 144         int freq, fp, divisor;
 145
 146         /* Unlock the SCCR. */
 147         ((volatile immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk = ~KAPWR_KEY;
 148         ((volatile immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk = KAPWR_KEY;
 149
 150         /* Force all 8xx processors to use divide by 16 processor clock. */
 151         ((volatile immap_t *)IMAP_ADDR)->im_clkrst.car_sccr |= 0x02000000;
 152
 153         /* Processor frequency is MHz.
 154          * The value 'fp' is the number of decrementer ticks per second.
 155          */
 156         fp = binfo->bi_intfreq / 16;
 157         freq = fp*60;   /* try to make freq/1e6 an integer */
 158         divisor = 60;
 159         printk("Decrementer Frequency = %d/%d\n", freq, divisor);
 160         tb_ticks_per_jiffy = freq / HZ / divisor;
 161         tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
 162
 163         /* Perform some more timer/timebase initialization.  This used
 164          * to be done elsewhere, but other changes caused it to get
 165          * called more than once....that is a bad thing.
 166          *
 167          * First, unlock all of the registers we are going to modify.
 168          * To protect them from corruption during power down, registers
 169          * that are maintained by keep alive power are "locked".  To
 170          * modify these registers we have to write the key value to
 171          * the key location associated with the register.
 172          * Some boards power up with these unlocked, while others
 173          * are locked.  Writing anything (including the unlock code?)
 174          * to the unlocked registers will lock them again.  So, here
 175          * we guarantee the registers are locked, then we unlock them
 176          * for our use.
 177          */
 178         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk = ~KAPWR_KEY;
 179         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck = ~KAPWR_KEY;
 180         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk    = ~KAPWR_KEY;
 181         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk =  KAPWR_KEY;
 182         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck =  KAPWR_KEY;
 183         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk    =  KAPWR_KEY;
 184
 185         /* Disable the RTC one second and alarm interrupts. */
 186         ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc &=
 187                                                 ~(RTCSC_SIE | RTCSC_ALE);
 188         /* Enable the RTC */
 189         ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc |=
 190                                                 (RTCSC_RTF | RTCSC_RTE);
 191
 192         /* Enabling the decrementer also enables the timebase interrupts
 193          * (or from the other point of view, to get decrementer interrupts
 194          * we have to enable the timebase).  The decrementer interrupt
 195          * is wired into the vector table, nothing to do here for that.
 196          */
 197         ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_tbscr =
 198                                 ((mk_int_int_mask(DEC_INTERRUPT) << 8) |
 199                                          (TBSCR_TBF | TBSCR_TBE));
 200
 201         if (setup_irq(DEC_INTERRUPT, &tbint_irqaction))
 202                 panic("Could not allocate timer IRQ!");
 203
 204 #ifdef CONFIG_8xx_WDT
 205         /* Install watchdog timer handler early because it might be
 206          * already enabled by the bootloader
 207          */
 208         m8xx_wdt_handler_install(binfo);
 209 #endif
 210 }
 211
 212 /* The RTC on the MPC8xx is an internal register.
 213  * We want to protect this during power down, so we need to unlock,
 214  * modify, and re-lock.
 215  */
 216 static int
 217 m8xx_set_rtc_time(unsigned long time)
 218 {
 219         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck = KAPWR_KEY;
 220         ((volatile immap_t *)IMAP_ADDR)->im_sit.sit_rtc = time;
 221         ((volatile immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck = ~KAPWR_KEY;
 222         return(0);
 223 }
 224
 225 static unsigned long
 226 m8xx_get_rtc_time(void)
 227 {
 228         /* Get time from the RTC. */
 229         return((unsigned long)(((immap_t *)IMAP_ADDR)->im_sit.sit_rtc));
 230 }
 231
 232 static void
 233 m8xx_restart(char *cmd)
 234 {
 235         __volatile__ unsigned char dummy;
 236
 237         local_irq_disable();
 238         ((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr |= 0x00000080;
 239
 240         /* Clear the ME bit in MSR to cause checkstop on machine check
 241         */
 242         mtmsr(mfmsr() & ~0x1000);
 243
 244         dummy = ((immap_t *)IMAP_ADDR)->im_clkrst.res[0];
 245         printk("Restart failed\n");
 246         while(1);
 247 }
 248
 249 static void
 250 m8xx_power_off(void)
 251 {
 252    m8xx_restart(NULL);
 253 }
 254
 255 static void
 256 m8xx_halt(void)
 257 {
 258    m8xx_restart(NULL);
 259 }
 260
 261
 262 static int
 263 m8xx_show_percpuinfo(struct seq_file *m, int i)
 264 {
 265         bd_t    *bp;
 266
 267         bp = (bd_t *)__res;
 268
 269         seq_printf(m, "clock\t\t: %uMHz\n"
 270                    "bus clock\t: %uMHz\n",
 271                    bp->bi_intfreq / 1000000,
 272                    bp->bi_busfreq / 1000000);
 273
 274         return 0;
 275 }
 276
 277 #ifdef CONFIG_PCI
 278 static struct irqaction mbx_i8259_irqaction = {
 279         .handler = mbx_i8259_action,
 280         .mask = CPU_MASK_NONE,
 281         .name = "i8259 cascade",
 282 };
 283 #endif
 284
 285 /* Initialize the internal interrupt controller.  The number of
 286  * interrupts supported can vary with the processor type, and the
 287  * 82xx family can have up to 64.
 288  * External interrupts can be either edge or level triggered, and
 289  * need to be initialized by the appropriate driver.
 290  */
 291 static void __init
 292 m8xx_init_IRQ(void)
 293 {
 294         int i;
 295
 296         for (i = SIU_IRQ_OFFSET ; i < SIU_IRQ_OFFSET + NR_SIU_INTS ; i++)
 297                 irq_desc[i].handler = &ppc8xx_pic;
 298
 299         cpm_interrupt_init();
 300
 301 #if defined(CONFIG_PCI)
 302         for (i = I8259_IRQ_OFFSET ; i < I8259_IRQ_OFFSET + NR_8259_INTS ; i++)
 303                 irq_desc[i].handler = &i8259_pic;
 304
 305         i8259_pic_irq_offset = I8259_IRQ_OFFSET;
 306         i8259_init(0);
 307
 308         /* The i8259 cascade interrupt must be level sensitive. */
 309         ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel &=
 310                 ~(0x80000000 >> ISA_BRIDGE_INT);
 311
 312         if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction))
 313                 enable_irq(ISA_BRIDGE_INT);
 314 #endif  /* CONFIG_PCI */
 315 }
 316
 317 /* -------------------------------------------------------------------- */
 318
 319 /*
 320  * This is a big hack right now, but it may turn into something real
 321  * someday.
 322  *
 323  * For the 8xx boards (at this time anyway), there is nothing to initialize
 324  * associated the PROM.  Rather than include all of the prom.c
 325  * functions in the image just to get prom_init, all we really need right
 326  * now is the initialization of the physical memory region.
 327  */
 328 static unsigned long __init
 329 m8xx_find_end_of_memory(void)
 330 {
 331         bd_t    *binfo;
 332         extern unsigned char __res[];
 333
 334         binfo = (bd_t *)__res;
 335
 336         return binfo->bi_memsize;
 337 }
 338
 339 /*
 340  * Now map in some of the I/O space that is generically needed
 341  * or shared with multiple devices.
 342  * All of this fits into the same 4Mbyte region, so it only
 343  * requires one page table page.  (or at least it used to  -- paulus)
 344  */
 345 static void __init
 346 m8xx_map_io(void)
 347 {
 348         io_block_mapping(IMAP_ADDR, IMAP_ADDR, IMAP_SIZE, _PAGE_IO);
 349 #ifdef CONFIG_MBX
 350         io_block_mapping(NVRAM_ADDR, NVRAM_ADDR, NVRAM_SIZE, _PAGE_IO);
 351         io_block_mapping(MBX_CSR_ADDR, MBX_CSR_ADDR, MBX_CSR_SIZE, _PAGE_IO);
 352         io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
 353
 354         /* Map some of the PCI/ISA I/O space to get the IDE interface.
 355         */
 356         io_block_mapping(PCI_ISA_IO_ADDR, PCI_ISA_IO_ADDR, 0x4000, _PAGE_IO);
 357         io_block_mapping(PCI_IDE_ADDR, PCI_IDE_ADDR, 0x4000, _PAGE_IO);
 358 #endif
 359 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
 360         io_block_mapping(RPX_CSR_ADDR, RPX_CSR_ADDR, RPX_CSR_SIZE, _PAGE_IO);
 361 #if !defined(CONFIG_PCI)
 362         io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
 363 #endif
 364 #endif
 365 #if defined(CONFIG_HTDMSOUND) || defined(CONFIG_RPXTOUCH) || defined(CONFIG_FB_RPX)
 366         io_block_mapping(HIOX_CSR_ADDR, HIOX_CSR_ADDR, HIOX_CSR_SIZE, _PAGE_IO);
 367 #endif
 368 #ifdef CONFIG_FADS
 369         io_block_mapping(BCSR_ADDR, BCSR_ADDR, BCSR_SIZE, _PAGE_IO);
 370 #endif
 371 #ifdef CONFIG_PCI
 372         io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
 373 #endif
 374 #if defined(CONFIG_NETTA)
 375         io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
 376 #endif
 377 }
 378
 379 void __init
 380 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 381                 unsigned long r6, unsigned long r7)
 382 {
 383         parse_bootinfo(find_bootinfo());
 384
 385         if ( r3 )
 386                 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
 387
 388 #ifdef CONFIG_PCI
 389         m8xx_setup_pci_ptrs();
 390 #endif
 391
 392 #ifdef CONFIG_BLK_DEV_INITRD
 393         /* take care of initrd if we have one */
 394         if ( r4 )
 395         {
 396                 initrd_start = r4 + KERNELBASE;
 397                 initrd_end = r5 + KERNELBASE;
 398         }
 399 #endif /* CONFIG_BLK_DEV_INITRD */
 400         /* take care of cmd line */
 401         if ( r6 )
 402         {
 403                 *(char *)(r7+KERNELBASE) = 0;
 404                 strcpy(cmd_line, (char *)(r6+KERNELBASE));
 405         }
 406
 407         ppc_md.setup_arch               = m8xx_setup_arch;
 408         ppc_md.show_percpuinfo          = m8xx_show_percpuinfo;
 409         ppc_md.irq_canonicalize = NULL;
 410         ppc_md.init_IRQ                 = m8xx_init_IRQ;
 411         ppc_md.get_irq                  = m8xx_get_irq;
 412         ppc_md.init                     = NULL;
 413
 414         ppc_md.restart                  = m8xx_restart;
 415         ppc_md.power_off                = m8xx_power_off;
 416         ppc_md.halt                     = m8xx_halt;
 417
 418         ppc_md.time_init                = NULL;
 419         ppc_md.set_rtc_time             = m8xx_set_rtc_time;
 420         ppc_md.get_rtc_time             = m8xx_get_rtc_time;
 421         ppc_md.calibrate_decr           = m8xx_calibrate_decr;
 422
 423         ppc_md.find_end_of_memory       = m8xx_find_end_of_memory;
 424         ppc_md.setup_io_mappings        = m8xx_map_io;
 425
 426 #if defined(CONFIG_BLK_DEV_MPC8xx_IDE)
 427         m8xx_ide_init();
 428 #endif
 429 }