2 * This file contains the routines for handling the MMU on those
3 * PowerPC implementations where the MMU substantially follows the
4 * architecture specification. This includes the 6xx, 7xx, 7xxx,
5 * 8260, and POWER3 implementations but excludes the 8xx and 4xx.
8 * Derived from arch/ppc/mm/init.c:
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
12 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
13 * Copyright (C) 1996 Paul Mackerras
14 * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
16 * Derived from "arch/i386/mm/init.c"
17 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
26 #include <linux/config.h>
27 #include <linux/kernel.h>
29 #include <linux/init.h>
30 #include <linux/highmem.h>
34 #include <asm/machdep.h>
37 #include "mem_pieces.h"
40 unsigned long Hash_size
, Hash_mask
;
43 union ubat
{ /* BAT register values to be loaded */
45 #ifdef CONFIG_PPC64BRIDGE
50 } BATS
[4][2]; /* 4 pairs of IBAT, DBAT */
52 struct batrange
{ /* stores address ranges mapped by BATs */
59 * Return PA for this VA if it is mapped by a BAT, or 0
61 unsigned long v_mapped_by_bats(unsigned long va
)
64 for (b
= 0; b
< 4; ++b
)
65 if (va
>= bat_addrs
[b
].start
&& va
< bat_addrs
[b
].limit
)
66 return bat_addrs
[b
].phys
+ (va
- bat_addrs
[b
].start
);
71 * Return VA for a given PA or 0 if not mapped
73 unsigned long p_mapped_by_bats(unsigned long pa
)
76 for (b
= 0; b
< 4; ++b
)
77 if (pa
>= bat_addrs
[b
].phys
78 && pa
< (bat_addrs
[b
].limit
-bat_addrs
[b
].start
)
80 return bat_addrs
[b
].start
+(pa
-bat_addrs
[b
].phys
);
84 unsigned long __init
mmu_mapin_ram(void)
89 unsigned long tot
, bl
, done
;
90 unsigned long max_size
= (256<<20);
93 if (__map_without_bats
)
96 /* Set up BAT2 and if necessary BAT3 to cover RAM. */
98 /* Make sure we don't map a block larger than the
99 smallest alignment of the physical address. */
100 /* alignment of PPC_MEMSTART */
101 align
= ~(PPC_MEMSTART
-1) & PPC_MEMSTART
;
102 /* set BAT block size to MIN(max_size, align) */
103 if (align
&& align
< max_size
)
107 for (bl
= 128<<10; bl
< max_size
; bl
<<= 1) {
112 setbat(2, KERNELBASE
, PPC_MEMSTART
, bl
, _PAGE_RAM
);
113 done
= (unsigned long)bat_addrs
[2].limit
- KERNELBASE
+ 1;
114 if ((done
< tot
) && !bat_addrs
[3].limit
) {
115 /* use BAT3 to cover a bit more */
117 for (bl
= 128<<10; bl
< max_size
; bl
<<= 1)
120 setbat(3, KERNELBASE
+done
, PPC_MEMSTART
+done
, bl
, _PAGE_RAM
);
121 done
= (unsigned long)bat_addrs
[3].limit
- KERNELBASE
+ 1;
129 * Set up one of the I/D BAT (block address translation) register pairs.
130 * The parameters are not checked; in particular size must be a power
131 * of 2 between 128k and 256M.
133 void __init
setbat(int index
, unsigned long virt
, unsigned long phys
,
134 unsigned int size
, int flags
)
138 union ubat
*bat
= BATS
[index
];
140 if (((flags
& _PAGE_NO_CACHE
) == 0) &&
141 cpu_has_feature(CPU_FTR_NEED_COHERENT
))
142 flags
|= _PAGE_COHERENT
;
144 bl
= (size
>> 17) - 1;
145 if (PVR_VER(mfspr(SPRN_PVR
)) != 1) {
148 wimgxpp
= flags
& (_PAGE_WRITETHRU
| _PAGE_NO_CACHE
149 | _PAGE_COHERENT
| _PAGE_GUARDED
);
150 wimgxpp
|= (flags
& _PAGE_RW
)? BPP_RW
: BPP_RX
;
151 bat
[1].word
[0] = virt
| (bl
<< 2) | 2; /* Vs=1, Vp=0 */
152 bat
[1].word
[1] = phys
| wimgxpp
;
153 #ifndef CONFIG_KGDB /* want user access for breakpoints */
154 if (flags
& _PAGE_USER
)
156 bat
[1].bat
.batu
.vp
= 1;
157 if (flags
& _PAGE_GUARDED
) {
158 /* G bit must be zero in IBATs */
159 bat
[0].word
[0] = bat
[0].word
[1] = 0;
161 /* make IBAT same as DBAT */
168 wimgxpp
= flags
& (_PAGE_WRITETHRU
| _PAGE_NO_CACHE
170 wimgxpp
|= (flags
& _PAGE_RW
)?
171 ((flags
& _PAGE_USER
)? PP_RWRW
: PP_RWXX
): PP_RXRX
;
172 bat
->word
[0] = virt
| wimgxpp
| 4; /* Ks=0, Ku=1 */
173 bat
->word
[1] = phys
| bl
| 0x40; /* V=1 */
176 bat_addrs
[index
].start
= virt
;
177 bat_addrs
[index
].limit
= virt
+ ((bl
+ 1) << 17) - 1;
178 bat_addrs
[index
].phys
= phys
;
182 * Initialize the hash table and patch the instructions in hashtable.S.
184 void __init
MMU_init_hw(void)
186 unsigned int hmask
, mb
, mb2
;
187 unsigned int n_hpteg
, lg_n_hpteg
;
189 extern unsigned int hash_page_patch_A
[];
190 extern unsigned int hash_page_patch_B
[], hash_page_patch_C
[];
191 extern unsigned int hash_page
[];
192 extern unsigned int flush_hash_patch_A
[], flush_hash_patch_B
[];
194 if (!cpu_has_feature(CPU_FTR_HPTE_TABLE
)) {
196 * Put a blr (procedure return) instruction at the
197 * start of hash_page, since we can still get DSI
198 * exceptions on a 603.
200 hash_page
[0] = 0x4e800020;
201 flush_icache_range((unsigned long) &hash_page
[0],
202 (unsigned long) &hash_page
[1]);
206 if ( ppc_md
.progress
) ppc_md
.progress("hash:enter", 0x105);
208 #ifdef CONFIG_PPC64BRIDGE
209 #define LG_HPTEG_SIZE 7 /* 128 bytes per HPTEG */
210 #define SDR1_LOW_BITS (lg_n_hpteg - 11)
211 #define MIN_N_HPTEG 2048 /* min 256kB hash table */
213 #define LG_HPTEG_SIZE 6 /* 64 bytes per HPTEG */
214 #define SDR1_LOW_BITS ((n_hpteg - 1) >> 10)
215 #define MIN_N_HPTEG 1024 /* min 64kB hash table */
219 /* The hash table has already been allocated and initialized
221 n_hpteg
= Hash_size
>> LG_HPTEG_SIZE
;
222 lg_n_hpteg
= __ilog2(n_hpteg
);
224 /* Remove the hash table from the available memory */
226 reserve_phys_mem(__pa(Hash
), Hash_size
);
228 #else /* CONFIG_POWER4 */
230 * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
231 * This is less than the recommended amount, but then
234 n_hpteg
= total_memory
/ (PAGE_SIZE
* 8);
235 if (n_hpteg
< MIN_N_HPTEG
)
236 n_hpteg
= MIN_N_HPTEG
;
237 lg_n_hpteg
= __ilog2(n_hpteg
);
238 if (n_hpteg
& (n_hpteg
- 1)) {
239 ++lg_n_hpteg
; /* round up if not power of 2 */
240 n_hpteg
= 1 << lg_n_hpteg
;
242 Hash_size
= n_hpteg
<< LG_HPTEG_SIZE
;
245 * Find some memory for the hash table.
247 if ( ppc_md
.progress
) ppc_md
.progress("hash:find piece", 0x322);
248 Hash
= mem_pieces_find(Hash_size
, Hash_size
);
249 cacheable_memzero(Hash
, Hash_size
);
250 _SDR1
= __pa(Hash
) | SDR1_LOW_BITS
;
251 #endif /* CONFIG_POWER4 */
253 Hash_end
= (PTE
*) ((unsigned long)Hash
+ Hash_size
);
255 printk("Total memory = %ldMB; using %ldkB for hash table (at %p)\n",
256 total_memory
>> 20, Hash_size
>> 10, Hash
);
260 * Patch up the instructions in hashtable.S:create_hpte
262 if ( ppc_md
.progress
) ppc_md
.progress("hash:patch", 0x345);
263 Hash_mask
= n_hpteg
- 1;
264 hmask
= Hash_mask
>> (16 - LG_HPTEG_SIZE
);
265 mb2
= mb
= 32 - LG_HPTEG_SIZE
- lg_n_hpteg
;
267 mb2
= 16 - LG_HPTEG_SIZE
;
269 hash_page_patch_A
[0] = (hash_page_patch_A
[0] & ~0xffff)
270 | ((unsigned int)(Hash
) >> 16);
271 hash_page_patch_A
[1] = (hash_page_patch_A
[1] & ~0x7c0) | (mb
<< 6);
272 hash_page_patch_A
[2] = (hash_page_patch_A
[2] & ~0x7c0) | (mb2
<< 6);
273 hash_page_patch_B
[0] = (hash_page_patch_B
[0] & ~0xffff) | hmask
;
274 hash_page_patch_C
[0] = (hash_page_patch_C
[0] & ~0xffff) | hmask
;
277 * Ensure that the locations we've patched have been written
278 * out from the data cache and invalidated in the instruction
279 * cache, on those machines with split caches.
281 flush_icache_range((unsigned long) &hash_page_patch_A
[0],
282 (unsigned long) &hash_page_patch_C
[1]);
285 * Patch up the instructions in hashtable.S:flush_hash_page
287 flush_hash_patch_A
[0] = (flush_hash_patch_A
[0] & ~0xffff)
288 | ((unsigned int)(Hash
) >> 16);
289 flush_hash_patch_A
[1] = (flush_hash_patch_A
[1] & ~0x7c0) | (mb
<< 6);
290 flush_hash_patch_A
[2] = (flush_hash_patch_A
[2] & ~0x7c0) | (mb2
<< 6);
291 flush_hash_patch_B
[0] = (flush_hash_patch_B
[0] & ~0xffff) | hmask
;
292 flush_icache_range((unsigned long) &flush_hash_patch_A
[0],
293 (unsigned long) &flush_hash_patch_B
[1]);
295 if ( ppc_md
.progress
) ppc_md
.progress("hash:done", 0x205);