PCI MSI: Don't disable MSIs if the mask bit isn't supported
[linux-2.6/mini2440.git] / drivers / pci / msi.c
blob18354817173ccaaeaf9110e0c5c9be4aeb50a2b1
1 /*
2 * File: msi.c
3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 */
9 #include <linux/err.h>
10 #include <linux/mm.h>
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
20 #include <asm/errno.h>
21 #include <asm/io.h>
23 #include "pci.h"
24 #include "msi.h"
26 static int pci_msi_enable = 1;
28 /* Arch hooks */
30 int __attribute__ ((weak))
31 arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
33 return 0;
36 int __attribute__ ((weak))
37 arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *entry)
39 return 0;
42 int __attribute__ ((weak))
43 arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
45 struct msi_desc *entry;
46 int ret;
48 list_for_each_entry(entry, &dev->msi_list, list) {
49 ret = arch_setup_msi_irq(dev, entry);
50 if (ret)
51 return ret;
54 return 0;
57 void __attribute__ ((weak)) arch_teardown_msi_irq(unsigned int irq)
59 return;
62 void __attribute__ ((weak))
63 arch_teardown_msi_irqs(struct pci_dev *dev)
65 struct msi_desc *entry;
67 list_for_each_entry(entry, &dev->msi_list, list) {
68 if (entry->irq != 0)
69 arch_teardown_msi_irq(entry->irq);
73 static void __msi_set_enable(struct pci_dev *dev, int pos, int enable)
75 u16 control;
77 if (pos) {
78 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
79 control &= ~PCI_MSI_FLAGS_ENABLE;
80 if (enable)
81 control |= PCI_MSI_FLAGS_ENABLE;
82 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
86 static void msi_set_enable(struct pci_dev *dev, int enable)
88 __msi_set_enable(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), enable);
91 static void msix_set_enable(struct pci_dev *dev, int enable)
93 int pos;
94 u16 control;
96 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
97 if (pos) {
98 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
99 control &= ~PCI_MSIX_FLAGS_ENABLE;
100 if (enable)
101 control |= PCI_MSIX_FLAGS_ENABLE;
102 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
106 static void msix_flush_writes(unsigned int irq)
108 struct msi_desc *entry;
110 entry = get_irq_msi(irq);
111 BUG_ON(!entry || !entry->dev);
112 switch (entry->msi_attrib.type) {
113 case PCI_CAP_ID_MSI:
114 /* nothing to do */
115 break;
116 case PCI_CAP_ID_MSIX:
118 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
119 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
120 readl(entry->mask_base + offset);
121 break;
123 default:
124 BUG();
125 break;
130 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
131 * mask all MSI interrupts by clearing the MSI enable bit does not work
132 * reliably as devices without an INTx disable bit will then generate a
133 * level IRQ which will never be cleared.
135 * Returns 1 if it succeeded in masking the interrupt and 0 if the device
136 * doesn't support MSI masking.
138 static int msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
140 struct msi_desc *entry;
142 entry = get_irq_msi(irq);
143 BUG_ON(!entry || !entry->dev);
144 switch (entry->msi_attrib.type) {
145 case PCI_CAP_ID_MSI:
146 if (entry->msi_attrib.maskbit) {
147 int pos;
148 u32 mask_bits;
150 pos = (long)entry->mask_base;
151 pci_read_config_dword(entry->dev, pos, &mask_bits);
152 mask_bits &= ~(mask);
153 mask_bits |= flag & mask;
154 pci_write_config_dword(entry->dev, pos, mask_bits);
155 } else {
156 return 0;
158 break;
159 case PCI_CAP_ID_MSIX:
161 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
162 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
163 writel(flag, entry->mask_base + offset);
164 readl(entry->mask_base + offset);
165 break;
167 default:
168 BUG();
169 break;
171 entry->msi_attrib.masked = !!flag;
172 return 1;
175 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
177 struct msi_desc *entry = get_irq_msi(irq);
178 switch(entry->msi_attrib.type) {
179 case PCI_CAP_ID_MSI:
181 struct pci_dev *dev = entry->dev;
182 int pos = entry->msi_attrib.pos;
183 u16 data;
185 pci_read_config_dword(dev, msi_lower_address_reg(pos),
186 &msg->address_lo);
187 if (entry->msi_attrib.is_64) {
188 pci_read_config_dword(dev, msi_upper_address_reg(pos),
189 &msg->address_hi);
190 pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
191 } else {
192 msg->address_hi = 0;
193 pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
195 msg->data = data;
196 break;
198 case PCI_CAP_ID_MSIX:
200 void __iomem *base;
201 base = entry->mask_base +
202 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
204 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
205 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
206 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
207 break;
209 default:
210 BUG();
214 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
216 struct msi_desc *entry = get_irq_msi(irq);
217 switch (entry->msi_attrib.type) {
218 case PCI_CAP_ID_MSI:
220 struct pci_dev *dev = entry->dev;
221 int pos = entry->msi_attrib.pos;
223 pci_write_config_dword(dev, msi_lower_address_reg(pos),
224 msg->address_lo);
225 if (entry->msi_attrib.is_64) {
226 pci_write_config_dword(dev, msi_upper_address_reg(pos),
227 msg->address_hi);
228 pci_write_config_word(dev, msi_data_reg(pos, 1),
229 msg->data);
230 } else {
231 pci_write_config_word(dev, msi_data_reg(pos, 0),
232 msg->data);
234 break;
236 case PCI_CAP_ID_MSIX:
238 void __iomem *base;
239 base = entry->mask_base +
240 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
242 writel(msg->address_lo,
243 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
244 writel(msg->address_hi,
245 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
246 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
247 break;
249 default:
250 BUG();
252 entry->msg = *msg;
255 void mask_msi_irq(unsigned int irq)
257 msi_set_mask_bits(irq, 1, 1);
258 msix_flush_writes(irq);
261 void unmask_msi_irq(unsigned int irq)
263 msi_set_mask_bits(irq, 1, 0);
264 msix_flush_writes(irq);
267 static int msi_free_irqs(struct pci_dev* dev);
270 static struct msi_desc* alloc_msi_entry(void)
272 struct msi_desc *entry;
274 entry = kzalloc(sizeof(struct msi_desc), GFP_KERNEL);
275 if (!entry)
276 return NULL;
278 INIT_LIST_HEAD(&entry->list);
279 entry->irq = 0;
280 entry->dev = NULL;
282 return entry;
285 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
287 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
288 pci_intx(dev, enable);
291 static void __pci_restore_msi_state(struct pci_dev *dev)
293 int pos;
294 u16 control;
295 struct msi_desc *entry;
297 if (!dev->msi_enabled)
298 return;
300 entry = get_irq_msi(dev->irq);
301 pos = entry->msi_attrib.pos;
303 pci_intx_for_msi(dev, 0);
304 msi_set_enable(dev, 0);
305 write_msi_msg(dev->irq, &entry->msg);
306 if (entry->msi_attrib.maskbit)
307 msi_set_mask_bits(dev->irq, entry->msi_attrib.maskbits_mask,
308 entry->msi_attrib.masked);
310 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
311 control &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
312 if (entry->msi_attrib.maskbit || !entry->msi_attrib.masked)
313 control |= PCI_MSI_FLAGS_ENABLE;
314 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
317 static void __pci_restore_msix_state(struct pci_dev *dev)
319 int pos;
320 struct msi_desc *entry;
321 u16 control;
323 if (!dev->msix_enabled)
324 return;
326 /* route the table */
327 pci_intx_for_msi(dev, 0);
328 msix_set_enable(dev, 0);
330 list_for_each_entry(entry, &dev->msi_list, list) {
331 write_msi_msg(entry->irq, &entry->msg);
332 msi_set_mask_bits(entry->irq, 1, entry->msi_attrib.masked);
335 BUG_ON(list_empty(&dev->msi_list));
336 entry = list_entry(dev->msi_list.next, struct msi_desc, list);
337 pos = entry->msi_attrib.pos;
338 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
339 control &= ~PCI_MSIX_FLAGS_MASKALL;
340 control |= PCI_MSIX_FLAGS_ENABLE;
341 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
344 void pci_restore_msi_state(struct pci_dev *dev)
346 __pci_restore_msi_state(dev);
347 __pci_restore_msix_state(dev);
349 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
352 * msi_capability_init - configure device's MSI capability structure
353 * @dev: pointer to the pci_dev data structure of MSI device function
355 * Setup the MSI capability structure of device function with a single
356 * MSI irq, regardless of device function is capable of handling
357 * multiple messages. A return of zero indicates the successful setup
358 * of an entry zero with the new MSI irq or non-zero for otherwise.
360 static int msi_capability_init(struct pci_dev *dev)
362 struct msi_desc *entry;
363 int pos, ret;
364 u16 control;
366 msi_set_enable(dev, 0); /* Ensure msi is disabled as I set it up */
368 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
369 pci_read_config_word(dev, msi_control_reg(pos), &control);
370 /* MSI Entry Initialization */
371 entry = alloc_msi_entry();
372 if (!entry)
373 return -ENOMEM;
375 entry->msi_attrib.type = PCI_CAP_ID_MSI;
376 entry->msi_attrib.is_64 = is_64bit_address(control);
377 entry->msi_attrib.entry_nr = 0;
378 entry->msi_attrib.maskbit = is_mask_bit_support(control);
379 entry->msi_attrib.masked = 1;
380 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
381 entry->msi_attrib.pos = pos;
382 if (is_mask_bit_support(control)) {
383 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
384 is_64bit_address(control));
386 entry->dev = dev;
387 if (entry->msi_attrib.maskbit) {
388 unsigned int maskbits, temp;
389 /* All MSIs are unmasked by default, Mask them all */
390 pci_read_config_dword(dev,
391 msi_mask_bits_reg(pos, is_64bit_address(control)),
392 &maskbits);
393 temp = (1 << multi_msi_capable(control));
394 temp = ((temp - 1) & ~temp);
395 maskbits |= temp;
396 pci_write_config_dword(dev,
397 msi_mask_bits_reg(pos, is_64bit_address(control)),
398 maskbits);
399 entry->msi_attrib.maskbits_mask = temp;
401 list_add_tail(&entry->list, &dev->msi_list);
403 /* Configure MSI capability structure */
404 ret = arch_setup_msi_irqs(dev, 1, PCI_CAP_ID_MSI);
405 if (ret) {
406 msi_free_irqs(dev);
407 return ret;
410 /* Set MSI enabled bits */
411 pci_intx_for_msi(dev, 0);
412 msi_set_enable(dev, 1);
413 dev->msi_enabled = 1;
415 dev->irq = entry->irq;
416 return 0;
420 * msix_capability_init - configure device's MSI-X capability
421 * @dev: pointer to the pci_dev data structure of MSI-X device function
422 * @entries: pointer to an array of struct msix_entry entries
423 * @nvec: number of @entries
425 * Setup the MSI-X capability structure of device function with a
426 * single MSI-X irq. A return of zero indicates the successful setup of
427 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
429 static int msix_capability_init(struct pci_dev *dev,
430 struct msix_entry *entries, int nvec)
432 struct msi_desc *entry;
433 int pos, i, j, nr_entries, ret;
434 unsigned long phys_addr;
435 u32 table_offset;
436 u16 control;
437 u8 bir;
438 void __iomem *base;
440 msix_set_enable(dev, 0);/* Ensure msix is disabled as I set it up */
442 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
443 /* Request & Map MSI-X table region */
444 pci_read_config_word(dev, msi_control_reg(pos), &control);
445 nr_entries = multi_msix_capable(control);
447 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
448 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
449 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
450 phys_addr = pci_resource_start (dev, bir) + table_offset;
451 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
452 if (base == NULL)
453 return -ENOMEM;
455 /* MSI-X Table Initialization */
456 for (i = 0; i < nvec; i++) {
457 entry = alloc_msi_entry();
458 if (!entry)
459 break;
461 j = entries[i].entry;
462 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
463 entry->msi_attrib.is_64 = 1;
464 entry->msi_attrib.entry_nr = j;
465 entry->msi_attrib.maskbit = 1;
466 entry->msi_attrib.masked = 1;
467 entry->msi_attrib.default_irq = dev->irq;
468 entry->msi_attrib.pos = pos;
469 entry->dev = dev;
470 entry->mask_base = base;
472 list_add_tail(&entry->list, &dev->msi_list);
475 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
476 if (ret) {
477 int avail = 0;
478 list_for_each_entry(entry, &dev->msi_list, list) {
479 if (entry->irq != 0) {
480 avail++;
484 msi_free_irqs(dev);
486 /* If we had some success report the number of irqs
487 * we succeeded in setting up.
489 if (avail == 0)
490 avail = ret;
491 return avail;
494 i = 0;
495 list_for_each_entry(entry, &dev->msi_list, list) {
496 entries[i].vector = entry->irq;
497 set_irq_msi(entry->irq, entry);
498 i++;
500 /* Set MSI-X enabled bits */
501 pci_intx_for_msi(dev, 0);
502 msix_set_enable(dev, 1);
503 dev->msix_enabled = 1;
505 return 0;
509 * pci_msi_check_device - check whether MSI may be enabled on a device
510 * @dev: pointer to the pci_dev data structure of MSI device function
511 * @nvec: how many MSIs have been requested ?
512 * @type: are we checking for MSI or MSI-X ?
514 * Look at global flags, the device itself, and its parent busses
515 * to determine if MSI/-X are supported for the device. If MSI/-X is
516 * supported return 0, else return an error code.
518 static int pci_msi_check_device(struct pci_dev* dev, int nvec, int type)
520 struct pci_bus *bus;
521 int ret;
523 /* MSI must be globally enabled and supported by the device */
524 if (!pci_msi_enable || !dev || dev->no_msi)
525 return -EINVAL;
528 * You can't ask to have 0 or less MSIs configured.
529 * a) it's stupid ..
530 * b) the list manipulation code assumes nvec >= 1.
532 if (nvec < 1)
533 return -ERANGE;
535 /* Any bridge which does NOT route MSI transactions from it's
536 * secondary bus to it's primary bus must set NO_MSI flag on
537 * the secondary pci_bus.
538 * We expect only arch-specific PCI host bus controller driver
539 * or quirks for specific PCI bridges to be setting NO_MSI.
541 for (bus = dev->bus; bus; bus = bus->parent)
542 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
543 return -EINVAL;
545 ret = arch_msi_check_device(dev, nvec, type);
546 if (ret)
547 return ret;
549 if (!pci_find_capability(dev, type))
550 return -EINVAL;
552 return 0;
556 * pci_enable_msi - configure device's MSI capability structure
557 * @dev: pointer to the pci_dev data structure of MSI device function
559 * Setup the MSI capability structure of device function with
560 * a single MSI irq upon its software driver call to request for
561 * MSI mode enabled on its hardware device function. A return of zero
562 * indicates the successful setup of an entry zero with the new MSI
563 * irq or non-zero for otherwise.
565 int pci_enable_msi(struct pci_dev* dev)
567 int status;
569 status = pci_msi_check_device(dev, 1, PCI_CAP_ID_MSI);
570 if (status)
571 return status;
573 WARN_ON(!!dev->msi_enabled);
575 /* Check whether driver already requested for MSI-X irqs */
576 if (dev->msix_enabled) {
577 dev_info(&dev->dev, "can't enable MSI "
578 "(MSI-X already enabled)\n");
579 return -EINVAL;
581 status = msi_capability_init(dev);
582 return status;
584 EXPORT_SYMBOL(pci_enable_msi);
586 void pci_msi_shutdown(struct pci_dev* dev)
588 struct msi_desc *entry;
590 if (!pci_msi_enable || !dev || !dev->msi_enabled)
591 return;
593 msi_set_enable(dev, 0);
594 pci_intx_for_msi(dev, 1);
595 dev->msi_enabled = 0;
597 BUG_ON(list_empty(&dev->msi_list));
598 entry = list_entry(dev->msi_list.next, struct msi_desc, list);
599 /* Return the the pci reset with msi irqs unmasked */
600 if (entry->msi_attrib.maskbit) {
601 u32 mask = entry->msi_attrib.maskbits_mask;
602 msi_set_mask_bits(dev->irq, mask, ~mask);
604 if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI)
605 return;
607 /* Restore dev->irq to its default pin-assertion irq */
608 dev->irq = entry->msi_attrib.default_irq;
610 void pci_disable_msi(struct pci_dev* dev)
612 struct msi_desc *entry;
614 if (!pci_msi_enable || !dev || !dev->msi_enabled)
615 return;
617 pci_msi_shutdown(dev);
619 entry = list_entry(dev->msi_list.next, struct msi_desc, list);
620 if (!entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI)
621 return;
623 msi_free_irqs(dev);
625 EXPORT_SYMBOL(pci_disable_msi);
627 static int msi_free_irqs(struct pci_dev* dev)
629 struct msi_desc *entry, *tmp;
631 list_for_each_entry(entry, &dev->msi_list, list) {
632 if (entry->irq)
633 BUG_ON(irq_has_action(entry->irq));
636 arch_teardown_msi_irqs(dev);
638 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
639 if (entry->msi_attrib.type == PCI_CAP_ID_MSIX) {
640 writel(1, entry->mask_base + entry->msi_attrib.entry_nr
641 * PCI_MSIX_ENTRY_SIZE
642 + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
644 if (list_is_last(&entry->list, &dev->msi_list))
645 iounmap(entry->mask_base);
647 list_del(&entry->list);
648 kfree(entry);
651 return 0;
655 * pci_enable_msix - configure device's MSI-X capability structure
656 * @dev: pointer to the pci_dev data structure of MSI-X device function
657 * @entries: pointer to an array of MSI-X entries
658 * @nvec: number of MSI-X irqs requested for allocation by device driver
660 * Setup the MSI-X capability structure of device function with the number
661 * of requested irqs upon its software driver call to request for
662 * MSI-X mode enabled on its hardware device function. A return of zero
663 * indicates the successful configuration of MSI-X capability structure
664 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
665 * Or a return of > 0 indicates that driver request is exceeding the number
666 * of irqs available. Driver should use the returned value to re-send
667 * its request.
669 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
671 int status, pos, nr_entries;
672 int i, j;
673 u16 control;
675 if (!entries)
676 return -EINVAL;
678 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
679 if (status)
680 return status;
682 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
683 pci_read_config_word(dev, msi_control_reg(pos), &control);
684 nr_entries = multi_msix_capable(control);
685 if (nvec > nr_entries)
686 return -EINVAL;
688 /* Check for any invalid entries */
689 for (i = 0; i < nvec; i++) {
690 if (entries[i].entry >= nr_entries)
691 return -EINVAL; /* invalid entry */
692 for (j = i + 1; j < nvec; j++) {
693 if (entries[i].entry == entries[j].entry)
694 return -EINVAL; /* duplicate entry */
697 WARN_ON(!!dev->msix_enabled);
699 /* Check whether driver already requested for MSI irq */
700 if (dev->msi_enabled) {
701 dev_info(&dev->dev, "can't enable MSI-X "
702 "(MSI IRQ already assigned)\n");
703 return -EINVAL;
705 status = msix_capability_init(dev, entries, nvec);
706 return status;
708 EXPORT_SYMBOL(pci_enable_msix);
710 static void msix_free_all_irqs(struct pci_dev *dev)
712 msi_free_irqs(dev);
715 void pci_msix_shutdown(struct pci_dev* dev)
717 if (!pci_msi_enable || !dev || !dev->msix_enabled)
718 return;
720 msix_set_enable(dev, 0);
721 pci_intx_for_msi(dev, 1);
722 dev->msix_enabled = 0;
724 void pci_disable_msix(struct pci_dev* dev)
726 if (!pci_msi_enable || !dev || !dev->msix_enabled)
727 return;
729 pci_msix_shutdown(dev);
731 msix_free_all_irqs(dev);
733 EXPORT_SYMBOL(pci_disable_msix);
736 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
737 * @dev: pointer to the pci_dev data structure of MSI(X) device function
739 * Being called during hotplug remove, from which the device function
740 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
741 * allocated for this device function, are reclaimed to unused state,
742 * which may be used later on.
744 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
746 if (!pci_msi_enable || !dev)
747 return;
749 if (dev->msi_enabled)
750 msi_free_irqs(dev);
752 if (dev->msix_enabled)
753 msix_free_all_irqs(dev);
756 void pci_no_msi(void)
758 pci_msi_enable = 0;
761 void pci_msi_init_pci_dev(struct pci_dev *dev)
763 INIT_LIST_HEAD(&dev->msi_list);