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[CPUFREQ] Re-enable cpufreq suspend and resume code
[linux-2.6/mini2440.git] / drivers / net / smsc9420.c
blob60abdb1081ad5277c5044227c59540ff6d4348a1
1 /***************************************************************************
2 *
3 * Copyright (C) 2007,2008 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 ***************************************************************************
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/netdevice.h>
24 #include <linux/phy.h>
25 #include <linux/pci.h>
26 #include <linux/if_vlan.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/crc32.h>
29 #include <asm/unaligned.h>
30 #include "smsc9420.h"
31
32 #define DRV_NAME "smsc9420"
33 #define PFX DRV_NAME ": "
34 #define DRV_MDIONAME "smsc9420-mdio"
35 #define DRV_DESCRIPTION "SMSC LAN9420 driver"
36 #define DRV_VERSION "1.01"
37
38 MODULE_LICENSE("GPL");
39 MODULE_VERSION(DRV_VERSION);
40
41 struct smsc9420_dma_desc {
42 u32 status;
43 u32 length;
44 u32 buffer1;
45 u32 buffer2;
46 };
47
48 struct smsc9420_ring_info {
49 struct sk_buff *skb;
50 dma_addr_t mapping;
51 };
52
53 struct smsc9420_pdata {
54 void __iomem *base_addr;
55 struct pci_dev *pdev;
56 struct net_device *dev;
57
58 struct smsc9420_dma_desc *rx_ring;
59 struct smsc9420_dma_desc *tx_ring;
60 struct smsc9420_ring_info *tx_buffers;
61 struct smsc9420_ring_info *rx_buffers;
62 dma_addr_t rx_dma_addr;
63 dma_addr_t tx_dma_addr;
64 int tx_ring_head, tx_ring_tail;
65 int rx_ring_head, rx_ring_tail;
66
67 spinlock_t int_lock;
68 spinlock_t phy_lock;
69
70 struct napi_struct napi;
71
72 bool software_irq_signal;
73 bool rx_csum;
74 u32 msg_enable;
75
76 struct phy_device *phy_dev;
77 struct mii_bus *mii_bus;
78 int phy_irq[PHY_MAX_ADDR];
79 int last_duplex;
80 int last_carrier;
81 };
82
83 static const struct pci_device_id smsc9420_id_table[] = {
84 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
85 { 0, }
86 };
87
88 MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
89
90 #define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
91
92 static uint smsc_debug;
93 static uint debug = -1;
94 module_param(debug, uint, 0);
95 MODULE_PARM_DESC(debug, "debug level");
96
97 #define smsc_dbg(TYPE, f, a...) \
98 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
99 printk(KERN_DEBUG PFX f "\n", ## a); \
100 } while (0)
101
102 #define smsc_info(TYPE, f, a...) \
103 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
104 printk(KERN_INFO PFX f "\n", ## a); \
105 } while (0)
106
107 #define smsc_warn(TYPE, f, a...) \
108 do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
109 printk(KERN_WARNING PFX f "\n", ## a); \
110 } while (0)
111
112 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
113 {
114 return ioread32(pd->base_addr + offset);
115 }
116
117 static inline void
118 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
119 {
120 iowrite32(value, pd->base_addr + offset);
121 }
122
123 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
124 {
125 /* to ensure PCI write completion, we must perform a PCI read */
126 smsc9420_reg_read(pd, ID_REV);
127 }
128
129 static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
130 {
131 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
132 unsigned long flags;
133 u32 addr;
134 int i, reg = -EIO;
135
136 spin_lock_irqsave(&pd->phy_lock, flags);
137
138 /* confirm MII not busy */
139 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
140 smsc_warn(DRV, "MII is busy???");
141 goto out;
142 }
143
144 /* set the address, index & direction (read from PHY) */
145 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
146 MII_ACCESS_MII_READ_;
147 smsc9420_reg_write(pd, MII_ACCESS, addr);
148
149 /* wait for read to complete with 50us timeout */
150 for (i = 0; i < 5; i++) {
151 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
152 MII_ACCESS_MII_BUSY_)) {
153 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
154 goto out;
155 }
156 udelay(10);
157 }
158
159 smsc_warn(DRV, "MII busy timeout!");
160
161 out:
162 spin_unlock_irqrestore(&pd->phy_lock, flags);
163 return reg;
164 }
165
166 static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
167 u16 val)
168 {
169 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
170 unsigned long flags;
171 u32 addr;
172 int i, reg = -EIO;
173
174 spin_lock_irqsave(&pd->phy_lock, flags);
175
176 /* confirm MII not busy */
177 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
178 smsc_warn(DRV, "MII is busy???");
179 goto out;
180 }
181
182 /* put the data to write in the MAC */
183 smsc9420_reg_write(pd, MII_DATA, (u32)val);
184
185 /* set the address, index & direction (write to PHY) */
186 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
187 MII_ACCESS_MII_WRITE_;
188 smsc9420_reg_write(pd, MII_ACCESS, addr);
189
190 /* wait for write to complete with 50us timeout */
191 for (i = 0; i < 5; i++) {
192 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
193 MII_ACCESS_MII_BUSY_)) {
194 reg = 0;
195 goto out;
196 }
197 udelay(10);
198 }
199
200 smsc_warn(DRV, "MII busy timeout!");
201
202 out:
203 spin_unlock_irqrestore(&pd->phy_lock, flags);
204 return reg;
205 }
206
207 /* Returns hash bit number for given MAC address
208 * Example:
209 * 01 00 5E 00 00 01 -> returns bit number 31 */
210 static u32 smsc9420_hash(u8 addr[ETH_ALEN])
211 {
212 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
213 }
214
215 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
216 {
217 int timeout = 100000;
218
219 BUG_ON(!pd);
220
221 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
222 smsc_dbg(DRV, "smsc9420_eeprom_reload: Eeprom busy");
223 return -EIO;
224 }
225
226 smsc9420_reg_write(pd, E2P_CMD,
227 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
228
229 do {
230 udelay(10);
231 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
232 return 0;
233 } while (timeout--);
234
235 smsc_warn(DRV, "smsc9420_eeprom_reload: Eeprom timed out");
236 return -EIO;
237 }
238
239 /* Standard ioctls for mii-tool */
240 static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
241 {
242 struct smsc9420_pdata *pd = netdev_priv(dev);
243
244 if (!netif_running(dev) || !pd->phy_dev)
245 return -EINVAL;
246
247 return phy_mii_ioctl(pd->phy_dev, if_mii(ifr), cmd);
248 }
249
250 static int smsc9420_ethtool_get_settings(struct net_device *dev,
251 struct ethtool_cmd *cmd)
252 {
253 struct smsc9420_pdata *pd = netdev_priv(dev);
254
255 cmd->maxtxpkt = 1;
256 cmd->maxrxpkt = 1;
257 return phy_ethtool_gset(pd->phy_dev, cmd);
258 }
259
260 static int smsc9420_ethtool_set_settings(struct net_device *dev,
261 struct ethtool_cmd *cmd)
262 {
263 struct smsc9420_pdata *pd = netdev_priv(dev);
264
265 return phy_ethtool_sset(pd->phy_dev, cmd);
266 }
267
268 static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
269 struct ethtool_drvinfo *drvinfo)
270 {
271 struct smsc9420_pdata *pd = netdev_priv(netdev);
272
273 strcpy(drvinfo->driver, DRV_NAME);
274 strcpy(drvinfo->bus_info, pci_name(pd->pdev));
275 strcpy(drvinfo->version, DRV_VERSION);
276 }
277
278 static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
279 {
280 struct smsc9420_pdata *pd = netdev_priv(netdev);
281 return pd->msg_enable;
282 }
283
284 static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
285 {
286 struct smsc9420_pdata *pd = netdev_priv(netdev);
287 pd->msg_enable = data;
288 }
289
290 static int smsc9420_ethtool_nway_reset(struct net_device *netdev)
291 {
292 struct smsc9420_pdata *pd = netdev_priv(netdev);
293 return phy_start_aneg(pd->phy_dev);
294 }
295
296 static int smsc9420_ethtool_getregslen(struct net_device *dev)
297 {
298 /* all smsc9420 registers plus all phy registers */
299 return 0x100 + (32 * sizeof(u32));
300 }
301
302 static void
303 smsc9420_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
304 void *buf)
305 {
306 struct smsc9420_pdata *pd = netdev_priv(dev);
307 struct phy_device *phy_dev = pd->phy_dev;
308 unsigned int i, j = 0;
309 u32 *data = buf;
310
311 regs->version = smsc9420_reg_read(pd, ID_REV);
312 for (i = 0; i < 0x100; i += (sizeof(u32)))
313 data[j++] = smsc9420_reg_read(pd, i);
314
315 for (i = 0; i <= 31; i++)
316 data[j++] = smsc9420_mii_read(phy_dev->bus, phy_dev->addr, i);
317 }
318
319 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
320 {
321 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
322 temp &= ~GPIO_CFG_EEPR_EN_;
323 smsc9420_reg_write(pd, GPIO_CFG, temp);
324 msleep(1);
325 }
326
327 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
328 {
329 int timeout = 100;
330 u32 e2cmd;
331
332 smsc_dbg(HW, "op 0x%08x", op);
333 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
334 smsc_warn(HW, "Busy at start");
335 return -EBUSY;
336 }
337
338 e2cmd = op | E2P_CMD_EPC_BUSY_;
339 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
340
341 do {
342 msleep(1);
343 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
344 } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
345
346 if (!timeout) {
347 smsc_info(HW, "TIMED OUT");
348 return -EAGAIN;
349 }
350
351 if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
352 smsc_info(HW, "Error occured during eeprom operation");
353 return -EINVAL;
354 }
355
356 return 0;
357 }
358
359 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
360 u8 address, u8 *data)
361 {
362 u32 op = E2P_CMD_EPC_CMD_READ_ | address;
363 int ret;
364
365 smsc_dbg(HW, "address 0x%x", address);
366 ret = smsc9420_eeprom_send_cmd(pd, op);
367
368 if (!ret)
369 data[address] = smsc9420_reg_read(pd, E2P_DATA);
370
371 return ret;
372 }
373
374 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
375 u8 address, u8 data)
376 {
377 u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
378 int ret;
379
380 smsc_dbg(HW, "address 0x%x, data 0x%x", address, data);
381 ret = smsc9420_eeprom_send_cmd(pd, op);
382
383 if (!ret) {
384 op = E2P_CMD_EPC_CMD_WRITE_ | address;
385 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
386 ret = smsc9420_eeprom_send_cmd(pd, op);
387 }
388
389 return ret;
390 }
391
392 static int smsc9420_ethtool_get_eeprom_len(struct net_device *dev)
393 {
394 return SMSC9420_EEPROM_SIZE;
395 }
396
397 static int smsc9420_ethtool_get_eeprom(struct net_device *dev,
398 struct ethtool_eeprom *eeprom, u8 *data)
399 {
400 struct smsc9420_pdata *pd = netdev_priv(dev);
401 u8 eeprom_data[SMSC9420_EEPROM_SIZE];
402 int len, i;
403
404 smsc9420_eeprom_enable_access(pd);
405
406 len = min(eeprom->len, SMSC9420_EEPROM_SIZE);
407 for (i = 0; i < len; i++) {
408 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
409 if (ret < 0) {
410 eeprom->len = 0;
411 return ret;
412 }
413 }
414
415 memcpy(data, &eeprom_data[eeprom->offset], len);
416 eeprom->magic = SMSC9420_EEPROM_MAGIC;
417 eeprom->len = len;
418 return 0;
419 }
420
421 static int smsc9420_ethtool_set_eeprom(struct net_device *dev,
422 struct ethtool_eeprom *eeprom, u8 *data)
423 {
424 struct smsc9420_pdata *pd = netdev_priv(dev);
425 int ret;
426
427 if (eeprom->magic != SMSC9420_EEPROM_MAGIC)
428 return -EINVAL;
429
430 smsc9420_eeprom_enable_access(pd);
431 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
432 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
433 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
434
435 /* Single byte write, according to man page */
436 eeprom->len = 1;
437
438 return ret;
439 }
440
441 static const struct ethtool_ops smsc9420_ethtool_ops = {
442 .get_settings = smsc9420_ethtool_get_settings,
443 .set_settings = smsc9420_ethtool_set_settings,
444 .get_drvinfo = smsc9420_ethtool_get_drvinfo,
445 .get_msglevel = smsc9420_ethtool_get_msglevel,
446 .set_msglevel = smsc9420_ethtool_set_msglevel,
447 .nway_reset = smsc9420_ethtool_nway_reset,
448 .get_link = ethtool_op_get_link,
449 .get_eeprom_len = smsc9420_ethtool_get_eeprom_len,
450 .get_eeprom = smsc9420_ethtool_get_eeprom,
451 .set_eeprom = smsc9420_ethtool_set_eeprom,
452 .get_regs_len = smsc9420_ethtool_getregslen,
453 .get_regs = smsc9420_ethtool_getregs,
454 };
455
456 /* Sets the device MAC address to dev_addr */
457 static void smsc9420_set_mac_address(struct net_device *dev)
458 {
459 struct smsc9420_pdata *pd = netdev_priv(dev);
460 u8 *dev_addr = dev->dev_addr;
461 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
462 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
463 (dev_addr[1] << 8) | dev_addr[0];
464
465 smsc9420_reg_write(pd, ADDRH, mac_high16);
466 smsc9420_reg_write(pd, ADDRL, mac_low32);
467 }
468
469 static void smsc9420_check_mac_address(struct net_device *dev)
470 {
471 struct smsc9420_pdata *pd = netdev_priv(dev);
472
473 /* Check if mac address has been specified when bringing interface up */
474 if (is_valid_ether_addr(dev->dev_addr)) {
475 smsc9420_set_mac_address(dev);
476 smsc_dbg(PROBE, "MAC Address is specified by configuration");
477 } else {
478 /* Try reading mac address from device. if EEPROM is present
479 * it will already have been set */
480 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
481 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
482 dev->dev_addr[0] = (u8)(mac_low32);
483 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
484 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
485 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
486 dev->dev_addr[4] = (u8)(mac_high16);
487 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
488
489 if (is_valid_ether_addr(dev->dev_addr)) {
490 /* eeprom values are valid so use them */
491 smsc_dbg(PROBE, "Mac Address is read from EEPROM");
492 } else {
493 /* eeprom values are invalid, generate random MAC */
494 random_ether_addr(dev->dev_addr);
495 smsc9420_set_mac_address(dev);
496 smsc_dbg(PROBE,
497 "MAC Address is set to random_ether_addr");
498 }
499 }
500 }
501
502 static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
503 {
504 u32 dmac_control, mac_cr, dma_intr_ena;
505 int timeout = 1000;
506
507 /* disable TX DMAC */
508 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
509 dmac_control &= (~DMAC_CONTROL_ST_);
510 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
511
512 /* Wait max 10ms for transmit process to stop */
513 while (--timeout) {
514 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
515 break;
516 udelay(10);
517 }
518
519 if (!timeout)
520 smsc_warn(IFDOWN, "TX DMAC failed to stop");
521
522 /* ACK Tx DMAC stop bit */
523 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
524
525 /* mask TX DMAC interrupts */
526 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
527 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
528 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
529 smsc9420_pci_flush_write(pd);
530
531 /* stop MAC TX */
532 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
533 smsc9420_reg_write(pd, MAC_CR, mac_cr);
534 smsc9420_pci_flush_write(pd);
535 }
536
537 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
538 {
539 int i;
540
541 BUG_ON(!pd->tx_ring);
542
543 if (!pd->tx_buffers)
544 return;
545
546 for (i = 0; i < TX_RING_SIZE; i++) {
547 struct sk_buff *skb = pd->tx_buffers[i].skb;
548
549 if (skb) {
550 BUG_ON(!pd->tx_buffers[i].mapping);
551 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping,
552 skb->len, PCI_DMA_TODEVICE);
553 dev_kfree_skb_any(skb);
554 }
555
556 pd->tx_ring[i].status = 0;
557 pd->tx_ring[i].length = 0;
558 pd->tx_ring[i].buffer1 = 0;
559 pd->tx_ring[i].buffer2 = 0;
560 }
561 wmb();
562
563 kfree(pd->tx_buffers);
564 pd->tx_buffers = NULL;
565
566 pd->tx_ring_head = 0;
567 pd->tx_ring_tail = 0;
568 }
569
570 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
571 {
572 int i;
573
574 BUG_ON(!pd->rx_ring);
575
576 if (!pd->rx_buffers)
577 return;
578
579 for (i = 0; i < RX_RING_SIZE; i++) {
580 if (pd->rx_buffers[i].skb)
581 dev_kfree_skb_any(pd->rx_buffers[i].skb);
582
583 if (pd->rx_buffers[i].mapping)
584 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping,
585 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
586
587 pd->rx_ring[i].status = 0;
588 pd->rx_ring[i].length = 0;
589 pd->rx_ring[i].buffer1 = 0;
590 pd->rx_ring[i].buffer2 = 0;
591 }
592 wmb();
593
594 kfree(pd->rx_buffers);
595 pd->rx_buffers = NULL;
596
597 pd->rx_ring_head = 0;
598 pd->rx_ring_tail = 0;
599 }
600
601 static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
602 {
603 int timeout = 1000;
604 u32 mac_cr, dmac_control, dma_intr_ena;
605
606 /* mask RX DMAC interrupts */
607 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
608 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
609 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
610 smsc9420_pci_flush_write(pd);
611
612 /* stop RX MAC prior to stoping DMA */
613 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
614 smsc9420_reg_write(pd, MAC_CR, mac_cr);
615 smsc9420_pci_flush_write(pd);
616
617 /* stop RX DMAC */
618 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
619 dmac_control &= (~DMAC_CONTROL_SR_);
620 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
621 smsc9420_pci_flush_write(pd);
622
623 /* wait up to 10ms for receive to stop */
624 while (--timeout) {
625 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
626 break;
627 udelay(10);
628 }
629
630 if (!timeout)
631 smsc_warn(IFDOWN, "RX DMAC did not stop! timeout.");
632
633 /* ACK the Rx DMAC stop bit */
634 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
635 }
636
637 static irqreturn_t smsc9420_isr(int irq, void *dev_id)
638 {
639 struct smsc9420_pdata *pd = dev_id;
640 u32 int_cfg, int_sts, int_ctl;
641 irqreturn_t ret = IRQ_NONE;
642 ulong flags;
643
644 BUG_ON(!pd);
645 BUG_ON(!pd->base_addr);
646
647 int_cfg = smsc9420_reg_read(pd, INT_CFG);
648
649 /* check if it's our interrupt */
650 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
651 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
652 return IRQ_NONE;
653
654 int_sts = smsc9420_reg_read(pd, INT_STAT);
655
656 if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
657 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
658 u32 ints_to_clear = 0;
659
660 if (status & DMAC_STS_TX_) {
661 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
662 netif_wake_queue(pd->dev);
663 }
664
665 if (status & DMAC_STS_RX_) {
666 /* mask RX DMAC interrupts */
667 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
668 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
669 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
670 smsc9420_pci_flush_write(pd);
671
672 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
673 napi_schedule(&pd->napi);
674 }
675
676 if (ints_to_clear)
677 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
678
679 ret = IRQ_HANDLED;
680 }
681
682 if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
683 /* mask software interrupt */
684 spin_lock_irqsave(&pd->int_lock, flags);
685 int_ctl = smsc9420_reg_read(pd, INT_CTL);
686 int_ctl &= (~INT_CTL_SW_INT_EN_);
687 smsc9420_reg_write(pd, INT_CTL, int_ctl);
688 spin_unlock_irqrestore(&pd->int_lock, flags);
689
690 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
691 pd->software_irq_signal = true;
692 smp_wmb();
693
694 ret = IRQ_HANDLED;
695 }
696
697 /* to ensure PCI write completion, we must perform a PCI read */
698 smsc9420_pci_flush_write(pd);
699
700 return ret;
701 }
702
703 #ifdef CONFIG_NET_POLL_CONTROLLER
704 static void smsc9420_poll_controller(struct net_device *dev)
705 {
706 disable_irq(dev->irq);
707 smsc9420_isr(0, dev);
708 enable_irq(dev->irq);
709 }
710 #endif /* CONFIG_NET_POLL_CONTROLLER */
711
712 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
713 {
714 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
715 smsc9420_reg_read(pd, BUS_MODE);
716 udelay(2);
717 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
718 smsc_warn(DRV, "Software reset not cleared");
719 }
720
721 static int smsc9420_stop(struct net_device *dev)
722 {
723 struct smsc9420_pdata *pd = netdev_priv(dev);
724 u32 int_cfg;
725 ulong flags;
726
727 BUG_ON(!pd);
728 BUG_ON(!pd->phy_dev);
729
730 /* disable master interrupt */
731 spin_lock_irqsave(&pd->int_lock, flags);
732 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
733 smsc9420_reg_write(pd, INT_CFG, int_cfg);
734 spin_unlock_irqrestore(&pd->int_lock, flags);
735
736 netif_tx_disable(dev);
737 napi_disable(&pd->napi);
738
739 smsc9420_stop_tx(pd);
740 smsc9420_free_tx_ring(pd);
741
742 smsc9420_stop_rx(pd);
743 smsc9420_free_rx_ring(pd);
744
745 free_irq(dev->irq, pd);
746
747 smsc9420_dmac_soft_reset(pd);
748
749 phy_stop(pd->phy_dev);
750
751 phy_disconnect(pd->phy_dev);
752 pd->phy_dev = NULL;
753 mdiobus_unregister(pd->mii_bus);
754 mdiobus_free(pd->mii_bus);
755
756 return 0;
757 }
758
759 static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
760 {
761 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
762 dev->stats.rx_errors++;
763 if (desc_status & RDES0_DESCRIPTOR_ERROR_)
764 dev->stats.rx_over_errors++;
765 else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
766 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
767 dev->stats.rx_frame_errors++;
768 else if (desc_status & RDES0_CRC_ERROR_)
769 dev->stats.rx_crc_errors++;
770 }
771
772 if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
773 dev->stats.rx_length_errors++;
774
775 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
776 (desc_status & RDES0_FIRST_DESCRIPTOR_))))
777 dev->stats.rx_length_errors++;
778
779 if (desc_status & RDES0_MULTICAST_FRAME_)
780 dev->stats.multicast++;
781 }
782
783 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
784 const u32 status)
785 {
786 struct net_device *dev = pd->dev;
787 struct sk_buff *skb;
788 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
789 >> RDES0_FRAME_LENGTH_SHFT_;
790
791 /* remove crc from packet lendth */
792 packet_length -= 4;
793
794 if (pd->rx_csum)
795 packet_length -= 2;
796
797 dev->stats.rx_packets++;
798 dev->stats.rx_bytes += packet_length;
799
800 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping,
801 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
802 pd->rx_buffers[index].mapping = 0;
803
804 skb = pd->rx_buffers[index].skb;
805 pd->rx_buffers[index].skb = NULL;
806
807 if (pd->rx_csum) {
808 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
809 NET_IP_ALIGN + packet_length + 4);
810 put_unaligned_le16(hw_csum, &skb->csum);
811 skb->ip_summed = CHECKSUM_COMPLETE;
812 }
813
814 skb_reserve(skb, NET_IP_ALIGN);
815 skb_put(skb, packet_length);
816
817 skb->protocol = eth_type_trans(skb, dev);
818
819 netif_receive_skb(skb);
820 dev->last_rx = jiffies;
821 }
822
823 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
824 {
825 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
826 dma_addr_t mapping;
827
828 BUG_ON(pd->rx_buffers[index].skb);
829 BUG_ON(pd->rx_buffers[index].mapping);
830
831 if (unlikely(!skb)) {
832 smsc_warn(RX_ERR, "Failed to allocate new skb!");
833 return -ENOMEM;
834 }
835
836 skb->dev = pd->dev;
837
838 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb),
839 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
840 if (pci_dma_mapping_error(pd->pdev, mapping)) {
841 dev_kfree_skb_any(skb);
842 smsc_warn(RX_ERR, "pci_map_single failed!");
843 return -ENOMEM;
844 }
845
846 pd->rx_buffers[index].skb = skb;
847 pd->rx_buffers[index].mapping = mapping;
848 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
849 pd->rx_ring[index].status = RDES0_OWN_;
850 wmb();
851
852 return 0;
853 }
854
855 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
856 {
857 while (pd->rx_ring_tail != pd->rx_ring_head) {
858 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
859 break;
860
861 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
862 }
863 }
864
865 static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
866 {
867 struct smsc9420_pdata *pd =
868 container_of(napi, struct smsc9420_pdata, napi);
869 struct net_device *dev = pd->dev;
870 u32 drop_frame_cnt, dma_intr_ena, status;
871 int work_done;
872
873 for (work_done = 0; work_done < budget; work_done++) {
874 rmb();
875 status = pd->rx_ring[pd->rx_ring_head].status;
876
877 /* stop if DMAC owns this dma descriptor */
878 if (status & RDES0_OWN_)
879 break;
880
881 smsc9420_rx_count_stats(dev, status);
882 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
883 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
884 smsc9420_alloc_new_rx_buffers(pd);
885 }
886
887 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
888 dev->stats.rx_dropped +=
889 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
890
891 /* Kick RXDMA */
892 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
893 smsc9420_pci_flush_write(pd);
894
895 if (work_done < budget) {
896 napi_complete(&pd->napi);
897
898 /* re-enable RX DMA interrupts */
899 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
900 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
901 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
902 smsc9420_pci_flush_write(pd);
903 }
904 return work_done;
905 }
906
907 static void
908 smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
909 {
910 if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
911 dev->stats.tx_errors++;
912 if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
913 TDES0_EXCESSIVE_COLLISIONS_))
914 dev->stats.tx_aborted_errors++;
915
916 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
917 dev->stats.tx_carrier_errors++;
918 } else {
919 dev->stats.tx_packets++;
920 dev->stats.tx_bytes += (length & 0x7FF);
921 }
922
923 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
924 dev->stats.collisions += 16;
925 } else {
926 dev->stats.collisions +=
927 (status & TDES0_COLLISION_COUNT_MASK_) >>
928 TDES0_COLLISION_COUNT_SHFT_;
929 }
930
931 if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
932 dev->stats.tx_heartbeat_errors++;
933 }
934
935 /* Check for completed dma transfers, update stats and free skbs */
936 static void smsc9420_complete_tx(struct net_device *dev)
937 {
938 struct smsc9420_pdata *pd = netdev_priv(dev);
939
940 while (pd->tx_ring_tail != pd->tx_ring_head) {
941 int index = pd->tx_ring_tail;
942 u32 status, length;
943
944 rmb();
945 status = pd->tx_ring[index].status;
946 length = pd->tx_ring[index].length;
947
948 /* Check if DMA still owns this descriptor */
949 if (unlikely(TDES0_OWN_ & status))
950 break;
951
952 smsc9420_tx_update_stats(dev, status, length);
953
954 BUG_ON(!pd->tx_buffers[index].skb);
955 BUG_ON(!pd->tx_buffers[index].mapping);
956
957 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping,
958 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE);
959 pd->tx_buffers[index].mapping = 0;
960
961 dev_kfree_skb_any(pd->tx_buffers[index].skb);
962 pd->tx_buffers[index].skb = NULL;
963
964 pd->tx_ring[index].buffer1 = 0;
965 wmb();
966
967 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
968 }
969 }
970
971 static int smsc9420_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
972 {
973 struct smsc9420_pdata *pd = netdev_priv(dev);
974 dma_addr_t mapping;
975 int index = pd->tx_ring_head;
976 u32 tmp_desc1;
977 bool about_to_take_last_desc =
978 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
979
980 smsc9420_complete_tx(dev);
981
982 rmb();
983 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
984 BUG_ON(pd->tx_buffers[index].skb);
985 BUG_ON(pd->tx_buffers[index].mapping);
986
987 mapping = pci_map_single(pd->pdev, skb->data,
988 skb->len, PCI_DMA_TODEVICE);
989 if (pci_dma_mapping_error(pd->pdev, mapping)) {
990 smsc_warn(TX_ERR, "pci_map_single failed, dropping packet");
991 return NETDEV_TX_BUSY;
992 }
993
994 pd->tx_buffers[index].skb = skb;
995 pd->tx_buffers[index].mapping = mapping;
996
997 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
998 if (unlikely(about_to_take_last_desc)) {
999 tmp_desc1 |= TDES1_IC_;
1000 netif_stop_queue(pd->dev);
1001 }
1002
1003 /* check if we are at the last descriptor and need to set EOR */
1004 if (unlikely(index == (TX_RING_SIZE - 1)))
1005 tmp_desc1 |= TDES1_TER_;
1006
1007 pd->tx_ring[index].buffer1 = mapping;
1008 pd->tx_ring[index].length = tmp_desc1;
1009 wmb();
1010
1011 /* increment head */
1012 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
1013
1014 /* assign ownership to DMAC */
1015 pd->tx_ring[index].status = TDES0_OWN_;
1016 wmb();
1017
1018 /* kick the DMA */
1019 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
1020 smsc9420_pci_flush_write(pd);
1021
1022 dev->trans_start = jiffies;
1023
1024 return NETDEV_TX_OK;
1025 }
1026
1027 static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
1028 {
1029 struct smsc9420_pdata *pd = netdev_priv(dev);
1030 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
1031 dev->stats.rx_dropped +=
1032 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
1033 return &dev->stats;
1034 }
1035
1036 static void smsc9420_set_multicast_list(struct net_device *dev)
1037 {
1038 struct smsc9420_pdata *pd = netdev_priv(dev);
1039 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1040
1041 if (dev->flags & IFF_PROMISC) {
1042 smsc_dbg(HW, "Promiscuous Mode Enabled");
1043 mac_cr |= MAC_CR_PRMS_;
1044 mac_cr &= (~MAC_CR_MCPAS_);
1045 mac_cr &= (~MAC_CR_HPFILT_);
1046 } else if (dev->flags & IFF_ALLMULTI) {
1047 smsc_dbg(HW, "Receive all Multicast Enabled");
1048 mac_cr &= (~MAC_CR_PRMS_);
1049 mac_cr |= MAC_CR_MCPAS_;
1050 mac_cr &= (~MAC_CR_HPFILT_);
1051 } else if (dev->mc_count > 0) {
1052 struct dev_mc_list *mc_list = dev->mc_list;
1053 u32 hash_lo = 0, hash_hi = 0;
1054
1055 smsc_dbg(HW, "Multicast filter enabled");
1056 while (mc_list) {
1057 u32 bit_num = smsc9420_hash(mc_list->dmi_addr);
1058 u32 mask = 1 << (bit_num & 0x1F);
1059
1060 if (bit_num & 0x20)
1061 hash_hi |= mask;
1062 else
1063 hash_lo |= mask;
1064
1065 mc_list = mc_list->next;
1066 }
1067 smsc9420_reg_write(pd, HASHH, hash_hi);
1068 smsc9420_reg_write(pd, HASHL, hash_lo);
1069
1070 mac_cr &= (~MAC_CR_PRMS_);
1071 mac_cr &= (~MAC_CR_MCPAS_);
1072 mac_cr |= MAC_CR_HPFILT_;
1073 } else {
1074 smsc_dbg(HW, "Receive own packets only.");
1075 smsc9420_reg_write(pd, HASHH, 0);
1076 smsc9420_reg_write(pd, HASHL, 0);
1077
1078 mac_cr &= (~MAC_CR_PRMS_);
1079 mac_cr &= (~MAC_CR_MCPAS_);
1080 mac_cr &= (~MAC_CR_HPFILT_);
1081 }
1082
1083 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1084 smsc9420_pci_flush_write(pd);
1085 }
1086
1087 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1088 {
1089 struct phy_device *phy_dev = pd->phy_dev;
1090 u32 flow;
1091
1092 if (phy_dev->duplex == DUPLEX_FULL) {
1093 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
1094 u16 rmtadv = phy_read(phy_dev, MII_LPA);
1095 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1096
1097 if (cap & FLOW_CTRL_RX)
1098 flow = 0xFFFF0002;
1099 else
1100 flow = 0;
1101
1102 smsc_info(LINK, "rx pause %s, tx pause %s",
1103 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
1104 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
1105 } else {
1106 smsc_info(LINK, "half duplex");
1107 flow = 0;
1108 }
1109
1110 smsc9420_reg_write(pd, FLOW, flow);
1111 }
1112
1113 /* Update link mode if anything has changed. Called periodically when the
1114 * PHY is in polling mode, even if nothing has changed. */
1115 static void smsc9420_phy_adjust_link(struct net_device *dev)
1116 {
1117 struct smsc9420_pdata *pd = netdev_priv(dev);
1118 struct phy_device *phy_dev = pd->phy_dev;
1119 int carrier;
1120
1121 if (phy_dev->duplex != pd->last_duplex) {
1122 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1123 if (phy_dev->duplex) {
1124 smsc_dbg(LINK, "full duplex mode");
1125 mac_cr |= MAC_CR_FDPX_;
1126 } else {
1127 smsc_dbg(LINK, "half duplex mode");
1128 mac_cr &= ~MAC_CR_FDPX_;
1129 }
1130 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1131
1132 smsc9420_phy_update_flowcontrol(pd);
1133 pd->last_duplex = phy_dev->duplex;
1134 }
1135
1136 carrier = netif_carrier_ok(dev);
1137 if (carrier != pd->last_carrier) {
1138 if (carrier)
1139 smsc_dbg(LINK, "carrier OK");
1140 else
1141 smsc_dbg(LINK, "no carrier");
1142 pd->last_carrier = carrier;
1143 }
1144 }
1145
1146 static int smsc9420_mii_probe(struct net_device *dev)
1147 {
1148 struct smsc9420_pdata *pd = netdev_priv(dev);
1149 struct phy_device *phydev = NULL;
1150
1151 BUG_ON(pd->phy_dev);
1152
1153 /* Device only supports internal PHY at address 1 */
1154 if (!pd->mii_bus->phy_map[1]) {
1155 pr_err("%s: no PHY found at address 1\n", dev->name);
1156 return -ENODEV;
1157 }
1158
1159 phydev = pd->mii_bus->phy_map[1];
1160 smsc_info(PROBE, "PHY addr %d, phy_id 0x%08X", phydev->addr,
1161 phydev->phy_id);
1162
1163 phydev = phy_connect(dev, dev_name(&phydev->dev),
1164 &smsc9420_phy_adjust_link, 0, PHY_INTERFACE_MODE_MII);
1165
1166 if (IS_ERR(phydev)) {
1167 pr_err("%s: Could not attach to PHY\n", dev->name);
1168 return PTR_ERR(phydev);
1169 }
1170
1171 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1172 dev->name, phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1173
1174 /* mask with MAC supported features */
1175 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
1176 SUPPORTED_Asym_Pause);
1177 phydev->advertising = phydev->supported;
1178
1179 pd->phy_dev = phydev;
1180 pd->last_duplex = -1;
1181 pd->last_carrier = -1;
1182
1183 return 0;
1184 }
1185
1186 static int smsc9420_mii_init(struct net_device *dev)
1187 {
1188 struct smsc9420_pdata *pd = netdev_priv(dev);
1189 int err = -ENXIO, i;
1190
1191 pd->mii_bus = mdiobus_alloc();
1192 if (!pd->mii_bus) {
1193 err = -ENOMEM;
1194 goto err_out_1;
1195 }
1196 pd->mii_bus->name = DRV_MDIONAME;
1197 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1198 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1199 pd->mii_bus->priv = pd;
1200 pd->mii_bus->read = smsc9420_mii_read;
1201 pd->mii_bus->write = smsc9420_mii_write;
1202 pd->mii_bus->irq = pd->phy_irq;
1203 for (i = 0; i < PHY_MAX_ADDR; ++i)
1204 pd->mii_bus->irq[i] = PHY_POLL;
1205
1206 /* Mask all PHYs except ID 1 (internal) */
1207 pd->mii_bus->phy_mask = ~(1 << 1);
1208
1209 if (mdiobus_register(pd->mii_bus)) {
1210 smsc_warn(PROBE, "Error registering mii bus");
1211 goto err_out_free_bus_2;
1212 }
1213
1214 if (smsc9420_mii_probe(dev) < 0) {
1215 smsc_warn(PROBE, "Error probing mii bus");
1216 goto err_out_unregister_bus_3;
1217 }
1218
1219 return 0;
1220
1221 err_out_unregister_bus_3:
1222 mdiobus_unregister(pd->mii_bus);
1223 err_out_free_bus_2:
1224 mdiobus_free(pd->mii_bus);
1225 err_out_1:
1226 return err;
1227 }
1228
1229 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1230 {
1231 int i;
1232
1233 BUG_ON(!pd->tx_ring);
1234
1235 pd->tx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1236 TX_RING_SIZE), GFP_KERNEL);
1237 if (!pd->tx_buffers) {
1238 smsc_warn(IFUP, "Failed to allocated tx_buffers");
1239 return -ENOMEM;
1240 }
1241
1242 /* Initialize the TX Ring */
1243 for (i = 0; i < TX_RING_SIZE; i++) {
1244 pd->tx_buffers[i].skb = NULL;
1245 pd->tx_buffers[i].mapping = 0;
1246 pd->tx_ring[i].status = 0;
1247 pd->tx_ring[i].length = 0;
1248 pd->tx_ring[i].buffer1 = 0;
1249 pd->tx_ring[i].buffer2 = 0;
1250 }
1251 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1252 wmb();
1253
1254 pd->tx_ring_head = 0;
1255 pd->tx_ring_tail = 0;
1256
1257 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1258 smsc9420_pci_flush_write(pd);
1259
1260 return 0;
1261 }
1262
1263 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1264 {
1265 int i;
1266
1267 BUG_ON(!pd->rx_ring);
1268
1269 pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1270 RX_RING_SIZE), GFP_KERNEL);
1271 if (pd->rx_buffers == NULL) {
1272 smsc_warn(IFUP, "Failed to allocated rx_buffers");
1273 goto out;
1274 }
1275
1276 /* initialize the rx ring */
1277 for (i = 0; i < RX_RING_SIZE; i++) {
1278 pd->rx_ring[i].status = 0;
1279 pd->rx_ring[i].length = PKT_BUF_SZ;
1280 pd->rx_ring[i].buffer2 = 0;
1281 pd->rx_buffers[i].skb = NULL;
1282 pd->rx_buffers[i].mapping = 0;
1283 }
1284 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1285
1286 /* now allocate the entire ring of skbs */
1287 for (i = 0; i < RX_RING_SIZE; i++) {
1288 if (smsc9420_alloc_rx_buffer(pd, i)) {
1289 smsc_warn(IFUP, "failed to allocate rx skb %d", i);
1290 goto out_free_rx_skbs;
1291 }
1292 }
1293
1294 pd->rx_ring_head = 0;
1295 pd->rx_ring_tail = 0;
1296
1297 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1298 smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1));
1299
1300 if (pd->rx_csum) {
1301 /* Enable RX COE */
1302 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1303 smsc9420_reg_write(pd, COE_CR, coe);
1304 smsc_dbg(IFUP, "COE_CR = 0x%08x", coe);
1305 }
1306
1307 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1308 smsc9420_pci_flush_write(pd);
1309
1310 return 0;
1311
1312 out_free_rx_skbs:
1313 smsc9420_free_rx_ring(pd);
1314 out:
1315 return -ENOMEM;
1316 }
1317
1318 static int smsc9420_open(struct net_device *dev)
1319 {
1320 struct smsc9420_pdata *pd;
1321 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
1322 unsigned long flags;
1323 int result = 0, timeout;
1324
1325 BUG_ON(!dev);
1326 pd = netdev_priv(dev);
1327 BUG_ON(!pd);
1328
1329 if (!is_valid_ether_addr(dev->dev_addr)) {
1330 smsc_warn(IFUP, "dev_addr is not a valid MAC address");
1331 result = -EADDRNOTAVAIL;
1332 goto out_0;
1333 }
1334
1335 netif_carrier_off(dev);
1336
1337 /* disable, mask and acknowlege all interrupts */
1338 spin_lock_irqsave(&pd->int_lock, flags);
1339 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1340 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1341 smsc9420_reg_write(pd, INT_CTL, 0);
1342 spin_unlock_irqrestore(&pd->int_lock, flags);
1343 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1344 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1345 smsc9420_pci_flush_write(pd);
1346
1347 if (request_irq(dev->irq, smsc9420_isr, IRQF_SHARED | IRQF_DISABLED,
1348 DRV_NAME, pd)) {
1349 smsc_warn(IFUP, "Unable to use IRQ = %d", dev->irq);
1350 result = -ENODEV;
1351 goto out_0;
1352 }
1353
1354 smsc9420_dmac_soft_reset(pd);
1355
1356 /* make sure MAC_CR is sane */
1357 smsc9420_reg_write(pd, MAC_CR, 0);
1358
1359 smsc9420_set_mac_address(dev);
1360
1361 /* Configure GPIO pins to drive LEDs */
1362 smsc9420_reg_write(pd, GPIO_CFG,
1363 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1364
1365 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1366
1367 #ifdef __BIG_ENDIAN
1368 bus_mode |= BUS_MODE_DBO_;
1369 #endif
1370
1371 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1372
1373 smsc9420_pci_flush_write(pd);
1374
1375 /* set bus master bridge arbitration priority for Rx and TX DMA */
1376 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1377
1378 smsc9420_reg_write(pd, DMAC_CONTROL,
1379 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1380
1381 smsc9420_pci_flush_write(pd);
1382
1383 /* test the IRQ connection to the ISR */
1384 smsc_dbg(IFUP, "Testing ISR using IRQ %d", dev->irq);
1385 pd->software_irq_signal = false;
1386
1387 spin_lock_irqsave(&pd->int_lock, flags);
1388 /* configure interrupt deassertion timer and enable interrupts */
1389 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1390 int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1391 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1392 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1393
1394 /* unmask software interrupt */
1395 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1396 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1397 spin_unlock_irqrestore(&pd->int_lock, flags);
1398 smsc9420_pci_flush_write(pd);
1399
1400 timeout = 1000;
1401 while (timeout--) {
1402 if (pd->software_irq_signal)
1403 break;
1404 msleep(1);
1405 }
1406
1407 /* disable interrupts */
1408 spin_lock_irqsave(&pd->int_lock, flags);
1409 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1410 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1411 spin_unlock_irqrestore(&pd->int_lock, flags);
1412
1413 if (!pd->software_irq_signal) {
1414 smsc_warn(IFUP, "ISR failed signaling test");
1415 result = -ENODEV;
1416 goto out_free_irq_1;
1417 }
1418
1419 smsc_dbg(IFUP, "ISR passed test using IRQ %d", dev->irq);
1420
1421 result = smsc9420_alloc_tx_ring(pd);
1422 if (result) {
1423 smsc_warn(IFUP, "Failed to Initialize tx dma ring");
1424 result = -ENOMEM;
1425 goto out_free_irq_1;
1426 }
1427
1428 result = smsc9420_alloc_rx_ring(pd);
1429 if (result) {
1430 smsc_warn(IFUP, "Failed to Initialize rx dma ring");
1431 result = -ENOMEM;
1432 goto out_free_tx_ring_2;
1433 }
1434
1435 result = smsc9420_mii_init(dev);
1436 if (result) {
1437 smsc_warn(IFUP, "Failed to initialize Phy");
1438 result = -ENODEV;
1439 goto out_free_rx_ring_3;
1440 }
1441
1442 /* Bring the PHY up */
1443 phy_start(pd->phy_dev);
1444
1445 napi_enable(&pd->napi);
1446
1447 /* start tx and rx */
1448 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1449 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1450
1451 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1452 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1453 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1454 smsc9420_pci_flush_write(pd);
1455
1456 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1457 dma_intr_ena |=
1458 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1459 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1460 smsc9420_pci_flush_write(pd);
1461
1462 netif_wake_queue(dev);
1463
1464 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1465
1466 /* enable interrupts */
1467 spin_lock_irqsave(&pd->int_lock, flags);
1468 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1469 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1470 spin_unlock_irqrestore(&pd->int_lock, flags);
1471
1472 return 0;
1473
1474 out_free_rx_ring_3:
1475 smsc9420_free_rx_ring(pd);
1476 out_free_tx_ring_2:
1477 smsc9420_free_tx_ring(pd);
1478 out_free_irq_1:
1479 free_irq(dev->irq, pd);
1480 out_0:
1481 return result;
1482 }
1483
1484 #ifdef CONFIG_PM
1485
1486 static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state)
1487 {
1488 struct net_device *dev = pci_get_drvdata(pdev);
1489 struct smsc9420_pdata *pd = netdev_priv(dev);
1490 u32 int_cfg;
1491 ulong flags;
1492
1493 /* disable interrupts */
1494 spin_lock_irqsave(&pd->int_lock, flags);
1495 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1496 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1497 spin_unlock_irqrestore(&pd->int_lock, flags);
1498
1499 if (netif_running(dev)) {
1500 netif_tx_disable(dev);
1501 smsc9420_stop_tx(pd);
1502 smsc9420_free_tx_ring(pd);
1503
1504 napi_disable(&pd->napi);
1505 smsc9420_stop_rx(pd);
1506 smsc9420_free_rx_ring(pd);
1507
1508 free_irq(dev->irq, pd);
1509
1510 netif_device_detach(dev);
1511 }
1512
1513 pci_save_state(pdev);
1514 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1515 pci_disable_device(pdev);
1516 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1517
1518 return 0;
1519 }
1520
1521 static int smsc9420_resume(struct pci_dev *pdev)
1522 {
1523 struct net_device *dev = pci_get_drvdata(pdev);
1524 struct smsc9420_pdata *pd = netdev_priv(dev);
1525 int err;
1526
1527 pci_set_power_state(pdev, PCI_D0);
1528 pci_restore_state(pdev);
1529
1530 err = pci_enable_device(pdev);
1531 if (err)
1532 return err;
1533
1534 pci_set_master(pdev);
1535
1536 err = pci_enable_wake(pdev, 0, 0);
1537 if (err)
1538 smsc_warn(IFUP, "pci_enable_wake failed: %d", err);
1539
1540 if (netif_running(dev)) {
1541 err = smsc9420_open(dev);
1542 netif_device_attach(dev);
1543 }
1544 return err;
1545 }
1546
1547 #endif /* CONFIG_PM */
1548
1549 static const struct net_device_ops smsc9420_netdev_ops = {
1550 .ndo_open = smsc9420_open,
1551 .ndo_stop = smsc9420_stop,
1552 .ndo_start_xmit = smsc9420_hard_start_xmit,
1553 .ndo_get_stats = smsc9420_get_stats,
1554 .ndo_set_multicast_list = smsc9420_set_multicast_list,
1555 .ndo_do_ioctl = smsc9420_do_ioctl,
1556 .ndo_validate_addr = eth_validate_addr,
1557 .ndo_set_mac_address = eth_mac_addr,
1558 #ifdef CONFIG_NET_POLL_CONTROLLER
1559 .ndo_poll_controller = smsc9420_poll_controller,
1560 #endif /* CONFIG_NET_POLL_CONTROLLER */
1561 };
1562
1563 static int __devinit
1564 smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1565 {
1566 struct net_device *dev;
1567 struct smsc9420_pdata *pd;
1568 void __iomem *virt_addr;
1569 int result = 0;
1570 u32 id_rev;
1571
1572 printk(KERN_INFO DRV_DESCRIPTION " version " DRV_VERSION "\n");
1573
1574 /* First do the PCI initialisation */
1575 result = pci_enable_device(pdev);
1576 if (unlikely(result)) {
1577 printk(KERN_ERR "Cannot enable smsc9420\n");
1578 goto out_0;
1579 }
1580
1581 pci_set_master(pdev);
1582
1583 dev = alloc_etherdev(sizeof(*pd));
1584 if (!dev) {
1585 printk(KERN_ERR "ether device alloc failed\n");
1586 goto out_disable_pci_device_1;
1587 }
1588
1589 SET_NETDEV_DEV(dev, &pdev->dev);
1590
1591 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
1592 printk(KERN_ERR "Cannot find PCI device base address\n");
1593 goto out_free_netdev_2;
1594 }
1595
1596 if ((pci_request_regions(pdev, DRV_NAME))) {
1597 printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n");
1598 goto out_free_netdev_2;
1599 }
1600
1601 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1602 printk(KERN_ERR "No usable DMA configuration, aborting.\n");
1603 goto out_free_regions_3;
1604 }
1605
1606 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1607 pci_resource_len(pdev, SMSC_BAR));
1608 if (!virt_addr) {
1609 printk(KERN_ERR "Cannot map device registers, aborting.\n");
1610 goto out_free_regions_3;
1611 }
1612
1613 /* registers are double mapped with 0 offset for LE and 0x200 for BE */
1614 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1615
1616 dev->base_addr = (ulong)virt_addr;
1617
1618 pd = netdev_priv(dev);
1619
1620 /* pci descriptors are created in the PCI consistent area */
1621 pd->rx_ring = pci_alloc_consistent(pdev,
1622 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE +
1623 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE,
1624 &pd->rx_dma_addr);
1625
1626 if (!pd->rx_ring)
1627 goto out_free_io_4;
1628
1629 /* descriptors are aligned due to the nature of pci_alloc_consistent */
1630 pd->tx_ring = (struct smsc9420_dma_desc *)
1631 (pd->rx_ring + RX_RING_SIZE);
1632 pd->tx_dma_addr = pd->rx_dma_addr +
1633 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1634
1635 pd->pdev = pdev;
1636 pd->dev = dev;
1637 pd->base_addr = virt_addr;
1638 pd->msg_enable = smsc_debug;
1639 pd->rx_csum = true;
1640
1641 smsc_dbg(PROBE, "lan_base=0x%08lx", (ulong)virt_addr);
1642
1643 id_rev = smsc9420_reg_read(pd, ID_REV);
1644 switch (id_rev & 0xFFFF0000) {
1645 case 0x94200000:
1646 smsc_info(PROBE, "LAN9420 identified, ID_REV=0x%08X", id_rev);
1647 break;
1648 default:
1649 smsc_warn(PROBE, "LAN9420 NOT identified");
1650 smsc_warn(PROBE, "ID_REV=0x%08X", id_rev);
1651 goto out_free_dmadesc_5;
1652 }
1653
1654 smsc9420_dmac_soft_reset(pd);
1655 smsc9420_eeprom_reload(pd);
1656 smsc9420_check_mac_address(dev);
1657
1658 dev->netdev_ops = &smsc9420_netdev_ops;
1659 dev->ethtool_ops = &smsc9420_ethtool_ops;
1660 dev->irq = pdev->irq;
1661
1662 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1663
1664 result = register_netdev(dev);
1665 if (result) {
1666 smsc_warn(PROBE, "error %i registering device", result);
1667 goto out_free_dmadesc_5;
1668 }
1669
1670 pci_set_drvdata(pdev, dev);
1671
1672 spin_lock_init(&pd->int_lock);
1673 spin_lock_init(&pd->phy_lock);
1674
1675 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1676
1677 return 0;
1678
1679 out_free_dmadesc_5:
1680 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1681 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1682 out_free_io_4:
1683 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1684 out_free_regions_3:
1685 pci_release_regions(pdev);
1686 out_free_netdev_2:
1687 free_netdev(dev);
1688 out_disable_pci_device_1:
1689 pci_disable_device(pdev);
1690 out_0:
1691 return -ENODEV;
1692 }
1693
1694 static void __devexit smsc9420_remove(struct pci_dev *pdev)
1695 {
1696 struct net_device *dev;
1697 struct smsc9420_pdata *pd;
1698
1699 dev = pci_get_drvdata(pdev);
1700 if (!dev)
1701 return;
1702
1703 pci_set_drvdata(pdev, NULL);
1704
1705 pd = netdev_priv(dev);
1706 unregister_netdev(dev);
1707
1708 /* tx_buffers and rx_buffers are freed in stop */
1709 BUG_ON(pd->tx_buffers);
1710 BUG_ON(pd->rx_buffers);
1711
1712 BUG_ON(!pd->tx_ring);
1713 BUG_ON(!pd->rx_ring);
1714
1715 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1716 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1717
1718 iounmap(pd->base_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1719 pci_release_regions(pdev);
1720 free_netdev(dev);
1721 pci_disable_device(pdev);
1722 }
1723
1724 static struct pci_driver smsc9420_driver = {
1725 .name = DRV_NAME,
1726 .id_table = smsc9420_id_table,
1727 .probe = smsc9420_probe,
1728 .remove = __devexit_p(smsc9420_remove),
1729 #ifdef CONFIG_PM
1730 .suspend = smsc9420_suspend,
1731 .resume = smsc9420_resume,
1732 #endif /* CONFIG_PM */
1733 };
1734
1735 static int __init smsc9420_init_module(void)
1736 {
1737 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1738
1739 return pci_register_driver(&smsc9420_driver);
1740 }
1741
1742 static void __exit smsc9420_exit_module(void)
1743 {
1744 pci_unregister_driver(&smsc9420_driver);
1745 }
1746
1747 module_init(smsc9420_init_module);
1748 module_exit(smsc9420_exit_module);
Support for the Chinese Samsung S3C2440 based development boards