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[CPUFREQ] Re-enable cpufreq suspend and resume code
[linux-2.6/mini2440.git] / drivers / net / jme.h
blob0996a069ac7b57aedf1b38daae8ee8a7f81264d5
1 /*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24 #ifndef __JME_H_INCLUDED__
25 #define __JME_H_INCLUDED__
26
27 #define DRV_NAME "jme"
28 #define DRV_VERSION "1.0.4"
29 #define PFX DRV_NAME ": "
30
31 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
32 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
33
34 /*
35 * Message related definitions
36 */
37 #define JME_DEF_MSG_ENABLE \
38 (NETIF_MSG_PROBE | \
39 NETIF_MSG_LINK | \
40 NETIF_MSG_RX_ERR | \
41 NETIF_MSG_TX_ERR | \
42 NETIF_MSG_HW)
43
44 #define jeprintk(pdev, fmt, args...) \
45 printk(KERN_ERR PFX fmt, ## args)
46
47 #ifdef TX_DEBUG
48 #define tx_dbg(priv, fmt, args...) \
49 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ## args)
50 #else
51 #define tx_dbg(priv, fmt, args...)
52 #endif
53
54 #define jme_msg(msglvl, type, priv, fmt, args...) \
55 if (netif_msg_##type(priv)) \
56 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
57
58 #define msg_probe(priv, fmt, args...) \
59 jme_msg(KERN_INFO, probe, priv, fmt, ## args)
60
61 #define msg_link(priv, fmt, args...) \
62 jme_msg(KERN_INFO, link, priv, fmt, ## args)
63
64 #define msg_intr(priv, fmt, args...) \
65 jme_msg(KERN_INFO, intr, priv, fmt, ## args)
66
67 #define msg_rx_err(priv, fmt, args...) \
68 jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
69
70 #define msg_rx_status(priv, fmt, args...) \
71 jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
72
73 #define msg_tx_err(priv, fmt, args...) \
74 jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
75
76 #define msg_tx_done(priv, fmt, args...) \
77 jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
78
79 #define msg_tx_queued(priv, fmt, args...) \
80 jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
81
82 #define msg_hw(priv, fmt, args...) \
83 jme_msg(KERN_ERR, hw, priv, fmt, ## args)
84
85 /*
86 * Extra PCI Configuration space interface
87 */
88 #define PCI_DCSR_MRRS 0x59
89 #define PCI_DCSR_MRRS_MASK 0x70
90
91 enum pci_dcsr_mrrs_vals {
92 MRRS_128B = 0x00,
93 MRRS_256B = 0x10,
94 MRRS_512B = 0x20,
95 MRRS_1024B = 0x30,
96 MRRS_2048B = 0x40,
97 MRRS_4096B = 0x50,
98 };
99
100 #define PCI_SPI 0xB0
101
102 enum pci_spi_bits {
103 SPI_EN = 0x10,
104 SPI_MISO = 0x08,
105 SPI_MOSI = 0x04,
106 SPI_SCLK = 0x02,
107 SPI_CS = 0x01,
108 };
109
110 struct jme_spi_op {
111 void __user *uwbuf;
112 void __user *urbuf;
113 __u8 wn; /* Number of write actions */
114 __u8 rn; /* Number of read actions */
115 __u8 bitn; /* Number of bits per action */
116 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
117 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
118
119 /* Internal use only */
120 u8 *kwbuf;
121 u8 *krbuf;
122 u8 sr;
123 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
124 };
125
126 enum jme_spi_op_bits {
127 SPI_MODE_CPHA = 0x01,
128 SPI_MODE_CPOL = 0x02,
129 SPI_MODE_DUP = 0x80,
130 };
131
132 #define HALF_US 500 /* 500 ns */
133 #define JMESPIIOCTL SIOCDEVPRIVATE
134
135 /*
136 * Dynamic(adaptive)/Static PCC values
137 */
138 enum dynamic_pcc_values {
139 PCC_OFF = 0,
140 PCC_P1 = 1,
141 PCC_P2 = 2,
142 PCC_P3 = 3,
143
144 PCC_OFF_TO = 0,
145 PCC_P1_TO = 1,
146 PCC_P2_TO = 64,
147 PCC_P3_TO = 128,
148
149 PCC_OFF_CNT = 0,
150 PCC_P1_CNT = 1,
151 PCC_P2_CNT = 16,
152 PCC_P3_CNT = 32,
153 };
154 struct dynpcc_info {
155 unsigned long last_bytes;
156 unsigned long last_pkts;
157 unsigned long intr_cnt;
158 unsigned char cur;
159 unsigned char attempt;
160 unsigned char cnt;
161 };
162 #define PCC_INTERVAL_US 100000
163 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
164 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
165 #define PCC_P2_THRESHOLD 800
166 #define PCC_INTR_THRESHOLD 800
167 #define PCC_TX_TO 1000
168 #define PCC_TX_CNT 8
169
170 /*
171 * TX/RX Descriptors
172 *
173 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
174 */
175 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
176 #define TX_DESC_SIZE 16
177 #define TX_RING_NR 8
178 #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
179
180 struct txdesc {
181 union {
182 __u8 all[16];
183 __le32 dw[4];
184 struct {
185 /* DW0 */
186 __le16 vlan;
187 __u8 rsv1;
188 __u8 flags;
189
190 /* DW1 */
191 __le16 datalen;
192 __le16 mss;
193
194 /* DW2 */
195 __le16 pktsize;
196 __le16 rsv2;
197
198 /* DW3 */
199 __le32 bufaddr;
200 } desc1;
201 struct {
202 /* DW0 */
203 __le16 rsv1;
204 __u8 rsv2;
205 __u8 flags;
206
207 /* DW1 */
208 __le16 datalen;
209 __le16 rsv3;
210
211 /* DW2 */
212 __le32 bufaddrh;
213
214 /* DW3 */
215 __le32 bufaddrl;
216 } desc2;
217 struct {
218 /* DW0 */
219 __u8 ehdrsz;
220 __u8 rsv1;
221 __u8 rsv2;
222 __u8 flags;
223
224 /* DW1 */
225 __le16 trycnt;
226 __le16 segcnt;
227
228 /* DW2 */
229 __le16 pktsz;
230 __le16 rsv3;
231
232 /* DW3 */
233 __le32 bufaddrl;
234 } descwb;
235 };
236 };
237
238 enum jme_txdesc_flags_bits {
239 TXFLAG_OWN = 0x80,
240 TXFLAG_INT = 0x40,
241 TXFLAG_64BIT = 0x20,
242 TXFLAG_TCPCS = 0x10,
243 TXFLAG_UDPCS = 0x08,
244 TXFLAG_IPCS = 0x04,
245 TXFLAG_LSEN = 0x02,
246 TXFLAG_TAGON = 0x01,
247 };
248
249 #define TXDESC_MSS_SHIFT 2
250 enum jme_rxdescwb_flags_bits {
251 TXWBFLAG_OWN = 0x80,
252 TXWBFLAG_INT = 0x40,
253 TXWBFLAG_TMOUT = 0x20,
254 TXWBFLAG_TRYOUT = 0x10,
255 TXWBFLAG_COL = 0x08,
256
257 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
258 TXWBFLAG_TRYOUT |
259 TXWBFLAG_COL,
260 };
261
262 #define RX_DESC_SIZE 16
263 #define RX_RING_NR 4
264 #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
265 #define RX_BUF_DMA_ALIGN 8
266 #define RX_PREPAD_SIZE 10
267 #define ETH_CRC_LEN 2
268 #define RX_VLANHDR_LEN 2
269 #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
270 ETH_HLEN + \
271 ETH_CRC_LEN + \
272 RX_VLANHDR_LEN + \
273 RX_BUF_DMA_ALIGN)
274
275 struct rxdesc {
276 union {
277 __u8 all[16];
278 __le32 dw[4];
279 struct {
280 /* DW0 */
281 __le16 rsv2;
282 __u8 rsv1;
283 __u8 flags;
284
285 /* DW1 */
286 __le16 datalen;
287 __le16 wbcpl;
288
289 /* DW2 */
290 __le32 bufaddrh;
291
292 /* DW3 */
293 __le32 bufaddrl;
294 } desc1;
295 struct {
296 /* DW0 */
297 __le16 vlan;
298 __le16 flags;
299
300 /* DW1 */
301 __le16 framesize;
302 __u8 errstat;
303 __u8 desccnt;
304
305 /* DW2 */
306 __le32 rsshash;
307
308 /* DW3 */
309 __u8 hashfun;
310 __u8 hashtype;
311 __le16 resrv;
312 } descwb;
313 };
314 };
315
316 enum jme_rxdesc_flags_bits {
317 RXFLAG_OWN = 0x80,
318 RXFLAG_INT = 0x40,
319 RXFLAG_64BIT = 0x20,
320 };
321
322 enum jme_rxwbdesc_flags_bits {
323 RXWBFLAG_OWN = 0x8000,
324 RXWBFLAG_INT = 0x4000,
325 RXWBFLAG_MF = 0x2000,
326 RXWBFLAG_64BIT = 0x2000,
327 RXWBFLAG_TCPON = 0x1000,
328 RXWBFLAG_UDPON = 0x0800,
329 RXWBFLAG_IPCS = 0x0400,
330 RXWBFLAG_TCPCS = 0x0200,
331 RXWBFLAG_UDPCS = 0x0100,
332 RXWBFLAG_TAGON = 0x0080,
333 RXWBFLAG_IPV4 = 0x0040,
334 RXWBFLAG_IPV6 = 0x0020,
335 RXWBFLAG_PAUSE = 0x0010,
336 RXWBFLAG_MAGIC = 0x0008,
337 RXWBFLAG_WAKEUP = 0x0004,
338 RXWBFLAG_DEST = 0x0003,
339 RXWBFLAG_DEST_UNI = 0x0001,
340 RXWBFLAG_DEST_MUL = 0x0002,
341 RXWBFLAG_DEST_BRO = 0x0003,
342 };
343
344 enum jme_rxwbdesc_desccnt_mask {
345 RXWBDCNT_WBCPL = 0x80,
346 RXWBDCNT_DCNT = 0x7F,
347 };
348
349 enum jme_rxwbdesc_errstat_bits {
350 RXWBERR_LIMIT = 0x80,
351 RXWBERR_MIIER = 0x40,
352 RXWBERR_NIBON = 0x20,
353 RXWBERR_COLON = 0x10,
354 RXWBERR_ABORT = 0x08,
355 RXWBERR_SHORT = 0x04,
356 RXWBERR_OVERUN = 0x02,
357 RXWBERR_CRCERR = 0x01,
358 RXWBERR_ALLERR = 0xFF,
359 };
360
361 /*
362 * Buffer information corresponding to ring descriptors.
363 */
364 struct jme_buffer_info {
365 struct sk_buff *skb;
366 dma_addr_t mapping;
367 int len;
368 int nr_desc;
369 unsigned long start_xmit;
370 };
371
372 /*
373 * The structure holding buffer information and ring descriptors all together.
374 */
375 #define MAX_RING_DESC_NR 1024
376 struct jme_ring {
377 void *alloc; /* pointer to allocated memory */
378 void *desc; /* pointer to ring memory */
379 dma_addr_t dmaalloc; /* phys address of ring alloc */
380 dma_addr_t dma; /* phys address for ring dma */
381
382 /* Buffer information corresponding to each descriptor */
383 struct jme_buffer_info bufinf[MAX_RING_DESC_NR];
384
385 int next_to_use;
386 atomic_t next_to_clean;
387 atomic_t nr_free;
388 };
389
390 #define NET_STAT(priv) (priv->dev->stats)
391 #define NETDEV_GET_STATS(netdev, fun_ptr)
392 #define DECLARE_NET_DEVICE_STATS
393
394 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
395 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
396 netif_napi_add(dev, napis, pollfn, q);
397 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
398 #define JME_NAPI_WEIGHT(w) int w
399 #define JME_NAPI_WEIGHT_VAL(w) w
400 #define JME_NAPI_WEIGHT_SET(w, r)
401 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
402 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
403 #define JME_NAPI_DISABLE(priv) \
404 if (!napi_disable_pending(&priv->napi)) \
405 napi_disable(&priv->napi);
406 #define JME_RX_SCHEDULE_PREP(priv) \
407 napi_schedule_prep(&priv->napi)
408 #define JME_RX_SCHEDULE(priv) \
409 __napi_schedule(&priv->napi);
410
411 /*
412 * Jmac Adapter Private data
413 */
414 #define SHADOW_REG_NR 8
415 struct jme_adapter {
416 struct pci_dev *pdev;
417 struct net_device *dev;
418 void __iomem *regs;
419 dma_addr_t shadow_dma;
420 u32 *shadow_regs;
421 struct mii_if_info mii_if;
422 struct jme_ring rxring[RX_RING_NR];
423 struct jme_ring txring[TX_RING_NR];
424 spinlock_t phy_lock;
425 spinlock_t macaddr_lock;
426 spinlock_t rxmcs_lock;
427 struct tasklet_struct rxempty_task;
428 struct tasklet_struct rxclean_task;
429 struct tasklet_struct txclean_task;
430 struct tasklet_struct linkch_task;
431 struct tasklet_struct pcc_task;
432 unsigned long flags;
433 u32 reg_txcs;
434 u32 reg_txpfc;
435 u32 reg_rxcs;
436 u32 reg_rxmcs;
437 u32 reg_ghc;
438 u32 reg_pmcs;
439 u32 phylink;
440 u32 tx_ring_size;
441 u32 tx_ring_mask;
442 u32 tx_wake_threshold;
443 u32 rx_ring_size;
444 u32 rx_ring_mask;
445 u8 mrrs;
446 unsigned int fpgaver;
447 unsigned int chiprev;
448 u8 rev;
449 u32 msg_enable;
450 struct ethtool_cmd old_ecmd;
451 unsigned int old_mtu;
452 struct vlan_group *vlgrp;
453 struct dynpcc_info dpi;
454 atomic_t intr_sem;
455 atomic_t link_changing;
456 atomic_t tx_cleaning;
457 atomic_t rx_cleaning;
458 atomic_t rx_empty;
459 int (*jme_rx)(struct sk_buff *skb);
460 int (*jme_vlan_rx)(struct sk_buff *skb,
461 struct vlan_group *grp,
462 unsigned short vlan_tag);
463 DECLARE_NAPI_STRUCT
464 DECLARE_NET_DEVICE_STATS
465 };
466
467 enum shadow_reg_val {
468 SHADOW_IEVE = 0,
469 };
470
471 enum jme_flags_bits {
472 JME_FLAG_MSI = 1,
473 JME_FLAG_SSET = 2,
474 JME_FLAG_TXCSUM = 3,
475 JME_FLAG_TSO = 4,
476 JME_FLAG_POLL = 5,
477 JME_FLAG_SHUTDOWN = 6,
478 };
479
480 #define TX_TIMEOUT (5 * HZ)
481 #define JME_REG_LEN 0x500
482 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
483
484 static inline struct jme_adapter*
485 jme_napi_priv(struct napi_struct *napi)
486 {
487 struct jme_adapter *jme;
488 jme = container_of(napi, struct jme_adapter, napi);
489 return jme;
490 }
491
492 /*
493 * MMaped I/O Resters
494 */
495 enum jme_iomap_offsets {
496 JME_MAC = 0x0000,
497 JME_PHY = 0x0400,
498 JME_MISC = 0x0800,
499 JME_RSS = 0x0C00,
500 };
501
502 enum jme_iomap_lens {
503 JME_MAC_LEN = 0x80,
504 JME_PHY_LEN = 0x58,
505 JME_MISC_LEN = 0x98,
506 JME_RSS_LEN = 0xFF,
507 };
508
509 enum jme_iomap_regs {
510 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
511 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
512 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
513 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
514 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
515 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
516 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
517 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
518
519 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
520 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
521 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
522 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
523 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
524 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
525 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
526 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
527 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
528 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
529 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
530 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
531
532 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
533 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
534 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
535
536
537 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
538 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
539 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
540 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
541
542
543 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
544 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
545 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
546 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
547 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
548 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
549 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
550 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
551 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
552 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
553 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
554 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
555 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
556 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
557 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
558 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
559 };
560
561 /*
562 * TX Control/Status Bits
563 */
564 enum jme_txcs_bits {
565 TXCS_QUEUE7S = 0x00008000,
566 TXCS_QUEUE6S = 0x00004000,
567 TXCS_QUEUE5S = 0x00002000,
568 TXCS_QUEUE4S = 0x00001000,
569 TXCS_QUEUE3S = 0x00000800,
570 TXCS_QUEUE2S = 0x00000400,
571 TXCS_QUEUE1S = 0x00000200,
572 TXCS_QUEUE0S = 0x00000100,
573 TXCS_FIFOTH = 0x000000C0,
574 TXCS_DMASIZE = 0x00000030,
575 TXCS_BURST = 0x00000004,
576 TXCS_ENABLE = 0x00000001,
577 };
578
579 enum jme_txcs_value {
580 TXCS_FIFOTH_16QW = 0x000000C0,
581 TXCS_FIFOTH_12QW = 0x00000080,
582 TXCS_FIFOTH_8QW = 0x00000040,
583 TXCS_FIFOTH_4QW = 0x00000000,
584
585 TXCS_DMASIZE_64B = 0x00000000,
586 TXCS_DMASIZE_128B = 0x00000010,
587 TXCS_DMASIZE_256B = 0x00000020,
588 TXCS_DMASIZE_512B = 0x00000030,
589
590 TXCS_SELECT_QUEUE0 = 0x00000000,
591 TXCS_SELECT_QUEUE1 = 0x00010000,
592 TXCS_SELECT_QUEUE2 = 0x00020000,
593 TXCS_SELECT_QUEUE3 = 0x00030000,
594 TXCS_SELECT_QUEUE4 = 0x00040000,
595 TXCS_SELECT_QUEUE5 = 0x00050000,
596 TXCS_SELECT_QUEUE6 = 0x00060000,
597 TXCS_SELECT_QUEUE7 = 0x00070000,
598
599 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
600 TXCS_BURST,
601 };
602
603 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
604
605 /*
606 * TX MAC Control/Status Bits
607 */
608 enum jme_txmcs_bit_masks {
609 TXMCS_IFG2 = 0xC0000000,
610 TXMCS_IFG1 = 0x30000000,
611 TXMCS_TTHOLD = 0x00000300,
612 TXMCS_FBURST = 0x00000080,
613 TXMCS_CARRIEREXT = 0x00000040,
614 TXMCS_DEFER = 0x00000020,
615 TXMCS_BACKOFF = 0x00000010,
616 TXMCS_CARRIERSENSE = 0x00000008,
617 TXMCS_COLLISION = 0x00000004,
618 TXMCS_CRC = 0x00000002,
619 TXMCS_PADDING = 0x00000001,
620 };
621
622 enum jme_txmcs_values {
623 TXMCS_IFG2_6_4 = 0x00000000,
624 TXMCS_IFG2_8_5 = 0x40000000,
625 TXMCS_IFG2_10_6 = 0x80000000,
626 TXMCS_IFG2_12_7 = 0xC0000000,
627
628 TXMCS_IFG1_8_4 = 0x00000000,
629 TXMCS_IFG1_12_6 = 0x10000000,
630 TXMCS_IFG1_16_8 = 0x20000000,
631 TXMCS_IFG1_20_10 = 0x30000000,
632
633 TXMCS_TTHOLD_1_8 = 0x00000000,
634 TXMCS_TTHOLD_1_4 = 0x00000100,
635 TXMCS_TTHOLD_1_2 = 0x00000200,
636 TXMCS_TTHOLD_FULL = 0x00000300,
637
638 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
639 TXMCS_IFG1_16_8 |
640 TXMCS_TTHOLD_FULL |
641 TXMCS_DEFER |
642 TXMCS_CRC |
643 TXMCS_PADDING,
644 };
645
646 enum jme_txpfc_bits_masks {
647 TXPFC_VLAN_TAG = 0xFFFF0000,
648 TXPFC_VLAN_EN = 0x00008000,
649 TXPFC_PF_EN = 0x00000001,
650 };
651
652 enum jme_txtrhd_bits_masks {
653 TXTRHD_TXPEN = 0x80000000,
654 TXTRHD_TXP = 0x7FFFFF00,
655 TXTRHD_TXREN = 0x00000080,
656 TXTRHD_TXRL = 0x0000007F,
657 };
658
659 enum jme_txtrhd_shifts {
660 TXTRHD_TXP_SHIFT = 8,
661 TXTRHD_TXRL_SHIFT = 0,
662 };
663
664 /*
665 * RX Control/Status Bits
666 */
667 enum jme_rxcs_bit_masks {
668 /* FIFO full threshold for transmitting Tx Pause Packet */
669 RXCS_FIFOTHTP = 0x30000000,
670 /* FIFO threshold for processing next packet */
671 RXCS_FIFOTHNP = 0x0C000000,
672 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
673 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
674 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
675 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
676 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
677 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
678 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
679 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
680 RXCS_QST = 0x00000004, /* Receive queue start */
681 RXCS_SUSPEND = 0x00000002,
682 RXCS_ENABLE = 0x00000001,
683 };
684
685 enum jme_rxcs_values {
686 RXCS_FIFOTHTP_16T = 0x00000000,
687 RXCS_FIFOTHTP_32T = 0x10000000,
688 RXCS_FIFOTHTP_64T = 0x20000000,
689 RXCS_FIFOTHTP_128T = 0x30000000,
690
691 RXCS_FIFOTHNP_16QW = 0x00000000,
692 RXCS_FIFOTHNP_32QW = 0x04000000,
693 RXCS_FIFOTHNP_64QW = 0x08000000,
694 RXCS_FIFOTHNP_128QW = 0x0C000000,
695
696 RXCS_DMAREQSZ_16B = 0x00000000,
697 RXCS_DMAREQSZ_32B = 0x01000000,
698 RXCS_DMAREQSZ_64B = 0x02000000,
699 RXCS_DMAREQSZ_128B = 0x03000000,
700
701 RXCS_QUEUESEL_Q0 = 0x00000000,
702 RXCS_QUEUESEL_Q1 = 0x00010000,
703 RXCS_QUEUESEL_Q2 = 0x00020000,
704 RXCS_QUEUESEL_Q3 = 0x00030000,
705
706 RXCS_RETRYGAP_256ns = 0x00000000,
707 RXCS_RETRYGAP_512ns = 0x00001000,
708 RXCS_RETRYGAP_1024ns = 0x00002000,
709 RXCS_RETRYGAP_2048ns = 0x00003000,
710 RXCS_RETRYGAP_4096ns = 0x00004000,
711 RXCS_RETRYGAP_8192ns = 0x00005000,
712 RXCS_RETRYGAP_16384ns = 0x00006000,
713 RXCS_RETRYGAP_32768ns = 0x00007000,
714
715 RXCS_RETRYCNT_0 = 0x00000000,
716 RXCS_RETRYCNT_4 = 0x00000100,
717 RXCS_RETRYCNT_8 = 0x00000200,
718 RXCS_RETRYCNT_12 = 0x00000300,
719 RXCS_RETRYCNT_16 = 0x00000400,
720 RXCS_RETRYCNT_20 = 0x00000500,
721 RXCS_RETRYCNT_24 = 0x00000600,
722 RXCS_RETRYCNT_28 = 0x00000700,
723 RXCS_RETRYCNT_32 = 0x00000800,
724 RXCS_RETRYCNT_36 = 0x00000900,
725 RXCS_RETRYCNT_40 = 0x00000A00,
726 RXCS_RETRYCNT_44 = 0x00000B00,
727 RXCS_RETRYCNT_48 = 0x00000C00,
728 RXCS_RETRYCNT_52 = 0x00000D00,
729 RXCS_RETRYCNT_56 = 0x00000E00,
730 RXCS_RETRYCNT_60 = 0x00000F00,
731
732 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
733 RXCS_FIFOTHNP_128QW |
734 RXCS_DMAREQSZ_128B |
735 RXCS_RETRYGAP_256ns |
736 RXCS_RETRYCNT_32,
737 };
738
739 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
740
741 /*
742 * RX MAC Control/Status Bits
743 */
744 enum jme_rxmcs_bits {
745 RXMCS_ALLFRAME = 0x00000800,
746 RXMCS_BRDFRAME = 0x00000400,
747 RXMCS_MULFRAME = 0x00000200,
748 RXMCS_UNIFRAME = 0x00000100,
749 RXMCS_ALLMULFRAME = 0x00000080,
750 RXMCS_MULFILTERED = 0x00000040,
751 RXMCS_RXCOLLDEC = 0x00000020,
752 RXMCS_FLOWCTRL = 0x00000008,
753 RXMCS_VTAGRM = 0x00000004,
754 RXMCS_PREPAD = 0x00000002,
755 RXMCS_CHECKSUM = 0x00000001,
756
757 RXMCS_DEFAULT = RXMCS_VTAGRM |
758 RXMCS_PREPAD |
759 RXMCS_FLOWCTRL |
760 RXMCS_CHECKSUM,
761 };
762
763 /*
764 * Wakeup Frame setup interface registers
765 */
766 #define WAKEUP_FRAME_NR 8
767 #define WAKEUP_FRAME_MASK_DWNR 4
768
769 enum jme_wfoi_bit_masks {
770 WFOI_MASK_SEL = 0x00000070,
771 WFOI_CRC_SEL = 0x00000008,
772 WFOI_FRAME_SEL = 0x00000007,
773 };
774
775 enum jme_wfoi_shifts {
776 WFOI_MASK_SHIFT = 4,
777 };
778
779 /*
780 * SMI Related definitions
781 */
782 enum jme_smi_bit_mask {
783 SMI_DATA_MASK = 0xFFFF0000,
784 SMI_REG_ADDR_MASK = 0x0000F800,
785 SMI_PHY_ADDR_MASK = 0x000007C0,
786 SMI_OP_WRITE = 0x00000020,
787 /* Set to 1, after req done it'll be cleared to 0 */
788 SMI_OP_REQ = 0x00000010,
789 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
790 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
791 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
792 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
793 };
794
795 enum jme_smi_bit_shift {
796 SMI_DATA_SHIFT = 16,
797 SMI_REG_ADDR_SHIFT = 11,
798 SMI_PHY_ADDR_SHIFT = 6,
799 };
800
801 static inline u32 smi_reg_addr(int x)
802 {
803 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
804 }
805
806 static inline u32 smi_phy_addr(int x)
807 {
808 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
809 }
810
811 #define JME_PHY_TIMEOUT 100 /* 100 msec */
812 #define JME_PHY_REG_NR 32
813
814 /*
815 * Global Host Control
816 */
817 enum jme_ghc_bit_mask {
818 GHC_SWRST = 0x40000000,
819 GHC_DPX = 0x00000040,
820 GHC_SPEED = 0x00000030,
821 GHC_LINK_POLL = 0x00000001,
822 };
823
824 enum jme_ghc_speed_val {
825 GHC_SPEED_10M = 0x00000010,
826 GHC_SPEED_100M = 0x00000020,
827 GHC_SPEED_1000M = 0x00000030,
828 };
829
830 enum jme_ghc_to_clk {
831 GHC_TO_CLK_OFF = 0x00000000,
832 GHC_TO_CLK_GPHY = 0x00400000,
833 GHC_TO_CLK_PCIE = 0x00800000,
834 GHC_TO_CLK_INVALID = 0x00C00000,
835 };
836
837 enum jme_ghc_txmac_clk {
838 GHC_TXMAC_CLK_OFF = 0x00000000,
839 GHC_TXMAC_CLK_GPHY = 0x00100000,
840 GHC_TXMAC_CLK_PCIE = 0x00200000,
841 GHC_TXMAC_CLK_INVALID = 0x00300000,
842 };
843
844 /*
845 * Power management control and status register
846 */
847 enum jme_pmcs_bit_masks {
848 PMCS_WF7DET = 0x80000000,
849 PMCS_WF6DET = 0x40000000,
850 PMCS_WF5DET = 0x20000000,
851 PMCS_WF4DET = 0x10000000,
852 PMCS_WF3DET = 0x08000000,
853 PMCS_WF2DET = 0x04000000,
854 PMCS_WF1DET = 0x02000000,
855 PMCS_WF0DET = 0x01000000,
856 PMCS_LFDET = 0x00040000,
857 PMCS_LRDET = 0x00020000,
858 PMCS_MFDET = 0x00010000,
859 PMCS_WF7EN = 0x00008000,
860 PMCS_WF6EN = 0x00004000,
861 PMCS_WF5EN = 0x00002000,
862 PMCS_WF4EN = 0x00001000,
863 PMCS_WF3EN = 0x00000800,
864 PMCS_WF2EN = 0x00000400,
865 PMCS_WF1EN = 0x00000200,
866 PMCS_WF0EN = 0x00000100,
867 PMCS_LFEN = 0x00000004,
868 PMCS_LREN = 0x00000002,
869 PMCS_MFEN = 0x00000001,
870 };
871
872 /*
873 * Giga PHY Status Registers
874 */
875 enum jme_phy_link_bit_mask {
876 PHY_LINK_SPEED_MASK = 0x0000C000,
877 PHY_LINK_DUPLEX = 0x00002000,
878 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
879 PHY_LINK_UP = 0x00000400,
880 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
881 PHY_LINK_MDI_STAT = 0x00000040,
882 };
883
884 enum jme_phy_link_speed_val {
885 PHY_LINK_SPEED_10M = 0x00000000,
886 PHY_LINK_SPEED_100M = 0x00004000,
887 PHY_LINK_SPEED_1000M = 0x00008000,
888 };
889
890 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
891
892 /*
893 * SMB Control and Status
894 */
895 enum jme_smbcsr_bit_mask {
896 SMBCSR_CNACK = 0x00020000,
897 SMBCSR_RELOAD = 0x00010000,
898 SMBCSR_EEPROMD = 0x00000020,
899 SMBCSR_INITDONE = 0x00000010,
900 SMBCSR_BUSY = 0x0000000F,
901 };
902
903 enum jme_smbintf_bit_mask {
904 SMBINTF_HWDATR = 0xFF000000,
905 SMBINTF_HWDATW = 0x00FF0000,
906 SMBINTF_HWADDR = 0x0000FF00,
907 SMBINTF_HWRWN = 0x00000020,
908 SMBINTF_HWCMD = 0x00000010,
909 SMBINTF_FASTM = 0x00000008,
910 SMBINTF_GPIOSCL = 0x00000004,
911 SMBINTF_GPIOSDA = 0x00000002,
912 SMBINTF_GPIOEN = 0x00000001,
913 };
914
915 enum jme_smbintf_vals {
916 SMBINTF_HWRWN_READ = 0x00000020,
917 SMBINTF_HWRWN_WRITE = 0x00000000,
918 };
919
920 enum jme_smbintf_shifts {
921 SMBINTF_HWDATR_SHIFT = 24,
922 SMBINTF_HWDATW_SHIFT = 16,
923 SMBINTF_HWADDR_SHIFT = 8,
924 };
925
926 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
927 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
928 #define JME_SMB_LEN 256
929 #define JME_EEPROM_MAGIC 0x250
930
931 /*
932 * Timer Control/Status Register
933 */
934 enum jme_tmcsr_bit_masks {
935 TMCSR_SWIT = 0x80000000,
936 TMCSR_EN = 0x01000000,
937 TMCSR_CNT = 0x00FFFFFF,
938 };
939
940 /*
941 * General Purpose REG-0
942 */
943 enum jme_gpreg0_masks {
944 GPREG0_DISSH = 0xFF000000,
945 GPREG0_PCIRLMT = 0x00300000,
946 GPREG0_PCCNOMUTCLR = 0x00040000,
947 GPREG0_LNKINTPOLL = 0x00001000,
948 GPREG0_PCCTMR = 0x00000300,
949 GPREG0_PHYADDR = 0x0000001F,
950 };
951
952 enum jme_gpreg0_vals {
953 GPREG0_DISSH_DW7 = 0x80000000,
954 GPREG0_DISSH_DW6 = 0x40000000,
955 GPREG0_DISSH_DW5 = 0x20000000,
956 GPREG0_DISSH_DW4 = 0x10000000,
957 GPREG0_DISSH_DW3 = 0x08000000,
958 GPREG0_DISSH_DW2 = 0x04000000,
959 GPREG0_DISSH_DW1 = 0x02000000,
960 GPREG0_DISSH_DW0 = 0x01000000,
961 GPREG0_DISSH_ALL = 0xFF000000,
962
963 GPREG0_PCIRLMT_8 = 0x00000000,
964 GPREG0_PCIRLMT_6 = 0x00100000,
965 GPREG0_PCIRLMT_5 = 0x00200000,
966 GPREG0_PCIRLMT_4 = 0x00300000,
967
968 GPREG0_PCCTMR_16ns = 0x00000000,
969 GPREG0_PCCTMR_256ns = 0x00000100,
970 GPREG0_PCCTMR_1us = 0x00000200,
971 GPREG0_PCCTMR_1ms = 0x00000300,
972
973 GPREG0_PHYADDR_1 = 0x00000001,
974
975 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
976 GPREG0_PCCTMR_1us |
977 GPREG0_PHYADDR_1,
978 };
979
980 /*
981 * General Purpose REG-1
982 * Note: All theses bits defined here are for
983 * Chip mode revision 0x11 only
984 */
985 enum jme_gpreg1_masks {
986 GPREG1_INTRDELAYUNIT = 0x00000018,
987 GPREG1_INTRDELAYENABLE = 0x00000007,
988 };
989
990 enum jme_gpreg1_vals {
991 GPREG1_RSSPATCH = 0x00000040,
992 GPREG1_HALFMODEPATCH = 0x00000020,
993
994 GPREG1_INTDLYUNIT_16NS = 0x00000000,
995 GPREG1_INTDLYUNIT_256NS = 0x00000008,
996 GPREG1_INTDLYUNIT_1US = 0x00000010,
997 GPREG1_INTDLYUNIT_16US = 0x00000018,
998
999 GPREG1_INTDLYEN_1U = 0x00000001,
1000 GPREG1_INTDLYEN_2U = 0x00000002,
1001 GPREG1_INTDLYEN_3U = 0x00000003,
1002 GPREG1_INTDLYEN_4U = 0x00000004,
1003 GPREG1_INTDLYEN_5U = 0x00000005,
1004 GPREG1_INTDLYEN_6U = 0x00000006,
1005 GPREG1_INTDLYEN_7U = 0x00000007,
1006
1007 GPREG1_DEFAULT = 0x00000000,
1008 };
1009
1010 /*
1011 * Interrupt Status Bits
1012 */
1013 enum jme_interrupt_bits {
1014 INTR_SWINTR = 0x80000000,
1015 INTR_TMINTR = 0x40000000,
1016 INTR_LINKCH = 0x20000000,
1017 INTR_PAUSERCV = 0x10000000,
1018 INTR_MAGICRCV = 0x08000000,
1019 INTR_WAKERCV = 0x04000000,
1020 INTR_PCCRX0TO = 0x02000000,
1021 INTR_PCCRX1TO = 0x01000000,
1022 INTR_PCCRX2TO = 0x00800000,
1023 INTR_PCCRX3TO = 0x00400000,
1024 INTR_PCCTXTO = 0x00200000,
1025 INTR_PCCRX0 = 0x00100000,
1026 INTR_PCCRX1 = 0x00080000,
1027 INTR_PCCRX2 = 0x00040000,
1028 INTR_PCCRX3 = 0x00020000,
1029 INTR_PCCTX = 0x00010000,
1030 INTR_RX3EMP = 0x00008000,
1031 INTR_RX2EMP = 0x00004000,
1032 INTR_RX1EMP = 0x00002000,
1033 INTR_RX0EMP = 0x00001000,
1034 INTR_RX3 = 0x00000800,
1035 INTR_RX2 = 0x00000400,
1036 INTR_RX1 = 0x00000200,
1037 INTR_RX0 = 0x00000100,
1038 INTR_TX7 = 0x00000080,
1039 INTR_TX6 = 0x00000040,
1040 INTR_TX5 = 0x00000020,
1041 INTR_TX4 = 0x00000010,
1042 INTR_TX3 = 0x00000008,
1043 INTR_TX2 = 0x00000004,
1044 INTR_TX1 = 0x00000002,
1045 INTR_TX0 = 0x00000001,
1046 };
1047
1048 static const u32 INTR_ENABLE = INTR_SWINTR |
1049 INTR_TMINTR |
1050 INTR_LINKCH |
1051 INTR_PCCRX0TO |
1052 INTR_PCCRX0 |
1053 INTR_PCCTXTO |
1054 INTR_PCCTX |
1055 INTR_RX0EMP;
1056
1057 /*
1058 * PCC Control Registers
1059 */
1060 enum jme_pccrx_masks {
1061 PCCRXTO_MASK = 0xFFFF0000,
1062 PCCRX_MASK = 0x0000FF00,
1063 };
1064
1065 enum jme_pcctx_masks {
1066 PCCTXTO_MASK = 0xFFFF0000,
1067 PCCTX_MASK = 0x0000FF00,
1068 PCCTX_QS_MASK = 0x000000FF,
1069 };
1070
1071 enum jme_pccrx_shifts {
1072 PCCRXTO_SHIFT = 16,
1073 PCCRX_SHIFT = 8,
1074 };
1075
1076 enum jme_pcctx_shifts {
1077 PCCTXTO_SHIFT = 16,
1078 PCCTX_SHIFT = 8,
1079 };
1080
1081 enum jme_pcctx_bits {
1082 PCCTXQ0_EN = 0x00000001,
1083 PCCTXQ1_EN = 0x00000002,
1084 PCCTXQ2_EN = 0x00000004,
1085 PCCTXQ3_EN = 0x00000008,
1086 PCCTXQ4_EN = 0x00000010,
1087 PCCTXQ5_EN = 0x00000020,
1088 PCCTXQ6_EN = 0x00000040,
1089 PCCTXQ7_EN = 0x00000080,
1090 };
1091
1092 /*
1093 * Chip Mode Register
1094 */
1095 enum jme_chipmode_bit_masks {
1096 CM_FPGAVER_MASK = 0xFFFF0000,
1097 CM_CHIPREV_MASK = 0x0000FF00,
1098 CM_CHIPMODE_MASK = 0x0000000F,
1099 };
1100
1101 enum jme_chipmode_shifts {
1102 CM_FPGAVER_SHIFT = 16,
1103 CM_CHIPREV_SHIFT = 8,
1104 };
1105
1106 /*
1107 * Shadow base address register bits
1108 */
1109 enum jme_shadow_base_address_bits {
1110 SHBA_POSTEN = 0x1,
1111 };
1112
1113 /*
1114 * Aggressive Power Mode Control
1115 */
1116 enum jme_apmc_bits {
1117 JME_APMC_PCIE_SD_EN = 0x40000000,
1118 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1119 JME_APMC_EPIEN = 0x04000000,
1120 JME_APMC_EPIEN_CTRL = 0x03000000,
1121 };
1122
1123 enum jme_apmc_values {
1124 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1125 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1126 };
1127
1128 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1129
1130 #ifdef REG_DEBUG
1131 static char *MAC_REG_NAME[] = {
1132 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1133 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1134 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1135 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1136 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1137 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1138 "JME_PMCS"};
1139
1140 static char *PE_REG_NAME[] = {
1141 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1142 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1143 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1144 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1145 "JME_SMBCSR", "JME_SMBINTF"};
1146
1147 static char *MISC_REG_NAME[] = {
1148 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1149 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1150 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1151 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1152 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1153 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1154 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1155 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1156 "JME_PCCSRX0"};
1157
1158 static inline void reg_dbg(const struct jme_adapter *jme,
1159 const char *msg, u32 val, u32 reg)
1160 {
1161 const char *regname;
1162 switch (reg & 0xF00) {
1163 case 0x000:
1164 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1165 break;
1166 case 0x400:
1167 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1168 break;
1169 case 0x800:
1170 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1171 break;
1172 default:
1173 regname = PE_REG_NAME[0];
1174 }
1175 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1176 msg, val, regname);
1177 }
1178 #else
1179 static inline void reg_dbg(const struct jme_adapter *jme,
1180 const char *msg, u32 val, u32 reg) {}
1181 #endif
1182
1183 /*
1184 * Read/Write MMaped I/O Registers
1185 */
1186 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1187 {
1188 return readl(jme->regs + reg);
1189 }
1190
1191 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1192 {
1193 reg_dbg(jme, "REG WRITE", val, reg);
1194 writel(val, jme->regs + reg);
1195 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1196 }
1197
1198 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1199 {
1200 /*
1201 * Read after write should cause flush
1202 */
1203 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1204 writel(val, jme->regs + reg);
1205 readl(jme->regs + reg);
1206 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1207 }
1208
1209 /*
1210 * PHY Regs
1211 */
1212 enum jme_phy_reg17_bit_masks {
1213 PREG17_SPEED = 0xC000,
1214 PREG17_DUPLEX = 0x2000,
1215 PREG17_SPDRSV = 0x0800,
1216 PREG17_LNKUP = 0x0400,
1217 PREG17_MDI = 0x0040,
1218 };
1219
1220 enum jme_phy_reg17_vals {
1221 PREG17_SPEED_10M = 0x0000,
1222 PREG17_SPEED_100M = 0x4000,
1223 PREG17_SPEED_1000M = 0x8000,
1224 };
1225
1226 #define BMSR_ANCOMP 0x0020
1227
1228 /*
1229 * Workaround
1230 */
1231 static inline int is_buggy250(unsigned short device, unsigned int chiprev)
1232 {
1233 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1234 }
1235
1236 /*
1237 * Function prototypes
1238 */
1239 static int jme_set_settings(struct net_device *netdev,
1240 struct ethtool_cmd *ecmd);
1241 static void jme_set_multi(struct net_device *netdev);
1242
1243 #endif
Support for the Chinese Samsung S3C2440 based development boards