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1 /* $Id: cassini.h,v 1.16 2004/08/17 21:15:16 zaumen Exp $
2 * cassini.h: Definitions for Sun Microsystems Cassini(+) ethernet driver.
3 *
4 * Copyright (C) 2004 Sun Microsystems Inc.
5 * Copyright (c) 2003 Adrian Sun (asun@darksunrising.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
20 * 02111-1307, USA.
21 *
22 * vendor id: 0x108E (Sun Microsystems, Inc.)
23 * device id: 0xabba (Cassini)
24 * revision ids: 0x01 = Cassini
25 * 0x02 = Cassini rev 2
26 * 0x10 = Cassini+
27 * 0x11 = Cassini+ 0.2u
28 *
29 * vendor id: 0x100b (National Semiconductor)
30 * device id: 0x0035 (DP83065/Saturn)
31 * revision ids: 0x30 = Saturn B2
32 *
33 * rings are all offset from 0.
34 *
35 * there are two clock domains:
36 * PCI: 33/66MHz clock
37 * chip: 125MHz clock
38 */
40 #ifndef _CASSINI_H
41 #define _CASSINI_H
43 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
44 * 32-bit words. there is no i/o port access. REG_ addresses are
45 * shared between cassini and cassini+. REG_PLUS_ addresses only
46 * appear in cassini+. REG_MINUS_ addresses only appear in cassini.
47 */
48 #define CAS_ID_REV2 0x02
49 #define CAS_ID_REVPLUS 0x10
50 #define CAS_ID_REVPLUS02u 0x11
51 #define CAS_ID_REVSATURNB2 0x30
53 /** global resources **/
55 /* this register sets the weights for the weighted round robin arbiter. e.g.,
56 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
57 * for its next turn to access the pci bus.
58 * map: 0x0 = x1, 0x1 = x2, 0x2 = x4, 0x3 = x8
59 * DEFAULT: 0x0, SIZE: 5 bits
60 */
62 #define CAWR_RX_DMA_WEIGHT_SHIFT 0
64 #define CAWR_TX_DMA_WEIGHT_SHIFT 2
68 /* if enabled, BIM can send bursts across PCI bus > cacheline size. burst
69 * sizes determined by length of packet or descriptor transfer and the
70 * max length allowed by the target.
71 * DEFAULT: 0x0, SIZE: 1 bit
72 */
76 /* top level interrupts [0-9] are auto-cleared to 0 when the status
77 * register is read. second level interrupts [13 - 18] are cleared at
78 * the source. tx completion register 3 is replicated in [19 - 31]
79 * DEFAULT: 0x00000000, SIZE: 29 bits
80 */
83 xferred from host queue to
84 TX FIFO */
86 TX FIFO. i.e.,
87 TX Kick == TX complete. if
88 PACED_MODE set, then TX FIFO
89 also empty */
91 FIFO */
93 corrupted. FATAL ERROR */
95 from RX FIFO to host mem.
96 RX completion reg updated.
97 may be delayed by recv
98 intr blanking. */
100 RX Kick == RX complete */
102 corrupted. FATAL ERROR */
104 ring to post descriptors.
105 RX complete head incr to
106 almost reach RX complete
107 tail */
109 programmable threshold #
110 of free descr avail for
111 hw use */
113 programmable threshold #
114 of descr spaces for hw
115 use in completion descr
116 ring */
118 len of non-reassembly pkt
119 from fifo during DMA or
120 header parser provides TCP
121 header and payload size >
122 MAC packet size.
123 FATAL ERROR */
125 bit will be set if an interrupt
126 generated on the pci bus. useful
127 when driver is polling for
128 interrupts */
131 least 1 unmasked interrupt set */
133 least 1 unmasked interrupt set */
135 at least 1 unmasked interrupt
136 set */
138 1 unmasked interrupt set */
140 BIF has at least 1 unmasked
141 interrupt set */
143 3 reg data */
144 #define INTR_TX_COMP_3_SHIFT 19
145 #define INTR_ERROR_MASK (INTR_MIF_STATUS | INTR_PCI_ERROR_STATUS | \
146 INTR_PCS_STATUS | INTR_RX_LEN_MISMATCH | \
147 INTR_TX_MAC_STATUS | INTR_RX_MAC_STATUS | \
148 INTR_TX_TAG_ERROR | INTR_RX_TAG_ERROR | \
149 INTR_MAC_CTRL_STATUS)
151 /* determines which status events will cause an interrupt. layout same
152 * as REG_INTR_STATUS.
153 * DEFAULT: 0xFFFFFFFF, SIZE: 16 bits
154 */
157 /* top level interrupt bits that are cleared during read of REG_INTR_STATUS_ALIAS.
158 * useful when driver is polling for interrupts. layout same as REG_INTR_MASK.
159 * DEFAULT: 0x00000000, SIZE: 12 bits
160 */
162 (used w/ status alias) */
163 /* same as REG_INTR_STATUS except that only bits cleared are those selected by
164 * REG_ALIAS_CLEAR
165 * DEFAULT: 0x00000000, SIZE: 29 bits
166 */
168 (selective clear) */
170 /* DEFAULT: 0x0, SIZE: 3 bits */
173 set if no ACK64# during ABS64 cycle
174 in Cassini. */
176 no read retry after 2^15 clocks */
179 unused in Cassini. */
181 unused in Cassini. */
183 DMA. unused in cassini. */
185 /* mask for PCI status events that will set PCI_ERR_STATUS. if cleared, event
186 * causes an interrupt to be generated.
187 * DEFAULT: 0x7, SIZE: 3 bits
188 */
191 /* used to configure PCI related parameters that are not in PCI config space.
192 * DEFAULT: 0bxx000, SIZE: 5 bits
193 */
205 reset. reserved in Cassini. */
207 reserved in Cassini. */
209 reserved in Cassini. */
211 /* DEFAULT: 0x00000000, SIZE: 32 bits */
214 machine bits [21:0] */
216 machine bits [6:0] */
218 /* writing to SW_RESET_TX and SW_RESET_RX will issue a global
219 * reset. poll until TX and RX read back as 0's for completion.
220 */
223 cleared to 0. */
225 cleared to 0. */
227 resets PHY and anything else
228 connected to RSTOUT#. RSTOUT#
229 is also activated by local PCI
230 reset when hot-swap is being
231 done. */
233 this bit set, PCS and SLINK
234 modules won't be reset.
235 i.e., link won't drop. */
238 0b000: ARB_IDLE1
239 0b001: ARB_IDLE2
240 0b010: ARB_WB_ACK
241 0b011: ARB_WB_WAT
242 0b100: ARB_RB_ACK
243 0b101: ARB_RB_WAT
244 0b110: ARB_RB_END
245 0b111: ARB_WB_END */
247 0b00: RD_PCI_WAT
248 0b01: RD_PCI_RDY
249 0b11: RD_PCI_ACK */
251 0b00: AD_IDL_RX
252 0b01: AD_ACK_RX
253 0b10: AD_ACK_TX
254 0b11: AD_IDL_TX */
256 0b00: WR_PCI_WAT
257 0b01: WR_PCI_RDY
258 0b11: WR_PCI_ACK */
260 0b000: ARB_IDLE1
261 0b001: ARB_IDLE2
262 0b010: ARB_TX_ACK
263 0b011: ARB_TX_WAT
264 0b100: ARB_RX_ACK
265 0b110: ARB_RX_WAT */
267 /* Cassini only. 64-bit register used to check PCI datapath. when read,
268 * value written has both lower and upper 32-bit halves rotated to the right
269 * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF
270 */
272 Cassini+: reserved */
274 /* output enables are provided for each device's chip select and for the rest
275 * of the outputs from cassini to its local bus devices. two sw programmable
276 * bits are connected to general purpus control/status bits.
277 * DEFAULT: 0x7
278 */
280 output EN. default: 0x7 */
282 OE signal output enable on the
283 local bus interface. these
284 are shared between both local
285 bus devices. tristate when 0. */
288 select output enable */
293 /* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR
294 * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI.
295 * _DATA_HI should be the last access of the sequence.
296 * DEFAULT: undefined
297 */
299 purposes. */
302 read buffer access = 0 */
303 /* DEFAULT: undefined */
307 /* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer.
308 * bit auto-clears when done with status read from _SUMMARY and _PASS bits.
309 */
311 control/status */
314 Cassini only. reserved in
315 Cassini+. */
317 buffer. */
319 buffer. Cassini only. reserved
320 in Cassini+. */
324 Cassini only. reserved in
325 Cassini+. */
327 Cassini only. reserved in
328 Cassini+. */
330 /* ASUN: i'm not sure what this does as it's not in the spec.
331 * DEFAULT: 0xFC
332 */
334 select register */
336 /* enable probe monitoring mode and select data appearing on the P_A* bus. bit
337 * values for _SEL_HI_MASK and _SEL_LOW_MASK:
338 * 0x0: internal probe[7:0] (pci arb state, wtc empty w, wtc full w, wtc empty w,
339 * wtc empty r, post pci)
340 * 0x1: internal probe[15:8] (pci wbuf comp, pci wpkt comp, pci rbuf comp,
341 * pci rpkt comp, txdma wr req, txdma wr ack,
342 * txdma wr rdy, txdma wr xfr done)
343 * 0x2: internal probe[23:16] (txdma rd req, txdma rd ack, txdma rd rdy, rxdma rd,
344 * rd arb state, rd pci state)
345 * 0x3: internal probe[31:24] (rxdma req, rxdma ack, rxdma rdy, wrarb state,
346 * wrpci state)
347 * 0x4: pci io probe[7:0] 0x5: pci io probe[15:8]
348 * 0x6: pci io probe[23:16] 0x7: pci io probe[31:24]
349 * 0x8: pci io probe[39:32] 0x9: pci io probe[47:40]
350 * 0xa: pci io probe[55:48] 0xb: pci io probe[63:56]
351 * the following are not available in Cassini:
352 * 0xc: rx probe[7:0] 0xd: tx probe[7:0]
353 * 0xe: hp probe[7:0] 0xf: mac probe[7:0]
354 */
357 driven on local bus P_A[15:0]
358 for debugging */
360 0x03 = mac[1:0]
361 0x0C = rx[1:0]
362 0x30 = tx[1:0]
363 0xC0 = hp[1:0] */
365 on P_A[15:8]. see above for
366 values. */
368 on P_A[7:0]. see above for
369 values. */
371 /* values mean the same thing as REG_INTR_MASK excep that it's for INTB.
372 DEFAULT: 0x1F */
374 register 2 for INTB */
375 #define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)
376 /* bits correspond to both _MASK and _STATUS registers. _ALT corresponds to
377 * all of the alternate (2-4) INTR registers while _1 corresponds to only
378 * _MASK_1 and _STATUS_1 registers.
379 * DEFAULT: 0x7 for MASK registers, 0x0 for ALIAS_CLEAR registers
380 */
381 #define INTR_RX_DONE_ALT 0x01
382 #define INTR_RX_COMP_FULL_ALT 0x02
383 #define INTR_RX_COMP_AF_ALT 0x04
384 #define INTR_RX_BUF_UNAVAIL_1 0x08
386 #define INTRN_MASK_RX_EN 0x80
387 #define INTRN_MASK_CLEAR_ALL (INTR_RX_DONE_ALT | \
388 INTR_RX_COMP_FULL_ALT | \
389 INTR_RX_COMP_AF_ALT | \
390 INTR_RX_BUF_UNAVAIL_1 | \
391 INTR_RX_BUF_AE_1)
393 register 2 for INTB. default: 0x1F */
394 #define REG_PLUS_INTRN_STATUS(x) (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16)
396 flags are set. enables desc ring. */
399 register 2 for INTB */
400 #define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)
403 register alias 2 for INTB */
404 #define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)
407 integrated macphy */
415 0 = normal */
418 GMII on SERDES pins for
419 monitoring. */
421 pins configed as outputs.
422 for power saving when using
423 internal phy. */
425 polarity from strapping
426 value.
427 1 = mac core led ctrl
428 polarity active low. */
431 /** transmit dma registers **/
432 #define MAX_TX_RINGS_SHIFT 2
433 #define MAX_TX_RINGS (1 << MAX_TX_RINGS_SHIFT)
434 #define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1)
436 /* TX configuration.
437 * descr ring sizes size = 32 * (1 << n), n < 9. e.g., 0x8 = 8k. default: 0x8
438 * DEFAULT: 0x3F000001
439 */
442 will stop after xfer of current
443 buffer has been completed. */
445 accessed w/ FIFO addr
446 and data registers.
447 TX DMA should be
448 disabled. */
450 ring 1. */
451 #define TX_CFG_DESC_RING0_SHIFT 2
452 #define TX_CFG_DESC_RINGN_MASK(a) (TX_CFG_DESC_RING0_MASK << (a)*4)
453 #define TX_CFG_DESC_RINGN_SHIFT(a) (TX_CFG_DESC_RING0_SHIFT + (a)*4)
455 TX FIFO becomes empty.
456 if 0, TX_ALL set
457 if descr queue empty. */
460 the end of every packet kicked
461 through Q1. */
463 the end of every packet kicked
464 through Q2. */
466 the end of every packet kicked
467 through Q3 */
469 the end of every packet kicked
470 through Q4 */
472 writeback */
474 connection
475 0b00: tx mac req,
476 tx mac retry req,
477 tx ack and tx tag.
478 0b01: txdma rd req,
479 txdma rd ack,
480 txdma rd rdy,
481 txdma rd type0
482 0b11: txdma wr req,
483 txdma wr ack,
484 txdma wr rdy,
485 txdma wr xfr done. */
486 #define TX_CFG_CTX_SEL_SHIFT 30
488 /* 11-bit counters that point to next location in FIFO to be loaded/retrieved.
489 * used for diagnostics only.
490 */
493 pointer. temp hold reg.
494 diagnostics only. */
497 pointer */
499 /* (ro) 11-bit up/down counter w/ # of frames currently in TX FIFO */
502 /* current state of all state machines in TX */
507 = 0x01 when TX disabled. */
510 state machine */
518 /* 64-bit pointer to the transmit data buffer. only the 50 LSB are incremented
519 * while the upper 23 bits are taken from the TX descriptor
520 */
524 /* 13 bit registers written by driver w/ descriptor value that follows
525 * last valid xmit descriptor. kick # and complete # values are used by
526 * the xmit dma engine to control tx descr fetching. if > 1 valid
527 * tx descr is available within the cache line being read, cassini will
528 * internally cache up to 4 of them. 0 on reset. _KICK = rw, _COMP = ro.
529 */
531 #define REG_TX_KICKN(x) (REG_TX_KICK0 + (x)*4)
533 #define REG_TX_COMPN(x) (REG_TX_COMP0 + (x)*4)
535 /* values of TX_COMPLETE_1-4 are written. each completion register
536 * is 2bytes in size and contiguous. 8B allocation w/ 8B alignment.
537 * NOTE: completion reg values are only written back prior to TX_INTME and
538 * TX_ALL interrupts. at all other times, the most up-to-date index values
539 * should be obtained from the REG_TX_COMPLETE_# registers.
540 * here's the layout:
541 * offset from base addr completion # byte
542 * 0 TX_COMPLETE_1_MSB
543 * 1 TX_COMPLETE_1_LSB
544 * 2 TX_COMPLETE_2_MSB
545 * 3 TX_COMPLETE_2_LSB
546 * 4 TX_COMPLETE_3_MSB
547 * 5 TX_COMPLETE_3_LSB
548 * 6 TX_COMPLETE_4_MSB
549 * 7 TX_COMPLETE_4_LSB
550 */
551 #define TX_COMPWB_SIZE 8
553 base low */
555 base high */
556 #define TX_COMPWB_MSB_MASK 0x00000000000000FFULL
557 #define TX_COMPWB_MSB_SHIFT 0
558 #define TX_COMPWB_LSB_MASK 0x000000000000FF00ULL
559 #define TX_COMPWB_LSB_SHIFT 8
560 #define TX_COMPWB_NEXT(x) ((x) >> 16)
562 /* 53 MSB used as base address. 11 LSB assumed to be 0. TX desc pointer must
563 * be 2KB-aligned. */
566 #define REG_TX_DBN_LOW(x) (REG_TX_DB0_LOW + (x)*8)
567 #define REG_TX_DBN_HI(x) (REG_TX_DB0_HI + (x)*8)
569 /* 16-bit registers hold weights for the weighted round-robin of the
570 * four CBQ TX descr rings. weights correspond to # bytes xferred from
571 * host to TXFIFO in a round of WRR arbitration. can be set
572 * dynamically with new weights set upon completion of the current
573 * packet transfer from host memory to TXFIFO. a dummy write to any of
574 * these registers causes a queue1 pre-emption with all historical bw
575 * deficit data reset to 0 (useful when congestion requires a
576 * pre-emption/re-allocation of network bandwidth
577 */
583 /* diagnostics access to any TX FIFO location. every access is 65
584 * bits. _DATA_LOW = 32 LSB, _DATA_HI_T1/T0 = 32 MSB. _TAG = tag bit.
585 * writing _DATA_HI_T0 sets tag bit low, writing _DATA_HI_T1 sets tag
586 * bit high. TX_FIFO_PIO_SEL must be set for TX FIFO PIO access. if
587 * TX FIFO data integrity is desired, TX DMA should be
588 * disabled. _DATA_HI_Tx should be the last access of the sequence.
589 */
597 /* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST
598 * passed for the specified memory
599 */
602 controller state machine */
609 clears on completion. */
611 /** receive dma registers **/
612 #define MAX_RX_DESC_RINGS 2
613 #define MAX_RX_COMP_RINGS 4
615 /* receive DMA channel configuration. default: 0x80910
616 * free ring size = (1 << n)*32 -> [32 - 8k]
617 * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9
618 * DEFAULT: 0x80910
619 */
622 channel as soon as current
623 frame xfer has completed.
624 driver should disable MAC
625 for 200ms before disabling
626 RX */
628 free desc ring.
629 def: 0x8 = 8k */
630 #define RX_CFG_DESC_RING_SHIFT 1
632 ring. def: 0x8 = 32k */
633 #define RX_CFG_COMP_RING_SHIFT 5
635 batching. def: 0x0 =
636 enabled */
638 data byte of the packet
639 w/in 8 byte boundares.
640 this swivels the data
641 DMA'ed to header
642 buffers, jumbo buffers
643 when header split is not
644 requested and MTU sized
645 buffers. def: 0x2 */
646 #define RX_CFG_SWIVEL_SHIFT 10
648 /* cassini+ only */
650 RX free desc ring 2.
651 def: 0x8 = 8k */
652 #define RX_CFG_DESC_RING1_SHIFT 16
655 /* the page size register allows cassini chips to do the following with
656 * received data:
657 * [--------------------------------------------------------------] page
658 * [off][buf1][pad][off][buf2][pad][off][buf3][pad][off][buf4][pad]
659 * |--------------| = PAGE_SIZE_BUFFER_STRIDE
660 * page = PAGE_SIZE
661 * offset = PAGE_SIZE_MTU_OFF
662 * for the above example, MTU_BUFFER_COUNT = 4.
663 * NOTE: as is apparent, you need to ensure that the following holds:
664 * MTU_BUFFER_COUNT <= PAGE_SIZE/PAGE_SIZE_BUFFER_STRIDE
665 * DEFAULT: 0x48002002 (8k pages)
666 */
669 by receive descriptors.
670 if jumbo buffers are
671 supported the page size
672 should not be < 8k.
673 0b00 = 2k, 0b01 = 4k
674 0b10 = 8k, 0b11 = 16k
675 DEFAULT: 8k */
676 #define RX_PAGE_SIZE_SHIFT 0
678 packs into a page.
679 DEFAULT: 4 */
680 #define RX_PAGE_SIZE_MTU_COUNT_SHIFT 11
682 each MTU buffer +
683 offset from each
684 other.
685 0b00 = 1k, 0b01 = 2k
686 0b10 = 4k, 0b11 = 8k
687 DEFAULT: 0x1 */
688 #define RX_PAGE_SIZE_MTU_STRIDE_SHIFT 27
690 hw writes the MTU buffer
691 into.
692 0b00 = 0,
693 0b01 = 64 bytes
694 0b10 = 96, 0b11 = 128
695 DEFAULT: 0x1 */
696 #define RX_PAGE_SIZE_MTU_OFF_SHIFT 30
698 /* 11-bit counter points to next location in RX FIFO to be loaded/read.
699 * shadow write pointers enable retries in case of early receive aborts.
700 * DEFAULT: 0x0. generated on 64-bit boundaries.
701 */
705 pointer */
707 pointer */
709 pointer. (8-bit counter) */
711 /* current state of RX DMA state engines + other info
712 * DEFAULT: 0x0
713 */
716 0x0 = idle, 0x1 = load_bop
717 0x2 = load 1, 0x3 = load 2
718 0x4 = load 3, 0x5 = load 4
719 0x6 = last detect
720 0x7 = wait req
721 0x8 = wait req statuss 1st
722 0x9 = load st
723 0xa = bubble mac
724 0xb = error */
726 RX FIFO:
727 0x0 = idle, 0x1 = hp xfr
728 0x2 = wait hp ready
729 0x3 = wait flow code
730 0x4 = fifo xfer
731 0x5 = make status
732 0x6 = csum ready
733 0x7 = error */
735 w/ MAC:
736 0x0 = idle
737 0x1 = wait xoff ack
738 0x2 = wait xon
739 0x3 = wait xon ack */
741 states:
742 0x0 = idle data
743 0x1 = header begin
744 0x2 = xfer header
745 0x3 = xfer header ld
746 0x4 = mtu begin
747 0x5 = xfer mtu
748 0x6 = xfer mtu ld
749 0x7 = jumbo begin
750 0x8 = xfer jumbo
751 0x9 = xfer jumbo ld
752 0xa = reas begin
753 0xb = xfer reas
754 0xc = flush tag
755 0xd = xfer reas ld
756 0xe = error
757 0xf = bubble idle */
759 states:
760 0x0 = idle desc
761 0x1 = wait ack
762 0x9 = wait ack 2
763 0x2 = fetch desc 1
764 0xa = fetch desc 2
765 0x3 = load ptrs
766 0x4 = wait dma
767 0x5 = wait ack batch
768 0x6 = post batch
769 0x7 = xfr done */
771 interrupt queue */
773 of the interrupt queue */
775 /* flow control frames are emmitted using two PAUSE thresholds:
776 * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg
777 * XON PAUSE uses a pause time of 0. granularity of threshold is 64bytes.
778 * PAUSE thresholds defined in terms of FIFO occupancy and may be translated
779 * into FIFO vacancy using RX_FIFO_SIZE. setting ON will trigger XON frames
780 * when FIFO reaches 0. OFF threshold should not be > size of RX FIFO. max
781 * value is is 0x6F.
782 * DEFAULT: 0x00078
783 */
785 #define RX_PAUSE_THRESH_QUANTUM 64
787 RX FIFO occupancy >
788 value*64B */
789 #define RX_PAUSE_THRESH_OFF_SHIFT 0
791 emitting XOFF PAUSE when RX
792 FIFO occupancy falls below
793 this value*64B. must be
794 < XOFF threshold. if =
795 RX_FIFO_SIZE< XON frames are
796 never emitted. */
797 #define RX_PAUSE_THRESH_ON_SHIFT 12
799 /* 13-bit register used to control RX desc fetching and intr generation. if 4+
800 * valid RX descriptors are available, Cassini will read 4 at a time.
801 * writing N means that all desc up to *but* excluding N are available. N must
802 * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned.
803 * DEFAULT: 0 on reset
804 */
807 /* 8KB aligned 64-bit pointer to the base of the RX free/completion rings.
808 * lower 13 bits of the low register are hard-wired to 0.
809 */
811 base low */
813 base hi */
815 base low */
817 base hi */
818 /* 13-bit register indicate desc used by cassini for receive frames. used
819 * for diagnostic purposes.
820 * DEFAULT: 0 on reset
821 */
824 /* HEAD and TAIL are used to control RX desc posting and interrupt
825 * generation. hw moves the head register to pass ownership to sw. sw
826 * moves the tail register to pass ownership back to hw. to give all
827 * entries to hw, set TAIL = HEAD. if HEAD and TAIL indicate that no
828 * more entries are available, DMA will pause and an interrupt will be
829 * generated to indicate no more entries are available. sw can use
830 * this interrupt to reduce the # of times it must update the
831 * completion tail register.
832 * DEFAULT: 0 on reset
833 */
837 /* values used for receive interrupt blanking. loaded each time the ISR is read
838 * DEFAULT: 0x00000000
839 */
841 for ISR read */
843 this many sets of completion
844 writebacks (up to 2 packets)
845 occur since the last time
846 the ISR was read. 0 = no
847 packet blanking */
848 #define RX_BLANK_INTR_PKT_SHIFT 0
850 if that many clocks were
851 counted since last time the
852 ISR was read.
853 each count is 512 core
854 clocks (125MHz). 0 = no
855 time blanking */
856 #define RX_BLANK_INTR_TIME_SHIFT 12
858 /* values used for interrupt generation based on threshold values of how
859 * many free desc and completion entries are available for hw use.
860 * DEFAULT: 0x00000000
861 */
863 thresholds */
865 generated if # desc
866 avail for hw use <=
867 # */
868 #define RX_AE_THRESH_FREE_SHIFT 0
870 generated if # of
871 completion entries
872 avail for hw use <=
873 # */
874 #define RX_AE_THRESH_COMP_SHIFT 13
876 /* probabilities for random early drop (RED) thresholds on a FIFO threshold
877 * basis. probability should increase when the FIFO level increases. control
878 * packets are never dropped and not counted in stats. probability programmed
879 * on a 12.5% granularity. e.g., 0x1 = 1/8 packets dropped.
880 * DEFAULT: 0x00000000
881 */
888 /* FIFO fullness levels for RX FIFO, RX control FIFO, and RX IPP FIFO.
889 * RX control FIFO = # of packets in RX FIFO.
890 * DEFAULT: 0x0
891 */
899 high */
901 /* BIST testing ro RX FIFO, RX control FIFO, and RX IPP FIFO. only RX BIST
902 * START/COMPLETE is writeable. START will clear when the BIST has completed
903 * checking all 17 RAMS.
904 * DEFAULT: 0bxxxx xxxxx xxxx xxxx xxxx x000 0000 0000 00x0
905 */
926 summary pass bit
927 contains AND of BIST
928 results of all 16
929 RAMS */
931 BIST. self clears
932 on completion. */
934 /* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read
935 * from to retrieve packet control info.
936 * DEFAULT: 0
937 */
939 write ptr */
941 ptr */
943 /* receive interrupt blanking. loaded each time interrupt alias register is
944 * read.
945 * DEFAULT: 0x0
946 */
948 alias read */
950 completion writebacks
951 > # since last ISR
952 read. 0 = no
953 blanking. up to 2
954 packets per
955 completion wb. */
957 clocks > # since last
958 ISR read. each count
959 is 512 core clocks
960 (125MHz). 0 = no
961 blanking. */
963 /* diagnostic access to RX FIFO. 32 LSB accessed via DATA_LOW. 32 MSB accessed
964 * via DATA_HI_T0 or DATA_HI_T1. TAG reads the tag bit. writing HI_T0
965 * will unset the tag bit while writing HI_T1 will set the tag bit. to reset
966 * to normal operation after diagnostics, write to address location 0x0.
967 * RX_DMA_EN bit must be set to 0x0 for RX FIFO PIO access. DATA_HI should
968 * be the last write access of a write sequence.
969 * DEFAULT: undefined
970 */
977 /* diagnostic assess to RX CTRL FIFO. 8-bit FIFO_ADDR holds address of
978 * 81 bit control entry and 6 bit flow id. LOW and MID are both 32-bit
979 * accesses. HI is 7-bits with 6-bit flow id and 1 bit control
980 * word. RX_DMA_EN must be 0 for RX CTRL FIFO PIO access. DATA_HI
981 * should be last write access of the write sequence.
982 * DEFAULT: undefined
983 */
985 Batching FIFO addr */
987 low */
989 mid */
991 hi and flow id */
995 /* diagnostic access to RX IPP FIFO. same semantics as RX_FIFO.
996 * DEFAULT: undefined
997 */
1002 T0 */
1004 T1 */
1006 /* 64-bit pointer to receive data buffer in host memory used for headers and
1007 * small packets. MSB in high register. loaded by DMA state machine and
1008 * increments as DMA writes receive data. only 50 LSB are incremented. top
1009 * 13 bits taken from RX descriptor.
1010 * DEFAULT: undefined
1011 */
1013 low */
1015 high */
1017 low */
1019 high */
1021 /* PIO diagnostic access to RX reassembly DMA Table RAM. 6-bit register holds
1022 * one of 64 79-bit locations in the RX Reassembly DMA table and the addr of
1023 * one of the 64 byte locations in the Batching table. LOW holds 32 LSB.
1024 * MID holds the next 32 LSB. HIGH holds the 15 MSB. RX_DMA_EN must be set
1025 * to 0 for PIO access. DATA_HIGH should be last write of write sequence.
1026 * layout:
1027 * reassmbl ptr [78:15] | reassmbl index [14:1] | reassmbl entry valid [0]
1028 * DEFAULT: undefined
1029 */
1031 address */
1035 data low */
1037 data mid */
1039 data high */
1041 /* cassini+ only */
1042 /* 8KB aligned 64-bit pointer to base of RX rings. lower 13 bits hardwired to
1043 * 0. same semantics as primary desc/complete rings.
1044 */
1046 2 base low */
1048 2 base high */
1050 2 base low. 4 total */
1052 2 base high. 4 total */
1053 #define REG_PLUS_RX_CBN_LOW(x) (REG_PLUS_RX_CB1_LOW + 8*((x) - 1))
1054 #define REG_PLUS_RX_CBN_HI(x) (REG_PLUS_RX_CB1_HI + 8*((x) - 1))
1057 reg */
1059 head reg. 4 total. */
1061 tail reg. 4 total. */
1062 #define REG_PLUS_RX_COMPN_HEAD(x) (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1))
1063 #define REG_PLUS_RX_COMPN_TAIL(x) (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1))
1065 thresholds */
1066 #define RX_AE1_THRESH_FREE_MASK RX_AE_THRESH_FREE_MASK
1067 #define RX_AE1_THRESH_FREE_SHIFT RX_AE_THRESH_FREE_SHIFT
1069 /** header parser registers **/
1071 /* RX parser configuration register.
1072 * DEFAULT: 0x1651004
1073 */
1075 configuration reg */
1078 0 = 64. 0x3f = 63 */
1079 #define HP_CFG_NUM_CPU_SHIFT 2
1081 TCP seq # by one when
1082 stored in FDBM */
1084 needed to be considered
1085 for reassembly */
1086 #define HP_CFG_TCP_THRESH_SHIFT 9
1088 /* access to RX Instruction RAM. 5-bit register/counter holds addr
1089 * of 39 bit entry to be read/written. 32 LSB in _DATA_LOW. 7 MSB in _DATA_HI.
1090 * RX_DMA_EN must be 0 for RX instr PIO access. DATA_HI should be last access
1091 * of sequence.
1092 * DEFAULT: undefined
1093 */
1095 address */
1098 data low */
1099 #define HP_INSTR_RAM_LOW_OUTMASK_MASK 0x0000FFFF
1100 #define HP_INSTR_RAM_LOW_OUTMASK_SHIFT 0
1101 #define HP_INSTR_RAM_LOW_OUTSHIFT_MASK 0x000F0000
1102 #define HP_INSTR_RAM_LOW_OUTSHIFT_SHIFT 16
1103 #define HP_INSTR_RAM_LOW_OUTEN_MASK 0x00300000
1104 #define HP_INSTR_RAM_LOW_OUTEN_SHIFT 20
1105 #define HP_INSTR_RAM_LOW_OUTARG_MASK 0xFFC00000
1106 #define HP_INSTR_RAM_LOW_OUTARG_SHIFT 22
1108 data mid */
1109 #define HP_INSTR_RAM_MID_OUTARG_MASK 0x00000003
1110 #define HP_INSTR_RAM_MID_OUTARG_SHIFT 0
1111 #define HP_INSTR_RAM_MID_OUTOP_MASK 0x0000003C
1112 #define HP_INSTR_RAM_MID_OUTOP_SHIFT 2
1113 #define HP_INSTR_RAM_MID_FNEXT_MASK 0x000007C0
1114 #define HP_INSTR_RAM_MID_FNEXT_SHIFT 6
1115 #define HP_INSTR_RAM_MID_FOFF_MASK 0x0003F800
1116 #define HP_INSTR_RAM_MID_FOFF_SHIFT 11
1117 #define HP_INSTR_RAM_MID_SNEXT_MASK 0x007C0000
1118 #define HP_INSTR_RAM_MID_SNEXT_SHIFT 18
1119 #define HP_INSTR_RAM_MID_SOFF_MASK 0x3F800000
1120 #define HP_INSTR_RAM_MID_SOFF_SHIFT 23
1121 #define HP_INSTR_RAM_MID_OP_MASK 0xC0000000
1122 #define HP_INSTR_RAM_MID_OP_SHIFT 30
1124 data high */
1125 #define HP_INSTR_RAM_HI_VAL_MASK 0x0000FFFF
1126 #define HP_INSTR_RAM_HI_VAL_SHIFT 0
1127 #define HP_INSTR_RAM_HI_MASK_MASK 0xFFFF0000
1128 #define HP_INSTR_RAM_HI_MASK_SHIFT 16
1130 /* PIO access into RX Header parser data RAM and flow database.
1131 * 11-bit register. Data fills the LSB portion of bus if less than 32 bits.
1132 * DATA_RAM: write RAM_FDB_DATA with index to access DATA_RAM.
1133 * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120]
1134 * FLOWDB: write DATA_RAM_FDB register and then read/write FDB1-12 to access
1135 * flow database.
1136 * RX_DMA_EN must be 0 for RX parser RAM PIO access. RX Parser RAM data reg
1137 * should be the last write access of the write sequence.
1138 * DEFAULT: undefined
1139 */
1141 RAM address */
1143 locations in header
1144 parser data ram to
1145 read/write */
1147 in the flow database */
1150 /* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes
1151 * FLOW_DB(1) = IP_SA[127:96], FLOW_DB(2) = IP_SA[95:64]
1152 * FLOW_DB(3) = IP_SA[63:32], FLOW_DB(4) = IP_SA[31:0]
1153 * FLOW_DB(5) = IP_DA[127:96], FLOW_DB(6) = IP_DA[95:64]
1154 * FLOW_DB(7) = IP_DA[63:32], FLOW_DB(8) = IP_DA[31:0]
1155 * FLOW_DB(9) = {TCP_SP[15:0],TCP_DP[15:0]}
1156 * FLOW_DB(10) = bit 0 has value for flow valid
1157 * FLOW_DB(11) = TCP_SEQ[63:32], FLOW_DB(12) = TCP_SEQ[31:0]
1158 */
1160 #define REG_HP_FLOW_DBN(x) (REG_HP_FLOW_DB0 + (x)*4)
1162 /* diagnostics for RX Header Parser block.
1163 * ASUN: the header parser state machine register is used for diagnostics
1164 * purposes. however, the spec doesn't have any details on it.
1165 */
1171 number */
1183 start offset */
1187 reassembly */
1189 enable */
1191 check */
1193 equal to zero */
1195 chk */
1197 threshold */
1205 /* BIST for header parser(HP) and flow database memories (FDBM). set _START
1206 * to start BIST. controller clears _START on completion. _START can also
1207 * be cleared to force termination of BIST. a bit set indicates that that
1208 * memory passed its BIST.
1209 */
1218 bank 0 */
1220 bank 0 */
1222 bank 0 */
1224 bank 0 */
1226 bank 1 */
1228 bank 2 */
1230 bank 1 */
1232 bank 1 */
1234 RAM */
1239 /** MAC registers. **/
1240 /* reset bits are set using a PIO write and self-cleared after the command
1241 * execution has completed.
1242 */
1244 command (default: 0x0) */
1246 command (default: 0x0) */
1247 /* execute a pause flow control frame transmission
1248 DEFAULT: 0x0XXXX */
1251 to be sent on network
1252 in units of slot
1253 times */
1255 frame on network */
1257 /* bit set indicates that event occurred. auto-cleared when status register
1258 * is read and have corresponding mask bits in mask register. events will
1259 * trigger an interrupt if the corresponding mask bit is 0.
1260 * status register default: 0x00000000
1261 * mask register default = 0xFFFFFFFF on reset
1262 */
1265 transmision */
1267 transmission due to
1268 data starvation in the
1269 xmit data path */
1271 length passed to TX MAC
1272 by the DMA engine */
1274 collision counter */
1276 collision counter */
1278 collision counter */
1280 collision counter */
1282 timer */
1284 attempts counter */
1288 a frame */
1290 RX FIFO overflow */
1292 counter */
1294 error counter */
1296 counter */
1298 error counter */
1300 violation error */
1302 /* DEFAULT: 0xXXXX0000 on reset */
1305 reception of a
1306 pause control
1307 frame */
1309 transition from
1310 "not paused" to
1311 "paused" */
1313 transition from
1314 "paused" to "not
1315 paused" */
1317 operand that was
1318 received in the last
1319 pause flow control
1320 frame */
1322 /* layout identical to TX MAC[8:0] */
1324 /* layout identical to RX MAC[6:0] */
1326 /* layout identical to CTRL MAC[2:0] */
1329 /* to ensure proper operation, CFG_EN must be cleared to 0 and a delay
1330 * imposed before writes to other bits in the TX_MAC_CFG register or any of
1331 * the MAC parameters is performed. delay dependent upon time required to
1332 * transmit a maximum size frame (= MAC_FRAMESIZE_MAX*8/Mbps). e.g.,
1333 * the delay for a 1518-byte frame on a 100Mbps network is 125us.
1334 * alternatively, just poll TX_CFG_EN until it reads back as 0.
1335 * NOTE: on half-duplex 1Gbps, TX_CFG_CARRIER_EXTEND and
1336 * RX_CFG_CARRIER_EXTEND should be set and the SLOT_TIME register should
1337 * be 0x200 (slot time of 512 bytes)
1338 */
1341 force TXMAC state
1342 machine to remain in
1343 idle state or to
1344 transition to idle state
1345 on completion of an
1346 ongoing packet. */
1348 process. set to 1 when
1349 full duplex and 0 when
1350 half duplex */
1352 algorithm. set to 1 when
1353 full duplex and 0 when
1354 half duplex */
1356 Rx-to-TX IPG. after
1357 receiving a frame, TX
1358 MAC will reset its
1359 deferral process to
1360 carrier sense for the
1361 amount of time = IPG0 +
1362 IPG1 and commit to
1363 transmission for time
1364 specified in IPG2. when
1365 0 or when xmitting frames
1366 back-to-pack (Tx-to-Tx
1367 IPG), TX MAC ignores
1368 IPG0 and will only use
1369 IPG1 for deferral time.
1370 IPG2 still used. */
1372 give up on frame
1373 xmission. if backoff
1374 algorithm reaches the
1375 ATTEMPT_LIMIT, it will
1376 clear attempts counter
1377 and continue trying to
1378 send the frame as
1379 specified by
1380 GIVE_UP_LIM. when 0,
1381 TX MAC will execute
1382 standard CSMA/CD prot. */
1384 continue to try to xmit
1385 until successful. when
1386 0, TX MAC will continue
1387 to try xmitting until
1388 successful or backoff
1389 algorithm reaches
1390 ATTEMPT_LIMIT*16 */
1392 backoff algorithm. TX
1393 MAC will not back off
1394 after a xmission attempt
1395 that resulted in a
1396 collision. */
1398 deferral process is reset
1399 in response to carrier
1400 sense during the entire
1401 duration of IPG. TX MAC
1402 will only commit to frame
1403 xmission after frame
1404 xmission has actually
1405 begun. */
1407 CRC for all xmitted
1408 packets. when clear, CRC
1409 generation is dependent
1410 upon NO_CRC bit in the
1411 xmit control word from
1412 TX DMA */
1414 carrier extension
1415 feature. this allows for
1416 longer collision domains
1417 by extending the carrier
1418 and collision window
1419 from the end of FCS until
1420 the end of the slot time
1421 if necessary. Required
1422 for half-duplex at 1Gbps,
1423 clear otherwise. */
1425 /* when CRC is not stripped, reassembly packets will not contain the CRC.
1426 * these will be stripped by HRP because it reassembles layer 4 data, and the
1427 * CRC is layer 2. however, non-reassembly packets will still contain the CRC
1428 * when passed to the host. to ensure proper operation, need to wait 3.2ms
1429 * after clearing RX_CFG_EN before writing to any other RX MAC registers
1430 * or other MAC parameters. alternatively, poll RX_CFG_EN until it clears
1431 * to 0. similary, HASH_FILTER_EN and ADDR_FILTER_EN have the same
1432 * restrictions as CFG_EN.
1433 */
1437 feature not supported */
1439 last 4 bytes of a
1440 received frame. */
1443 multicast frames (group
1444 bit in DA field set) */
1446 multicast addresses */
1448 address filtering regs
1449 to filter both unicast
1450 and multicast
1451 addresses */
1453 RX DMA by setting BAD
1454 bit but not Abort bit
1455 in the status. CRC,
1456 framing, and length errs
1457 will not increment
1458 error counters. frames
1459 which don't match dest
1460 addr will be passed up
1461 w/ BAD bit set. */
1463 packet bursts generated
1464 by carrier extension
1465 with packet bursting
1466 senders. only applies
1467 to half-duplex 1Gbps */
1469 /* DEFAULT: 0x0 */
1472 sending pause flow ctrl
1473 frames */
1475 pause flow ctrl frames */
1477 packets to RX DMA */
1479 /* to ensure proper operation, a global initialization sequence should be
1480 * performed when a loopback config is entered or exited. if programmed after
1481 * a hw or global sw reset, RX/TX MAC software reset and initialization
1482 * should be done to ensure stable clocking.
1483 * DEFAULT: 0x0
1484 */
1487 on MII xmit bus */
1489 path to GMII recv data
1490 path. phy mode register
1491 clock selection must be
1492 set to GMII mode and
1493 GMII_MODE should be set
1494 to 1. in loopback mode,
1495 REFCLK will drive the
1496 entire mac core. 0 for
1497 normal operation. */
1499 path during packet
1500 xmission. clear to 0
1501 in any full duplex mode,
1502 in any loopback mode,
1503 or in half-duplex SERDES
1504 or SLINK modes. set when
1505 in half-duplex when
1506 using external phy. */
1508 clocks and datapath */
1510 external tristate buffer
1511 on the MII receive
1512 bus. */
1517 recommended: 0x00 */
1519 recommended: 0x08 */
1521 recommended: 0x04 */
1523 recommended: 0x40 */
1525 recommended: 0x40 */
1527 /* FRAMESIZE_MAX holds both the max frame size as well as the max burst size.
1528 * recommended value: 0x2000.05EE
1529 */
1532 #define MAC_FRAMESIZE_MAX_BURST_SHIFT 16
1534 #define MAC_FRAMESIZE_MAX_FRAME_SHIFT 0
1536 preamble bytes that the
1537 TX MAC will xmit at the
1538 beginning of each frame
1539 value should be 2 or
1540 greater. recommended
1541 value: 0x07 */
1543 of jam in units of media
1544 byte time. recommended
1545 value: 0x04 */
1547 of attempts TX MAC will
1548 make to xmit a frame
1549 before it resets its
1550 attempts counter. after
1551 the limit has been
1552 reached, TX MAC may or
1553 may not drop the frame
1554 dependent upon value
1555 in TX_MAC_CFG.
1556 recommended
1557 value: 0x10 */
1559 type field of a MAC
1560 ctrl frame. recommended
1561 value: 0x8808 */
1563 /* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes.
1564 * register contains comparison
1565 * 0 16 MSB of primary MAC addr [47:32] of DA field
1566 * 1 16 middle bits "" [31:16] of DA field
1567 * 2 16 LSB "" [15:0] of DA field
1568 * 3*x 16MSB of alt MAC addr 1-15 [47:32] of DA field
1569 * 4*x 16 middle bits "" [31:16]
1570 * 5*x 16 LSB "" [15:0]
1571 * 42 16 MSB of MAC CTRL addr [47:32] of DA.
1572 * 43 16 middle bits "" [31:16]
1573 * 44 16 LSB "" [15:0]
1574 * MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames.
1575 * if there is a match, MAC will set the bit for alternative address
1576 * filter pass [15]
1578 * here is the map of registers given MAC address notation: a:b:c:d:e:f
1579 * ab cd ef
1580 * primary addr reg 2 reg 1 reg 0
1581 * alt addr 1 reg 5 reg 4 reg 3
1582 * alt addr x reg 5*x reg 4*x reg 3*x
1583 * ctrl addr reg 44 reg 43 reg 42
1584 */
1586 #define REG_MAC_ADDRN(x) (REG_MAC_ADDR0 + (x)*4)
1588 [47:32] */
1590 [31:16] */
1592 [15:0] */
1594 mask reg. 8-bit reg
1595 contains nibble mask for
1596 reg 2 and 1. */
1598 reg */
1600 /* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes
1601 * 16-bit registers contain bits of the hash table.
1602 * reg x -> [16*(15 - x) + 15 : 16*(15 - x)].
1603 * e.g., 15 -> [15:0], 0 -> [255:240]
1604 */
1606 #define REG_MAC_HASH_TABLEN(x) (REG_MAC_HASH_TABLE0 + (x)*4)
1608 /* statistics registers. these registers generate an interrupt on
1609 * overflow. recommended initialization: 0x0000. most are 16-bits except
1610 * for PEAK_ATTEMPTS register which is 8 bits.
1611 */
1613 counter. */
1615 successful collision
1616 counter */
1618 counter */
1621 is the media byte
1622 clock/256 */
1629 error counter */
1631 /* misc registers */
1633 10-bit register used as a
1634 seed for the random number
1635 generator for the CSMA/CD
1636 backoff algorithm. only
1637 programmed after power-on
1638 reset and should be a
1639 random value which has a
1640 high likelihood of being
1641 unique for each MAC
1642 attached to a network
1643 segment (e.g., 10 LSB of
1644 MAC address) */
1646 /* ASUN: there's a PAUSE_TIMER (ro) described, but it's not in the address
1647 * map
1648 */
1650 /* 27-bit register has the current state for key state machines in the MAC */
1652 #define MAC_SM_RLM_MASK 0x07800000
1653 #define MAC_SM_RLM_SHIFT 23
1654 #define MAC_SM_RX_FC_MASK 0x00700000
1655 #define MAC_SM_RX_FC_SHIFT 20
1656 #define MAC_SM_TLM_MASK 0x000F0000
1657 #define MAC_SM_TLM_SHIFT 16
1658 #define MAC_SM_ENCAP_SM_MASK 0x0000F000
1659 #define MAC_SM_ENCAP_SM_SHIFT 12
1660 #define MAC_SM_TX_REQ_MASK 0x00000C00
1661 #define MAC_SM_TX_REQ_SHIFT 10
1662 #define MAC_SM_TX_FC_MASK 0x000003C0
1663 #define MAC_SM_TX_FC_SHIFT 6
1664 #define MAC_SM_FIFO_WRITE_SEL_MASK 0x00000038
1665 #define MAC_SM_FIFO_WRITE_SEL_SHIFT 3
1666 #define MAC_SM_TX_FIFO_EMPTY_MASK 0x00000007
1667 #define MAC_SM_TX_FIFO_EMPTY_SHIFT 0
1669 /** MIF registers. the MIF can be programmed in either bit-bang or
1670 * frame mode.
1671 **/
1673 1 -> 0 will generate a
1674 rising edge. 0 -> 1 will
1675 generate a falling edge. */
1677 register generates data */
1679 enable. enable when
1680 xmitting data from MIF to
1681 transceiver. */
1683 /* 32-bit register serves as an instruction register when the MIF is
1684 * programmed in frame mode. load this register w/ a valid instruction
1685 * (as per IEEE 802.3u MII spec). poll this register to check for instruction
1686 * execution completion. during a read operation, this register will also
1687 * contain the 16-bit data returned by the tranceiver. unless specified
1688 * otherwise, fields are considered "don't care" when polling for
1689 * completion.
1690 */
1693 load w/ 01 when
1694 issuing an instr */
1697 write. 10 for a
1698 read */
1702 issuing an instr,
1703 this field should be
1704 loaded w/ the XCVR
1705 addr */
1706 #define MIF_FRAME_PHY_ADDR_SHIFT 23
1708 when issuing an instr,
1709 addr of register
1710 to be read/written */
1711 #define MIF_FRAME_REG_ADDR_SHIFT 18
1713 when issuing an instr,
1714 set this bit to 1 */
1716 when issuing an instr,
1717 set this bit to 0.
1718 when polling for
1719 completion, 1 means
1720 that instr execution
1721 has been completed */
1723 load with 16-bit data
1724 to be written in
1725 transceiver reg for a
1726 write. doesn't matter
1727 in a read. when
1728 polling for
1729 completion, field is
1730 "don't care" for write
1731 and 16-bit data
1732 returned by the
1733 transceiver for a
1734 read (if valid bit
1735 is set) */
1738 0 -> select MDIO_0 */
1740 mechanism. if set,
1741 BB_MODE should be 0 */
1743 0 -> frame mode */
1745 used by polling mode.
1746 only meaningful if POLL_EN
1747 is set to 1 */
1748 #define MIF_CFG_POLL_REG_SHIFT 3
1750 when MDIO_0 is idle,
1751 1 -> tranceiver is
1752 connected to MDIO_0.
1753 when MIF is communicating
1754 w/ MDIO_0 in bit-bang
1755 mode, this bit indicates
1756 the incoming bit stream
1757 during a read op */
1759 when MDIO_1 is idle,
1760 1 -> transceiver is
1761 connected to MDIO_1.
1762 when MIF is communicating
1763 w/ MDIO_1 in bit-bang
1764 mode, this bit indicates
1765 the incoming bit stream
1766 during a read op */
1768 be polled */
1769 #define MIF_CFG_POLL_PHY_SHIFT 10
1771 /* 16-bit register used to determine which bits in the POLL_STATUS portion of
1772 * the MIF_STATUS register will cause an interrupt. if a mask bit is 0,
1773 * corresponding bit of the POLL_STATUS will generate a MIF interrupt when
1774 * set. DEFAULT: 0xFFFF
1775 */
1778 /* 32-bit register used when in poll mode. auto-cleared after being read */
1781 the "latest image"
1782 update of the XCVR
1783 reg being read */
1784 #define MIF_STATUS_POLL_DATA_SHIFT 16
1786 which bits in the
1787 POLL_DATA field have
1788 changed since the
1789 MIF_STATUS reg was
1790 last read */
1791 #define MIF_STATUS_POLL_STATUS_SHIFT 0
1793 /* 7-bit register has current state for all state machines in the MIF */
1796 state */
1798 state */
1800 /** PCS/Serialink. the following registers are equivalent to the standard
1801 * MII management registers except that they're directly mapped in
1802 * Cassini's register space.
1803 **/
1805 /* the auto-negotiation enable bit should be programmed the same at
1806 * the link partner as in the local device to enable auto-negotiation to
1807 * complete. when that bit is reprogrammed, auto-neg/manual config is
1808 * restarted automatically.
1809 * DEFAULT: 0x1040
1810 */
1813 writes */
1815 to MAC interface is
1816 activated regardless
1817 of activity */
1819 behaviour same for
1820 half and full dplx */
1822 restart auto-
1823 negotiation */
1825 on writes */
1827 on writes */
1829 through automatic
1830 link config before it
1831 can be used. when 0,
1832 link can be used
1833 w/out any link config
1834 phase */
1836 writes */
1838 when done */
1840 /* DEFAULT: 0x0108 */
1845 0 -> link down. 0 is
1846 latched so that 0 is
1847 kept until read. read
1848 2x to determine if the
1849 link has gone up again */
1851 auto-neg) */
1853 from received link code
1854 word. only valid after
1855 auto-neg completed */
1857 completed
1858 0 -> auto-negotiation not
1859 completed */
1861 indication that this is
1862 a 1000 Base-X PHY. writes
1863 to it are ignored */
1865 /* used during auto-negotiation.
1866 * DEFAULT: 0x00E0
1867 */
1869 reg */
1871 1000 Base-X */
1873 1000 Base-X */
1875 symmetric capability */
1877 asymmetric capability */
1879 to optionally indicate to
1880 link partner that chip is
1881 going off-line. bit12 will
1882 get set when signal
1883 detect == FAIL and will
1884 remain set until
1885 successful negotiation */
1889 /* contents updated as a result of autonegotiation. layout and definitions
1890 * identical to PCS_MII_ADVERT
1891 */
1893 ability reg */
1894 #define PCS_MII_LPA_FD PCS_MII_ADVERT_FD
1895 #define PCS_MII_LPA_HD PCS_MII_ADVERT_HD
1896 #define PCS_MII_LPA_SYM_PAUSE PCS_MII_ADVERT_SYM_PAUSE
1897 #define PCS_MII_LPA_ASYM_PAUSE PCS_MII_ADVERT_ASYM_PAUSE
1898 #define PCS_MII_LPA_RF_MASK PCS_MII_ADVERT_RF_MASK
1899 #define PCS_MII_LPA_ACK PCS_MII_ADVERT_ACK
1900 #define PCS_MII_LPA_NEXT_PAGE PCS_MII_ADVERT_NEXT_PAGE
1902 /* DEFAULT: 0x0 */
1905 0 when modifying
1906 PCS_MII_ADVERT */
1908 OK. bit is
1909 non-resettable */
1911 of optical signal to make
1912 signal detect okay when
1913 signal is low */
1915 measurements. a single
1916 code group is xmitted
1917 regularly.
1918 0x0 = normal operation
1919 0x1 = high freq test
1920 pattern, D21.5
1921 0x2 = low freq test
1922 pattern, K28.7
1923 0x3 = reserved */
1925 negotiation timer to
1926 a few cycles for test
1927 purposes */
1929 /* used for diagnostic purposes. bits 20-22 autoclear on read */
1931 and diagnostic reg */
1933 xmission of idle.
1934 otherwise, xmission of
1935 a packet */
1937 of idle. otherwise,
1938 reception of packet */
1940 sync */
1942 indicates reception of
1943 Config codes. cycling
1944 through 0-1 indicates
1945 reception of idles */
1946 #define PCS_SM_LINK_STATE_MASK 0x0001E000
1950 recept of Config
1951 codes */
1953 loss of sync */
1955 from OK to FAIL. bit29
1956 will also be set if
1957 this is set */
1959 receipt of breaklink
1960 C codes from partner.
1961 C codes w/ 0 content
1962 received triggering
1963 start/restart of
1964 autonegotiation.
1965 should be sent for
1966 no longer than 20ms */
1968 initialized. see serdes
1969 state reg */
1971 not received */
1973 achieved */
1975 w/ ack bit set */
1977 to send C codes
1978 instead of idle
1979 symbols or pkt data */
1981 /* this register indicates interrupt changes in specific PCS MII status bits.
1982 * PCS_INT may be masked at the ISR level. only a single bit is implemented
1983 * for link status change.
1984 */
1987 since last read */
1989 /* control which network interface is used. no more than one bit should
1990 * be set.
1991 * DEFAULT: none
1992 */
1995 MII/GMII is selected.
1996 selection between MII and
1997 GMII is controlled by
1998 XIF_CFG */
2000 10-bit interface */
2002 /* input to serdes chip or serialink block */
2005 serdes interface */
2007 detection. should be
2008 0x0 for normal
2009 operation */
2011 to REFCLK when set.
2012 when clear, receiver
2013 clock locks to incoming
2014 serial data */
2016 /* multiplex test outputs into the PROM address (PA_3 through PA_0) pins.
2017 * should be 0x0 for normal operations.
2018 * 0b000 normal operation, PROM address[3:0] selected
2019 * 0b001 rxdma req, rxdma ack, rxdma ready, rxdma read
2020 * 0b010 rxmac req, rx ack, rx tag, rx clk shared
2021 * 0b011 txmac req, tx ack, tx tag, tx retry req
2022 * 0b100 tx tp3, tx tp2, tx tp1, tx tp0
2023 * 0b101 R period RX, R period TX, R period HP, R period BIM
2024 * DEFAULT: 0x0
2025 */
2027 #define PCS_SOS_PROM_ADDR_MASK 0x0007
2029 /* used for diagnostics. this register indicates progress of the SERDES
2030 * boot up.
2031 * 0b00 undergoing reset
2032 * 0b01 waiting 500us while lockrefn is asserted
2033 * 0b10 waiting for comma detect
2034 * 0b11 receive data is synchronized
2035 * DEFAULT: 0x0
2036 */
2038 #define PCS_SERDES_STATE_MASK 0x03
2040 /* used for diagnostics. indicates number of packets transmitted or received.
2041 * counters rollover w/out generating an interrupt.
2042 * DEFAULT: 0x0
2043 */
2047 whether they
2048 encountered an error
2049 or not */
2051 /** LocalBus Devices. the following provides run-time access to the
2052 * Cassini's PROM
2053 ***/
2055 access */
2056 #define REG_EXPANSION_ROM_RUN_END 0x17FFFF
2059 device */
2060 #define REG_SECOND_LOCALBUS_END 0x1FFFFF
2062 /* entropy device */
2063 #define REG_ENTROPY_START REG_SECOND_LOCALBUS_START
2064 #define REG_ENTROPY_DATA (REG_ENTROPY_START + 0x00)
2065 #define REG_ENTROPY_STATUS (REG_ENTROPY_START + 0x04)
2066 #define ENTROPY_STATUS_DRDY 0x01
2067 #define ENTROPY_STATUS_BUSY 0x02
2068 #define ENTROPY_STATUS_CIPHER 0x04
2069 #define ENTROPY_STATUS_BYPASS_MASK 0x18
2070 #define REG_ENTROPY_MODE (REG_ENTROPY_START + 0x05)
2071 #define ENTROPY_MODE_KEY_MASK 0x07
2072 #define ENTROPY_MODE_ENCRYPT 0x40
2073 #define REG_ENTROPY_RAND_REG (REG_ENTROPY_START + 0x06)
2074 #define REG_ENTROPY_RESET (REG_ENTROPY_START + 0x07)
2075 #define ENTROPY_RESET_DES_IO 0x01
2076 #define ENTROPY_RESET_STC_MODE 0x02
2077 #define ENTROPY_RESET_KEY_CACHE 0x04
2078 #define ENTROPY_RESET_IV 0x08
2079 #define REG_ENTROPY_IV (REG_ENTROPY_START + 0x08)
2080 #define REG_ENTROPY_KEY0 (REG_ENTROPY_START + 0x10)
2081 #define REG_ENTROPY_KEYN(x) (REG_ENTROPY_KEY0 + 4*(x))
2083 /* phys of interest w/ their special mii registers */
2084 #define PHY_LUCENT_B0 0x00437421
2085 #define LUCENT_MII_REG 0x1F
2087 #define PHY_NS_DP83065 0x20005c78
2088 #define DP83065_MII_MEM 0x16
2089 #define DP83065_MII_REGD 0x1D
2090 #define DP83065_MII_REGE 0x1E
2092 #define PHY_BROADCOM_5411 0x00206071
2093 #define PHY_BROADCOM_B0 0x00206050
2094 #define BROADCOM_MII_REG4 0x14
2095 #define BROADCOM_MII_REG5 0x15
2096 #define BROADCOM_MII_REG7 0x17
2097 #define BROADCOM_MII_REG8 0x18
2099 #define CAS_MII_ANNPTR 0x07
2100 #define CAS_MII_ANNPRR 0x08
2101 #define CAS_MII_1000_CTRL 0x09
2102 #define CAS_MII_1000_STATUS 0x0A
2103 #define CAS_MII_1000_EXTEND 0x0F
2106 /*
2107 * if autoneg is disabled, here's the table:
2108 * BMCR_SPEED100 = 100Mbps
2109 * BMCR_SPEED1000 = 1000Mbps
2110 * ~(BMCR_SPEED100 | BMCR_SPEED1000) = 10Mbps
2111 */
2114 #define CAS_ADVERTISE_1000HALF 0x0100
2115 #define CAS_ADVERTISE_1000FULL 0x0200
2116 #define CAS_ADVERTISE_PAUSE 0x0400
2117 #define CAS_ADVERTISE_ASYM_PAUSE 0x0800
2119 /* regular lpa register */
2120 #define CAS_LPA_PAUSE CAS_ADVERTISE_PAUSE
2121 #define CAS_LPA_ASYM_PAUSE CAS_ADVERTISE_ASYM_PAUSE
2123 /* 1000_STATUS register */
2124 #define CAS_LPA_1000HALF 0x0400
2125 #define CAS_LPA_1000FULL 0x0800
2127 #define CAS_EXTEND_1000XFULL 0x8000
2128 #define CAS_EXTEND_1000XHALF 0x4000
2129 #define CAS_EXTEND_1000TFULL 0x2000
2130 #define CAS_EXTEND_1000THALF 0x1000
2132 /* cassini header parser firmware */
2138 u8 op;
2141 /* output info */
2146 2 = if !match, 3 = always */
2148 u16 outmask;
2151 /* comparison */
2157 /* output opcodes */
2158 #define CL_REG 0
2159 #define LD_FID 1
2160 #define LD_SEQ 2
2161 #define LD_CTL 3
2162 #define LD_SAP 4
2163 #define LD_R1 5
2164 #define LD_L3 6
2165 #define LD_SUM 7
2166 #define LD_HDR 8
2167 #define IM_FID 9
2168 #define IM_SEQ 10
2169 #define IM_SAP 11
2170 #define IM_R1 12
2171 #define IM_CTL 13
2172 #define LD_LEN 14
2173 #define ST_FLG 15
2175 /* match setp #s for IP4TCP4 */
2176 #define S1_PCKT 0
2177 #define S1_VLAN 1
2178 #define S1_CFI 2
2179 #define S1_8023 3
2180 #define S1_LLC 4
2181 #define S1_LLCc 5
2182 #define S1_IPV4 6
2183 #define S1_IPV4c 7
2184 #define S1_IPV4F 8
2185 #define S1_TCP44 9
2186 #define S1_IPV6 10
2187 #define S1_IPV6L 11
2188 #define S1_IPV6c 12
2189 #define S1_TCP64 13
2190 #define S1_TCPSQ 14
2191 #define S1_TCPFG 15
2192 #define S1_TCPHL 16
2193 #define S1_TCPHc 17
2194 #define S1_CLNP 18
2195 #define S1_CLNP2 19
2196 #define S1_DROP 20
2197 #define S2_HTTP 21
2198 #define S1_ESP4 22
2199 #define S1_AH4 23
2200 #define S1_ESP6 24
2201 #define S1_AH6 25
2203 #define CAS_PROG_IP46TCP4_PREAMBLE \
2205 CL_REG, 0x3ff, 1, 0x0, 0x0000}, \
2207 IM_CTL, 0x00a, 3, 0x0, 0xffff}, \
2209 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2211 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2213 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2215 CL_REG, 0x000, 0, 0x0, 0x0000}, \
2217 LD_SAP, 0x100, 3, 0x0, 0xffff}, \
2219 LD_SUM, 0x00a, 1, 0x0, 0x0000}, \
2221 LD_LEN, 0x03e, 1, 0x0, 0xffff}, \
2225 LD_SUM, 0x015, 1, 0x0, 0x0000}, \
2227 IM_R1, 0x128, 1, 0x0, 0xffff}, \
2231 LD_LEN, 0x03f, 1, 0x0, 0xffff}
2233 #ifdef USE_HP_IP46TCP4
2235 CAS_PROG_IP46TCP4_PREAMBLE,
2252 };
2253 #ifdef HP_IP46TCP4_DEFAULT
2254 #define CAS_HP_FIRMWARE cas_prog_ip46tcp4tab
2255 #endif
2256 #endif
2258 /*
2259 * Alternate table load which excludes HTTP server traffic from reassembly.
2260 * It is substantially similar to the basic table, with one extra state
2261 * and a few extra compares. */
2262 #ifdef USE_HP_IP46TCP4NOHTTP
2264 CAS_PROG_IP46TCP4_PREAMBLE,
2283 };
2284 #ifdef HP_IP46TCP4NOHTTP_DEFAULT
2285 #define CAS_HP_FIRMWARE cas_prog_ip46tcp4nohttptab
2286 #endif
2287 #endif
2289 /* match step #s for IP4FRAG */
2290 #define S3_IPV6c 11
2291 #define S3_TCP64 12
2292 #define S3_TCPSQ 13
2293 #define S3_TCPFG 14
2294 #define S3_TCPHL 15
2295 #define S3_TCPHc 16
2296 #define S3_FRAG 17
2297 #define S3_FOFF 18
2298 #define S3_CLNP 19
2300 #ifdef USE_HP_IP4FRAG
2344 };
2345 #ifdef HP_IP4FRAG_DEFAULT
2346 #define CAS_HP_FIRMWARE cas_prog_ip4fragtab
2347 #endif
2348 #endif
2350 /*
2351 * Alternate table which does batching without reassembly
2352 */
2353 #ifdef USE_HP_IP46TCP4BATCH
2355 CAS_PROG_IP46TCP4_PREAMBLE,
2370 };
2371 #ifdef HP_IP46TCP4BATCH_DEFAULT
2372 #define CAS_HP_FIRMWARE cas_prog_ip46tcp4batchtab
2373 #endif
2374 #endif
2376 /* Workaround for Cassini rev2 descriptor corruption problem.
2377 * Does batching without reassembly, and sets the SAP to a known
2378 * data pattern for all packets.
2379 */
2380 #ifdef USE_HP_WORKAROUND
2424 };
2425 #ifdef HP_WORKAROUND_DEFAULT
2426 #define CAS_HP_FIRMWARE cas_prog_workaroundtab
2427 #endif
2428 #endif
2430 #ifdef USE_HP_ENCRYPT
2436 #if 0
2437 //"CFI?", /* 02 FIND CFI and If FIND go to S1_DROP */
2438 //0x1000, 0x1000, OP_EQ, 0, S1_DROP, 1, S1_8023, CL_REG, 0x000, 0, 0x0, 0x00
2440 #endif
2465 #if 0
2466 //@@@0xff00, 0x0600, OP_EQ, 18, S1_TCPSQ, 0, S1_ESP6, LD_LEN, 0x03f, 1, 0x0, 0xffff,
2467 #endif
2494 #if 0
2495 //@@@0x00ff, 0x0032, OP_EQ, 0, S1_CLNP2, 0, S1_AH6, IM_CTL, 0x021, 1, 0x0, 0xffff,
2496 #endif
2500 #if 0
2501 //@@@0x00ff, 0x0033, OP_EQ, 0, S1_CLNP2, 0, S1_CLNP, IM_CTL, 0x021, 1, 0x0, 0xffff,
2502 #endif
2506 };
2507 #ifdef HP_ENCRYPT_DEFAULT
2508 #define CAS_HP_FIRMWARE cas_prog_encryptiontab
2509 #endif
2510 #endif
2513 #ifdef HP_NULL_DEFAULT
2514 #define CAS_HP_FIRMWARE cas_prog_null
2515 #endif
2517 /* phy types */
2518 #define CAS_PHY_UNKNOWN 0x00
2519 #define CAS_PHY_SERDES 0x01
2520 #define CAS_PHY_MII_MDIO0 0x02
2521 #define CAS_PHY_MII_MDIO1 0x04
2522 #define CAS_PHY_MII(x) ((x) & (CAS_PHY_MII_MDIO0 | CAS_PHY_MII_MDIO1))
2524 /* _RING_INDEX is the index for the ring sizes to be used. _RING_SIZE
2525 * is the actual size. the default index for the various rings is
2526 * 8. NOTE: there a bunch of alignment constraints for the rings. to
2527 * deal with that, i just allocate rings to create the desired
2528 * alignment. here are the constraints:
2529 * RX DESC and COMP rings must be 8KB aligned
2530 * TX DESC must be 2KB aligned.
2531 * if you change the numbers, be cognizant of how the alignment will change
2532 * in INIT_BLOCK as well.
2533 */
2535 #define DESC_RING_I_TO_S(x) (32*(1 << (x)))
2536 #define COMP_RING_I_TO_S(x) (128*(1 << (x)))
2541 #if (TX_DESC_RING_INDEX > 8) || (TX_DESC_RING_INDEX < 0)
2542 #error TX_DESC_RING_INDEX must be between 0 and 8
2543 #endif
2545 #if (RX_DESC_RING_INDEX > 8) || (RX_DESC_RING_INDEX < 0)
2546 #error RX_DESC_RING_INDEX must be between 0 and 8
2547 #endif
2549 #if (RX_COMP_RING_INDEX > 8) || (RX_COMP_RING_INDEX < 0)
2550 #error RX_COMP_RING_INDEX must be between 0 and 8
2551 #endif
2554 #define N_TX_RINGS_MASK MAX_TX_RINGS_MASK
2558 /* number of flows that can go through re-assembly */
2559 #define N_RX_FLOWS 64
2561 #define TX_DESC_RING_SIZE DESC_RING_I_TO_S(TX_DESC_RING_INDEX)
2562 #define RX_DESC_RING_SIZE DESC_RING_I_TO_S(RX_DESC_RING_INDEX)
2563 #define RX_COMP_RING_SIZE COMP_RING_I_TO_S(RX_COMP_RING_INDEX)
2564 #define TX_DESC_RINGN_INDEX(x) TX_DESC_RING_INDEX
2565 #define RX_DESC_RINGN_INDEX(x) RX_DESC_RING_INDEX
2566 #define RX_COMP_RINGN_INDEX(x) RX_COMP_RING_INDEX
2567 #define TX_DESC_RINGN_SIZE(x) TX_DESC_RING_SIZE
2568 #define RX_DESC_RINGN_SIZE(x) RX_DESC_RING_SIZE
2569 #define RX_COMP_RINGN_SIZE(x) RX_COMP_RING_SIZE
2571 /* convert values */
2572 #define CAS_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK))
2573 #define CAS_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT))
2574 #define CAS_TX_RINGN_BASE(y) ((TX_DESC_RINGN_INDEX(y) << \
2575 TX_CFG_DESC_RINGN_SHIFT(y)) & \
2576 TX_CFG_DESC_RINGN_MASK(y))
2578 /* min is 2k, but we can't do jumbo frames unless it's at least 8k */
2584 bytes. 0 - 9256 */
2585 #define TX_DESC_BUFLEN_SHIFT 0
2587 of bytes to be
2588 skipped before
2589 csum calc begins.
2590 value must be
2591 even */
2592 #define TX_DESC_CSUM_START_SHIFT 15
2594 byte offset w/in
2595 the pkt for the
2596 1st csum byte.
2597 must be > 8 */
2598 #define TX_DESC_CSUM_STUFF_SHIFT 21
2604 CRC will not be
2605 inserted into
2606 outgoing frame. */
2608 __le64 control;
2609 __le64 buffer;
2610 };
2612 /* descriptor ring for free buffers contains page-sized buffers. the index
2613 * value is not used by the hw in any way. it's just stored and returned in
2614 * the completion ring.
2615 */
2617 __le64 index;
2618 __le64 buffer;
2619 };
2621 /* received packets are put on the completion ring. */
2622 /* word 1 */
2623 #define RX_COMP1_DATA_SIZE_MASK 0x0000000007FFE000ULL
2624 #define RX_COMP1_DATA_SIZE_SHIFT 13
2625 #define RX_COMP1_DATA_OFF_MASK 0x000001FFF8000000ULL
2626 #define RX_COMP1_DATA_OFF_SHIFT 27
2627 #define RX_COMP1_DATA_INDEX_MASK 0x007FFE0000000000ULL
2628 #define RX_COMP1_DATA_INDEX_SHIFT 41
2629 #define RX_COMP1_SKIP_MASK 0x0180000000000000ULL
2630 #define RX_COMP1_SKIP_SHIFT 55
2631 #define RX_COMP1_RELEASE_NEXT 0x0200000000000000ULL
2632 #define RX_COMP1_SPLIT_PKT 0x0400000000000000ULL
2633 #define RX_COMP1_RELEASE_FLOW 0x0800000000000000ULL
2634 #define RX_COMP1_RELEASE_DATA 0x1000000000000000ULL
2635 #define RX_COMP1_RELEASE_HDR 0x2000000000000000ULL
2636 #define RX_COMP1_TYPE_MASK 0xC000000000000000ULL
2637 #define RX_COMP1_TYPE_SHIFT 62
2639 /* word 2 */
2640 #define RX_COMP2_NEXT_INDEX_MASK 0x00000007FFE00000ULL
2641 #define RX_COMP2_NEXT_INDEX_SHIFT 21
2642 #define RX_COMP2_HDR_SIZE_MASK 0x00000FF800000000ULL
2643 #define RX_COMP2_HDR_SIZE_SHIFT 35
2644 #define RX_COMP2_HDR_OFF_MASK 0x0003F00000000000ULL
2645 #define RX_COMP2_HDR_OFF_SHIFT 44
2646 #define RX_COMP2_HDR_INDEX_MASK 0xFFFC000000000000ULL
2647 #define RX_COMP2_HDR_INDEX_SHIFT 50
2649 /* word 3 */
2650 #define RX_COMP3_SMALL_PKT 0x0000000000000001ULL
2651 #define RX_COMP3_JUMBO_PKT 0x0000000000000002ULL
2652 #define RX_COMP3_JUMBO_HDR_SPLIT_EN 0x0000000000000004ULL
2653 #define RX_COMP3_CSUM_START_MASK 0x000000000007F000ULL
2654 #define RX_COMP3_CSUM_START_SHIFT 12
2655 #define RX_COMP3_FLOWID_MASK 0x0000000001F80000ULL
2656 #define RX_COMP3_FLOWID_SHIFT 19
2657 #define RX_COMP3_OPCODE_MASK 0x000000000E000000ULL
2658 #define RX_COMP3_OPCODE_SHIFT 25
2659 #define RX_COMP3_FORCE_FLAG 0x0000000010000000ULL
2660 #define RX_COMP3_NO_ASSIST 0x0000000020000000ULL
2661 #define RX_COMP3_LOAD_BAL_MASK 0x000001F800000000ULL
2662 #define RX_COMP3_LOAD_BAL_SHIFT 35
2665 #define RX_COMP3_L3_HEAD_OFF_SHIFT 41
2667 #define RX_PLUS_COMP_L3_HEAD_OFF_SHIFT 42
2668 #define RX_COMP3_SAP_MASK 0xFFFF000000000000ULL
2669 #define RX_COMP3_SAP_SHIFT 48
2671 /* word 4 */
2672 #define RX_COMP4_TCP_CSUM_MASK 0x000000000000FFFFULL
2673 #define RX_COMP4_TCP_CSUM_SHIFT 0
2674 #define RX_COMP4_PKT_LEN_MASK 0x000000003FFF0000ULL
2675 #define RX_COMP4_PKT_LEN_SHIFT 16
2676 #define RX_COMP4_PERFECT_MATCH_MASK 0x00000003C0000000ULL
2677 #define RX_COMP4_PERFECT_MATCH_SHIFT 30
2678 #define RX_COMP4_ZERO 0x0000080000000000ULL
2679 #define RX_COMP4_HASH_VAL_MASK 0x0FFFF00000000000ULL
2680 #define RX_COMP4_HASH_VAL_SHIFT 44
2681 #define RX_COMP4_HASH_PASS 0x1000000000000000ULL
2682 #define RX_COMP4_BAD 0x4000000000000000ULL
2683 #define RX_COMP4_LEN_MISMATCH 0x8000000000000000ULL
2685 /* we encode the following: ring/index/release. only 14 bits
2686 * are usable.
2687 * NOTE: the encoding is dependent upon RX_DESC_RING_SIZE and
2688 * MAX_RX_DESC_RINGS. */
2689 #define RX_INDEX_NUM_MASK 0x0000000000000FFFULL
2690 #define RX_INDEX_NUM_SHIFT 0
2691 #define RX_INDEX_RING_MASK 0x0000000000001000ULL
2692 #define RX_INDEX_RING_SHIFT 12
2693 #define RX_INDEX_RELEASE 0x0000000000002000ULL
2696 __le64 word1;
2697 __le64 word2;
2698 __le64 word3;
2699 __le64 word4;
2700 };
2708 link_up /* Link is up */
2709 };
2714 dma_addr_t dma_addr;
2719 /* some alignment constraints:
2720 * TX DESC, RX DESC, and RX COMP must each be 8K aligned.
2721 * TX COMPWB must be 8-byte aligned.
2722 * to accomplish this, here's what we do:
2723 *
2724 * INIT_BLOCK_RX_COMP = 64k (already aligned)
2725 * INIT_BLOCK_RX_DESC = 8k
2726 * INIT_BLOCK_TX = 8k
2727 * INIT_BLOCK_RX1_DESC = 8k
2728 * TX COMPWB
2729 */
2730 #define INIT_BLOCK_TX (TX_DESC_RING_SIZE)
2731 #define INIT_BLOCK_RX_DESC (RX_DESC_RING_SIZE)
2732 #define INIT_BLOCK_RX_COMP (RX_COMP_RING_SIZE)
2738 __le64 tx_compwb;
2739 };
2741 /* tiny buffers to deal with target abort issue. we allocate a bit
2742 * over so that we don't have target abort issues with these buffers
2743 * as well.
2744 */
2745 #define TX_TINY_BUF_LEN 0x100
2746 #define TX_TINY_BUF_BLOCK ((INIT_BLOCK_TX + 1)*TX_TINY_BUF_LEN)
2751 };
2768 /* Set when chip is actually in operational state
2769 * (ie. not power managed) */
2779 /* we use sk_buffs for tx and pages for rx. the rx skbuffs
2780 * are there for flow re-assembly. */
2787 /* for small packets when copying would be quicker than
2788 mapping */
2792 u32 msg_enable;
2794 /* N_TX_RINGS must be >= N_RX_DESC_RINGS */
2798 u8 pci_revision;
2802 u32 phy_id;
2803 #define CAS_FLAG_1000MB_CAP 0x00000001
2804 #define CAS_FLAG_REG_PLUS 0x00000002
2805 #define CAS_FLAG_TARGET_ABORT 0x00000004
2806 #define CAS_FLAG_SATURN 0x00000008
2807 #define CAS_FLAG_RXD_POST_MASK 0x000000F0
2808 #define CAS_FLAG_RXD_POST_SHIFT 4
2809 #define CAS_FLAG_RXD_POST(x) ((1 << (CAS_FLAG_RXD_POST_SHIFT + (x))) & \
2810 CAS_FLAG_RXD_POST_MASK)
2811 #define CAS_FLAG_ENTROPY_DEV 0x00000100
2812 #define CAS_FLAG_NO_HW_CSUM 0x00000200
2813 u32 cas_flags;
2824 /* page size allocation */
2829 u32 mac_rx_cfg;
2831 /* Autoneg & PHY control */
2838 #if 0
2839 atomic_t reset_task_pending;
2840 #else
2841 atomic_t reset_task_pending;
2842 atomic_t reset_task_pending_mtu;
2843 atomic_t reset_task_pending_spare;
2844 atomic_t reset_task_pending_all;
2845 #endif
2847 #ifdef CONFIG_CASSINI_QGE_DEBUG
2849 #endif
2851 /* Link-down problem workaround */
2852 #define LINK_TRANSITION_UNKNOWN 0
2853 #define LINK_TRANSITION_ON_FAILURE 1
2854 #define LINK_TRANSITION_STILL_FAILED 2
2855 #define LINK_TRANSITION_LINK_UP 3
2856 #define LINK_TRANSITION_LINK_CONFIG 4
2857 #define LINK_TRANSITION_LINK_DOWN 5
2858 #define LINK_TRANSITION_REQUESTED_RESET 6
2863 /* Tuning */
2867 /* Diagnostic counters and state. */
2869 u64 pause_entered;
2870 u16 pause_last_time_recvd;
2876 /* Firmware Info */
2877 u16 fw_load_addr;
2878 u32 fw_size;
2880 };
2882 #define TX_DESC_NEXT(r, x) (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1))
2883 #define RX_DESC_ENTRY(r, x) ((x) & (RX_DESC_RINGN_SIZE(r) - 1))
2884 #define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1))
2886 #define TX_BUFF_COUNT(r, x, y) ((x) <= (y) ? ((y) - (x)) : \
2887 (TX_DESC_RINGN_SIZE(r) - (x) + (y)))
2889 #define TX_BUFFS_AVAIL(cp, i) ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \
2890 (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \
2891 (cp)->tx_old[(i)] - (cp)->tx_new[(i)] - 1)
2893 #define CAS_ALIGN(addr, align) \
2894 (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1))
2896 #define RX_FIFO_SIZE 16384
2897 #define EXPANSION_ROM_SIZE 65536
2899 #define CAS_MC_EXACT_MATCH_SIZE 15
2900 #define CAS_MC_HASH_SIZE 256
2901 #define CAS_MC_HASH_MAX (CAS_MC_EXACT_MATCH_SIZE + \
2902 CAS_MC_HASH_SIZE)
2904 #define TX_TARGET_ABORT_LEN 0x20
2905 #define RX_SWIVEL_OFF_VAL 0x2
2906 #define RX_AE_FREEN_VAL(x) (RX_DESC_RINGN_SIZE(x) >> 1)
2907 #define RX_AE_COMP_VAL (RX_COMP_RING_SIZE >> 1)
2908 #define RX_BLANK_INTR_PKT_VAL 0x05
2909 #define RX_BLANK_INTR_TIME_VAL 0x0F
2912 #define RX_SPARE_COUNT (RX_DESC_RING_SIZE >> 1)
2913 #define RX_SPARE_RECOVER_VAL (RX_SPARE_COUNT >> 2)