arch/x86/oprofile/op_model_amd.c

   1 /*
   2  * @file op_model_amd.c
   3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
   4  *
   5  * @remark Copyright 2002-2008 OProfile authors
   6  * @remark Read the file COPYING
   7  *
   8  * @author John Levon
   9  * @author Philippe Elie
  10  * @author Graydon Hoare
  11  * @author Robert Richter <robert.richter@amd.com>
  12  * @author Barry Kasindorf
  13 */
  14
  15 #include <linux/oprofile.h>
  16 #include <linux/device.h>
  17 #include <linux/pci.h>
  18
  19 #include <asm/ptrace.h>
  20 #include <asm/msr.h>
  21 #include <asm/nmi.h>
  22
  23 #include "op_x86_model.h"
  24 #include "op_counter.h"
  25
  26 #define NUM_COUNTERS 4
  27 #define NUM_CONTROLS 4
  28
  29 #define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
  30 #define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
  31 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0)
  32 #define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
  33
  34 #define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
  35 #define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
  36 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
  37 #define CTRL_SET_ACTIVE(n) (n |= (1<<22))
  38 #define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
  39 #define CTRL_CLEAR_LO(x) (x &= (1<<21))
  40 #define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)
  41 #define CTRL_SET_ENABLE(val) (val |= 1<<20)
  42 #define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))
  43 #define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))
  44 #define CTRL_SET_UM(val, m) (val |= (m << 8))
  45 #define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))
  46 #define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))
  47 #define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
  48 #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
  49
  50 static unsigned long reset_value[NUM_COUNTERS];
  51
  52 #ifdef CONFIG_OPROFILE_IBS
  53
  54 /* IbsFetchCtl bits/masks */
  55 #define IBS_FETCH_HIGH_VALID_BIT        (1UL << 17)     /* bit 49 */
  56 #define IBS_FETCH_HIGH_ENABLE           (1UL << 16)     /* bit 48 */
  57 #define IBS_FETCH_LOW_MAX_CNT_MASK      0x0000FFFFUL    /* MaxCnt mask */
  58
  59 /*IbsOpCtl bits */
  60 #define IBS_OP_LOW_VALID_BIT            (1ULL<<18)      /* bit 18 */
  61 #define IBS_OP_LOW_ENABLE               (1ULL<<17)      /* bit 17 */
  62
  63 /* Codes used in cpu_buffer.c */
  64 /* This produces duplicate code, need to be fixed */
  65 #define IBS_FETCH_BEGIN 3
  66 #define IBS_OP_BEGIN    4
  67
  68 /*
  69  * The function interface needs to be fixed, something like add
  70  * data. Should then be added to linux/oprofile.h.
  71  */
  72 extern void
  73 oprofile_add_ibs_sample(struct pt_regs * const regs,
  74                         unsigned int * const ibs_sample, int ibs_code);
  75
  76 struct ibs_fetch_sample {
  77         /* MSRC001_1031 IBS Fetch Linear Address Register */
  78         unsigned int ibs_fetch_lin_addr_low;
  79         unsigned int ibs_fetch_lin_addr_high;
  80         /* MSRC001_1030 IBS Fetch Control Register */
  81         unsigned int ibs_fetch_ctl_low;
  82         unsigned int ibs_fetch_ctl_high;
  83         /* MSRC001_1032 IBS Fetch Physical Address Register */
  84         unsigned int ibs_fetch_phys_addr_low;
  85         unsigned int ibs_fetch_phys_addr_high;
  86 };
  87
  88 struct ibs_op_sample {
  89         /* MSRC001_1034 IBS Op Logical Address Register (IbsRIP) */
  90         unsigned int ibs_op_rip_low;
  91         unsigned int ibs_op_rip_high;
  92         /* MSRC001_1035 IBS Op Data Register */
  93         unsigned int ibs_op_data1_low;
  94         unsigned int ibs_op_data1_high;
  95         /* MSRC001_1036 IBS Op Data 2 Register */
  96         unsigned int ibs_op_data2_low;
  97         unsigned int ibs_op_data2_high;
  98         /* MSRC001_1037 IBS Op Data 3 Register */
  99         unsigned int ibs_op_data3_low;
 100         unsigned int ibs_op_data3_high;
 101         /* MSRC001_1038 IBS DC Linear Address Register (IbsDcLinAd) */
 102         unsigned int ibs_dc_linear_low;
 103         unsigned int ibs_dc_linear_high;
 104         /* MSRC001_1039 IBS DC Physical Address Register (IbsDcPhysAd) */
 105         unsigned int ibs_dc_phys_low;
 106         unsigned int ibs_dc_phys_high;
 107 };
 108
 109 /*
 110  * unitialize the APIC for the IBS interrupts if needed on AMD Family10h+
 111  */
 112 static void clear_ibs_nmi(void);
 113
 114 static int ibs_allowed; /* AMD Family10h and later */
 115
 116 struct op_ibs_config {
 117         unsigned long op_enabled;
 118         unsigned long fetch_enabled;
 119         unsigned long max_cnt_fetch;
 120         unsigned long max_cnt_op;
 121         unsigned long rand_en;
 122         unsigned long dispatched_ops;
 123 };
 124
 125 static struct op_ibs_config ibs_config;
 126
 127 #endif
 128
 129 /* functions for op_amd_spec */
 130
 131 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
 132 {
 133         int i;
 134
 135         for (i = 0; i < NUM_COUNTERS; i++) {
 136                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
 137                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
 138                 else
 139                         msrs->counters[i].addr = 0;
 140         }
 141
 142         for (i = 0; i < NUM_CONTROLS; i++) {
 143                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
 144                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
 145                 else
 146                         msrs->controls[i].addr = 0;
 147         }
 148 }
 149
 150
 151 static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
 152 {
 153         unsigned int low, high;
 154         int i;
 155
 156         /* clear all counters */
 157         for (i = 0 ; i < NUM_CONTROLS; ++i) {
 158                 if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
 159                         continue;
 160                 CTRL_READ(low, high, msrs, i);
 161                 CTRL_CLEAR_LO(low);
 162                 CTRL_CLEAR_HI(high);
 163                 CTRL_WRITE(low, high, msrs, i);
 164         }
 165
 166         /* avoid a false detection of ctr overflows in NMI handler */
 167         for (i = 0; i < NUM_COUNTERS; ++i) {
 168                 if (unlikely(!CTR_IS_RESERVED(msrs, i)))
 169                         continue;
 170                 CTR_WRITE(1, msrs, i);
 171         }
 172
 173         /* enable active counters */
 174         for (i = 0; i < NUM_COUNTERS; ++i) {
 175                 if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
 176                         reset_value[i] = counter_config[i].count;
 177
 178                         CTR_WRITE(counter_config[i].count, msrs, i);
 179
 180                         CTRL_READ(low, high, msrs, i);
 181                         CTRL_CLEAR_LO(low);
 182                         CTRL_CLEAR_HI(high);
 183                         CTRL_SET_ENABLE(low);
 184                         CTRL_SET_USR(low, counter_config[i].user);
 185                         CTRL_SET_KERN(low, counter_config[i].kernel);
 186                         CTRL_SET_UM(low, counter_config[i].unit_mask);
 187                         CTRL_SET_EVENT_LOW(low, counter_config[i].event);
 188                         CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
 189                         CTRL_SET_HOST_ONLY(high, 0);
 190                         CTRL_SET_GUEST_ONLY(high, 0);
 191
 192                         CTRL_WRITE(low, high, msrs, i);
 193                 } else {
 194                         reset_value[i] = 0;
 195                 }
 196         }
 197 }
 198
 199 #ifdef CONFIG_OPROFILE_IBS
 200
 201 static inline int
 202 op_amd_handle_ibs(struct pt_regs * const regs,
 203                   struct op_msrs const * const msrs)
 204 {
 205         unsigned int low, high;
 206         struct ibs_fetch_sample ibs_fetch;
 207         struct ibs_op_sample ibs_op;
 208
 209         if (!ibs_allowed)
 210                 return 1;
 211
 212         if (ibs_config.fetch_enabled) {
 213                 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 214                 if (high & IBS_FETCH_HIGH_VALID_BIT) {
 215                         ibs_fetch.ibs_fetch_ctl_high = high;
 216                         ibs_fetch.ibs_fetch_ctl_low = low;
 217                         rdmsr(MSR_AMD64_IBSFETCHLINAD, low, high);
 218                         ibs_fetch.ibs_fetch_lin_addr_high = high;
 219                         ibs_fetch.ibs_fetch_lin_addr_low = low;
 220                         rdmsr(MSR_AMD64_IBSFETCHPHYSAD, low, high);
 221                         ibs_fetch.ibs_fetch_phys_addr_high = high;
 222                         ibs_fetch.ibs_fetch_phys_addr_low = low;
 223
 224                         oprofile_add_ibs_sample(regs,
 225                                                 (unsigned int *)&ibs_fetch,
 226                                                 IBS_FETCH_BEGIN);
 227
 228                         /* reenable the IRQ */
 229                         rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 230                         high &= ~IBS_FETCH_HIGH_VALID_BIT;
 231                         high |= IBS_FETCH_HIGH_ENABLE;
 232                         low &= IBS_FETCH_LOW_MAX_CNT_MASK;
 233                         wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 234                 }
 235         }
 236
 237         if (ibs_config.op_enabled) {
 238                 rdmsr(MSR_AMD64_IBSOPCTL, low, high);
 239                 if (low & IBS_OP_LOW_VALID_BIT) {
 240                         rdmsr(MSR_AMD64_IBSOPRIP, low, high);
 241                         ibs_op.ibs_op_rip_low = low;
 242                         ibs_op.ibs_op_rip_high = high;
 243                         rdmsr(MSR_AMD64_IBSOPDATA, low, high);
 244                         ibs_op.ibs_op_data1_low = low;
 245                         ibs_op.ibs_op_data1_high = high;
 246                         rdmsr(MSR_AMD64_IBSOPDATA2, low, high);
 247                         ibs_op.ibs_op_data2_low = low;
 248                         ibs_op.ibs_op_data2_high = high;
 249                         rdmsr(MSR_AMD64_IBSOPDATA3, low, high);
 250                         ibs_op.ibs_op_data3_low = low;
 251                         ibs_op.ibs_op_data3_high = high;
 252                         rdmsr(MSR_AMD64_IBSDCLINAD, low, high);
 253                         ibs_op.ibs_dc_linear_low = low;
 254                         ibs_op.ibs_dc_linear_high = high;
 255                         rdmsr(MSR_AMD64_IBSDCPHYSAD, low, high);
 256                         ibs_op.ibs_dc_phys_low = low;
 257                         ibs_op.ibs_dc_phys_high = high;
 258
 259                         /* reenable the IRQ */
 260                         oprofile_add_ibs_sample(regs,
 261                                                 (unsigned int *)&ibs_op,
 262                                                 IBS_OP_BEGIN);
 263                         rdmsr(MSR_AMD64_IBSOPCTL, low, high);
 264                         high = 0;
 265                         low &= ~IBS_OP_LOW_VALID_BIT;
 266                         low |= IBS_OP_LOW_ENABLE;
 267                         wrmsr(MSR_AMD64_IBSOPCTL, low, high);
 268                 }
 269         }
 270
 271         return 1;
 272 }
 273
 274 #endif
 275
 276 static int op_amd_check_ctrs(struct pt_regs * const regs,
 277                              struct op_msrs const * const msrs)
 278 {
 279         unsigned int low, high;
 280         int i;
 281
 282         for (i = 0 ; i < NUM_COUNTERS; ++i) {
 283                 if (!reset_value[i])
 284                         continue;
 285                 CTR_READ(low, high, msrs, i);
 286                 if (CTR_OVERFLOWED(low)) {
 287                         oprofile_add_sample(regs, i);
 288                         CTR_WRITE(reset_value[i], msrs, i);
 289                 }
 290         }
 291
 292 #ifdef CONFIG_OPROFILE_IBS
 293         op_amd_handle_ibs(regs, msrs);
 294 #endif
 295
 296         /* See op_model_ppro.c */
 297         return 1;
 298 }
 299
 300 static void op_amd_start(struct op_msrs const * const msrs)
 301 {
 302         unsigned int low, high;
 303         int i;
 304         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
 305                 if (reset_value[i]) {
 306                         CTRL_READ(low, high, msrs, i);
 307                         CTRL_SET_ACTIVE(low);
 308                         CTRL_WRITE(low, high, msrs, i);
 309                 }
 310         }
 311
 312 #ifdef CONFIG_OPROFILE_IBS
 313         if (ibs_allowed && ibs_config.fetch_enabled) {
 314                 low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
 315                 high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */
 316                         + IBS_FETCH_HIGH_ENABLE;
 317                 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 318         }
 319
 320         if (ibs_allowed && ibs_config.op_enabled) {
 321                 low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF)
 322                         + ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */
 323                         + IBS_OP_LOW_ENABLE;
 324                 high = 0;
 325                 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
 326         }
 327 #endif
 328 }
 329
 330
 331 static void op_amd_stop(struct op_msrs const * const msrs)
 332 {
 333         unsigned int low, high;
 334         int i;
 335
 336         /*
 337          * Subtle: stop on all counters to avoid race with setting our
 338          * pm callback
 339          */
 340         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
 341                 if (!reset_value[i])
 342                         continue;
 343                 CTRL_READ(low, high, msrs, i);
 344                 CTRL_SET_INACTIVE(low);
 345                 CTRL_WRITE(low, high, msrs, i);
 346         }
 347
 348 #ifdef CONFIG_OPROFILE_IBS
 349         if (ibs_allowed && ibs_config.fetch_enabled) {
 350                 /* clear max count and enable */
 351                 low = 0;
 352                 high = 0;
 353                 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
 354         }
 355
 356         if (ibs_allowed && ibs_config.op_enabled) {
 357                 /* clear max count and enable */
 358                 low = 0;
 359                 high = 0;
 360                 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
 361         }
 362 #endif
 363 }
 364
 365 static void op_amd_shutdown(struct op_msrs const * const msrs)
 366 {
 367         int i;
 368
 369         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
 370                 if (CTR_IS_RESERVED(msrs, i))
 371                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
 372         }
 373         for (i = 0 ; i < NUM_CONTROLS ; ++i) {
 374                 if (CTRL_IS_RESERVED(msrs, i))
 375                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
 376         }
 377 }
 378
 379 #ifndef CONFIG_OPROFILE_IBS
 380
 381 /* no IBS support */
 382
 383 static int op_amd_init(struct oprofile_operations *ops)
 384 {
 385         return 0;
 386 }
 387
 388 static void op_amd_exit(void) {}
 389
 390 #else
 391
 392 static u8 ibs_eilvt_off;
 393
 394 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
 395 {
 396         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
 397 }
 398
 399 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
 400 {
 401         setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
 402 }
 403
 404 static int pfm_amd64_setup_eilvt(void)
 405 {
 406 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
 407 #define IBSCTL                          0x1cc
 408         struct pci_dev *cpu_cfg;
 409         int nodes;
 410         u32 value = 0;
 411
 412         /* per CPU setup */
 413         on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
 414
 415         nodes = 0;
 416         cpu_cfg = NULL;
 417         do {
 418                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
 419                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
 420                                          cpu_cfg);
 421                 if (!cpu_cfg)
 422                         break;
 423                 ++nodes;
 424                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
 425                                        | IBSCTL_LVTOFFSETVAL);
 426                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
 427                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
 428                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
 429                                 "IBSCTL = 0x%08x", value);
 430                         return 1;
 431                 }
 432         } while (1);
 433
 434         if (!nodes) {
 435                 printk(KERN_DEBUG "No CPU node configured for IBS");
 436                 return 1;
 437         }
 438
 439 #ifdef CONFIG_NUMA
 440         /* Sanity check */
 441         /* Works only for 64bit with proper numa implementation. */
 442         if (nodes != num_possible_nodes()) {
 443                 printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
 444                         "found: %d, expected %d",
 445                         nodes, num_possible_nodes());
 446                 return 1;
 447         }
 448 #endif
 449         return 0;
 450 }
 451
 452 /* initialize the APIC for the IBS interrupts if available */
 453 static void setup_ibs(void)
 454 {
 455         ibs_allowed = boot_cpu_has(X86_FEATURE_IBS);
 456
 457         if (!ibs_allowed)
 458                 return;
 459
 460         if (pfm_amd64_setup_eilvt()) {
 461                 ibs_allowed = 0;
 462                 return;
 463         }
 464
 465         printk(KERN_INFO "oprofile: AMD IBS detected\n");
 466 }
 467
 468
 469 /* uninitialize the APIC for the IBS interrupts if needed */
 470 static void clear_ibs_nmi(void)
 471 {
 472         if (ibs_allowed)
 473                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
 474 }
 475
 476 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
 477
 478 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
 479 {
 480         struct dentry *dir;
 481         int ret = 0;
 482
 483         /* architecture specific files */
 484         if (create_arch_files)
 485                 ret = create_arch_files(sb, root);
 486
 487         if (ret)
 488                 return ret;
 489
 490         if (!ibs_allowed)
 491                 return ret;
 492
 493         /* model specific files */
 494
 495         /* setup some reasonable defaults */
 496         ibs_config.max_cnt_fetch = 250000;
 497         ibs_config.fetch_enabled = 0;
 498         ibs_config.max_cnt_op = 250000;
 499         ibs_config.op_enabled = 0;
 500         ibs_config.dispatched_ops = 1;
 501
 502         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
 503         oprofilefs_create_ulong(sb, dir, "enable",
 504                                 &ibs_config.fetch_enabled);
 505         oprofilefs_create_ulong(sb, dir, "max_count",
 506                                 &ibs_config.max_cnt_fetch);
 507         oprofilefs_create_ulong(sb, dir, "rand_enable",
 508                                 &ibs_config.rand_en);
 509
 510         dir = oprofilefs_mkdir(sb, root, "ibs_op");
 511         oprofilefs_create_ulong(sb, dir, "enable",
 512                                 &ibs_config.op_enabled);
 513         oprofilefs_create_ulong(sb, dir, "max_count",
 514                                 &ibs_config.max_cnt_op);
 515         oprofilefs_create_ulong(sb, dir, "dispatched_ops",
 516                                 &ibs_config.dispatched_ops);
 517
 518         return 0;
 519 }
 520
 521 static int op_amd_init(struct oprofile_operations *ops)
 522 {
 523         setup_ibs();
 524         create_arch_files = ops->create_files;
 525         ops->create_files = setup_ibs_files;
 526         return 0;
 527 }
 528
 529 static void op_amd_exit(void)
 530 {
 531         clear_ibs_nmi();
 532 }
 533
 534 #endif
 535
 536 struct op_x86_model_spec const op_amd_spec = {
 537         .init                   = op_amd_init,
 538         .exit                   = op_amd_exit,
 539         .num_counters           = NUM_COUNTERS,
 540         .num_controls           = NUM_CONTROLS,
 541         .fill_in_addresses      = &op_amd_fill_in_addresses,
 542         .setup_ctrs             = &op_amd_setup_ctrs,
 543         .check_ctrs             = &op_amd_check_ctrs,
 544         .start                  = &op_amd_start,
 545         .stop                   = &op_amd_stop,
 546         .shutdown               = &op_amd_shutdown
 547 };