2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
5 * See LICENSE.qla3xxx for copyright and licensing details.
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/dmapool.h>
18 #include <linux/mempool.h>
19 #include <linux/spinlock.h>
20 #include <linux/kthread.h>
21 #include <linux/interrupt.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
26 #include <linux/if_arp.h>
27 #include <linux/if_ether.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/skbuff.h>
32 #include <linux/rtnetlink.h>
33 #include <linux/if_vlan.h>
34 #include <linux/init.h>
35 #include <linux/delay.h>
40 #define DRV_NAME "qla3xxx"
41 #define DRV_STRING "QLogic ISP3XXX Network Driver"
42 #define DRV_VERSION "v2.02.00-k36"
43 #define PFX DRV_NAME " "
45 static const char ql3xxx_driver_name
[] = DRV_NAME
;
46 static const char ql3xxx_driver_version
[] = DRV_VERSION
;
48 MODULE_AUTHOR("QLogic Corporation");
49 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION
" ");
50 MODULE_LICENSE("GPL");
51 MODULE_VERSION(DRV_VERSION
);
53 static const u32 default_msg
54 = NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
55 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
57 static int debug
= -1; /* defaults above */
58 module_param(debug
, int, 0);
59 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
62 module_param(msi
, int, 0);
63 MODULE_PARM_DESC(msi
, "Turn on Message Signaled Interrupts.");
65 static struct pci_device_id ql3xxx_pci_tbl
[] __devinitdata
= {
66 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC
, QL3022_DEVICE_ID
)},
67 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC
, QL3032_DEVICE_ID
)},
68 /* required last entry */
72 MODULE_DEVICE_TABLE(pci
, ql3xxx_pci_tbl
);
75 * Caller must take hw_lock.
77 static int ql_sem_spinlock(struct ql3_adapter
*qdev
,
78 u32 sem_mask
, u32 sem_bits
)
80 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
82 unsigned int seconds
= 3;
85 writel((sem_mask
| sem_bits
),
86 &port_regs
->CommonRegs
.semaphoreReg
);
87 value
= readl(&port_regs
->CommonRegs
.semaphoreReg
);
88 if ((value
& (sem_mask
>> 16)) == sem_bits
)
95 static void ql_sem_unlock(struct ql3_adapter
*qdev
, u32 sem_mask
)
97 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
98 writel(sem_mask
, &port_regs
->CommonRegs
.semaphoreReg
);
99 readl(&port_regs
->CommonRegs
.semaphoreReg
);
102 static int ql_sem_lock(struct ql3_adapter
*qdev
, u32 sem_mask
, u32 sem_bits
)
104 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
107 writel((sem_mask
| sem_bits
), &port_regs
->CommonRegs
.semaphoreReg
);
108 value
= readl(&port_regs
->CommonRegs
.semaphoreReg
);
109 return ((value
& (sem_mask
>> 16)) == sem_bits
);
113 * Caller holds hw_lock.
115 static int ql_wait_for_drvr_lock(struct ql3_adapter
*qdev
)
120 if (!ql_sem_lock(qdev
,
122 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
)
128 printk(KERN_ERR PFX
"%s: Timed out waiting for "
134 printk(KERN_DEBUG PFX
135 "%s: driver lock acquired.\n",
142 static void ql_set_register_page(struct ql3_adapter
*qdev
, u32 page
)
144 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
146 writel(((ISP_CONTROL_NP_MASK
<< 16) | page
),
147 &port_regs
->CommonRegs
.ispControlStatus
);
148 readl(&port_regs
->CommonRegs
.ispControlStatus
);
149 qdev
->current_page
= page
;
152 static u32
ql_read_common_reg_l(struct ql3_adapter
*qdev
,
156 unsigned long hw_flags
;
158 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
160 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
165 static u32
ql_read_common_reg(struct ql3_adapter
*qdev
,
171 static u32
ql_read_page0_reg_l(struct ql3_adapter
*qdev
, u32 __iomem
*reg
)
174 unsigned long hw_flags
;
176 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
178 if (qdev
->current_page
!= 0)
179 ql_set_register_page(qdev
,0);
182 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
186 static u32
ql_read_page0_reg(struct ql3_adapter
*qdev
, u32 __iomem
*reg
)
188 if (qdev
->current_page
!= 0)
189 ql_set_register_page(qdev
,0);
193 static void ql_write_common_reg_l(struct ql3_adapter
*qdev
,
194 u32 __iomem
*reg
, u32 value
)
196 unsigned long hw_flags
;
198 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
201 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
205 static void ql_write_common_reg(struct ql3_adapter
*qdev
,
206 u32 __iomem
*reg
, u32 value
)
213 static void ql_write_nvram_reg(struct ql3_adapter
*qdev
,
214 u32 __iomem
*reg
, u32 value
)
222 static void ql_write_page0_reg(struct ql3_adapter
*qdev
,
223 u32 __iomem
*reg
, u32 value
)
225 if (qdev
->current_page
!= 0)
226 ql_set_register_page(qdev
,0);
233 * Caller holds hw_lock. Only called during init.
235 static void ql_write_page1_reg(struct ql3_adapter
*qdev
,
236 u32 __iomem
*reg
, u32 value
)
238 if (qdev
->current_page
!= 1)
239 ql_set_register_page(qdev
,1);
246 * Caller holds hw_lock. Only called during init.
248 static void ql_write_page2_reg(struct ql3_adapter
*qdev
,
249 u32 __iomem
*reg
, u32 value
)
251 if (qdev
->current_page
!= 2)
252 ql_set_register_page(qdev
,2);
258 static void ql_disable_interrupts(struct ql3_adapter
*qdev
)
260 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
262 ql_write_common_reg_l(qdev
, &port_regs
->CommonRegs
.ispInterruptMaskReg
,
263 (ISP_IMR_ENABLE_INT
<< 16));
267 static void ql_enable_interrupts(struct ql3_adapter
*qdev
)
269 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
271 ql_write_common_reg_l(qdev
, &port_regs
->CommonRegs
.ispInterruptMaskReg
,
272 ((0xff << 16) | ISP_IMR_ENABLE_INT
));
276 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter
*qdev
,
277 struct ql_rcv_buf_cb
*lrg_buf_cb
)
280 lrg_buf_cb
->next
= NULL
;
282 if (qdev
->lrg_buf_free_tail
== NULL
) { /* The list is empty */
283 qdev
->lrg_buf_free_head
= qdev
->lrg_buf_free_tail
= lrg_buf_cb
;
285 qdev
->lrg_buf_free_tail
->next
= lrg_buf_cb
;
286 qdev
->lrg_buf_free_tail
= lrg_buf_cb
;
289 if (!lrg_buf_cb
->skb
) {
290 lrg_buf_cb
->skb
= netdev_alloc_skb(qdev
->ndev
,
291 qdev
->lrg_buffer_len
);
292 if (unlikely(!lrg_buf_cb
->skb
)) {
293 printk(KERN_ERR PFX
"%s: failed netdev_alloc_skb().\n",
295 qdev
->lrg_buf_skb_check
++;
298 * We save some space to copy the ethhdr from first
301 skb_reserve(lrg_buf_cb
->skb
, QL_HEADER_SPACE
);
302 map
= pci_map_single(qdev
->pdev
,
303 lrg_buf_cb
->skb
->data
,
304 qdev
->lrg_buffer_len
-
307 lrg_buf_cb
->buf_phy_addr_low
=
308 cpu_to_le32(LS_64BITS(map
));
309 lrg_buf_cb
->buf_phy_addr_high
=
310 cpu_to_le32(MS_64BITS(map
));
311 pci_unmap_addr_set(lrg_buf_cb
, mapaddr
, map
);
312 pci_unmap_len_set(lrg_buf_cb
, maplen
,
313 qdev
->lrg_buffer_len
-
318 qdev
->lrg_buf_free_count
++;
321 static struct ql_rcv_buf_cb
*ql_get_from_lrg_buf_free_list(struct ql3_adapter
324 struct ql_rcv_buf_cb
*lrg_buf_cb
;
326 if ((lrg_buf_cb
= qdev
->lrg_buf_free_head
) != NULL
) {
327 if ((qdev
->lrg_buf_free_head
= lrg_buf_cb
->next
) == NULL
)
328 qdev
->lrg_buf_free_tail
= NULL
;
329 qdev
->lrg_buf_free_count
--;
335 static u32 addrBits
= EEPROM_NO_ADDR_BITS
;
336 static u32 dataBits
= EEPROM_NO_DATA_BITS
;
338 static void fm93c56a_deselect(struct ql3_adapter
*qdev
);
339 static void eeprom_readword(struct ql3_adapter
*qdev
, u32 eepromAddr
,
340 unsigned short *value
);
343 * Caller holds hw_lock.
345 static void fm93c56a_select(struct ql3_adapter
*qdev
)
347 struct ql3xxx_port_registers __iomem
*port_regs
=
348 qdev
->mem_map_registers
;
350 qdev
->eeprom_cmd_data
= AUBURN_EEPROM_CS_1
;
351 ql_write_nvram_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
352 ISP_NVRAM_MASK
| qdev
->eeprom_cmd_data
);
353 ql_write_nvram_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
354 ((ISP_NVRAM_MASK
<< 16) | qdev
->eeprom_cmd_data
));
358 * Caller holds hw_lock.
360 static void fm93c56a_cmd(struct ql3_adapter
*qdev
, u32 cmd
, u32 eepromAddr
)
366 struct ql3xxx_port_registers __iomem
*port_regs
=
367 qdev
->mem_map_registers
;
369 /* Clock in a zero, then do the start bit */
370 ql_write_nvram_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
371 ISP_NVRAM_MASK
| qdev
->eeprom_cmd_data
|
373 ql_write_nvram_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
374 ISP_NVRAM_MASK
| qdev
->
375 eeprom_cmd_data
| AUBURN_EEPROM_DO_1
|
376 AUBURN_EEPROM_CLK_RISE
);
377 ql_write_nvram_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
378 ISP_NVRAM_MASK
| qdev
->
379 eeprom_cmd_data
| AUBURN_EEPROM_DO_1
|
380 AUBURN_EEPROM_CLK_FALL
);
382 mask
= 1 << (FM93C56A_CMD_BITS
- 1);
383 /* Force the previous data bit to be different */
384 previousBit
= 0xffff;
385 for (i
= 0; i
< FM93C56A_CMD_BITS
; i
++) {
387 (cmd
& mask
) ? AUBURN_EEPROM_DO_1
: AUBURN_EEPROM_DO_0
;
388 if (previousBit
!= dataBit
) {
390 * If the bit changed, then change the DO state to
393 ql_write_nvram_reg(qdev
,
394 &port_regs
->CommonRegs
.
395 serialPortInterfaceReg
,
396 ISP_NVRAM_MASK
| qdev
->
397 eeprom_cmd_data
| dataBit
);
398 previousBit
= dataBit
;
400 ql_write_nvram_reg(qdev
,
401 &port_regs
->CommonRegs
.
402 serialPortInterfaceReg
,
403 ISP_NVRAM_MASK
| qdev
->
404 eeprom_cmd_data
| dataBit
|
405 AUBURN_EEPROM_CLK_RISE
);
406 ql_write_nvram_reg(qdev
,
407 &port_regs
->CommonRegs
.
408 serialPortInterfaceReg
,
409 ISP_NVRAM_MASK
| qdev
->
410 eeprom_cmd_data
| dataBit
|
411 AUBURN_EEPROM_CLK_FALL
);
415 mask
= 1 << (addrBits
- 1);
416 /* Force the previous data bit to be different */
417 previousBit
= 0xffff;
418 for (i
= 0; i
< addrBits
; i
++) {
420 (eepromAddr
& mask
) ? AUBURN_EEPROM_DO_1
:
422 if (previousBit
!= dataBit
) {
424 * If the bit changed, then change the DO state to
427 ql_write_nvram_reg(qdev
,
428 &port_regs
->CommonRegs
.
429 serialPortInterfaceReg
,
430 ISP_NVRAM_MASK
| qdev
->
431 eeprom_cmd_data
| dataBit
);
432 previousBit
= dataBit
;
434 ql_write_nvram_reg(qdev
,
435 &port_regs
->CommonRegs
.
436 serialPortInterfaceReg
,
437 ISP_NVRAM_MASK
| qdev
->
438 eeprom_cmd_data
| dataBit
|
439 AUBURN_EEPROM_CLK_RISE
);
440 ql_write_nvram_reg(qdev
,
441 &port_regs
->CommonRegs
.
442 serialPortInterfaceReg
,
443 ISP_NVRAM_MASK
| qdev
->
444 eeprom_cmd_data
| dataBit
|
445 AUBURN_EEPROM_CLK_FALL
);
446 eepromAddr
= eepromAddr
<< 1;
451 * Caller holds hw_lock.
453 static void fm93c56a_deselect(struct ql3_adapter
*qdev
)
455 struct ql3xxx_port_registers __iomem
*port_regs
=
456 qdev
->mem_map_registers
;
457 qdev
->eeprom_cmd_data
= AUBURN_EEPROM_CS_0
;
458 ql_write_nvram_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
459 ISP_NVRAM_MASK
| qdev
->eeprom_cmd_data
);
463 * Caller holds hw_lock.
465 static void fm93c56a_datain(struct ql3_adapter
*qdev
, unsigned short *value
)
470 struct ql3xxx_port_registers __iomem
*port_regs
=
471 qdev
->mem_map_registers
;
473 /* Read the data bits */
474 /* The first bit is a dummy. Clock right over it. */
475 for (i
= 0; i
< dataBits
; i
++) {
476 ql_write_nvram_reg(qdev
,
477 &port_regs
->CommonRegs
.
478 serialPortInterfaceReg
,
479 ISP_NVRAM_MASK
| qdev
->eeprom_cmd_data
|
480 AUBURN_EEPROM_CLK_RISE
);
481 ql_write_nvram_reg(qdev
,
482 &port_regs
->CommonRegs
.
483 serialPortInterfaceReg
,
484 ISP_NVRAM_MASK
| qdev
->eeprom_cmd_data
|
485 AUBURN_EEPROM_CLK_FALL
);
489 &port_regs
->CommonRegs
.
490 serialPortInterfaceReg
) & AUBURN_EEPROM_DI_1
) ? 1 : 0;
491 data
= (data
<< 1) | dataBit
;
497 * Caller holds hw_lock.
499 static void eeprom_readword(struct ql3_adapter
*qdev
,
500 u32 eepromAddr
, unsigned short *value
)
502 fm93c56a_select(qdev
);
503 fm93c56a_cmd(qdev
, (int)FM93C56A_READ
, eepromAddr
);
504 fm93c56a_datain(qdev
, value
);
505 fm93c56a_deselect(qdev
);
508 static void ql_swap_mac_addr(u8
* macAddress
)
512 temp
= macAddress
[0];
513 macAddress
[0] = macAddress
[1];
514 macAddress
[1] = temp
;
515 temp
= macAddress
[2];
516 macAddress
[2] = macAddress
[3];
517 macAddress
[3] = temp
;
518 temp
= macAddress
[4];
519 macAddress
[4] = macAddress
[5];
520 macAddress
[5] = temp
;
524 static int ql_get_nvram_params(struct ql3_adapter
*qdev
)
529 unsigned long hw_flags
;
531 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
533 pEEPROMData
= (u16
*) & qdev
->nvram_data
;
534 qdev
->eeprom_cmd_data
= 0;
535 if(ql_sem_spinlock(qdev
, QL_NVRAM_SEM_MASK
,
536 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
538 printk(KERN_ERR PFX
"%s: Failed ql_sem_spinlock().\n",
540 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
544 for (index
= 0; index
< EEPROM_SIZE
; index
++) {
545 eeprom_readword(qdev
, index
, pEEPROMData
);
546 checksum
+= *pEEPROMData
;
549 ql_sem_unlock(qdev
, QL_NVRAM_SEM_MASK
);
552 printk(KERN_ERR PFX
"%s: checksum should be zero, is %x!!\n",
553 qdev
->ndev
->name
, checksum
);
554 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
559 * We have a problem with endianness for the MAC addresses
560 * and the two 8-bit values version, and numPorts. We
561 * have to swap them on big endian systems.
563 ql_swap_mac_addr(qdev
->nvram_data
.funcCfg_fn0
.macAddress
);
564 ql_swap_mac_addr(qdev
->nvram_data
.funcCfg_fn1
.macAddress
);
565 ql_swap_mac_addr(qdev
->nvram_data
.funcCfg_fn2
.macAddress
);
566 ql_swap_mac_addr(qdev
->nvram_data
.funcCfg_fn3
.macAddress
);
567 pEEPROMData
= (u16
*) & qdev
->nvram_data
.version
;
568 *pEEPROMData
= le16_to_cpu(*pEEPROMData
);
570 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
574 static const u32 PHYAddr
[2] = {
575 PORT0_PHY_ADDRESS
, PORT1_PHY_ADDRESS
578 static int ql_wait_for_mii_ready(struct ql3_adapter
*qdev
)
580 struct ql3xxx_port_registers __iomem
*port_regs
=
581 qdev
->mem_map_registers
;
586 temp
= ql_read_page0_reg(qdev
, &port_regs
->macMIIStatusReg
);
587 if (!(temp
& MAC_MII_STATUS_BSY
))
595 static void ql_mii_enable_scan_mode(struct ql3_adapter
*qdev
)
597 struct ql3xxx_port_registers __iomem
*port_regs
=
598 qdev
->mem_map_registers
;
601 if (qdev
->numPorts
> 1) {
602 /* Auto scan will cycle through multiple ports */
603 scanControl
= MAC_MII_CONTROL_AS
| MAC_MII_CONTROL_SC
;
605 scanControl
= MAC_MII_CONTROL_SC
;
609 * Scan register 1 of PHY/PETBI,
610 * Set up to scan both devices
611 * The autoscan starts from the first register, completes
612 * the last one before rolling over to the first
614 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtAddrReg
,
615 PHYAddr
[0] | MII_SCAN_REGISTER
);
617 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
,
619 ((MAC_MII_CONTROL_SC
| MAC_MII_CONTROL_AS
) << 16));
622 static u8
ql_mii_disable_scan_mode(struct ql3_adapter
*qdev
)
625 struct ql3xxx_port_registers __iomem
*port_regs
=
626 qdev
->mem_map_registers
;
628 /* See if scan mode is enabled before we turn it off */
629 if (ql_read_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
) &
630 (MAC_MII_CONTROL_AS
| MAC_MII_CONTROL_SC
)) {
631 /* Scan is enabled */
634 /* Scan is disabled */
639 * When disabling scan mode you must first change the MII register
642 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtAddrReg
,
643 PHYAddr
[0] | MII_SCAN_REGISTER
);
645 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
,
646 ((MAC_MII_CONTROL_SC
| MAC_MII_CONTROL_AS
|
647 MAC_MII_CONTROL_RC
) << 16));
652 static int ql_mii_write_reg_ex(struct ql3_adapter
*qdev
,
653 u16 regAddr
, u16 value
, u32 mac_index
)
655 struct ql3xxx_port_registers __iomem
*port_regs
=
656 qdev
->mem_map_registers
;
659 scanWasEnabled
= ql_mii_disable_scan_mode(qdev
);
661 if (ql_wait_for_mii_ready(qdev
)) {
662 if (netif_msg_link(qdev
))
663 printk(KERN_WARNING PFX
664 "%s Timed out waiting for management port to "
665 "get free before issuing command.\n",
670 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtAddrReg
,
671 PHYAddr
[mac_index
] | regAddr
);
673 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtDataReg
, value
);
675 /* Wait for write to complete 9/10/04 SJP */
676 if (ql_wait_for_mii_ready(qdev
)) {
677 if (netif_msg_link(qdev
))
678 printk(KERN_WARNING PFX
679 "%s: Timed out waiting for management port to"
680 "get free before issuing command.\n",
686 ql_mii_enable_scan_mode(qdev
);
691 static int ql_mii_read_reg_ex(struct ql3_adapter
*qdev
, u16 regAddr
,
692 u16
* value
, u32 mac_index
)
694 struct ql3xxx_port_registers __iomem
*port_regs
=
695 qdev
->mem_map_registers
;
699 scanWasEnabled
= ql_mii_disable_scan_mode(qdev
);
701 if (ql_wait_for_mii_ready(qdev
)) {
702 if (netif_msg_link(qdev
))
703 printk(KERN_WARNING PFX
704 "%s: Timed out waiting for management port to "
705 "get free before issuing command.\n",
710 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtAddrReg
,
711 PHYAddr
[mac_index
] | regAddr
);
713 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
,
714 (MAC_MII_CONTROL_RC
<< 16));
716 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
,
717 (MAC_MII_CONTROL_RC
<< 16) | MAC_MII_CONTROL_RC
);
719 /* Wait for the read to complete */
720 if (ql_wait_for_mii_ready(qdev
)) {
721 if (netif_msg_link(qdev
))
722 printk(KERN_WARNING PFX
723 "%s: Timed out waiting for management port to "
724 "get free after issuing command.\n",
729 temp
= ql_read_page0_reg(qdev
, &port_regs
->macMIIMgmtDataReg
);
733 ql_mii_enable_scan_mode(qdev
);
738 static int ql_mii_write_reg(struct ql3_adapter
*qdev
, u16 regAddr
, u16 value
)
740 struct ql3xxx_port_registers __iomem
*port_regs
=
741 qdev
->mem_map_registers
;
743 ql_mii_disable_scan_mode(qdev
);
745 if (ql_wait_for_mii_ready(qdev
)) {
746 if (netif_msg_link(qdev
))
747 printk(KERN_WARNING PFX
748 "%s: Timed out waiting for management port to "
749 "get free before issuing command.\n",
754 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtAddrReg
,
755 qdev
->PHYAddr
| regAddr
);
757 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtDataReg
, value
);
759 /* Wait for write to complete. */
760 if (ql_wait_for_mii_ready(qdev
)) {
761 if (netif_msg_link(qdev
))
762 printk(KERN_WARNING PFX
763 "%s: Timed out waiting for management port to "
764 "get free before issuing command.\n",
769 ql_mii_enable_scan_mode(qdev
);
774 static int ql_mii_read_reg(struct ql3_adapter
*qdev
, u16 regAddr
, u16
*value
)
777 struct ql3xxx_port_registers __iomem
*port_regs
=
778 qdev
->mem_map_registers
;
780 ql_mii_disable_scan_mode(qdev
);
782 if (ql_wait_for_mii_ready(qdev
)) {
783 if (netif_msg_link(qdev
))
784 printk(KERN_WARNING PFX
785 "%s: Timed out waiting for management port to "
786 "get free before issuing command.\n",
791 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtAddrReg
,
792 qdev
->PHYAddr
| regAddr
);
794 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
,
795 (MAC_MII_CONTROL_RC
<< 16));
797 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
,
798 (MAC_MII_CONTROL_RC
<< 16) | MAC_MII_CONTROL_RC
);
800 /* Wait for the read to complete */
801 if (ql_wait_for_mii_ready(qdev
)) {
802 if (netif_msg_link(qdev
))
803 printk(KERN_WARNING PFX
804 "%s: Timed out waiting for management port to "
805 "get free before issuing command.\n",
810 temp
= ql_read_page0_reg(qdev
, &port_regs
->macMIIMgmtDataReg
);
813 ql_mii_enable_scan_mode(qdev
);
818 static void ql_petbi_reset(struct ql3_adapter
*qdev
)
820 ql_mii_write_reg(qdev
, PETBI_CONTROL_REG
, PETBI_CTRL_SOFT_RESET
);
823 static void ql_petbi_start_neg(struct ql3_adapter
*qdev
)
827 /* Enable Auto-negotiation sense */
828 ql_mii_read_reg(qdev
, PETBI_TBI_CTRL
, ®
);
829 reg
|= PETBI_TBI_AUTO_SENSE
;
830 ql_mii_write_reg(qdev
, PETBI_TBI_CTRL
, reg
);
832 ql_mii_write_reg(qdev
, PETBI_NEG_ADVER
,
833 PETBI_NEG_PAUSE
| PETBI_NEG_DUPLEX
);
835 ql_mii_write_reg(qdev
, PETBI_CONTROL_REG
,
836 PETBI_CTRL_AUTO_NEG
| PETBI_CTRL_RESTART_NEG
|
837 PETBI_CTRL_FULL_DUPLEX
| PETBI_CTRL_SPEED_1000
);
841 static void ql_petbi_reset_ex(struct ql3_adapter
*qdev
, u32 mac_index
)
843 ql_mii_write_reg_ex(qdev
, PETBI_CONTROL_REG
, PETBI_CTRL_SOFT_RESET
,
847 static void ql_petbi_start_neg_ex(struct ql3_adapter
*qdev
, u32 mac_index
)
851 /* Enable Auto-negotiation sense */
852 ql_mii_read_reg_ex(qdev
, PETBI_TBI_CTRL
, ®
, mac_index
);
853 reg
|= PETBI_TBI_AUTO_SENSE
;
854 ql_mii_write_reg_ex(qdev
, PETBI_TBI_CTRL
, reg
, mac_index
);
856 ql_mii_write_reg_ex(qdev
, PETBI_NEG_ADVER
,
857 PETBI_NEG_PAUSE
| PETBI_NEG_DUPLEX
, mac_index
);
859 ql_mii_write_reg_ex(qdev
, PETBI_CONTROL_REG
,
860 PETBI_CTRL_AUTO_NEG
| PETBI_CTRL_RESTART_NEG
|
861 PETBI_CTRL_FULL_DUPLEX
| PETBI_CTRL_SPEED_1000
,
865 static void ql_petbi_init(struct ql3_adapter
*qdev
)
867 ql_petbi_reset(qdev
);
868 ql_petbi_start_neg(qdev
);
871 static void ql_petbi_init_ex(struct ql3_adapter
*qdev
, u32 mac_index
)
873 ql_petbi_reset_ex(qdev
, mac_index
);
874 ql_petbi_start_neg_ex(qdev
, mac_index
);
877 static int ql_is_petbi_neg_pause(struct ql3_adapter
*qdev
)
881 if (ql_mii_read_reg(qdev
, PETBI_NEG_PARTNER
, ®
) < 0)
884 return (reg
& PETBI_NEG_PAUSE_MASK
) == PETBI_NEG_PAUSE
;
887 static int ql_phy_get_speed(struct ql3_adapter
*qdev
)
891 if (ql_mii_read_reg(qdev
, AUX_CONTROL_STATUS
, ®
) < 0)
894 reg
= (((reg
& 0x18) >> 3) & 3);
906 static int ql_is_full_dup(struct ql3_adapter
*qdev
)
910 if (ql_mii_read_reg(qdev
, AUX_CONTROL_STATUS
, ®
) < 0)
913 return (reg
& PHY_AUX_DUPLEX_STAT
) != 0;
916 static int ql_is_phy_neg_pause(struct ql3_adapter
*qdev
)
920 if (ql_mii_read_reg(qdev
, PHY_NEG_PARTNER
, ®
) < 0)
923 return (reg
& PHY_NEG_PAUSE
) != 0;
927 * Caller holds hw_lock.
929 static void ql_mac_enable(struct ql3_adapter
*qdev
, u32 enable
)
931 struct ql3xxx_port_registers __iomem
*port_regs
=
932 qdev
->mem_map_registers
;
936 value
= (MAC_CONFIG_REG_PE
| (MAC_CONFIG_REG_PE
<< 16));
938 value
= (MAC_CONFIG_REG_PE
<< 16);
941 ql_write_page0_reg(qdev
, &port_regs
->mac1ConfigReg
, value
);
943 ql_write_page0_reg(qdev
, &port_regs
->mac0ConfigReg
, value
);
947 * Caller holds hw_lock.
949 static void ql_mac_cfg_soft_reset(struct ql3_adapter
*qdev
, u32 enable
)
951 struct ql3xxx_port_registers __iomem
*port_regs
=
952 qdev
->mem_map_registers
;
956 value
= (MAC_CONFIG_REG_SR
| (MAC_CONFIG_REG_SR
<< 16));
958 value
= (MAC_CONFIG_REG_SR
<< 16);
961 ql_write_page0_reg(qdev
, &port_regs
->mac1ConfigReg
, value
);
963 ql_write_page0_reg(qdev
, &port_regs
->mac0ConfigReg
, value
);
967 * Caller holds hw_lock.
969 static void ql_mac_cfg_gig(struct ql3_adapter
*qdev
, u32 enable
)
971 struct ql3xxx_port_registers __iomem
*port_regs
=
972 qdev
->mem_map_registers
;
976 value
= (MAC_CONFIG_REG_GM
| (MAC_CONFIG_REG_GM
<< 16));
978 value
= (MAC_CONFIG_REG_GM
<< 16);
981 ql_write_page0_reg(qdev
, &port_regs
->mac1ConfigReg
, value
);
983 ql_write_page0_reg(qdev
, &port_regs
->mac0ConfigReg
, value
);
987 * Caller holds hw_lock.
989 static void ql_mac_cfg_full_dup(struct ql3_adapter
*qdev
, u32 enable
)
991 struct ql3xxx_port_registers __iomem
*port_regs
=
992 qdev
->mem_map_registers
;
996 value
= (MAC_CONFIG_REG_FD
| (MAC_CONFIG_REG_FD
<< 16));
998 value
= (MAC_CONFIG_REG_FD
<< 16);
1000 if (qdev
->mac_index
)
1001 ql_write_page0_reg(qdev
, &port_regs
->mac1ConfigReg
, value
);
1003 ql_write_page0_reg(qdev
, &port_regs
->mac0ConfigReg
, value
);
1007 * Caller holds hw_lock.
1009 static void ql_mac_cfg_pause(struct ql3_adapter
*qdev
, u32 enable
)
1011 struct ql3xxx_port_registers __iomem
*port_regs
=
1012 qdev
->mem_map_registers
;
1017 ((MAC_CONFIG_REG_TF
| MAC_CONFIG_REG_RF
) |
1018 ((MAC_CONFIG_REG_TF
| MAC_CONFIG_REG_RF
) << 16));
1020 value
= ((MAC_CONFIG_REG_TF
| MAC_CONFIG_REG_RF
) << 16);
1022 if (qdev
->mac_index
)
1023 ql_write_page0_reg(qdev
, &port_regs
->mac1ConfigReg
, value
);
1025 ql_write_page0_reg(qdev
, &port_regs
->mac0ConfigReg
, value
);
1029 * Caller holds hw_lock.
1031 static int ql_is_fiber(struct ql3_adapter
*qdev
)
1033 struct ql3xxx_port_registers __iomem
*port_regs
=
1034 qdev
->mem_map_registers
;
1038 switch (qdev
->mac_index
) {
1040 bitToCheck
= PORT_STATUS_SM0
;
1043 bitToCheck
= PORT_STATUS_SM1
;
1047 temp
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
1048 return (temp
& bitToCheck
) != 0;
1051 static int ql_is_auto_cfg(struct ql3_adapter
*qdev
)
1054 ql_mii_read_reg(qdev
, 0x00, ®
);
1055 return (reg
& 0x1000) != 0;
1059 * Caller holds hw_lock.
1061 static int ql_is_auto_neg_complete(struct ql3_adapter
*qdev
)
1063 struct ql3xxx_port_registers __iomem
*port_regs
=
1064 qdev
->mem_map_registers
;
1068 switch (qdev
->mac_index
) {
1070 bitToCheck
= PORT_STATUS_AC0
;
1073 bitToCheck
= PORT_STATUS_AC1
;
1077 temp
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
1078 if (temp
& bitToCheck
) {
1079 if (netif_msg_link(qdev
))
1080 printk(KERN_INFO PFX
1081 "%s: Auto-Negotiate complete.\n",
1085 if (netif_msg_link(qdev
))
1086 printk(KERN_WARNING PFX
1087 "%s: Auto-Negotiate incomplete.\n",
1094 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1096 static int ql_is_neg_pause(struct ql3_adapter
*qdev
)
1098 if (ql_is_fiber(qdev
))
1099 return ql_is_petbi_neg_pause(qdev
);
1101 return ql_is_phy_neg_pause(qdev
);
1104 static int ql_auto_neg_error(struct ql3_adapter
*qdev
)
1106 struct ql3xxx_port_registers __iomem
*port_regs
=
1107 qdev
->mem_map_registers
;
1111 switch (qdev
->mac_index
) {
1113 bitToCheck
= PORT_STATUS_AE0
;
1116 bitToCheck
= PORT_STATUS_AE1
;
1119 temp
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
1120 return (temp
& bitToCheck
) != 0;
1123 static u32
ql_get_link_speed(struct ql3_adapter
*qdev
)
1125 if (ql_is_fiber(qdev
))
1128 return ql_phy_get_speed(qdev
);
1131 static int ql_is_link_full_dup(struct ql3_adapter
*qdev
)
1133 if (ql_is_fiber(qdev
))
1136 return ql_is_full_dup(qdev
);
1140 * Caller holds hw_lock.
1142 static int ql_link_down_detect(struct ql3_adapter
*qdev
)
1144 struct ql3xxx_port_registers __iomem
*port_regs
=
1145 qdev
->mem_map_registers
;
1149 switch (qdev
->mac_index
) {
1151 bitToCheck
= ISP_CONTROL_LINK_DN_0
;
1154 bitToCheck
= ISP_CONTROL_LINK_DN_1
;
1159 ql_read_common_reg(qdev
, &port_regs
->CommonRegs
.ispControlStatus
);
1160 return (temp
& bitToCheck
) != 0;
1164 * Caller holds hw_lock.
1166 static int ql_link_down_detect_clear(struct ql3_adapter
*qdev
)
1168 struct ql3xxx_port_registers __iomem
*port_regs
=
1169 qdev
->mem_map_registers
;
1171 switch (qdev
->mac_index
) {
1173 ql_write_common_reg(qdev
,
1174 &port_regs
->CommonRegs
.ispControlStatus
,
1175 (ISP_CONTROL_LINK_DN_0
) |
1176 (ISP_CONTROL_LINK_DN_0
<< 16));
1180 ql_write_common_reg(qdev
,
1181 &port_regs
->CommonRegs
.ispControlStatus
,
1182 (ISP_CONTROL_LINK_DN_1
) |
1183 (ISP_CONTROL_LINK_DN_1
<< 16));
1194 * Caller holds hw_lock.
1196 static int ql_this_adapter_controls_port(struct ql3_adapter
*qdev
,
1199 struct ql3xxx_port_registers __iomem
*port_regs
=
1200 qdev
->mem_map_registers
;
1204 switch (mac_index
) {
1206 bitToCheck
= PORT_STATUS_F1_ENABLED
;
1209 bitToCheck
= PORT_STATUS_F3_ENABLED
;
1215 temp
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
1216 if (temp
& bitToCheck
) {
1217 if (netif_msg_link(qdev
))
1218 printk(KERN_DEBUG PFX
1219 "%s: is not link master.\n", qdev
->ndev
->name
);
1222 if (netif_msg_link(qdev
))
1223 printk(KERN_DEBUG PFX
1224 "%s: is link master.\n", qdev
->ndev
->name
);
1229 static void ql_phy_reset_ex(struct ql3_adapter
*qdev
, u32 mac_index
)
1231 ql_mii_write_reg_ex(qdev
, CONTROL_REG
, PHY_CTRL_SOFT_RESET
, mac_index
);
1234 static void ql_phy_start_neg_ex(struct ql3_adapter
*qdev
, u32 mac_index
)
1238 ql_mii_write_reg_ex(qdev
, PHY_NEG_ADVER
,
1239 PHY_NEG_PAUSE
| PHY_NEG_ADV_SPEED
| 1, mac_index
);
1241 ql_mii_read_reg_ex(qdev
, CONTROL_REG
, ®
, mac_index
);
1242 ql_mii_write_reg_ex(qdev
, CONTROL_REG
, reg
| PHY_CTRL_RESTART_NEG
,
1246 static void ql_phy_init_ex(struct ql3_adapter
*qdev
, u32 mac_index
)
1248 ql_phy_reset_ex(qdev
, mac_index
);
1249 ql_phy_start_neg_ex(qdev
, mac_index
);
1253 * Caller holds hw_lock.
1255 static u32
ql_get_link_state(struct ql3_adapter
*qdev
)
1257 struct ql3xxx_port_registers __iomem
*port_regs
=
1258 qdev
->mem_map_registers
;
1260 u32 temp
, linkState
;
1262 switch (qdev
->mac_index
) {
1264 bitToCheck
= PORT_STATUS_UP0
;
1267 bitToCheck
= PORT_STATUS_UP1
;
1270 temp
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
1271 if (temp
& bitToCheck
) {
1274 linkState
= LS_DOWN
;
1275 if (netif_msg_link(qdev
))
1276 printk(KERN_WARNING PFX
1277 "%s: Link is down.\n", qdev
->ndev
->name
);
1282 static int ql_port_start(struct ql3_adapter
*qdev
)
1284 if(ql_sem_spinlock(qdev
, QL_PHY_GIO_SEM_MASK
,
1285 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
1289 if (ql_is_fiber(qdev
)) {
1290 ql_petbi_init(qdev
);
1293 ql_phy_init_ex(qdev
, qdev
->mac_index
);
1296 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
1300 static int ql_finish_auto_neg(struct ql3_adapter
*qdev
)
1303 if(ql_sem_spinlock(qdev
, QL_PHY_GIO_SEM_MASK
,
1304 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
1308 if (!ql_auto_neg_error(qdev
)) {
1309 if (test_bit(QL_LINK_MASTER
,&qdev
->flags
)) {
1310 /* configure the MAC */
1311 if (netif_msg_link(qdev
))
1312 printk(KERN_DEBUG PFX
1313 "%s: Configuring link.\n",
1316 ql_mac_cfg_soft_reset(qdev
, 1);
1317 ql_mac_cfg_gig(qdev
,
1321 ql_mac_cfg_full_dup(qdev
,
1324 ql_mac_cfg_pause(qdev
,
1327 ql_mac_cfg_soft_reset(qdev
, 0);
1329 /* enable the MAC */
1330 if (netif_msg_link(qdev
))
1331 printk(KERN_DEBUG PFX
1332 "%s: Enabling mac.\n",
1335 ql_mac_enable(qdev
, 1);
1338 if (netif_msg_link(qdev
))
1339 printk(KERN_DEBUG PFX
1340 "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1342 qdev
->port_link_state
= LS_UP
;
1343 netif_start_queue(qdev
->ndev
);
1344 netif_carrier_on(qdev
->ndev
);
1345 if (netif_msg_link(qdev
))
1346 printk(KERN_INFO PFX
1347 "%s: Link is up at %d Mbps, %s duplex.\n",
1349 ql_get_link_speed(qdev
),
1350 ql_is_link_full_dup(qdev
)
1353 } else { /* Remote error detected */
1355 if (test_bit(QL_LINK_MASTER
,&qdev
->flags
)) {
1356 if (netif_msg_link(qdev
))
1357 printk(KERN_DEBUG PFX
1358 "%s: Remote error detected. "
1359 "Calling ql_port_start().\n",
1363 * ql_port_start() is shared code and needs
1364 * to lock the PHY on it's own.
1366 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
1367 if(ql_port_start(qdev
)) {/* Restart port */
1373 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
1377 static void ql_link_state_machine(struct ql3_adapter
*qdev
)
1379 u32 curr_link_state
;
1380 unsigned long hw_flags
;
1382 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
1384 curr_link_state
= ql_get_link_state(qdev
);
1386 if (test_bit(QL_RESET_ACTIVE
,&qdev
->flags
)) {
1387 if (netif_msg_link(qdev
))
1388 printk(KERN_INFO PFX
1389 "%s: Reset in progress, skip processing link "
1390 "state.\n", qdev
->ndev
->name
);
1394 switch (qdev
->port_link_state
) {
1396 if (test_bit(QL_LINK_MASTER
,&qdev
->flags
)) {
1397 ql_port_start(qdev
);
1399 qdev
->port_link_state
= LS_DOWN
;
1403 if (netif_msg_link(qdev
))
1404 printk(KERN_DEBUG PFX
1405 "%s: port_link_state = LS_DOWN.\n",
1407 if (curr_link_state
== LS_UP
) {
1408 if (netif_msg_link(qdev
))
1409 printk(KERN_DEBUG PFX
1410 "%s: curr_link_state = LS_UP.\n",
1412 if (ql_is_auto_neg_complete(qdev
))
1413 ql_finish_auto_neg(qdev
);
1415 if (qdev
->port_link_state
== LS_UP
)
1416 ql_link_down_detect_clear(qdev
);
1423 * See if the link is currently down or went down and came
1426 if ((curr_link_state
== LS_DOWN
) || ql_link_down_detect(qdev
)) {
1427 if (netif_msg_link(qdev
))
1428 printk(KERN_INFO PFX
"%s: Link is down.\n",
1430 qdev
->port_link_state
= LS_DOWN
;
1434 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
1438 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1440 static void ql_get_phy_owner(struct ql3_adapter
*qdev
)
1442 if (ql_this_adapter_controls_port(qdev
, qdev
->mac_index
))
1443 set_bit(QL_LINK_MASTER
,&qdev
->flags
);
1445 clear_bit(QL_LINK_MASTER
,&qdev
->flags
);
1449 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1451 static void ql_init_scan_mode(struct ql3_adapter
*qdev
)
1453 ql_mii_enable_scan_mode(qdev
);
1455 if (test_bit(QL_LINK_OPTICAL
,&qdev
->flags
)) {
1456 if (ql_this_adapter_controls_port(qdev
, qdev
->mac_index
))
1457 ql_petbi_init_ex(qdev
, qdev
->mac_index
);
1459 if (ql_this_adapter_controls_port(qdev
, qdev
->mac_index
))
1460 ql_phy_init_ex(qdev
, qdev
->mac_index
);
1465 * MII_Setup needs to be called before taking the PHY out of reset so that the
1466 * management interface clock speed can be set properly. It would be better if
1467 * we had a way to disable MDC until after the PHY is out of reset, but we
1468 * don't have that capability.
1470 static int ql_mii_setup(struct ql3_adapter
*qdev
)
1473 struct ql3xxx_port_registers __iomem
*port_regs
=
1474 qdev
->mem_map_registers
;
1476 if(ql_sem_spinlock(qdev
, QL_PHY_GIO_SEM_MASK
,
1477 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
1481 if (qdev
->device_id
== QL3032_DEVICE_ID
)
1482 ql_write_page0_reg(qdev
,
1483 &port_regs
->macMIIMgmtControlReg
, 0x0f00000);
1485 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1486 reg
= MAC_MII_CONTROL_CLK_SEL_DIV28
;
1488 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
,
1489 reg
| ((MAC_MII_CONTROL_CLK_SEL_MASK
) << 16));
1491 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
1495 static u32
ql_supported_modes(struct ql3_adapter
*qdev
)
1499 if (test_bit(QL_LINK_OPTICAL
,&qdev
->flags
)) {
1500 supported
= SUPPORTED_1000baseT_Full
| SUPPORTED_FIBRE
1501 | SUPPORTED_Autoneg
;
1503 supported
= SUPPORTED_10baseT_Half
1504 | SUPPORTED_10baseT_Full
1505 | SUPPORTED_100baseT_Half
1506 | SUPPORTED_100baseT_Full
1507 | SUPPORTED_1000baseT_Half
1508 | SUPPORTED_1000baseT_Full
1509 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
1515 static int ql_get_auto_cfg_status(struct ql3_adapter
*qdev
)
1518 unsigned long hw_flags
;
1519 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
1520 if(ql_sem_spinlock(qdev
, QL_PHY_GIO_SEM_MASK
,
1521 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
1524 status
= ql_is_auto_cfg(qdev
);
1525 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
1526 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
1530 static u32
ql_get_speed(struct ql3_adapter
*qdev
)
1533 unsigned long hw_flags
;
1534 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
1535 if(ql_sem_spinlock(qdev
, QL_PHY_GIO_SEM_MASK
,
1536 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
1539 status
= ql_get_link_speed(qdev
);
1540 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
1541 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
1545 static int ql_get_full_dup(struct ql3_adapter
*qdev
)
1548 unsigned long hw_flags
;
1549 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
1550 if(ql_sem_spinlock(qdev
, QL_PHY_GIO_SEM_MASK
,
1551 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
1554 status
= ql_is_link_full_dup(qdev
);
1555 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
1556 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
1561 static int ql_get_settings(struct net_device
*ndev
, struct ethtool_cmd
*ecmd
)
1563 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
1565 ecmd
->transceiver
= XCVR_INTERNAL
;
1566 ecmd
->supported
= ql_supported_modes(qdev
);
1568 if (test_bit(QL_LINK_OPTICAL
,&qdev
->flags
)) {
1569 ecmd
->port
= PORT_FIBRE
;
1571 ecmd
->port
= PORT_TP
;
1572 ecmd
->phy_address
= qdev
->PHYAddr
;
1574 ecmd
->advertising
= ql_supported_modes(qdev
);
1575 ecmd
->autoneg
= ql_get_auto_cfg_status(qdev
);
1576 ecmd
->speed
= ql_get_speed(qdev
);
1577 ecmd
->duplex
= ql_get_full_dup(qdev
);
1581 static void ql_get_drvinfo(struct net_device
*ndev
,
1582 struct ethtool_drvinfo
*drvinfo
)
1584 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
1585 strncpy(drvinfo
->driver
, ql3xxx_driver_name
, 32);
1586 strncpy(drvinfo
->version
, ql3xxx_driver_version
, 32);
1587 strncpy(drvinfo
->fw_version
, "N/A", 32);
1588 strncpy(drvinfo
->bus_info
, pci_name(qdev
->pdev
), 32);
1589 drvinfo
->n_stats
= 0;
1590 drvinfo
->testinfo_len
= 0;
1591 drvinfo
->regdump_len
= 0;
1592 drvinfo
->eedump_len
= 0;
1595 static u32
ql_get_msglevel(struct net_device
*ndev
)
1597 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
1598 return qdev
->msg_enable
;
1601 static void ql_set_msglevel(struct net_device
*ndev
, u32 value
)
1603 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
1604 qdev
->msg_enable
= value
;
1607 static const struct ethtool_ops ql3xxx_ethtool_ops
= {
1608 .get_settings
= ql_get_settings
,
1609 .get_drvinfo
= ql_get_drvinfo
,
1610 .get_perm_addr
= ethtool_op_get_perm_addr
,
1611 .get_link
= ethtool_op_get_link
,
1612 .get_msglevel
= ql_get_msglevel
,
1613 .set_msglevel
= ql_set_msglevel
,
1616 static int ql_populate_free_queue(struct ql3_adapter
*qdev
)
1618 struct ql_rcv_buf_cb
*lrg_buf_cb
= qdev
->lrg_buf_free_head
;
1621 while (lrg_buf_cb
) {
1622 if (!lrg_buf_cb
->skb
) {
1623 lrg_buf_cb
->skb
= netdev_alloc_skb(qdev
->ndev
,
1624 qdev
->lrg_buffer_len
);
1625 if (unlikely(!lrg_buf_cb
->skb
)) {
1626 printk(KERN_DEBUG PFX
1627 "%s: Failed netdev_alloc_skb().\n",
1632 * We save some space to copy the ethhdr from
1635 skb_reserve(lrg_buf_cb
->skb
, QL_HEADER_SPACE
);
1636 map
= pci_map_single(qdev
->pdev
,
1637 lrg_buf_cb
->skb
->data
,
1638 qdev
->lrg_buffer_len
-
1640 PCI_DMA_FROMDEVICE
);
1641 lrg_buf_cb
->buf_phy_addr_low
=
1642 cpu_to_le32(LS_64BITS(map
));
1643 lrg_buf_cb
->buf_phy_addr_high
=
1644 cpu_to_le32(MS_64BITS(map
));
1645 pci_unmap_addr_set(lrg_buf_cb
, mapaddr
, map
);
1646 pci_unmap_len_set(lrg_buf_cb
, maplen
,
1647 qdev
->lrg_buffer_len
-
1649 --qdev
->lrg_buf_skb_check
;
1650 if (!qdev
->lrg_buf_skb_check
)
1654 lrg_buf_cb
= lrg_buf_cb
->next
;
1660 * Caller holds hw_lock.
1662 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter
*qdev
)
1664 struct bufq_addr_element
*lrg_buf_q_ele
;
1666 struct ql_rcv_buf_cb
*lrg_buf_cb
;
1667 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
1669 if ((qdev
->lrg_buf_free_count
>= 8)
1670 && (qdev
->lrg_buf_release_cnt
>= 16)) {
1672 if (qdev
->lrg_buf_skb_check
)
1673 if (!ql_populate_free_queue(qdev
))
1676 lrg_buf_q_ele
= qdev
->lrg_buf_next_free
;
1678 while ((qdev
->lrg_buf_release_cnt
>= 16)
1679 && (qdev
->lrg_buf_free_count
>= 8)) {
1681 for (i
= 0; i
< 8; i
++) {
1683 ql_get_from_lrg_buf_free_list(qdev
);
1684 lrg_buf_q_ele
->addr_high
=
1685 lrg_buf_cb
->buf_phy_addr_high
;
1686 lrg_buf_q_ele
->addr_low
=
1687 lrg_buf_cb
->buf_phy_addr_low
;
1690 qdev
->lrg_buf_release_cnt
--;
1693 qdev
->lrg_buf_q_producer_index
++;
1695 if (qdev
->lrg_buf_q_producer_index
== NUM_LBUFQ_ENTRIES
)
1696 qdev
->lrg_buf_q_producer_index
= 0;
1698 if (qdev
->lrg_buf_q_producer_index
==
1699 (NUM_LBUFQ_ENTRIES
- 1)) {
1700 lrg_buf_q_ele
= qdev
->lrg_buf_q_virt_addr
;
1704 qdev
->lrg_buf_next_free
= lrg_buf_q_ele
;
1706 ql_write_common_reg(qdev
,
1707 &port_regs
->CommonRegs
.
1708 rxLargeQProducerIndex
,
1709 qdev
->lrg_buf_q_producer_index
);
1713 static void ql_process_mac_tx_intr(struct ql3_adapter
*qdev
,
1714 struct ob_mac_iocb_rsp
*mac_rsp
)
1716 struct ql_tx_buf_cb
*tx_cb
;
1719 tx_cb
= &qdev
->tx_buf
[mac_rsp
->transaction_id
];
1720 pci_unmap_single(qdev
->pdev
,
1721 pci_unmap_addr(&tx_cb
->map
[0], mapaddr
),
1722 pci_unmap_len(&tx_cb
->map
[0], maplen
),
1725 if (tx_cb
->seg_count
) {
1726 for (i
= 1; i
< tx_cb
->seg_count
; i
++) {
1727 pci_unmap_page(qdev
->pdev
,
1728 pci_unmap_addr(&tx_cb
->map
[i
],
1730 pci_unmap_len(&tx_cb
->map
[i
], maplen
),
1734 qdev
->stats
.tx_packets
++;
1735 qdev
->stats
.tx_bytes
+= tx_cb
->skb
->len
;
1736 dev_kfree_skb_irq(tx_cb
->skb
);
1738 atomic_inc(&qdev
->tx_count
);
1742 * The difference between 3022 and 3032 for inbound completions:
1743 * 3022 uses two buffers per completion. The first buffer contains
1744 * (some) header info, the second the remainder of the headers plus
1745 * the data. For this chip we reserve some space at the top of the
1746 * receive buffer so that the header info in buffer one can be
1747 * prepended to the buffer two. Buffer two is the sent up while
1748 * buffer one is returned to the hardware to be reused.
1749 * 3032 receives all of it's data and headers in one buffer for a
1750 * simpler process. 3032 also supports checksum verification as
1751 * can be seen in ql_process_macip_rx_intr().
1753 static void ql_process_mac_rx_intr(struct ql3_adapter
*qdev
,
1754 struct ib_mac_iocb_rsp
*ib_mac_rsp_ptr
)
1757 u32 lrg_buf_phy_addr_low
= 0;
1758 struct ql_rcv_buf_cb
*lrg_buf_cb1
= NULL
;
1759 struct ql_rcv_buf_cb
*lrg_buf_cb2
= NULL
;
1761 struct sk_buff
*skb
;
1762 u16 length
= le16_to_cpu(ib_mac_rsp_ptr
->length
);
1765 * Get the inbound address list (small buffer).
1767 offset
= qdev
->small_buf_index
* QL_SMALL_BUFFER_SIZE
;
1768 if (++qdev
->small_buf_index
== NUM_SMALL_BUFFERS
)
1769 qdev
->small_buf_index
= 0;
1771 curr_ial_ptr
= (u32
*) (qdev
->small_buf_virt_addr
+ offset
);
1772 qdev
->last_rsp_offset
= qdev
->small_buf_phy_addr_low
+ offset
;
1773 qdev
->small_buf_release_cnt
++;
1775 if (qdev
->device_id
== QL3022_DEVICE_ID
) {
1776 /* start of first buffer (3022 only) */
1777 lrg_buf_phy_addr_low
= le32_to_cpu(*curr_ial_ptr
);
1778 lrg_buf_cb1
= &qdev
->lrg_buf
[qdev
->lrg_buf_index
];
1779 qdev
->lrg_buf_release_cnt
++;
1780 if (++qdev
->lrg_buf_index
== NUM_LARGE_BUFFERS
) {
1781 qdev
->lrg_buf_index
= 0;
1783 curr_ial_ptr
++; /* 64-bit pointers require two incs. */
1787 /* start of second buffer */
1788 lrg_buf_phy_addr_low
= le32_to_cpu(*curr_ial_ptr
);
1789 lrg_buf_cb2
= &qdev
->lrg_buf
[qdev
->lrg_buf_index
];
1792 * Second buffer gets sent up the stack.
1794 qdev
->lrg_buf_release_cnt
++;
1795 if (++qdev
->lrg_buf_index
== NUM_LARGE_BUFFERS
)
1796 qdev
->lrg_buf_index
= 0;
1797 skb
= lrg_buf_cb2
->skb
;
1799 qdev
->stats
.rx_packets
++;
1800 qdev
->stats
.rx_bytes
+= length
;
1802 skb_put(skb
, length
);
1803 pci_unmap_single(qdev
->pdev
,
1804 pci_unmap_addr(lrg_buf_cb2
, mapaddr
),
1805 pci_unmap_len(lrg_buf_cb2
, maplen
),
1806 PCI_DMA_FROMDEVICE
);
1807 prefetch(skb
->data
);
1808 skb
->dev
= qdev
->ndev
;
1809 skb
->ip_summed
= CHECKSUM_NONE
;
1810 skb
->protocol
= eth_type_trans(skb
, qdev
->ndev
);
1812 netif_receive_skb(skb
);
1813 qdev
->ndev
->last_rx
= jiffies
;
1814 lrg_buf_cb2
->skb
= NULL
;
1816 if (qdev
->device_id
== QL3022_DEVICE_ID
)
1817 ql_release_to_lrg_buf_free_list(qdev
, lrg_buf_cb1
);
1818 ql_release_to_lrg_buf_free_list(qdev
, lrg_buf_cb2
);
1821 static void ql_process_macip_rx_intr(struct ql3_adapter
*qdev
,
1822 struct ib_ip_iocb_rsp
*ib_ip_rsp_ptr
)
1825 u32 lrg_buf_phy_addr_low
= 0;
1826 struct ql_rcv_buf_cb
*lrg_buf_cb1
= NULL
;
1827 struct ql_rcv_buf_cb
*lrg_buf_cb2
= NULL
;
1829 struct sk_buff
*skb1
= NULL
, *skb2
;
1830 struct net_device
*ndev
= qdev
->ndev
;
1831 u16 length
= le16_to_cpu(ib_ip_rsp_ptr
->length
);
1835 * Get the inbound address list (small buffer).
1838 offset
= qdev
->small_buf_index
* QL_SMALL_BUFFER_SIZE
;
1839 if (++qdev
->small_buf_index
== NUM_SMALL_BUFFERS
)
1840 qdev
->small_buf_index
= 0;
1841 curr_ial_ptr
= (u32
*) (qdev
->small_buf_virt_addr
+ offset
);
1842 qdev
->last_rsp_offset
= qdev
->small_buf_phy_addr_low
+ offset
;
1843 qdev
->small_buf_release_cnt
++;
1845 if (qdev
->device_id
== QL3022_DEVICE_ID
) {
1846 /* start of first buffer on 3022 */
1847 lrg_buf_phy_addr_low
= le32_to_cpu(*curr_ial_ptr
);
1848 lrg_buf_cb1
= &qdev
->lrg_buf
[qdev
->lrg_buf_index
];
1849 qdev
->lrg_buf_release_cnt
++;
1850 if (++qdev
->lrg_buf_index
== NUM_LARGE_BUFFERS
)
1851 qdev
->lrg_buf_index
= 0;
1852 skb1
= lrg_buf_cb1
->skb
;
1853 curr_ial_ptr
++; /* 64-bit pointers require two incs. */
1856 if (*((u16
*) skb1
->data
) != 0xFFFF)
1857 size
+= VLAN_ETH_HLEN
- ETH_HLEN
;
1860 /* start of second buffer */
1861 lrg_buf_phy_addr_low
= le32_to_cpu(*curr_ial_ptr
);
1862 lrg_buf_cb2
= &qdev
->lrg_buf
[qdev
->lrg_buf_index
];
1863 skb2
= lrg_buf_cb2
->skb
;
1864 qdev
->lrg_buf_release_cnt
++;
1865 if (++qdev
->lrg_buf_index
== NUM_LARGE_BUFFERS
)
1866 qdev
->lrg_buf_index
= 0;
1868 skb_put(skb2
, length
); /* Just the second buffer length here. */
1869 pci_unmap_single(qdev
->pdev
,
1870 pci_unmap_addr(lrg_buf_cb2
, mapaddr
),
1871 pci_unmap_len(lrg_buf_cb2
, maplen
),
1872 PCI_DMA_FROMDEVICE
);
1873 prefetch(skb2
->data
);
1875 skb2
->ip_summed
= CHECKSUM_NONE
;
1876 if (qdev
->device_id
== QL3022_DEVICE_ID
) {
1878 * Copy the ethhdr from first buffer to second. This
1879 * is necessary for 3022 IP completions.
1881 memcpy(skb_push(skb2
, size
), skb1
->data
+ VLAN_ID_LEN
, size
);
1883 u16 checksum
= le16_to_cpu(ib_ip_rsp_ptr
->checksum
);
1885 (IB_IP_IOCB_RSP_3032_ICE
|
1886 IB_IP_IOCB_RSP_3032_CE
|
1887 IB_IP_IOCB_RSP_3032_NUC
)) {
1889 "%s: Bad checksum for this %s packet, checksum = %x.\n",
1892 IB_IP_IOCB_RSP_3032_TCP
) ? "TCP" :
1894 } else if (checksum
& IB_IP_IOCB_RSP_3032_TCP
) {
1895 skb2
->ip_summed
= CHECKSUM_UNNECESSARY
;
1898 skb2
->dev
= qdev
->ndev
;
1899 skb2
->protocol
= eth_type_trans(skb2
, qdev
->ndev
);
1901 netif_receive_skb(skb2
);
1902 qdev
->stats
.rx_packets
++;
1903 qdev
->stats
.rx_bytes
+= length
;
1904 ndev
->last_rx
= jiffies
;
1905 lrg_buf_cb2
->skb
= NULL
;
1907 if (qdev
->device_id
== QL3022_DEVICE_ID
)
1908 ql_release_to_lrg_buf_free_list(qdev
, lrg_buf_cb1
);
1909 ql_release_to_lrg_buf_free_list(qdev
, lrg_buf_cb2
);
1912 static int ql_tx_rx_clean(struct ql3_adapter
*qdev
,
1913 int *tx_cleaned
, int *rx_cleaned
, int work_to_do
)
1915 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
1916 struct net_rsp_iocb
*net_rsp
;
1917 struct net_device
*ndev
= qdev
->ndev
;
1918 unsigned long hw_flags
;
1920 /* While there are entries in the completion queue. */
1921 while ((cpu_to_le32(*(qdev
->prsp_producer_index
)) !=
1922 qdev
->rsp_consumer_index
) && (*rx_cleaned
< work_to_do
)) {
1924 net_rsp
= qdev
->rsp_current
;
1925 switch (net_rsp
->opcode
) {
1927 case OPCODE_OB_MAC_IOCB_FN0
:
1928 case OPCODE_OB_MAC_IOCB_FN2
:
1929 ql_process_mac_tx_intr(qdev
, (struct ob_mac_iocb_rsp
*)
1934 case OPCODE_IB_MAC_IOCB
:
1935 case OPCODE_IB_3032_MAC_IOCB
:
1936 ql_process_mac_rx_intr(qdev
, (struct ib_mac_iocb_rsp
*)
1941 case OPCODE_IB_IP_IOCB
:
1942 case OPCODE_IB_3032_IP_IOCB
:
1943 ql_process_macip_rx_intr(qdev
, (struct ib_ip_iocb_rsp
*)
1949 u32
*tmp
= (u32
*) net_rsp
;
1951 "%s: Hit default case, not "
1953 " dropping the packet, opcode = "
1955 ndev
->name
, net_rsp
->opcode
);
1957 "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
1958 (unsigned long int)tmp
[0],
1959 (unsigned long int)tmp
[1],
1960 (unsigned long int)tmp
[2],
1961 (unsigned long int)tmp
[3]);
1965 qdev
->rsp_consumer_index
++;
1967 if (qdev
->rsp_consumer_index
== NUM_RSP_Q_ENTRIES
) {
1968 qdev
->rsp_consumer_index
= 0;
1969 qdev
->rsp_current
= qdev
->rsp_q_virt_addr
;
1971 qdev
->rsp_current
++;
1975 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
1977 ql_update_lrg_bufq_prod_index(qdev
);
1979 if (qdev
->small_buf_release_cnt
>= 16) {
1980 while (qdev
->small_buf_release_cnt
>= 16) {
1981 qdev
->small_buf_q_producer_index
++;
1983 if (qdev
->small_buf_q_producer_index
==
1985 qdev
->small_buf_q_producer_index
= 0;
1986 qdev
->small_buf_release_cnt
-= 8;
1989 ql_write_common_reg(qdev
,
1990 &port_regs
->CommonRegs
.
1991 rxSmallQProducerIndex
,
1992 qdev
->small_buf_q_producer_index
);
1995 ql_write_common_reg(qdev
,
1996 &port_regs
->CommonRegs
.rspQConsumerIndex
,
1997 qdev
->rsp_consumer_index
);
1998 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
2000 if (unlikely(netif_queue_stopped(qdev
->ndev
))) {
2001 if (netif_queue_stopped(qdev
->ndev
) &&
2002 (atomic_read(&qdev
->tx_count
) > (NUM_REQ_Q_ENTRIES
/ 4)))
2003 netif_wake_queue(qdev
->ndev
);
2006 return *tx_cleaned
+ *rx_cleaned
;
2009 static int ql_poll(struct net_device
*ndev
, int *budget
)
2011 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
2012 int work_to_do
= min(*budget
, ndev
->quota
);
2013 int rx_cleaned
= 0, tx_cleaned
= 0;
2015 if (!netif_carrier_ok(ndev
))
2018 ql_tx_rx_clean(qdev
, &tx_cleaned
, &rx_cleaned
, work_to_do
);
2019 *budget
-= rx_cleaned
;
2020 ndev
->quota
-= rx_cleaned
;
2022 if ((!tx_cleaned
&& !rx_cleaned
) || !netif_running(ndev
)) {
2024 netif_rx_complete(ndev
);
2025 ql_enable_interrupts(qdev
);
2031 static irqreturn_t
ql3xxx_isr(int irq
, void *dev_id
)
2034 struct net_device
*ndev
= dev_id
;
2035 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
2036 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
2041 port_regs
= qdev
->mem_map_registers
;
2044 ql_read_common_reg_l(qdev
, &port_regs
->CommonRegs
.ispControlStatus
);
2046 if (value
& (ISP_CONTROL_FE
| ISP_CONTROL_RI
)) {
2047 spin_lock(&qdev
->adapter_lock
);
2048 netif_stop_queue(qdev
->ndev
);
2049 netif_carrier_off(qdev
->ndev
);
2050 ql_disable_interrupts(qdev
);
2051 qdev
->port_link_state
= LS_DOWN
;
2052 set_bit(QL_RESET_ACTIVE
,&qdev
->flags
) ;
2054 if (value
& ISP_CONTROL_FE
) {
2059 ql_read_page0_reg_l(qdev
,
2060 &port_regs
->PortFatalErrStatus
);
2061 printk(KERN_WARNING PFX
2062 "%s: Resetting chip. PortFatalErrStatus "
2063 "register = 0x%x\n", ndev
->name
, var
);
2064 set_bit(QL_RESET_START
,&qdev
->flags
) ;
2067 * Soft Reset Requested.
2069 set_bit(QL_RESET_PER_SCSI
,&qdev
->flags
) ;
2071 "%s: Another function issued a reset to the "
2072 "chip. ISR value = %x.\n", ndev
->name
, value
);
2074 queue_delayed_work(qdev
->workqueue
, &qdev
->reset_work
, 0);
2075 spin_unlock(&qdev
->adapter_lock
);
2076 } else if (value
& ISP_IMR_DISABLE_CMPL_INT
) {
2077 ql_disable_interrupts(qdev
);
2078 if (likely(netif_rx_schedule_prep(ndev
)))
2079 __netif_rx_schedule(ndev
);
2081 ql_enable_interrupts(qdev
);
2086 return IRQ_RETVAL(handled
);
2090 * Get the total number of segments needed for the
2091 * given number of fragments. This is necessary because
2092 * outbound address lists (OAL) will be used when more than
2093 * two frags are given. Each address list has 5 addr/len
2094 * pairs. The 5th pair in each AOL is used to point to
2095 * the next AOL if more frags are coming.
2096 * That is why the frags:segment count ratio is not linear.
2098 static int ql_get_seg_count(unsigned short frags
)
2101 case 0: return 1; /* just the skb->data seg */
2102 case 1: return 2; /* skb->data + 1 frag */
2103 case 2: return 3; /* skb->data + 2 frags */
2104 case 3: return 5; /* skb->data + 1 frag + 1 AOL containting 2 frags */
2124 static void ql_hw_csum_setup(struct sk_buff
*skb
,
2125 struct ob_mac_iocb_req
*mac_iocb_ptr
)
2128 struct iphdr
*ip
= NULL
;
2129 u8 offset
= ETH_HLEN
;
2131 eth
= (struct ethhdr
*)(skb
->data
);
2133 if (eth
->h_proto
== __constant_htons(ETH_P_IP
)) {
2134 ip
= (struct iphdr
*)&skb
->data
[ETH_HLEN
];
2135 } else if (eth
->h_proto
== htons(ETH_P_8021Q
) &&
2136 ((struct vlan_ethhdr
*)skb
->data
)->
2137 h_vlan_encapsulated_proto
== __constant_htons(ETH_P_IP
)) {
2138 ip
= (struct iphdr
*)&skb
->data
[VLAN_ETH_HLEN
];
2139 offset
= VLAN_ETH_HLEN
;
2143 if (ip
->protocol
== IPPROTO_TCP
) {
2144 mac_iocb_ptr
->flags1
|= OB_3032MAC_IOCB_REQ_TC
;
2145 mac_iocb_ptr
->ip_hdr_off
= offset
;
2146 mac_iocb_ptr
->ip_hdr_len
= ip
->ihl
;
2147 } else if (ip
->protocol
== IPPROTO_UDP
) {
2148 mac_iocb_ptr
->flags1
|= OB_3032MAC_IOCB_REQ_UC
;
2149 mac_iocb_ptr
->ip_hdr_off
= offset
;
2150 mac_iocb_ptr
->ip_hdr_len
= ip
->ihl
;
2156 * The difference between 3022 and 3032 sends:
2157 * 3022 only supports a simple single segment transmission.
2158 * 3032 supports checksumming and scatter/gather lists (fragments).
2159 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2160 * in the IOCB plus a chain of outbound address lists (OAL) that
2161 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2162 * will used to point to an OAL when more ALP entries are required.
2163 * The IOCB is always the top of the chain followed by one or more
2164 * OALs (when necessary).
2166 static int ql3xxx_send(struct sk_buff
*skb
, struct net_device
*ndev
)
2168 struct ql3_adapter
*qdev
= (struct ql3_adapter
*)netdev_priv(ndev
);
2169 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
2170 struct ql_tx_buf_cb
*tx_cb
;
2171 u32 tot_len
= skb
->len
;
2173 struct oal_entry
*oal_entry
;
2175 struct ob_mac_iocb_req
*mac_iocb_ptr
;
2177 int seg_cnt
, seg
= 0;
2178 int frag_cnt
= (int)skb_shinfo(skb
)->nr_frags
;
2180 if (unlikely(atomic_read(&qdev
->tx_count
) < 2)) {
2181 if (!netif_queue_stopped(ndev
))
2182 netif_stop_queue(ndev
);
2183 return NETDEV_TX_BUSY
;
2185 tx_cb
= &qdev
->tx_buf
[qdev
->req_producer_index
] ;
2186 seg_cnt
= tx_cb
->seg_count
= ql_get_seg_count((skb_shinfo(skb
)->nr_frags
));
2188 printk(KERN_ERR PFX
"%s: invalid segment count!\n",__func__
);
2189 return NETDEV_TX_OK
;
2192 mac_iocb_ptr
= tx_cb
->queue_entry
;
2193 mac_iocb_ptr
->opcode
= qdev
->mac_ob_opcode
;
2194 mac_iocb_ptr
->flags
|= qdev
->mb_bit_mask
;
2195 mac_iocb_ptr
->transaction_id
= qdev
->req_producer_index
;
2196 mac_iocb_ptr
->data_len
= cpu_to_le16((u16
) tot_len
);
2198 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
2199 ql_hw_csum_setup(skb
, mac_iocb_ptr
);
2200 len
= skb_headlen(skb
);
2201 map
= pci_map_single(qdev
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
2202 oal_entry
= (struct oal_entry
*)&mac_iocb_ptr
->buf_addr0_low
;
2203 oal_entry
->dma_lo
= cpu_to_le32(LS_64BITS(map
));
2204 oal_entry
->dma_hi
= cpu_to_le32(MS_64BITS(map
));
2205 oal_entry
->len
= cpu_to_le32(len
);
2206 pci_unmap_addr_set(&tx_cb
->map
[seg
], mapaddr
, map
);
2207 pci_unmap_len_set(&tx_cb
->map
[seg
], maplen
, len
);
2210 if (!skb_shinfo(skb
)->nr_frags
) {
2211 /* Terminate the last segment. */
2213 cpu_to_le32(le32_to_cpu(oal_entry
->len
) | OAL_LAST_ENTRY
);
2217 for (i
=0; i
<frag_cnt
; i
++,seg
++) {
2218 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2220 if ((seg
== 2 && seg_cnt
> 3) || /* Check for continuation */
2221 (seg
== 7 && seg_cnt
> 8) || /* requirements. It's strange */
2222 (seg
== 12 && seg_cnt
> 13) || /* but necessary. */
2223 (seg
== 17 && seg_cnt
> 18)) {
2224 /* Continuation entry points to outbound address list. */
2225 map
= pci_map_single(qdev
->pdev
, oal
,
2228 oal_entry
->dma_lo
= cpu_to_le32(LS_64BITS(map
));
2229 oal_entry
->dma_hi
= cpu_to_le32(MS_64BITS(map
));
2231 cpu_to_le32(sizeof(struct oal
) |
2233 pci_unmap_addr_set(&tx_cb
->map
[seg
], mapaddr
,
2235 pci_unmap_len_set(&tx_cb
->map
[seg
], maplen
,
2237 oal_entry
= (struct oal_entry
*)oal
;
2243 pci_map_page(qdev
->pdev
, frag
->page
,
2244 frag
->page_offset
, frag
->size
,
2246 oal_entry
->dma_lo
= cpu_to_le32(LS_64BITS(map
));
2247 oal_entry
->dma_hi
= cpu_to_le32(MS_64BITS(map
));
2248 oal_entry
->len
= cpu_to_le32(frag
->size
);
2249 pci_unmap_addr_set(&tx_cb
->map
[seg
], mapaddr
, map
);
2250 pci_unmap_len_set(&tx_cb
->map
[seg
], maplen
,
2253 /* Terminate the last segment. */
2255 cpu_to_le32(le32_to_cpu(oal_entry
->len
) | OAL_LAST_ENTRY
);
2258 qdev
->req_producer_index
++;
2259 if (qdev
->req_producer_index
== NUM_REQ_Q_ENTRIES
)
2260 qdev
->req_producer_index
= 0;
2262 ql_write_common_reg_l(qdev
,
2263 &port_regs
->CommonRegs
.reqQProducerIndex
,
2264 qdev
->req_producer_index
);
2266 ndev
->trans_start
= jiffies
;
2267 if (netif_msg_tx_queued(qdev
))
2268 printk(KERN_DEBUG PFX
"%s: tx queued, slot %d, len %d\n",
2269 ndev
->name
, qdev
->req_producer_index
, skb
->len
);
2271 atomic_dec(&qdev
->tx_count
);
2272 return NETDEV_TX_OK
;
2275 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter
*qdev
)
2278 (u32
) (NUM_REQ_Q_ENTRIES
* sizeof(struct ob_mac_iocb_req
));
2280 qdev
->req_q_virt_addr
=
2281 pci_alloc_consistent(qdev
->pdev
,
2282 (size_t) qdev
->req_q_size
,
2283 &qdev
->req_q_phy_addr
);
2285 if ((qdev
->req_q_virt_addr
== NULL
) ||
2286 LS_64BITS(qdev
->req_q_phy_addr
) & (qdev
->req_q_size
- 1)) {
2287 printk(KERN_ERR PFX
"%s: reqQ failed.\n",
2292 qdev
->rsp_q_size
= NUM_RSP_Q_ENTRIES
* sizeof(struct net_rsp_iocb
);
2294 qdev
->rsp_q_virt_addr
=
2295 pci_alloc_consistent(qdev
->pdev
,
2296 (size_t) qdev
->rsp_q_size
,
2297 &qdev
->rsp_q_phy_addr
);
2299 if ((qdev
->rsp_q_virt_addr
== NULL
) ||
2300 LS_64BITS(qdev
->rsp_q_phy_addr
) & (qdev
->rsp_q_size
- 1)) {
2302 "%s: rspQ allocation failed\n",
2304 pci_free_consistent(qdev
->pdev
, (size_t) qdev
->req_q_size
,
2305 qdev
->req_q_virt_addr
,
2306 qdev
->req_q_phy_addr
);
2310 set_bit(QL_ALLOC_REQ_RSP_Q_DONE
,&qdev
->flags
);
2315 static void ql_free_net_req_rsp_queues(struct ql3_adapter
*qdev
)
2317 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE
,&qdev
->flags
)) {
2318 printk(KERN_INFO PFX
2319 "%s: Already done.\n", qdev
->ndev
->name
);
2323 pci_free_consistent(qdev
->pdev
,
2325 qdev
->req_q_virt_addr
, qdev
->req_q_phy_addr
);
2327 qdev
->req_q_virt_addr
= NULL
;
2329 pci_free_consistent(qdev
->pdev
,
2331 qdev
->rsp_q_virt_addr
, qdev
->rsp_q_phy_addr
);
2333 qdev
->rsp_q_virt_addr
= NULL
;
2335 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE
,&qdev
->flags
);
2338 static int ql_alloc_buffer_queues(struct ql3_adapter
*qdev
)
2340 /* Create Large Buffer Queue */
2341 qdev
->lrg_buf_q_size
=
2342 NUM_LBUFQ_ENTRIES
* sizeof(struct lrg_buf_q_entry
);
2343 if (qdev
->lrg_buf_q_size
< PAGE_SIZE
)
2344 qdev
->lrg_buf_q_alloc_size
= PAGE_SIZE
;
2346 qdev
->lrg_buf_q_alloc_size
= qdev
->lrg_buf_q_size
* 2;
2348 qdev
->lrg_buf_q_alloc_virt_addr
=
2349 pci_alloc_consistent(qdev
->pdev
,
2350 qdev
->lrg_buf_q_alloc_size
,
2351 &qdev
->lrg_buf_q_alloc_phy_addr
);
2353 if (qdev
->lrg_buf_q_alloc_virt_addr
== NULL
) {
2355 "%s: lBufQ failed\n", qdev
->ndev
->name
);
2358 qdev
->lrg_buf_q_virt_addr
= qdev
->lrg_buf_q_alloc_virt_addr
;
2359 qdev
->lrg_buf_q_phy_addr
= qdev
->lrg_buf_q_alloc_phy_addr
;
2361 /* Create Small Buffer Queue */
2362 qdev
->small_buf_q_size
=
2363 NUM_SBUFQ_ENTRIES
* sizeof(struct lrg_buf_q_entry
);
2364 if (qdev
->small_buf_q_size
< PAGE_SIZE
)
2365 qdev
->small_buf_q_alloc_size
= PAGE_SIZE
;
2367 qdev
->small_buf_q_alloc_size
= qdev
->small_buf_q_size
* 2;
2369 qdev
->small_buf_q_alloc_virt_addr
=
2370 pci_alloc_consistent(qdev
->pdev
,
2371 qdev
->small_buf_q_alloc_size
,
2372 &qdev
->small_buf_q_alloc_phy_addr
);
2374 if (qdev
->small_buf_q_alloc_virt_addr
== NULL
) {
2376 "%s: Small Buffer Queue allocation failed.\n",
2378 pci_free_consistent(qdev
->pdev
, qdev
->lrg_buf_q_alloc_size
,
2379 qdev
->lrg_buf_q_alloc_virt_addr
,
2380 qdev
->lrg_buf_q_alloc_phy_addr
);
2384 qdev
->small_buf_q_virt_addr
= qdev
->small_buf_q_alloc_virt_addr
;
2385 qdev
->small_buf_q_phy_addr
= qdev
->small_buf_q_alloc_phy_addr
;
2386 set_bit(QL_ALLOC_BUFQS_DONE
,&qdev
->flags
);
2390 static void ql_free_buffer_queues(struct ql3_adapter
*qdev
)
2392 if (!test_bit(QL_ALLOC_BUFQS_DONE
,&qdev
->flags
)) {
2393 printk(KERN_INFO PFX
2394 "%s: Already done.\n", qdev
->ndev
->name
);
2398 pci_free_consistent(qdev
->pdev
,
2399 qdev
->lrg_buf_q_alloc_size
,
2400 qdev
->lrg_buf_q_alloc_virt_addr
,
2401 qdev
->lrg_buf_q_alloc_phy_addr
);
2403 qdev
->lrg_buf_q_virt_addr
= NULL
;
2405 pci_free_consistent(qdev
->pdev
,
2406 qdev
->small_buf_q_alloc_size
,
2407 qdev
->small_buf_q_alloc_virt_addr
,
2408 qdev
->small_buf_q_alloc_phy_addr
);
2410 qdev
->small_buf_q_virt_addr
= NULL
;
2412 clear_bit(QL_ALLOC_BUFQS_DONE
,&qdev
->flags
);
2415 static int ql_alloc_small_buffers(struct ql3_adapter
*qdev
)
2418 struct bufq_addr_element
*small_buf_q_entry
;
2420 /* Currently we allocate on one of memory and use it for smallbuffers */
2421 qdev
->small_buf_total_size
=
2422 (QL_ADDR_ELE_PER_BUFQ_ENTRY
* NUM_SBUFQ_ENTRIES
*
2423 QL_SMALL_BUFFER_SIZE
);
2425 qdev
->small_buf_virt_addr
=
2426 pci_alloc_consistent(qdev
->pdev
,
2427 qdev
->small_buf_total_size
,
2428 &qdev
->small_buf_phy_addr
);
2430 if (qdev
->small_buf_virt_addr
== NULL
) {
2432 "%s: Failed to get small buffer memory.\n",
2437 qdev
->small_buf_phy_addr_low
= LS_64BITS(qdev
->small_buf_phy_addr
);
2438 qdev
->small_buf_phy_addr_high
= MS_64BITS(qdev
->small_buf_phy_addr
);
2440 small_buf_q_entry
= qdev
->small_buf_q_virt_addr
;
2442 qdev
->last_rsp_offset
= qdev
->small_buf_phy_addr_low
;
2444 /* Initialize the small buffer queue. */
2445 for (i
= 0; i
< (QL_ADDR_ELE_PER_BUFQ_ENTRY
* NUM_SBUFQ_ENTRIES
); i
++) {
2446 small_buf_q_entry
->addr_high
=
2447 cpu_to_le32(qdev
->small_buf_phy_addr_high
);
2448 small_buf_q_entry
->addr_low
=
2449 cpu_to_le32(qdev
->small_buf_phy_addr_low
+
2450 (i
* QL_SMALL_BUFFER_SIZE
));
2451 small_buf_q_entry
++;
2453 qdev
->small_buf_index
= 0;
2454 set_bit(QL_ALLOC_SMALL_BUF_DONE
,&qdev
->flags
);
2458 static void ql_free_small_buffers(struct ql3_adapter
*qdev
)
2460 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE
,&qdev
->flags
)) {
2461 printk(KERN_INFO PFX
2462 "%s: Already done.\n", qdev
->ndev
->name
);
2465 if (qdev
->small_buf_virt_addr
!= NULL
) {
2466 pci_free_consistent(qdev
->pdev
,
2467 qdev
->small_buf_total_size
,
2468 qdev
->small_buf_virt_addr
,
2469 qdev
->small_buf_phy_addr
);
2471 qdev
->small_buf_virt_addr
= NULL
;
2475 static void ql_free_large_buffers(struct ql3_adapter
*qdev
)
2478 struct ql_rcv_buf_cb
*lrg_buf_cb
;
2480 for (i
= 0; i
< NUM_LARGE_BUFFERS
; i
++) {
2481 lrg_buf_cb
= &qdev
->lrg_buf
[i
];
2482 if (lrg_buf_cb
->skb
) {
2483 dev_kfree_skb(lrg_buf_cb
->skb
);
2484 pci_unmap_single(qdev
->pdev
,
2485 pci_unmap_addr(lrg_buf_cb
, mapaddr
),
2486 pci_unmap_len(lrg_buf_cb
, maplen
),
2487 PCI_DMA_FROMDEVICE
);
2488 memset(lrg_buf_cb
, 0, sizeof(struct ql_rcv_buf_cb
));
2495 static void ql_init_large_buffers(struct ql3_adapter
*qdev
)
2498 struct ql_rcv_buf_cb
*lrg_buf_cb
;
2499 struct bufq_addr_element
*buf_addr_ele
= qdev
->lrg_buf_q_virt_addr
;
2501 for (i
= 0; i
< NUM_LARGE_BUFFERS
; i
++) {
2502 lrg_buf_cb
= &qdev
->lrg_buf
[i
];
2503 buf_addr_ele
->addr_high
= lrg_buf_cb
->buf_phy_addr_high
;
2504 buf_addr_ele
->addr_low
= lrg_buf_cb
->buf_phy_addr_low
;
2507 qdev
->lrg_buf_index
= 0;
2508 qdev
->lrg_buf_skb_check
= 0;
2511 static int ql_alloc_large_buffers(struct ql3_adapter
*qdev
)
2514 struct ql_rcv_buf_cb
*lrg_buf_cb
;
2515 struct sk_buff
*skb
;
2518 for (i
= 0; i
< NUM_LARGE_BUFFERS
; i
++) {
2519 skb
= netdev_alloc_skb(qdev
->ndev
,
2520 qdev
->lrg_buffer_len
);
2521 if (unlikely(!skb
)) {
2522 /* Better luck next round */
2524 "%s: large buff alloc failed, "
2525 "for %d bytes at index %d.\n",
2527 qdev
->lrg_buffer_len
* 2, i
);
2528 ql_free_large_buffers(qdev
);
2532 lrg_buf_cb
= &qdev
->lrg_buf
[i
];
2533 memset(lrg_buf_cb
, 0, sizeof(struct ql_rcv_buf_cb
));
2534 lrg_buf_cb
->index
= i
;
2535 lrg_buf_cb
->skb
= skb
;
2537 * We save some space to copy the ethhdr from first
2540 skb_reserve(skb
, QL_HEADER_SPACE
);
2541 map
= pci_map_single(qdev
->pdev
,
2543 qdev
->lrg_buffer_len
-
2545 PCI_DMA_FROMDEVICE
);
2546 pci_unmap_addr_set(lrg_buf_cb
, mapaddr
, map
);
2547 pci_unmap_len_set(lrg_buf_cb
, maplen
,
2548 qdev
->lrg_buffer_len
-
2550 lrg_buf_cb
->buf_phy_addr_low
=
2551 cpu_to_le32(LS_64BITS(map
));
2552 lrg_buf_cb
->buf_phy_addr_high
=
2553 cpu_to_le32(MS_64BITS(map
));
2559 static void ql_free_send_free_list(struct ql3_adapter
*qdev
)
2561 struct ql_tx_buf_cb
*tx_cb
;
2564 tx_cb
= &qdev
->tx_buf
[0];
2565 for (i
= 0; i
< NUM_REQ_Q_ENTRIES
; i
++) {
2574 static int ql_create_send_free_list(struct ql3_adapter
*qdev
)
2576 struct ql_tx_buf_cb
*tx_cb
;
2578 struct ob_mac_iocb_req
*req_q_curr
=
2579 qdev
->req_q_virt_addr
;
2581 /* Create free list of transmit buffers */
2582 for (i
= 0; i
< NUM_REQ_Q_ENTRIES
; i
++) {
2584 tx_cb
= &qdev
->tx_buf
[i
];
2586 tx_cb
->queue_entry
= req_q_curr
;
2588 tx_cb
->oal
= kmalloc(512, GFP_KERNEL
);
2589 if (tx_cb
->oal
== NULL
)
2595 static int ql_alloc_mem_resources(struct ql3_adapter
*qdev
)
2597 if (qdev
->ndev
->mtu
== NORMAL_MTU_SIZE
)
2598 qdev
->lrg_buffer_len
= NORMAL_MTU_SIZE
;
2599 else if (qdev
->ndev
->mtu
== JUMBO_MTU_SIZE
) {
2600 qdev
->lrg_buffer_len
= JUMBO_MTU_SIZE
;
2603 "%s: Invalid mtu size. Only 1500 and 9000 are accepted.\n",
2607 qdev
->lrg_buffer_len
+= VLAN_ETH_HLEN
+ VLAN_ID_LEN
+ QL_HEADER_SPACE
;
2608 qdev
->max_frame_size
=
2609 (qdev
->lrg_buffer_len
- QL_HEADER_SPACE
) + ETHERNET_CRC_SIZE
;
2612 * First allocate a page of shared memory and use it for shadow
2613 * locations of Network Request Queue Consumer Address Register and
2614 * Network Completion Queue Producer Index Register
2616 qdev
->shadow_reg_virt_addr
=
2617 pci_alloc_consistent(qdev
->pdev
,
2618 PAGE_SIZE
, &qdev
->shadow_reg_phy_addr
);
2620 if (qdev
->shadow_reg_virt_addr
!= NULL
) {
2621 qdev
->preq_consumer_index
= (u16
*) qdev
->shadow_reg_virt_addr
;
2622 qdev
->req_consumer_index_phy_addr_high
=
2623 MS_64BITS(qdev
->shadow_reg_phy_addr
);
2624 qdev
->req_consumer_index_phy_addr_low
=
2625 LS_64BITS(qdev
->shadow_reg_phy_addr
);
2627 qdev
->prsp_producer_index
=
2628 (u32
*) (((u8
*) qdev
->preq_consumer_index
) + 8);
2629 qdev
->rsp_producer_index_phy_addr_high
=
2630 qdev
->req_consumer_index_phy_addr_high
;
2631 qdev
->rsp_producer_index_phy_addr_low
=
2632 qdev
->req_consumer_index_phy_addr_low
+ 8;
2635 "%s: shadowReg Alloc failed.\n", qdev
->ndev
->name
);
2639 if (ql_alloc_net_req_rsp_queues(qdev
) != 0) {
2641 "%s: ql_alloc_net_req_rsp_queues failed.\n",
2646 if (ql_alloc_buffer_queues(qdev
) != 0) {
2648 "%s: ql_alloc_buffer_queues failed.\n",
2650 goto err_buffer_queues
;
2653 if (ql_alloc_small_buffers(qdev
) != 0) {
2655 "%s: ql_alloc_small_buffers failed\n", qdev
->ndev
->name
);
2656 goto err_small_buffers
;
2659 if (ql_alloc_large_buffers(qdev
) != 0) {
2661 "%s: ql_alloc_large_buffers failed\n", qdev
->ndev
->name
);
2662 goto err_small_buffers
;
2665 /* Initialize the large buffer queue. */
2666 ql_init_large_buffers(qdev
);
2667 if (ql_create_send_free_list(qdev
))
2670 qdev
->rsp_current
= qdev
->rsp_q_virt_addr
;
2674 ql_free_send_free_list(qdev
);
2676 ql_free_buffer_queues(qdev
);
2678 ql_free_net_req_rsp_queues(qdev
);
2680 pci_free_consistent(qdev
->pdev
,
2682 qdev
->shadow_reg_virt_addr
,
2683 qdev
->shadow_reg_phy_addr
);
2688 static void ql_free_mem_resources(struct ql3_adapter
*qdev
)
2690 ql_free_send_free_list(qdev
);
2691 ql_free_large_buffers(qdev
);
2692 ql_free_small_buffers(qdev
);
2693 ql_free_buffer_queues(qdev
);
2694 ql_free_net_req_rsp_queues(qdev
);
2695 if (qdev
->shadow_reg_virt_addr
!= NULL
) {
2696 pci_free_consistent(qdev
->pdev
,
2698 qdev
->shadow_reg_virt_addr
,
2699 qdev
->shadow_reg_phy_addr
);
2700 qdev
->shadow_reg_virt_addr
= NULL
;
2704 static int ql_init_misc_registers(struct ql3_adapter
*qdev
)
2706 struct ql3xxx_local_ram_registers __iomem
*local_ram
=
2707 (void __iomem
*)qdev
->mem_map_registers
;
2709 if(ql_sem_spinlock(qdev
, QL_DDR_RAM_SEM_MASK
,
2710 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
2714 ql_write_page2_reg(qdev
,
2715 &local_ram
->bufletSize
, qdev
->nvram_data
.bufletSize
);
2717 ql_write_page2_reg(qdev
,
2718 &local_ram
->maxBufletCount
,
2719 qdev
->nvram_data
.bufletCount
);
2721 ql_write_page2_reg(qdev
,
2722 &local_ram
->freeBufletThresholdLow
,
2723 (qdev
->nvram_data
.tcpWindowThreshold25
<< 16) |
2724 (qdev
->nvram_data
.tcpWindowThreshold0
));
2726 ql_write_page2_reg(qdev
,
2727 &local_ram
->freeBufletThresholdHigh
,
2728 qdev
->nvram_data
.tcpWindowThreshold50
);
2730 ql_write_page2_reg(qdev
,
2731 &local_ram
->ipHashTableBase
,
2732 (qdev
->nvram_data
.ipHashTableBaseHi
<< 16) |
2733 qdev
->nvram_data
.ipHashTableBaseLo
);
2734 ql_write_page2_reg(qdev
,
2735 &local_ram
->ipHashTableCount
,
2736 qdev
->nvram_data
.ipHashTableSize
);
2737 ql_write_page2_reg(qdev
,
2738 &local_ram
->tcpHashTableBase
,
2739 (qdev
->nvram_data
.tcpHashTableBaseHi
<< 16) |
2740 qdev
->nvram_data
.tcpHashTableBaseLo
);
2741 ql_write_page2_reg(qdev
,
2742 &local_ram
->tcpHashTableCount
,
2743 qdev
->nvram_data
.tcpHashTableSize
);
2744 ql_write_page2_reg(qdev
,
2745 &local_ram
->ncbBase
,
2746 (qdev
->nvram_data
.ncbTableBaseHi
<< 16) |
2747 qdev
->nvram_data
.ncbTableBaseLo
);
2748 ql_write_page2_reg(qdev
,
2749 &local_ram
->maxNcbCount
,
2750 qdev
->nvram_data
.ncbTableSize
);
2751 ql_write_page2_reg(qdev
,
2752 &local_ram
->drbBase
,
2753 (qdev
->nvram_data
.drbTableBaseHi
<< 16) |
2754 qdev
->nvram_data
.drbTableBaseLo
);
2755 ql_write_page2_reg(qdev
,
2756 &local_ram
->maxDrbCount
,
2757 qdev
->nvram_data
.drbTableSize
);
2758 ql_sem_unlock(qdev
, QL_DDR_RAM_SEM_MASK
);
2762 static int ql_adapter_initialize(struct ql3_adapter
*qdev
)
2765 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
2766 struct ql3xxx_host_memory_registers __iomem
*hmem_regs
=
2767 (void __iomem
*)port_regs
;
2771 if(ql_mii_setup(qdev
))
2774 /* Bring out PHY out of reset */
2775 ql_write_common_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
2776 (ISP_SERIAL_PORT_IF_WE
|
2777 (ISP_SERIAL_PORT_IF_WE
<< 16)));
2779 qdev
->port_link_state
= LS_DOWN
;
2780 netif_carrier_off(qdev
->ndev
);
2782 /* V2 chip fix for ARS-39168. */
2783 ql_write_common_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
2784 (ISP_SERIAL_PORT_IF_SDE
|
2785 (ISP_SERIAL_PORT_IF_SDE
<< 16)));
2787 /* Request Queue Registers */
2788 *((u32
*) (qdev
->preq_consumer_index
)) = 0;
2789 atomic_set(&qdev
->tx_count
,NUM_REQ_Q_ENTRIES
);
2790 qdev
->req_producer_index
= 0;
2792 ql_write_page1_reg(qdev
,
2793 &hmem_regs
->reqConsumerIndexAddrHigh
,
2794 qdev
->req_consumer_index_phy_addr_high
);
2795 ql_write_page1_reg(qdev
,
2796 &hmem_regs
->reqConsumerIndexAddrLow
,
2797 qdev
->req_consumer_index_phy_addr_low
);
2799 ql_write_page1_reg(qdev
,
2800 &hmem_regs
->reqBaseAddrHigh
,
2801 MS_64BITS(qdev
->req_q_phy_addr
));
2802 ql_write_page1_reg(qdev
,
2803 &hmem_regs
->reqBaseAddrLow
,
2804 LS_64BITS(qdev
->req_q_phy_addr
));
2805 ql_write_page1_reg(qdev
, &hmem_regs
->reqLength
, NUM_REQ_Q_ENTRIES
);
2807 /* Response Queue Registers */
2808 *((u16
*) (qdev
->prsp_producer_index
)) = 0;
2809 qdev
->rsp_consumer_index
= 0;
2810 qdev
->rsp_current
= qdev
->rsp_q_virt_addr
;
2812 ql_write_page1_reg(qdev
,
2813 &hmem_regs
->rspProducerIndexAddrHigh
,
2814 qdev
->rsp_producer_index_phy_addr_high
);
2816 ql_write_page1_reg(qdev
,
2817 &hmem_regs
->rspProducerIndexAddrLow
,
2818 qdev
->rsp_producer_index_phy_addr_low
);
2820 ql_write_page1_reg(qdev
,
2821 &hmem_regs
->rspBaseAddrHigh
,
2822 MS_64BITS(qdev
->rsp_q_phy_addr
));
2824 ql_write_page1_reg(qdev
,
2825 &hmem_regs
->rspBaseAddrLow
,
2826 LS_64BITS(qdev
->rsp_q_phy_addr
));
2828 ql_write_page1_reg(qdev
, &hmem_regs
->rspLength
, NUM_RSP_Q_ENTRIES
);
2830 /* Large Buffer Queue */
2831 ql_write_page1_reg(qdev
,
2832 &hmem_regs
->rxLargeQBaseAddrHigh
,
2833 MS_64BITS(qdev
->lrg_buf_q_phy_addr
));
2835 ql_write_page1_reg(qdev
,
2836 &hmem_regs
->rxLargeQBaseAddrLow
,
2837 LS_64BITS(qdev
->lrg_buf_q_phy_addr
));
2839 ql_write_page1_reg(qdev
, &hmem_regs
->rxLargeQLength
, NUM_LBUFQ_ENTRIES
);
2841 ql_write_page1_reg(qdev
,
2842 &hmem_regs
->rxLargeBufferLength
,
2843 qdev
->lrg_buffer_len
);
2845 /* Small Buffer Queue */
2846 ql_write_page1_reg(qdev
,
2847 &hmem_regs
->rxSmallQBaseAddrHigh
,
2848 MS_64BITS(qdev
->small_buf_q_phy_addr
));
2850 ql_write_page1_reg(qdev
,
2851 &hmem_regs
->rxSmallQBaseAddrLow
,
2852 LS_64BITS(qdev
->small_buf_q_phy_addr
));
2854 ql_write_page1_reg(qdev
, &hmem_regs
->rxSmallQLength
, NUM_SBUFQ_ENTRIES
);
2855 ql_write_page1_reg(qdev
,
2856 &hmem_regs
->rxSmallBufferLength
,
2857 QL_SMALL_BUFFER_SIZE
);
2859 qdev
->small_buf_q_producer_index
= NUM_SBUFQ_ENTRIES
- 1;
2860 qdev
->small_buf_release_cnt
= 8;
2861 qdev
->lrg_buf_q_producer_index
= NUM_LBUFQ_ENTRIES
- 1;
2862 qdev
->lrg_buf_release_cnt
= 8;
2863 qdev
->lrg_buf_next_free
=
2864 (struct bufq_addr_element
*)qdev
->lrg_buf_q_virt_addr
;
2865 qdev
->small_buf_index
= 0;
2866 qdev
->lrg_buf_index
= 0;
2867 qdev
->lrg_buf_free_count
= 0;
2868 qdev
->lrg_buf_free_head
= NULL
;
2869 qdev
->lrg_buf_free_tail
= NULL
;
2871 ql_write_common_reg(qdev
,
2872 &port_regs
->CommonRegs
.
2873 rxSmallQProducerIndex
,
2874 qdev
->small_buf_q_producer_index
);
2875 ql_write_common_reg(qdev
,
2876 &port_regs
->CommonRegs
.
2877 rxLargeQProducerIndex
,
2878 qdev
->lrg_buf_q_producer_index
);
2881 * Find out if the chip has already been initialized. If it has, then
2882 * we skip some of the initialization.
2884 clear_bit(QL_LINK_MASTER
, &qdev
->flags
);
2885 value
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
2886 if ((value
& PORT_STATUS_IC
) == 0) {
2888 /* Chip has not been configured yet, so let it rip. */
2889 if(ql_init_misc_registers(qdev
)) {
2894 if (qdev
->mac_index
)
2895 ql_write_page0_reg(qdev
,
2896 &port_regs
->mac1MaxFrameLengthReg
,
2897 qdev
->max_frame_size
);
2899 ql_write_page0_reg(qdev
,
2900 &port_regs
->mac0MaxFrameLengthReg
,
2901 qdev
->max_frame_size
);
2903 value
= qdev
->nvram_data
.tcpMaxWindowSize
;
2904 ql_write_page0_reg(qdev
, &port_regs
->tcpMaxWindow
, value
);
2906 value
= (0xFFFF << 16) | qdev
->nvram_data
.extHwConfig
;
2908 if(ql_sem_spinlock(qdev
, QL_FLASH_SEM_MASK
,
2909 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
)
2914 ql_write_page0_reg(qdev
, &port_regs
->ExternalHWConfig
, value
);
2915 ql_write_page0_reg(qdev
, &port_regs
->InternalChipConfig
,
2916 (((INTERNAL_CHIP_SD
| INTERNAL_CHIP_WE
) <<
2917 16) | (INTERNAL_CHIP_SD
|
2918 INTERNAL_CHIP_WE
)));
2919 ql_sem_unlock(qdev
, QL_FLASH_SEM_MASK
);
2923 if(ql_sem_spinlock(qdev
, QL_PHY_GIO_SEM_MASK
,
2924 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
2930 ql_init_scan_mode(qdev
);
2931 ql_get_phy_owner(qdev
);
2933 /* Load the MAC Configuration */
2935 /* Program lower 32 bits of the MAC address */
2936 ql_write_page0_reg(qdev
, &port_regs
->macAddrIndirectPtrReg
,
2937 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK
<< 16));
2938 ql_write_page0_reg(qdev
, &port_regs
->macAddrDataReg
,
2939 ((qdev
->ndev
->dev_addr
[2] << 24)
2940 | (qdev
->ndev
->dev_addr
[3] << 16)
2941 | (qdev
->ndev
->dev_addr
[4] << 8)
2942 | qdev
->ndev
->dev_addr
[5]));
2944 /* Program top 16 bits of the MAC address */
2945 ql_write_page0_reg(qdev
, &port_regs
->macAddrIndirectPtrReg
,
2946 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK
<< 16) | 1));
2947 ql_write_page0_reg(qdev
, &port_regs
->macAddrDataReg
,
2948 ((qdev
->ndev
->dev_addr
[0] << 8)
2949 | qdev
->ndev
->dev_addr
[1]));
2951 /* Enable Primary MAC */
2952 ql_write_page0_reg(qdev
, &port_regs
->macAddrIndirectPtrReg
,
2953 ((MAC_ADDR_INDIRECT_PTR_REG_PE
<< 16) |
2954 MAC_ADDR_INDIRECT_PTR_REG_PE
));
2956 /* Clear Primary and Secondary IP addresses */
2957 ql_write_page0_reg(qdev
, &port_regs
->ipAddrIndexReg
,
2958 ((IP_ADDR_INDEX_REG_MASK
<< 16) |
2959 (qdev
->mac_index
<< 2)));
2960 ql_write_page0_reg(qdev
, &port_regs
->ipAddrDataReg
, 0);
2962 ql_write_page0_reg(qdev
, &port_regs
->ipAddrIndexReg
,
2963 ((IP_ADDR_INDEX_REG_MASK
<< 16) |
2964 ((qdev
->mac_index
<< 2) + 1)));
2965 ql_write_page0_reg(qdev
, &port_regs
->ipAddrDataReg
, 0);
2967 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
2969 /* Indicate Configuration Complete */
2970 ql_write_page0_reg(qdev
,
2971 &port_regs
->portControl
,
2972 ((PORT_CONTROL_CC
<< 16) | PORT_CONTROL_CC
));
2975 value
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
2976 if (value
& PORT_STATUS_IC
)
2983 "%s: Hw Initialization timeout.\n", qdev
->ndev
->name
);
2988 /* Enable Ethernet Function */
2989 if (qdev
->device_id
== QL3032_DEVICE_ID
) {
2991 (QL3032_PORT_CONTROL_EF
| QL3032_PORT_CONTROL_KIE
|
2992 QL3032_PORT_CONTROL_EIv6
| QL3032_PORT_CONTROL_EIv4
);
2993 ql_write_page0_reg(qdev
, &port_regs
->functionControl
,
2994 ((value
<< 16) | value
));
2997 (PORT_CONTROL_EF
| PORT_CONTROL_ET
| PORT_CONTROL_EI
|
2999 ql_write_page0_reg(qdev
, &port_regs
->portControl
,
3000 ((value
<< 16) | value
));
3009 * Caller holds hw_lock.
3011 static int ql_adapter_reset(struct ql3_adapter
*qdev
)
3013 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
3018 set_bit(QL_RESET_ACTIVE
, &qdev
->flags
);
3019 clear_bit(QL_RESET_DONE
, &qdev
->flags
);
3022 * Issue soft reset to chip.
3024 printk(KERN_DEBUG PFX
3025 "%s: Issue soft reset to chip.\n",
3027 ql_write_common_reg(qdev
,
3028 &port_regs
->CommonRegs
.ispControlStatus
,
3029 ((ISP_CONTROL_SR
<< 16) | ISP_CONTROL_SR
));
3031 /* Wait 3 seconds for reset to complete. */
3032 printk(KERN_DEBUG PFX
3033 "%s: Wait 10 milliseconds for reset to complete.\n",
3036 /* Wait until the firmware tells us the Soft Reset is done */
3040 ql_read_common_reg(qdev
,
3041 &port_regs
->CommonRegs
.ispControlStatus
);
3042 if ((value
& ISP_CONTROL_SR
) == 0)
3046 } while ((--max_wait_time
));
3049 * Also, make sure that the Network Reset Interrupt bit has been
3050 * cleared after the soft reset has taken place.
3053 ql_read_common_reg(qdev
, &port_regs
->CommonRegs
.ispControlStatus
);
3054 if (value
& ISP_CONTROL_RI
) {
3055 printk(KERN_DEBUG PFX
3056 "ql_adapter_reset: clearing RI after reset.\n");
3057 ql_write_common_reg(qdev
,
3058 &port_regs
->CommonRegs
.
3060 ((ISP_CONTROL_RI
<< 16) | ISP_CONTROL_RI
));
3063 if (max_wait_time
== 0) {
3064 /* Issue Force Soft Reset */
3065 ql_write_common_reg(qdev
,
3066 &port_regs
->CommonRegs
.
3068 ((ISP_CONTROL_FSR
<< 16) |
3071 * Wait until the firmware tells us the Force Soft Reset is
3077 ql_read_common_reg(qdev
,
3078 &port_regs
->CommonRegs
.
3080 if ((value
& ISP_CONTROL_FSR
) == 0) {
3084 } while ((--max_wait_time
));
3086 if (max_wait_time
== 0)
3089 clear_bit(QL_RESET_ACTIVE
, &qdev
->flags
);
3090 set_bit(QL_RESET_DONE
, &qdev
->flags
);
3094 static void ql_set_mac_info(struct ql3_adapter
*qdev
)
3096 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
3097 u32 value
, port_status
;
3100 /* Get the function number */
3102 ql_read_common_reg_l(qdev
, &port_regs
->CommonRegs
.ispControlStatus
);
3103 func_number
= (u8
) ((value
>> 4) & OPCODE_FUNC_ID_MASK
);
3104 port_status
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
3105 switch (value
& ISP_CONTROL_FN_MASK
) {
3106 case ISP_CONTROL_FN0_NET
:
3107 qdev
->mac_index
= 0;
3108 qdev
->mac_ob_opcode
= OUTBOUND_MAC_IOCB
| func_number
;
3109 qdev
->tcp_ob_opcode
= OUTBOUND_TCP_IOCB
| func_number
;
3110 qdev
->update_ob_opcode
= UPDATE_NCB_IOCB
| func_number
;
3111 qdev
->mb_bit_mask
= FN0_MA_BITS_MASK
;
3112 qdev
->PHYAddr
= PORT0_PHY_ADDRESS
;
3113 if (port_status
& PORT_STATUS_SM0
)
3114 set_bit(QL_LINK_OPTICAL
,&qdev
->flags
);
3116 clear_bit(QL_LINK_OPTICAL
,&qdev
->flags
);
3119 case ISP_CONTROL_FN1_NET
:
3120 qdev
->mac_index
= 1;
3121 qdev
->mac_ob_opcode
= OUTBOUND_MAC_IOCB
| func_number
;
3122 qdev
->tcp_ob_opcode
= OUTBOUND_TCP_IOCB
| func_number
;
3123 qdev
->update_ob_opcode
= UPDATE_NCB_IOCB
| func_number
;
3124 qdev
->mb_bit_mask
= FN1_MA_BITS_MASK
;
3125 qdev
->PHYAddr
= PORT1_PHY_ADDRESS
;
3126 if (port_status
& PORT_STATUS_SM1
)
3127 set_bit(QL_LINK_OPTICAL
,&qdev
->flags
);
3129 clear_bit(QL_LINK_OPTICAL
,&qdev
->flags
);
3132 case ISP_CONTROL_FN0_SCSI
:
3133 case ISP_CONTROL_FN1_SCSI
:
3135 printk(KERN_DEBUG PFX
3136 "%s: Invalid function number, ispControlStatus = 0x%x\n",
3137 qdev
->ndev
->name
,value
);
3140 qdev
->numPorts
= qdev
->nvram_data
.numPorts
;
3143 static void ql_display_dev_info(struct net_device
*ndev
)
3145 struct ql3_adapter
*qdev
= (struct ql3_adapter
*)netdev_priv(ndev
);
3146 struct pci_dev
*pdev
= qdev
->pdev
;
3148 printk(KERN_INFO PFX
3149 "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3150 DRV_NAME
, qdev
->index
, qdev
->chip_rev_id
,
3151 (qdev
->device_id
== QL3032_DEVICE_ID
) ? "QLA3032" : "QLA3022",
3153 printk(KERN_INFO PFX
3155 test_bit(QL_LINK_OPTICAL
,&qdev
->flags
) ? "OPTICAL" : "COPPER");
3158 * Print PCI bus width/type.
3160 printk(KERN_INFO PFX
3161 "Bus interface is %s %s.\n",
3162 ((qdev
->pci_width
== 64) ? "64-bit" : "32-bit"),
3163 ((qdev
->pci_x
) ? "PCI-X" : "PCI"));
3165 printk(KERN_INFO PFX
3166 "mem IO base address adjusted = 0x%p\n",
3167 qdev
->mem_map_registers
);
3168 printk(KERN_INFO PFX
"Interrupt number = %d\n", pdev
->irq
);
3170 if (netif_msg_probe(qdev
))
3171 printk(KERN_INFO PFX
3172 "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
3173 ndev
->name
, ndev
->dev_addr
[0], ndev
->dev_addr
[1],
3174 ndev
->dev_addr
[2], ndev
->dev_addr
[3], ndev
->dev_addr
[4],
3178 static int ql_adapter_down(struct ql3_adapter
*qdev
, int do_reset
)
3180 struct net_device
*ndev
= qdev
->ndev
;
3183 netif_stop_queue(ndev
);
3184 netif_carrier_off(ndev
);
3186 clear_bit(QL_ADAPTER_UP
,&qdev
->flags
);
3187 clear_bit(QL_LINK_MASTER
,&qdev
->flags
);
3189 ql_disable_interrupts(qdev
);
3191 free_irq(qdev
->pdev
->irq
, ndev
);
3193 if (qdev
->msi
&& test_bit(QL_MSI_ENABLED
,&qdev
->flags
)) {
3194 printk(KERN_INFO PFX
3195 "%s: calling pci_disable_msi().\n", qdev
->ndev
->name
);
3196 clear_bit(QL_MSI_ENABLED
,&qdev
->flags
);
3197 pci_disable_msi(qdev
->pdev
);
3200 del_timer_sync(&qdev
->adapter_timer
);
3202 netif_poll_disable(ndev
);
3206 unsigned long hw_flags
;
3208 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
3209 if (ql_wait_for_drvr_lock(qdev
)) {
3210 if ((soft_reset
= ql_adapter_reset(qdev
))) {
3212 "%s: ql_adapter_reset(%d) FAILED!\n",
3213 ndev
->name
, qdev
->index
);
3216 "%s: Releaseing driver lock via chip reset.\n",ndev
->name
);
3219 "%s: Could not acquire driver lock to do "
3220 "reset!\n", ndev
->name
);
3223 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
3225 ql_free_mem_resources(qdev
);
3229 static int ql_adapter_up(struct ql3_adapter
*qdev
)
3231 struct net_device
*ndev
= qdev
->ndev
;
3233 unsigned long irq_flags
= IRQF_SAMPLE_RANDOM
| IRQF_SHARED
;
3234 unsigned long hw_flags
;
3236 if (ql_alloc_mem_resources(qdev
)) {
3238 "%s Unable to allocate buffers.\n", ndev
->name
);
3243 if (pci_enable_msi(qdev
->pdev
)) {
3245 "%s: User requested MSI, but MSI failed to "
3246 "initialize. Continuing without MSI.\n",
3250 printk(KERN_INFO PFX
"%s: MSI Enabled...\n", qdev
->ndev
->name
);
3251 set_bit(QL_MSI_ENABLED
,&qdev
->flags
);
3252 irq_flags
&= ~IRQF_SHARED
;
3256 if ((err
= request_irq(qdev
->pdev
->irq
,
3258 irq_flags
, ndev
->name
, ndev
))) {
3260 "%s: Failed to reserve interrupt %d already in use.\n",
3261 ndev
->name
, qdev
->pdev
->irq
);
3265 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
3267 if ((err
= ql_wait_for_drvr_lock(qdev
))) {
3268 if ((err
= ql_adapter_initialize(qdev
))) {
3270 "%s: Unable to initialize adapter.\n",
3275 "%s: Releaseing driver lock.\n",ndev
->name
);
3276 ql_sem_unlock(qdev
, QL_DRVR_SEM_MASK
);
3279 "%s: Could not aquire driver lock.\n",
3284 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
3286 set_bit(QL_ADAPTER_UP
,&qdev
->flags
);
3288 mod_timer(&qdev
->adapter_timer
, jiffies
+ HZ
* 1);
3290 netif_poll_enable(ndev
);
3291 ql_enable_interrupts(qdev
);
3295 ql_sem_unlock(qdev
, QL_DRVR_SEM_MASK
);
3297 free_irq(qdev
->pdev
->irq
, ndev
);
3299 if (qdev
->msi
&& test_bit(QL_MSI_ENABLED
,&qdev
->flags
)) {
3300 printk(KERN_INFO PFX
3301 "%s: calling pci_disable_msi().\n",
3303 clear_bit(QL_MSI_ENABLED
,&qdev
->flags
);
3304 pci_disable_msi(qdev
->pdev
);
3309 static int ql_cycle_adapter(struct ql3_adapter
*qdev
, int reset
)
3311 if( ql_adapter_down(qdev
,reset
) || ql_adapter_up(qdev
)) {
3313 "%s: Driver up/down cycle failed, "
3314 "closing device\n",qdev
->ndev
->name
);
3315 dev_close(qdev
->ndev
);
3321 static int ql3xxx_close(struct net_device
*ndev
)
3323 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
3326 * Wait for device to recover from a reset.
3327 * (Rarely happens, but possible.)
3329 while (!test_bit(QL_ADAPTER_UP
,&qdev
->flags
))
3332 ql_adapter_down(qdev
,QL_DO_RESET
);
3336 static int ql3xxx_open(struct net_device
*ndev
)
3338 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
3339 return (ql_adapter_up(qdev
));
3342 static struct net_device_stats
*ql3xxx_get_stats(struct net_device
*dev
)
3344 struct ql3_adapter
*qdev
= (struct ql3_adapter
*)dev
->priv
;
3345 return &qdev
->stats
;
3348 static int ql3xxx_change_mtu(struct net_device
*ndev
, int new_mtu
)
3350 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
3351 printk(KERN_ERR PFX
"%s: new mtu size = %d.\n", ndev
->name
, new_mtu
);
3352 if (new_mtu
!= NORMAL_MTU_SIZE
&& new_mtu
!= JUMBO_MTU_SIZE
) {
3354 "%s: mtu size of %d is not valid. Use exactly %d or "
3355 "%d.\n", ndev
->name
, new_mtu
, NORMAL_MTU_SIZE
,
3360 if (!netif_running(ndev
)) {
3361 ndev
->mtu
= new_mtu
;
3365 ndev
->mtu
= new_mtu
;
3366 return ql_cycle_adapter(qdev
,QL_DO_RESET
);
3369 static void ql3xxx_set_multicast_list(struct net_device
*ndev
)
3372 * We are manually parsing the list in the net_device structure.
3377 static int ql3xxx_set_mac_address(struct net_device
*ndev
, void *p
)
3379 struct ql3_adapter
*qdev
= (struct ql3_adapter
*)netdev_priv(ndev
);
3380 struct ql3xxx_port_registers __iomem
*port_regs
=
3381 qdev
->mem_map_registers
;
3382 struct sockaddr
*addr
= p
;
3383 unsigned long hw_flags
;
3385 if (netif_running(ndev
))
3388 if (!is_valid_ether_addr(addr
->sa_data
))
3389 return -EADDRNOTAVAIL
;
3391 memcpy(ndev
->dev_addr
, addr
->sa_data
, ndev
->addr_len
);
3393 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
3394 /* Program lower 32 bits of the MAC address */
3395 ql_write_page0_reg(qdev
, &port_regs
->macAddrIndirectPtrReg
,
3396 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK
<< 16));
3397 ql_write_page0_reg(qdev
, &port_regs
->macAddrDataReg
,
3398 ((ndev
->dev_addr
[2] << 24) | (ndev
->
3399 dev_addr
[3] << 16) |
3400 (ndev
->dev_addr
[4] << 8) | ndev
->dev_addr
[5]));
3402 /* Program top 16 bits of the MAC address */
3403 ql_write_page0_reg(qdev
, &port_regs
->macAddrIndirectPtrReg
,
3404 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK
<< 16) | 1));
3405 ql_write_page0_reg(qdev
, &port_regs
->macAddrDataReg
,
3406 ((ndev
->dev_addr
[0] << 8) | ndev
->dev_addr
[1]));
3407 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
3412 static void ql3xxx_tx_timeout(struct net_device
*ndev
)
3414 struct ql3_adapter
*qdev
= (struct ql3_adapter
*)netdev_priv(ndev
);
3416 printk(KERN_ERR PFX
"%s: Resetting...\n", ndev
->name
);
3418 * Stop the queues, we've got a problem.
3420 netif_stop_queue(ndev
);
3423 * Wake up the worker to process this event.
3425 queue_delayed_work(qdev
->workqueue
, &qdev
->tx_timeout_work
, 0);
3428 static void ql_reset_work(struct work_struct
*work
)
3430 struct ql3_adapter
*qdev
=
3431 container_of(work
, struct ql3_adapter
, reset_work
.work
);
3432 struct net_device
*ndev
= qdev
->ndev
;
3434 struct ql_tx_buf_cb
*tx_cb
;
3435 int max_wait_time
, i
;
3436 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
3437 unsigned long hw_flags
;
3439 if (test_bit((QL_RESET_PER_SCSI
| QL_RESET_START
),&qdev
->flags
)) {
3440 clear_bit(QL_LINK_MASTER
,&qdev
->flags
);
3443 * Loop through the active list and return the skb.
3445 for (i
= 0; i
< NUM_REQ_Q_ENTRIES
; i
++) {
3447 tx_cb
= &qdev
->tx_buf
[i
];
3449 printk(KERN_DEBUG PFX
3450 "%s: Freeing lost SKB.\n",
3452 pci_unmap_single(qdev
->pdev
,
3453 pci_unmap_addr(&tx_cb
->map
[0], mapaddr
),
3454 pci_unmap_len(&tx_cb
->map
[0], maplen
),
3456 for(j
=1;j
<tx_cb
->seg_count
;j
++) {
3457 pci_unmap_page(qdev
->pdev
,
3458 pci_unmap_addr(&tx_cb
->map
[j
],mapaddr
),
3459 pci_unmap_len(&tx_cb
->map
[j
],maplen
),
3462 dev_kfree_skb(tx_cb
->skb
);
3468 "%s: Clearing NRI after reset.\n", qdev
->ndev
->name
);
3469 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
3470 ql_write_common_reg(qdev
,
3471 &port_regs
->CommonRegs
.
3473 ((ISP_CONTROL_RI
<< 16) | ISP_CONTROL_RI
));
3475 * Wait the for Soft Reset to Complete.
3479 value
= ql_read_common_reg(qdev
,
3480 &port_regs
->CommonRegs
.
3483 if ((value
& ISP_CONTROL_SR
) == 0) {
3484 printk(KERN_DEBUG PFX
3485 "%s: reset completed.\n",
3490 if (value
& ISP_CONTROL_RI
) {
3491 printk(KERN_DEBUG PFX
3492 "%s: clearing NRI after reset.\n",
3494 ql_write_common_reg(qdev
,
3499 16) | ISP_CONTROL_RI
));
3503 } while (--max_wait_time
);
3504 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
3506 if (value
& ISP_CONTROL_SR
) {
3509 * Set the reset flags and clear the board again.
3510 * Nothing else to do...
3513 "%s: Timed out waiting for reset to "
3514 "complete.\n", ndev
->name
);
3516 "%s: Do a reset.\n", ndev
->name
);
3517 clear_bit(QL_RESET_PER_SCSI
,&qdev
->flags
);
3518 clear_bit(QL_RESET_START
,&qdev
->flags
);
3519 ql_cycle_adapter(qdev
,QL_DO_RESET
);
3523 clear_bit(QL_RESET_ACTIVE
,&qdev
->flags
);
3524 clear_bit(QL_RESET_PER_SCSI
,&qdev
->flags
);
3525 clear_bit(QL_RESET_START
,&qdev
->flags
);
3526 ql_cycle_adapter(qdev
,QL_NO_RESET
);
3530 static void ql_tx_timeout_work(struct work_struct
*work
)
3532 struct ql3_adapter
*qdev
=
3533 container_of(work
, struct ql3_adapter
, tx_timeout_work
.work
);
3535 ql_cycle_adapter(qdev
, QL_DO_RESET
);
3538 static void ql_get_board_info(struct ql3_adapter
*qdev
)
3540 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
3543 value
= ql_read_page0_reg_l(qdev
, &port_regs
->portStatus
);
3545 qdev
->chip_rev_id
= ((value
& PORT_STATUS_REV_ID_MASK
) >> 12);
3546 if (value
& PORT_STATUS_64
)
3547 qdev
->pci_width
= 64;
3549 qdev
->pci_width
= 32;
3550 if (value
& PORT_STATUS_X
)
3554 qdev
->pci_slot
= (u8
) PCI_SLOT(qdev
->pdev
->devfn
);
3557 static void ql3xxx_timer(unsigned long ptr
)
3559 struct ql3_adapter
*qdev
= (struct ql3_adapter
*)ptr
;
3561 if (test_bit(QL_RESET_ACTIVE
,&qdev
->flags
)) {
3562 printk(KERN_DEBUG PFX
3563 "%s: Reset in progress.\n",
3568 ql_link_state_machine(qdev
);
3570 /* Restart timer on 2 second interval. */
3572 mod_timer(&qdev
->adapter_timer
, jiffies
+ HZ
* 1);
3575 static int __devinit
ql3xxx_probe(struct pci_dev
*pdev
,
3576 const struct pci_device_id
*pci_entry
)
3578 struct net_device
*ndev
= NULL
;
3579 struct ql3_adapter
*qdev
= NULL
;
3580 static int cards_found
= 0;
3581 int pci_using_dac
, err
;
3583 err
= pci_enable_device(pdev
);
3585 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3590 err
= pci_request_regions(pdev
, DRV_NAME
);
3592 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3594 goto err_out_disable_pdev
;
3597 pci_set_master(pdev
);
3599 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
3601 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3602 } else if (!(err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
))) {
3604 err
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
3608 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3610 goto err_out_free_regions
;
3613 ndev
= alloc_etherdev(sizeof(struct ql3_adapter
));
3615 printk(KERN_ERR PFX
"%s could not alloc etherdev\n",
3618 goto err_out_free_regions
;
3621 SET_MODULE_OWNER(ndev
);
3622 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
3624 pci_set_drvdata(pdev
, ndev
);
3626 qdev
= netdev_priv(ndev
);
3627 qdev
->index
= cards_found
;
3630 qdev
->device_id
= pci_entry
->device
;
3631 qdev
->port_link_state
= LS_DOWN
;
3635 qdev
->msg_enable
= netif_msg_init(debug
, default_msg
);
3638 ndev
->features
|= NETIF_F_HIGHDMA
;
3639 if (qdev
->device_id
== QL3032_DEVICE_ID
)
3640 ndev
->features
|= (NETIF_F_HW_CSUM
| NETIF_F_SG
);
3642 qdev
->mem_map_registers
=
3643 ioremap_nocache(pci_resource_start(pdev
, 1),
3644 pci_resource_len(qdev
->pdev
, 1));
3645 if (!qdev
->mem_map_registers
) {
3646 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3649 goto err_out_free_ndev
;
3652 spin_lock_init(&qdev
->adapter_lock
);
3653 spin_lock_init(&qdev
->hw_lock
);
3655 /* Set driver entry points */
3656 ndev
->open
= ql3xxx_open
;
3657 ndev
->hard_start_xmit
= ql3xxx_send
;
3658 ndev
->stop
= ql3xxx_close
;
3659 ndev
->get_stats
= ql3xxx_get_stats
;
3660 ndev
->change_mtu
= ql3xxx_change_mtu
;
3661 ndev
->set_multicast_list
= ql3xxx_set_multicast_list
;
3662 SET_ETHTOOL_OPS(ndev
, &ql3xxx_ethtool_ops
);
3663 ndev
->set_mac_address
= ql3xxx_set_mac_address
;
3664 ndev
->tx_timeout
= ql3xxx_tx_timeout
;
3665 ndev
->watchdog_timeo
= 5 * HZ
;
3667 ndev
->poll
= &ql_poll
;
3670 ndev
->irq
= pdev
->irq
;
3672 /* make sure the EEPROM is good */
3673 if (ql_get_nvram_params(qdev
)) {
3674 printk(KERN_ALERT PFX
3675 "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
3678 goto err_out_iounmap
;
3681 ql_set_mac_info(qdev
);
3683 /* Validate and set parameters */
3684 if (qdev
->mac_index
) {
3685 memcpy(ndev
->dev_addr
, &qdev
->nvram_data
.funcCfg_fn2
.macAddress
,
3688 memcpy(ndev
->dev_addr
, &qdev
->nvram_data
.funcCfg_fn0
.macAddress
,
3691 memcpy(ndev
->perm_addr
, ndev
->dev_addr
, ndev
->addr_len
);
3693 ndev
->tx_queue_len
= NUM_REQ_Q_ENTRIES
;
3695 /* Turn off support for multicasting */
3696 ndev
->flags
&= ~IFF_MULTICAST
;
3698 /* Record PCI bus information. */
3699 ql_get_board_info(qdev
);
3702 * Set the Maximum Memory Read Byte Count value. We do this to handle
3706 pci_write_config_word(pdev
, (int)0x4e, (u16
) 0x0036);
3709 err
= register_netdev(ndev
);
3711 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3713 goto err_out_iounmap
;
3716 /* we're going to reset, so assume we have no link for now */
3718 netif_carrier_off(ndev
);
3719 netif_stop_queue(ndev
);
3721 qdev
->workqueue
= create_singlethread_workqueue(ndev
->name
);
3722 INIT_DELAYED_WORK(&qdev
->reset_work
, ql_reset_work
);
3723 INIT_DELAYED_WORK(&qdev
->tx_timeout_work
, ql_tx_timeout_work
);
3725 init_timer(&qdev
->adapter_timer
);
3726 qdev
->adapter_timer
.function
= ql3xxx_timer
;
3727 qdev
->adapter_timer
.expires
= jiffies
+ HZ
* 2; /* two second delay */
3728 qdev
->adapter_timer
.data
= (unsigned long)qdev
;
3731 printk(KERN_ALERT PFX
"%s\n", DRV_STRING
);
3732 printk(KERN_ALERT PFX
"Driver name: %s, Version: %s.\n",
3733 DRV_NAME
, DRV_VERSION
);
3735 ql_display_dev_info(ndev
);
3741 iounmap(qdev
->mem_map_registers
);
3744 err_out_free_regions
:
3745 pci_release_regions(pdev
);
3746 err_out_disable_pdev
:
3747 pci_disable_device(pdev
);
3748 pci_set_drvdata(pdev
, NULL
);
3753 static void __devexit
ql3xxx_remove(struct pci_dev
*pdev
)
3755 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3756 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
3758 unregister_netdev(ndev
);
3759 qdev
= netdev_priv(ndev
);
3761 ql_disable_interrupts(qdev
);
3763 if (qdev
->workqueue
) {
3764 cancel_delayed_work(&qdev
->reset_work
);
3765 cancel_delayed_work(&qdev
->tx_timeout_work
);
3766 destroy_workqueue(qdev
->workqueue
);
3767 qdev
->workqueue
= NULL
;
3770 iounmap(qdev
->mem_map_registers
);
3771 pci_release_regions(pdev
);
3772 pci_set_drvdata(pdev
, NULL
);
3776 static struct pci_driver ql3xxx_driver
= {
3779 .id_table
= ql3xxx_pci_tbl
,
3780 .probe
= ql3xxx_probe
,
3781 .remove
= __devexit_p(ql3xxx_remove
),
3784 static int __init
ql3xxx_init_module(void)
3786 return pci_register_driver(&ql3xxx_driver
);
3789 static void __exit
ql3xxx_exit(void)
3791 pci_unregister_driver(&ql3xxx_driver
);
3794 module_init(ql3xxx_init_module
);
3795 module_exit(ql3xxx_exit
);