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[PATCH] skge: use ethX for irq assigments
[linux-2.6/mini2440.git] / drivers / net / skge.c
blobbcdf9f59607dd47bc59d5be8b327fafeb62cfc2c
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/in.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/mii.h>
41 #include <asm/irq.h>
42
43 #include "skge.h"
44
45 #define DRV_NAME "skge"
46 #define DRV_VERSION "1.6"
47 #define PFX DRV_NAME " "
48
49 #define DEFAULT_TX_RING_SIZE 128
50 #define DEFAULT_RX_RING_SIZE 512
51 #define MAX_TX_RING_SIZE 1024
52 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
53 #define MAX_RX_RING_SIZE 4096
54 #define RX_COPY_THRESHOLD 128
55 #define RX_BUF_SIZE 1536
56 #define PHY_RETRIES 1000
57 #define ETH_JUMBO_MTU 9000
58 #define TX_WATCHDOG (5 * HZ)
59 #define NAPI_WEIGHT 64
60 #define BLINK_MS 250
61
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION);
66
67 static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71 static int debug = -1; /* defaults above */
72 module_param(debug, int, 0);
73 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75 static const struct pci_device_id skge_id_table[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
87 { 0 }
88 };
89 MODULE_DEVICE_TABLE(pci, skge_id_table);
90
91 static int skge_up(struct net_device *dev);
92 static int skge_down(struct net_device *dev);
93 static void skge_phy_reset(struct skge_port *skge);
94 static void skge_tx_clean(struct skge_port *skge);
95 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97 static void genesis_get_stats(struct skge_port *skge, u64 *data);
98 static void yukon_get_stats(struct skge_port *skge, u64 *data);
99 static void yukon_init(struct skge_hw *hw, int port);
100 static void genesis_mac_init(struct skge_hw *hw, int port);
101 static void genesis_link_up(struct skge_port *skge);
102
103 /* Avoid conditionals by using array */
104 static const int txqaddr[] = { Q_XA1, Q_XA2 };
105 static const int rxqaddr[] = { Q_R1, Q_R2 };
106 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
108
109 static int skge_get_regs_len(struct net_device *dev)
110 {
111 return 0x4000;
112 }
113
114 /*
115 * Returns copy of whole control register region
116 * Note: skip RAM address register because accessing it will
117 * cause bus hangs!
118 */
119 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
120 void *p)
121 {
122 const struct skge_port *skge = netdev_priv(dev);
123 const void __iomem *io = skge->hw->regs;
124
125 regs->version = 1;
126 memset(p, 0, regs->len);
127 memcpy_fromio(p, io, B3_RAM_ADDR);
128
129 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
130 regs->len - B3_RI_WTO_R1);
131 }
132
133 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
134 static int wol_supported(const struct skge_hw *hw)
135 {
136 return !((hw->chip_id == CHIP_ID_GENESIS ||
137 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
138 }
139
140 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
141 {
142 struct skge_port *skge = netdev_priv(dev);
143
144 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
145 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
146 }
147
148 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
149 {
150 struct skge_port *skge = netdev_priv(dev);
151 struct skge_hw *hw = skge->hw;
152
153 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
154 return -EOPNOTSUPP;
155
156 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
157 return -EOPNOTSUPP;
158
159 skge->wol = wol->wolopts == WAKE_MAGIC;
160
161 if (skge->wol) {
162 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
163
164 skge_write16(hw, WOL_CTRL_STAT,
165 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
166 WOL_CTL_ENA_MAGIC_PKT_UNIT);
167 } else
168 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
169
170 return 0;
171 }
172
173 /* Determine supported/advertised modes based on hardware.
174 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
175 */
176 static u32 skge_supported_modes(const struct skge_hw *hw)
177 {
178 u32 supported;
179
180 if (hw->copper) {
181 supported = SUPPORTED_10baseT_Half
182 | SUPPORTED_10baseT_Full
183 | SUPPORTED_100baseT_Half
184 | SUPPORTED_100baseT_Full
185 | SUPPORTED_1000baseT_Half
186 | SUPPORTED_1000baseT_Full
187 | SUPPORTED_Autoneg| SUPPORTED_TP;
188
189 if (hw->chip_id == CHIP_ID_GENESIS)
190 supported &= ~(SUPPORTED_10baseT_Half
191 | SUPPORTED_10baseT_Full
192 | SUPPORTED_100baseT_Half
193 | SUPPORTED_100baseT_Full);
194
195 else if (hw->chip_id == CHIP_ID_YUKON)
196 supported &= ~SUPPORTED_1000baseT_Half;
197 } else
198 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
199 | SUPPORTED_Autoneg;
200
201 return supported;
202 }
203
204 static int skge_get_settings(struct net_device *dev,
205 struct ethtool_cmd *ecmd)
206 {
207 struct skge_port *skge = netdev_priv(dev);
208 struct skge_hw *hw = skge->hw;
209
210 ecmd->transceiver = XCVR_INTERNAL;
211 ecmd->supported = skge_supported_modes(hw);
212
213 if (hw->copper) {
214 ecmd->port = PORT_TP;
215 ecmd->phy_address = hw->phy_addr;
216 } else
217 ecmd->port = PORT_FIBRE;
218
219 ecmd->advertising = skge->advertising;
220 ecmd->autoneg = skge->autoneg;
221 ecmd->speed = skge->speed;
222 ecmd->duplex = skge->duplex;
223 return 0;
224 }
225
226 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
227 {
228 struct skge_port *skge = netdev_priv(dev);
229 const struct skge_hw *hw = skge->hw;
230 u32 supported = skge_supported_modes(hw);
231
232 if (ecmd->autoneg == AUTONEG_ENABLE) {
233 ecmd->advertising = supported;
234 skge->duplex = -1;
235 skge->speed = -1;
236 } else {
237 u32 setting;
238
239 switch (ecmd->speed) {
240 case SPEED_1000:
241 if (ecmd->duplex == DUPLEX_FULL)
242 setting = SUPPORTED_1000baseT_Full;
243 else if (ecmd->duplex == DUPLEX_HALF)
244 setting = SUPPORTED_1000baseT_Half;
245 else
246 return -EINVAL;
247 break;
248 case SPEED_100:
249 if (ecmd->duplex == DUPLEX_FULL)
250 setting = SUPPORTED_100baseT_Full;
251 else if (ecmd->duplex == DUPLEX_HALF)
252 setting = SUPPORTED_100baseT_Half;
253 else
254 return -EINVAL;
255 break;
256
257 case SPEED_10:
258 if (ecmd->duplex == DUPLEX_FULL)
259 setting = SUPPORTED_10baseT_Full;
260 else if (ecmd->duplex == DUPLEX_HALF)
261 setting = SUPPORTED_10baseT_Half;
262 else
263 return -EINVAL;
264 break;
265 default:
266 return -EINVAL;
267 }
268
269 if ((setting & supported) == 0)
270 return -EINVAL;
271
272 skge->speed = ecmd->speed;
273 skge->duplex = ecmd->duplex;
274 }
275
276 skge->autoneg = ecmd->autoneg;
277 skge->advertising = ecmd->advertising;
278
279 if (netif_running(dev))
280 skge_phy_reset(skge);
281
282 return (0);
283 }
284
285 static void skge_get_drvinfo(struct net_device *dev,
286 struct ethtool_drvinfo *info)
287 {
288 struct skge_port *skge = netdev_priv(dev);
289
290 strcpy(info->driver, DRV_NAME);
291 strcpy(info->version, DRV_VERSION);
292 strcpy(info->fw_version, "N/A");
293 strcpy(info->bus_info, pci_name(skge->hw->pdev));
294 }
295
296 static const struct skge_stat {
297 char name[ETH_GSTRING_LEN];
298 u16 xmac_offset;
299 u16 gma_offset;
300 } skge_stats[] = {
301 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
302 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
303
304 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
305 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
306 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
307 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
308 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
309 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
310 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
311 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
312
313 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
314 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
315 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
316 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
317 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
318 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
319
320 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
321 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
322 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
323 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
324 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
325 };
326
327 static int skge_get_stats_count(struct net_device *dev)
328 {
329 return ARRAY_SIZE(skge_stats);
330 }
331
332 static void skge_get_ethtool_stats(struct net_device *dev,
333 struct ethtool_stats *stats, u64 *data)
334 {
335 struct skge_port *skge = netdev_priv(dev);
336
337 if (skge->hw->chip_id == CHIP_ID_GENESIS)
338 genesis_get_stats(skge, data);
339 else
340 yukon_get_stats(skge, data);
341 }
342
343 /* Use hardware MIB variables for critical path statistics and
344 * transmit feedback not reported at interrupt.
345 * Other errors are accounted for in interrupt handler.
346 */
347 static struct net_device_stats *skge_get_stats(struct net_device *dev)
348 {
349 struct skge_port *skge = netdev_priv(dev);
350 u64 data[ARRAY_SIZE(skge_stats)];
351
352 if (skge->hw->chip_id == CHIP_ID_GENESIS)
353 genesis_get_stats(skge, data);
354 else
355 yukon_get_stats(skge, data);
356
357 skge->net_stats.tx_bytes = data[0];
358 skge->net_stats.rx_bytes = data[1];
359 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
360 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
361 skge->net_stats.multicast = data[3] + data[5];
362 skge->net_stats.collisions = data[10];
363 skge->net_stats.tx_aborted_errors = data[12];
364
365 return &skge->net_stats;
366 }
367
368 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
369 {
370 int i;
371
372 switch (stringset) {
373 case ETH_SS_STATS:
374 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
375 memcpy(data + i * ETH_GSTRING_LEN,
376 skge_stats[i].name, ETH_GSTRING_LEN);
377 break;
378 }
379 }
380
381 static void skge_get_ring_param(struct net_device *dev,
382 struct ethtool_ringparam *p)
383 {
384 struct skge_port *skge = netdev_priv(dev);
385
386 p->rx_max_pending = MAX_RX_RING_SIZE;
387 p->tx_max_pending = MAX_TX_RING_SIZE;
388 p->rx_mini_max_pending = 0;
389 p->rx_jumbo_max_pending = 0;
390
391 p->rx_pending = skge->rx_ring.count;
392 p->tx_pending = skge->tx_ring.count;
393 p->rx_mini_pending = 0;
394 p->rx_jumbo_pending = 0;
395 }
396
397 static int skge_set_ring_param(struct net_device *dev,
398 struct ethtool_ringparam *p)
399 {
400 struct skge_port *skge = netdev_priv(dev);
401 int err;
402
403 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
404 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
405 return -EINVAL;
406
407 skge->rx_ring.count = p->rx_pending;
408 skge->tx_ring.count = p->tx_pending;
409
410 if (netif_running(dev)) {
411 skge_down(dev);
412 err = skge_up(dev);
413 if (err)
414 dev_close(dev);
415 }
416
417 return 0;
418 }
419
420 static u32 skge_get_msglevel(struct net_device *netdev)
421 {
422 struct skge_port *skge = netdev_priv(netdev);
423 return skge->msg_enable;
424 }
425
426 static void skge_set_msglevel(struct net_device *netdev, u32 value)
427 {
428 struct skge_port *skge = netdev_priv(netdev);
429 skge->msg_enable = value;
430 }
431
432 static int skge_nway_reset(struct net_device *dev)
433 {
434 struct skge_port *skge = netdev_priv(dev);
435
436 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
437 return -EINVAL;
438
439 skge_phy_reset(skge);
440 return 0;
441 }
442
443 static int skge_set_sg(struct net_device *dev, u32 data)
444 {
445 struct skge_port *skge = netdev_priv(dev);
446 struct skge_hw *hw = skge->hw;
447
448 if (hw->chip_id == CHIP_ID_GENESIS && data)
449 return -EOPNOTSUPP;
450 return ethtool_op_set_sg(dev, data);
451 }
452
453 static int skge_set_tx_csum(struct net_device *dev, u32 data)
454 {
455 struct skge_port *skge = netdev_priv(dev);
456 struct skge_hw *hw = skge->hw;
457
458 if (hw->chip_id == CHIP_ID_GENESIS && data)
459 return -EOPNOTSUPP;
460
461 return ethtool_op_set_tx_csum(dev, data);
462 }
463
464 static u32 skge_get_rx_csum(struct net_device *dev)
465 {
466 struct skge_port *skge = netdev_priv(dev);
467
468 return skge->rx_csum;
469 }
470
471 /* Only Yukon supports checksum offload. */
472 static int skge_set_rx_csum(struct net_device *dev, u32 data)
473 {
474 struct skge_port *skge = netdev_priv(dev);
475
476 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
477 return -EOPNOTSUPP;
478
479 skge->rx_csum = data;
480 return 0;
481 }
482
483 static void skge_get_pauseparam(struct net_device *dev,
484 struct ethtool_pauseparam *ecmd)
485 {
486 struct skge_port *skge = netdev_priv(dev);
487
488 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
489 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
490 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
491 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
492
493 ecmd->autoneg = skge->autoneg;
494 }
495
496 static int skge_set_pauseparam(struct net_device *dev,
497 struct ethtool_pauseparam *ecmd)
498 {
499 struct skge_port *skge = netdev_priv(dev);
500
501 skge->autoneg = ecmd->autoneg;
502 if (ecmd->rx_pause && ecmd->tx_pause)
503 skge->flow_control = FLOW_MODE_SYMMETRIC;
504 else if (ecmd->rx_pause && !ecmd->tx_pause)
505 skge->flow_control = FLOW_MODE_REM_SEND;
506 else if (!ecmd->rx_pause && ecmd->tx_pause)
507 skge->flow_control = FLOW_MODE_LOC_SEND;
508 else
509 skge->flow_control = FLOW_MODE_NONE;
510
511 if (netif_running(dev))
512 skge_phy_reset(skge);
513 return 0;
514 }
515
516 /* Chip internal frequency for clock calculations */
517 static inline u32 hwkhz(const struct skge_hw *hw)
518 {
519 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
520 }
521
522 /* Chip HZ to microseconds */
523 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
524 {
525 return (ticks * 1000) / hwkhz(hw);
526 }
527
528 /* Microseconds to chip HZ */
529 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
530 {
531 return hwkhz(hw) * usec / 1000;
532 }
533
534 static int skge_get_coalesce(struct net_device *dev,
535 struct ethtool_coalesce *ecmd)
536 {
537 struct skge_port *skge = netdev_priv(dev);
538 struct skge_hw *hw = skge->hw;
539 int port = skge->port;
540
541 ecmd->rx_coalesce_usecs = 0;
542 ecmd->tx_coalesce_usecs = 0;
543
544 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
545 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
546 u32 msk = skge_read32(hw, B2_IRQM_MSK);
547
548 if (msk & rxirqmask[port])
549 ecmd->rx_coalesce_usecs = delay;
550 if (msk & txirqmask[port])
551 ecmd->tx_coalesce_usecs = delay;
552 }
553
554 return 0;
555 }
556
557 /* Note: interrupt timer is per board, but can turn on/off per port */
558 static int skge_set_coalesce(struct net_device *dev,
559 struct ethtool_coalesce *ecmd)
560 {
561 struct skge_port *skge = netdev_priv(dev);
562 struct skge_hw *hw = skge->hw;
563 int port = skge->port;
564 u32 msk = skge_read32(hw, B2_IRQM_MSK);
565 u32 delay = 25;
566
567 if (ecmd->rx_coalesce_usecs == 0)
568 msk &= ~rxirqmask[port];
569 else if (ecmd->rx_coalesce_usecs < 25 ||
570 ecmd->rx_coalesce_usecs > 33333)
571 return -EINVAL;
572 else {
573 msk |= rxirqmask[port];
574 delay = ecmd->rx_coalesce_usecs;
575 }
576
577 if (ecmd->tx_coalesce_usecs == 0)
578 msk &= ~txirqmask[port];
579 else if (ecmd->tx_coalesce_usecs < 25 ||
580 ecmd->tx_coalesce_usecs > 33333)
581 return -EINVAL;
582 else {
583 msk |= txirqmask[port];
584 delay = min(delay, ecmd->rx_coalesce_usecs);
585 }
586
587 skge_write32(hw, B2_IRQM_MSK, msk);
588 if (msk == 0)
589 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
590 else {
591 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
592 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
593 }
594 return 0;
595 }
596
597 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
598 static void skge_led(struct skge_port *skge, enum led_mode mode)
599 {
600 struct skge_hw *hw = skge->hw;
601 int port = skge->port;
602
603 mutex_lock(&hw->phy_mutex);
604 if (hw->chip_id == CHIP_ID_GENESIS) {
605 switch (mode) {
606 case LED_MODE_OFF:
607 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
608 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
609 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
610 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
611 break;
612
613 case LED_MODE_ON:
614 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
615 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
616
617 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
618 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
619
620 break;
621
622 case LED_MODE_TST:
623 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
624 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
625 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
626
627 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
628 break;
629 }
630 } else {
631 switch (mode) {
632 case LED_MODE_OFF:
633 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
634 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
635 PHY_M_LED_MO_DUP(MO_LED_OFF) |
636 PHY_M_LED_MO_10(MO_LED_OFF) |
637 PHY_M_LED_MO_100(MO_LED_OFF) |
638 PHY_M_LED_MO_1000(MO_LED_OFF) |
639 PHY_M_LED_MO_RX(MO_LED_OFF));
640 break;
641 case LED_MODE_ON:
642 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
643 PHY_M_LED_PULS_DUR(PULS_170MS) |
644 PHY_M_LED_BLINK_RT(BLINK_84MS) |
645 PHY_M_LEDC_TX_CTRL |
646 PHY_M_LEDC_DP_CTRL);
647
648 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
649 PHY_M_LED_MO_RX(MO_LED_OFF) |
650 (skge->speed == SPEED_100 ?
651 PHY_M_LED_MO_100(MO_LED_ON) : 0));
652 break;
653 case LED_MODE_TST:
654 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
655 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
656 PHY_M_LED_MO_DUP(MO_LED_ON) |
657 PHY_M_LED_MO_10(MO_LED_ON) |
658 PHY_M_LED_MO_100(MO_LED_ON) |
659 PHY_M_LED_MO_1000(MO_LED_ON) |
660 PHY_M_LED_MO_RX(MO_LED_ON));
661 }
662 }
663 mutex_unlock(&hw->phy_mutex);
664 }
665
666 /* blink LED's for finding board */
667 static int skge_phys_id(struct net_device *dev, u32 data)
668 {
669 struct skge_port *skge = netdev_priv(dev);
670 unsigned long ms;
671 enum led_mode mode = LED_MODE_TST;
672
673 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
674 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
675 else
676 ms = data * 1000;
677
678 while (ms > 0) {
679 skge_led(skge, mode);
680 mode ^= LED_MODE_TST;
681
682 if (msleep_interruptible(BLINK_MS))
683 break;
684 ms -= BLINK_MS;
685 }
686
687 /* back to regular LED state */
688 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
689
690 return 0;
691 }
692
693 static struct ethtool_ops skge_ethtool_ops = {
694 .get_settings = skge_get_settings,
695 .set_settings = skge_set_settings,
696 .get_drvinfo = skge_get_drvinfo,
697 .get_regs_len = skge_get_regs_len,
698 .get_regs = skge_get_regs,
699 .get_wol = skge_get_wol,
700 .set_wol = skge_set_wol,
701 .get_msglevel = skge_get_msglevel,
702 .set_msglevel = skge_set_msglevel,
703 .nway_reset = skge_nway_reset,
704 .get_link = ethtool_op_get_link,
705 .get_ringparam = skge_get_ring_param,
706 .set_ringparam = skge_set_ring_param,
707 .get_pauseparam = skge_get_pauseparam,
708 .set_pauseparam = skge_set_pauseparam,
709 .get_coalesce = skge_get_coalesce,
710 .set_coalesce = skge_set_coalesce,
711 .get_sg = ethtool_op_get_sg,
712 .set_sg = skge_set_sg,
713 .get_tx_csum = ethtool_op_get_tx_csum,
714 .set_tx_csum = skge_set_tx_csum,
715 .get_rx_csum = skge_get_rx_csum,
716 .set_rx_csum = skge_set_rx_csum,
717 .get_strings = skge_get_strings,
718 .phys_id = skge_phys_id,
719 .get_stats_count = skge_get_stats_count,
720 .get_ethtool_stats = skge_get_ethtool_stats,
721 .get_perm_addr = ethtool_op_get_perm_addr,
722 };
723
724 /*
725 * Allocate ring elements and chain them together
726 * One-to-one association of board descriptors with ring elements
727 */
728 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
729 {
730 struct skge_tx_desc *d;
731 struct skge_element *e;
732 int i;
733
734 ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);
735 if (!ring->start)
736 return -ENOMEM;
737
738 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
739 e->desc = d;
740 if (i == ring->count - 1) {
741 e->next = ring->start;
742 d->next_offset = base;
743 } else {
744 e->next = e + 1;
745 d->next_offset = base + (i+1) * sizeof(*d);
746 }
747 }
748 ring->to_use = ring->to_clean = ring->start;
749
750 return 0;
751 }
752
753 /* Allocate and setup a new buffer for receiving */
754 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
755 struct sk_buff *skb, unsigned int bufsize)
756 {
757 struct skge_rx_desc *rd = e->desc;
758 u64 map;
759
760 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
761 PCI_DMA_FROMDEVICE);
762
763 rd->dma_lo = map;
764 rd->dma_hi = map >> 32;
765 e->skb = skb;
766 rd->csum1_start = ETH_HLEN;
767 rd->csum2_start = ETH_HLEN;
768 rd->csum1 = 0;
769 rd->csum2 = 0;
770
771 wmb();
772
773 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
774 pci_unmap_addr_set(e, mapaddr, map);
775 pci_unmap_len_set(e, maplen, bufsize);
776 }
777
778 /* Resume receiving using existing skb,
779 * Note: DMA address is not changed by chip.
780 * MTU not changed while receiver active.
781 */
782 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
783 {
784 struct skge_rx_desc *rd = e->desc;
785
786 rd->csum2 = 0;
787 rd->csum2_start = ETH_HLEN;
788
789 wmb();
790
791 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
792 }
793
794
795 /* Free all buffers in receive ring, assumes receiver stopped */
796 static void skge_rx_clean(struct skge_port *skge)
797 {
798 struct skge_hw *hw = skge->hw;
799 struct skge_ring *ring = &skge->rx_ring;
800 struct skge_element *e;
801
802 e = ring->start;
803 do {
804 struct skge_rx_desc *rd = e->desc;
805 rd->control = 0;
806 if (e->skb) {
807 pci_unmap_single(hw->pdev,
808 pci_unmap_addr(e, mapaddr),
809 pci_unmap_len(e, maplen),
810 PCI_DMA_FROMDEVICE);
811 dev_kfree_skb(e->skb);
812 e->skb = NULL;
813 }
814 } while ((e = e->next) != ring->start);
815 }
816
817
818 /* Allocate buffers for receive ring
819 * For receive: to_clean is next received frame.
820 */
821 static int skge_rx_fill(struct skge_port *skge)
822 {
823 struct skge_ring *ring = &skge->rx_ring;
824 struct skge_element *e;
825
826 e = ring->start;
827 do {
828 struct sk_buff *skb;
829
830 skb = __dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN,
831 GFP_KERNEL);
832 if (!skb)
833 return -ENOMEM;
834
835 skb_reserve(skb, NET_IP_ALIGN);
836 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
837 } while ( (e = e->next) != ring->start);
838
839 ring->to_clean = ring->start;
840 return 0;
841 }
842
843 static void skge_link_up(struct skge_port *skge)
844 {
845 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
846 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
847
848 netif_carrier_on(skge->netdev);
849 netif_wake_queue(skge->netdev);
850
851 if (netif_msg_link(skge))
852 printk(KERN_INFO PFX
853 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
854 skge->netdev->name, skge->speed,
855 skge->duplex == DUPLEX_FULL ? "full" : "half",
856 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
857 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
858 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
859 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
860 "unknown");
861 }
862
863 static void skge_link_down(struct skge_port *skge)
864 {
865 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
866 netif_carrier_off(skge->netdev);
867 netif_stop_queue(skge->netdev);
868
869 if (netif_msg_link(skge))
870 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
871 }
872
873 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
874 {
875 int i;
876
877 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
878 *val = xm_read16(hw, port, XM_PHY_DATA);
879
880 for (i = 0; i < PHY_RETRIES; i++) {
881 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
882 goto ready;
883 udelay(1);
884 }
885
886 return -ETIMEDOUT;
887 ready:
888 *val = xm_read16(hw, port, XM_PHY_DATA);
889
890 return 0;
891 }
892
893 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
894 {
895 u16 v = 0;
896 if (__xm_phy_read(hw, port, reg, &v))
897 printk(KERN_WARNING PFX "%s: phy read timed out\n",
898 hw->dev[port]->name);
899 return v;
900 }
901
902 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
903 {
904 int i;
905
906 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
907 for (i = 0; i < PHY_RETRIES; i++) {
908 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
909 goto ready;
910 udelay(1);
911 }
912 return -EIO;
913
914 ready:
915 xm_write16(hw, port, XM_PHY_DATA, val);
916 for (i = 0; i < PHY_RETRIES; i++) {
917 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
918 return 0;
919 udelay(1);
920 }
921 return -ETIMEDOUT;
922 }
923
924 static void genesis_init(struct skge_hw *hw)
925 {
926 /* set blink source counter */
927 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
928 skge_write8(hw, B2_BSC_CTRL, BSC_START);
929
930 /* configure mac arbiter */
931 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
932
933 /* configure mac arbiter timeout values */
934 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
935 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
936 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
937 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
938
939 skge_write8(hw, B3_MA_RCINI_RX1, 0);
940 skge_write8(hw, B3_MA_RCINI_RX2, 0);
941 skge_write8(hw, B3_MA_RCINI_TX1, 0);
942 skge_write8(hw, B3_MA_RCINI_TX2, 0);
943
944 /* configure packet arbiter timeout */
945 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
946 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
947 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
948 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
949 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
950 }
951
952 static void genesis_reset(struct skge_hw *hw, int port)
953 {
954 const u8 zero[8] = { 0 };
955
956 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
957
958 /* reset the statistics module */
959 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
960 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
961 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
962 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
963 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
964
965 /* disable Broadcom PHY IRQ */
966 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
967
968 xm_outhash(hw, port, XM_HSM, zero);
969 }
970
971
972 /* Convert mode to MII values */
973 static const u16 phy_pause_map[] = {
974 [FLOW_MODE_NONE] = 0,
975 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
976 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
977 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
978 };
979
980
981 /* Check status of Broadcom phy link */
982 static void bcom_check_link(struct skge_hw *hw, int port)
983 {
984 struct net_device *dev = hw->dev[port];
985 struct skge_port *skge = netdev_priv(dev);
986 u16 status;
987
988 /* read twice because of latch */
989 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
990 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
991
992 if ((status & PHY_ST_LSYNC) == 0) {
993 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
994 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
995 xm_write16(hw, port, XM_MMU_CMD, cmd);
996 /* dummy read to ensure writing */
997 (void) xm_read16(hw, port, XM_MMU_CMD);
998
999 if (netif_carrier_ok(dev))
1000 skge_link_down(skge);
1001 } else {
1002 if (skge->autoneg == AUTONEG_ENABLE &&
1003 (status & PHY_ST_AN_OVER)) {
1004 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1005 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1006
1007 if (lpa & PHY_B_AN_RF) {
1008 printk(KERN_NOTICE PFX "%s: remote fault\n",
1009 dev->name);
1010 return;
1011 }
1012
1013 /* Check Duplex mismatch */
1014 switch (aux & PHY_B_AS_AN_RES_MSK) {
1015 case PHY_B_RES_1000FD:
1016 skge->duplex = DUPLEX_FULL;
1017 break;
1018 case PHY_B_RES_1000HD:
1019 skge->duplex = DUPLEX_HALF;
1020 break;
1021 default:
1022 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1023 dev->name);
1024 return;
1025 }
1026
1027
1028 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1029 switch (aux & PHY_B_AS_PAUSE_MSK) {
1030 case PHY_B_AS_PAUSE_MSK:
1031 skge->flow_control = FLOW_MODE_SYMMETRIC;
1032 break;
1033 case PHY_B_AS_PRR:
1034 skge->flow_control = FLOW_MODE_REM_SEND;
1035 break;
1036 case PHY_B_AS_PRT:
1037 skge->flow_control = FLOW_MODE_LOC_SEND;
1038 break;
1039 default:
1040 skge->flow_control = FLOW_MODE_NONE;
1041 }
1042
1043 skge->speed = SPEED_1000;
1044 }
1045
1046 if (!netif_carrier_ok(dev))
1047 genesis_link_up(skge);
1048 }
1049 }
1050
1051 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1052 * Phy on for 100 or 10Mbit operation
1053 */
1054 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1055 {
1056 struct skge_hw *hw = skge->hw;
1057 int port = skge->port;
1058 int i;
1059 u16 id1, r, ext, ctl;
1060
1061 /* magic workaround patterns for Broadcom */
1062 static const struct {
1063 u16 reg;
1064 u16 val;
1065 } A1hack[] = {
1066 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1067 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1068 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1069 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1070 }, C0hack[] = {
1071 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1072 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1073 };
1074
1075 /* read Id from external PHY (all have the same address) */
1076 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1077
1078 /* Optimize MDIO transfer by suppressing preamble. */
1079 r = xm_read16(hw, port, XM_MMU_CMD);
1080 r |= XM_MMU_NO_PRE;
1081 xm_write16(hw, port, XM_MMU_CMD,r);
1082
1083 switch (id1) {
1084 case PHY_BCOM_ID1_C0:
1085 /*
1086 * Workaround BCOM Errata for the C0 type.
1087 * Write magic patterns to reserved registers.
1088 */
1089 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1090 xm_phy_write(hw, port,
1091 C0hack[i].reg, C0hack[i].val);
1092
1093 break;
1094 case PHY_BCOM_ID1_A1:
1095 /*
1096 * Workaround BCOM Errata for the A1 type.
1097 * Write magic patterns to reserved registers.
1098 */
1099 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1100 xm_phy_write(hw, port,
1101 A1hack[i].reg, A1hack[i].val);
1102 break;
1103 }
1104
1105 /*
1106 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1107 * Disable Power Management after reset.
1108 */
1109 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1110 r |= PHY_B_AC_DIS_PM;
1111 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1112
1113 /* Dummy read */
1114 xm_read16(hw, port, XM_ISRC);
1115
1116 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1117 ctl = PHY_CT_SP1000; /* always 1000mbit */
1118
1119 if (skge->autoneg == AUTONEG_ENABLE) {
1120 /*
1121 * Workaround BCOM Errata #1 for the C5 type.
1122 * 1000Base-T Link Acquisition Failure in Slave Mode
1123 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1124 */
1125 u16 adv = PHY_B_1000C_RD;
1126 if (skge->advertising & ADVERTISED_1000baseT_Half)
1127 adv |= PHY_B_1000C_AHD;
1128 if (skge->advertising & ADVERTISED_1000baseT_Full)
1129 adv |= PHY_B_1000C_AFD;
1130 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1131
1132 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1133 } else {
1134 if (skge->duplex == DUPLEX_FULL)
1135 ctl |= PHY_CT_DUP_MD;
1136 /* Force to slave */
1137 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1138 }
1139
1140 /* Set autonegotiation pause parameters */
1141 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1142 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1143
1144 /* Handle Jumbo frames */
1145 if (jumbo) {
1146 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1147 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1148
1149 ext |= PHY_B_PEC_HIGH_LA;
1150
1151 }
1152
1153 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1154 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1155
1156 /* Use link status change interrupt */
1157 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1158
1159 bcom_check_link(hw, port);
1160 }
1161
1162 static void genesis_mac_init(struct skge_hw *hw, int port)
1163 {
1164 struct net_device *dev = hw->dev[port];
1165 struct skge_port *skge = netdev_priv(dev);
1166 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1167 int i;
1168 u32 r;
1169 const u8 zero[6] = { 0 };
1170
1171 for (i = 0; i < 10; i++) {
1172 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1173 MFF_SET_MAC_RST);
1174 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1175 goto reset_ok;
1176 udelay(1);
1177 }
1178
1179 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1180
1181 reset_ok:
1182 /* Unreset the XMAC. */
1183 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1184
1185 /*
1186 * Perform additional initialization for external PHYs,
1187 * namely for the 1000baseTX cards that use the XMAC's
1188 * GMII mode.
1189 */
1190 /* Take external Phy out of reset */
1191 r = skge_read32(hw, B2_GP_IO);
1192 if (port == 0)
1193 r |= GP_DIR_0|GP_IO_0;
1194 else
1195 r |= GP_DIR_2|GP_IO_2;
1196
1197 skge_write32(hw, B2_GP_IO, r);
1198
1199
1200 /* Enable GMII interface */
1201 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1202
1203 bcom_phy_init(skge, jumbo);
1204
1205 /* Set Station Address */
1206 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1207
1208 /* We don't use match addresses so clear */
1209 for (i = 1; i < 16; i++)
1210 xm_outaddr(hw, port, XM_EXM(i), zero);
1211
1212 /* Clear MIB counters */
1213 xm_write16(hw, port, XM_STAT_CMD,
1214 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1215 /* Clear two times according to Errata #3 */
1216 xm_write16(hw, port, XM_STAT_CMD,
1217 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1218
1219 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1220 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1221
1222 /* We don't need the FCS appended to the packet. */
1223 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1224 if (jumbo)
1225 r |= XM_RX_BIG_PK_OK;
1226
1227 if (skge->duplex == DUPLEX_HALF) {
1228 /*
1229 * If in manual half duplex mode the other side might be in
1230 * full duplex mode, so ignore if a carrier extension is not seen
1231 * on frames received
1232 */
1233 r |= XM_RX_DIS_CEXT;
1234 }
1235 xm_write16(hw, port, XM_RX_CMD, r);
1236
1237
1238 /* We want short frames padded to 60 bytes. */
1239 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1240
1241 /*
1242 * Bump up the transmit threshold. This helps hold off transmit
1243 * underruns when we're blasting traffic from both ports at once.
1244 */
1245 xm_write16(hw, port, XM_TX_THR, 512);
1246
1247 /*
1248 * Enable the reception of all error frames. This is is
1249 * a necessary evil due to the design of the XMAC. The
1250 * XMAC's receive FIFO is only 8K in size, however jumbo
1251 * frames can be up to 9000 bytes in length. When bad
1252 * frame filtering is enabled, the XMAC's RX FIFO operates
1253 * in 'store and forward' mode. For this to work, the
1254 * entire frame has to fit into the FIFO, but that means
1255 * that jumbo frames larger than 8192 bytes will be
1256 * truncated. Disabling all bad frame filtering causes
1257 * the RX FIFO to operate in streaming mode, in which
1258 * case the XMAC will start transferring frames out of the
1259 * RX FIFO as soon as the FIFO threshold is reached.
1260 */
1261 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1262
1263
1264 /*
1265 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1266 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1267 * and 'Octets Rx OK Hi Cnt Ov'.
1268 */
1269 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1270
1271 /*
1272 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1273 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1274 * and 'Octets Tx OK Hi Cnt Ov'.
1275 */
1276 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1277
1278 /* Configure MAC arbiter */
1279 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1280
1281 /* configure timeout values */
1282 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1283 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1284 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1285 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1286
1287 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1288 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1289 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1290 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1291
1292 /* Configure Rx MAC FIFO */
1293 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1294 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1295 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1296
1297 /* Configure Tx MAC FIFO */
1298 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1299 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1300 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1301
1302 if (jumbo) {
1303 /* Enable frame flushing if jumbo frames used */
1304 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1305 } else {
1306 /* enable timeout timers if normal frames */
1307 skge_write16(hw, B3_PA_CTRL,
1308 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1309 }
1310 }
1311
1312 static void genesis_stop(struct skge_port *skge)
1313 {
1314 struct skge_hw *hw = skge->hw;
1315 int port = skge->port;
1316 u32 reg;
1317
1318 genesis_reset(hw, port);
1319
1320 /* Clear Tx packet arbiter timeout IRQ */
1321 skge_write16(hw, B3_PA_CTRL,
1322 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1323
1324 /*
1325 * If the transfer sticks at the MAC the STOP command will not
1326 * terminate if we don't flush the XMAC's transmit FIFO !
1327 */
1328 xm_write32(hw, port, XM_MODE,
1329 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1330
1331
1332 /* Reset the MAC */
1333 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1334
1335 /* For external PHYs there must be special handling */
1336 reg = skge_read32(hw, B2_GP_IO);
1337 if (port == 0) {
1338 reg |= GP_DIR_0;
1339 reg &= ~GP_IO_0;
1340 } else {
1341 reg |= GP_DIR_2;
1342 reg &= ~GP_IO_2;
1343 }
1344 skge_write32(hw, B2_GP_IO, reg);
1345 skge_read32(hw, B2_GP_IO);
1346
1347 xm_write16(hw, port, XM_MMU_CMD,
1348 xm_read16(hw, port, XM_MMU_CMD)
1349 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1350
1351 xm_read16(hw, port, XM_MMU_CMD);
1352 }
1353
1354
1355 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1356 {
1357 struct skge_hw *hw = skge->hw;
1358 int port = skge->port;
1359 int i;
1360 unsigned long timeout = jiffies + HZ;
1361
1362 xm_write16(hw, port,
1363 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1364
1365 /* wait for update to complete */
1366 while (xm_read16(hw, port, XM_STAT_CMD)
1367 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1368 if (time_after(jiffies, timeout))
1369 break;
1370 udelay(10);
1371 }
1372
1373 /* special case for 64 bit octet counter */
1374 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1375 | xm_read32(hw, port, XM_TXO_OK_LO);
1376 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1377 | xm_read32(hw, port, XM_RXO_OK_LO);
1378
1379 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1380 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1381 }
1382
1383 static void genesis_mac_intr(struct skge_hw *hw, int port)
1384 {
1385 struct skge_port *skge = netdev_priv(hw->dev[port]);
1386 u16 status = xm_read16(hw, port, XM_ISRC);
1387
1388 if (netif_msg_intr(skge))
1389 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1390 skge->netdev->name, status);
1391
1392 if (status & XM_IS_TXF_UR) {
1393 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1394 ++skge->net_stats.tx_fifo_errors;
1395 }
1396 if (status & XM_IS_RXF_OV) {
1397 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1398 ++skge->net_stats.rx_fifo_errors;
1399 }
1400 }
1401
1402 static void genesis_link_up(struct skge_port *skge)
1403 {
1404 struct skge_hw *hw = skge->hw;
1405 int port = skge->port;
1406 u16 cmd;
1407 u32 mode, msk;
1408
1409 cmd = xm_read16(hw, port, XM_MMU_CMD);
1410
1411 /*
1412 * enabling pause frame reception is required for 1000BT
1413 * because the XMAC is not reset if the link is going down
1414 */
1415 if (skge->flow_control == FLOW_MODE_NONE ||
1416 skge->flow_control == FLOW_MODE_LOC_SEND)
1417 /* Disable Pause Frame Reception */
1418 cmd |= XM_MMU_IGN_PF;
1419 else
1420 /* Enable Pause Frame Reception */
1421 cmd &= ~XM_MMU_IGN_PF;
1422
1423 xm_write16(hw, port, XM_MMU_CMD, cmd);
1424
1425 mode = xm_read32(hw, port, XM_MODE);
1426 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1427 skge->flow_control == FLOW_MODE_LOC_SEND) {
1428 /*
1429 * Configure Pause Frame Generation
1430 * Use internal and external Pause Frame Generation.
1431 * Sending pause frames is edge triggered.
1432 * Send a Pause frame with the maximum pause time if
1433 * internal oder external FIFO full condition occurs.
1434 * Send a zero pause time frame to re-start transmission.
1435 */
1436 /* XM_PAUSE_DA = '010000C28001' (default) */
1437 /* XM_MAC_PTIME = 0xffff (maximum) */
1438 /* remember this value is defined in big endian (!) */
1439 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1440
1441 mode |= XM_PAUSE_MODE;
1442 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1443 } else {
1444 /*
1445 * disable pause frame generation is required for 1000BT
1446 * because the XMAC is not reset if the link is going down
1447 */
1448 /* Disable Pause Mode in Mode Register */
1449 mode &= ~XM_PAUSE_MODE;
1450
1451 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1452 }
1453
1454 xm_write32(hw, port, XM_MODE, mode);
1455
1456 msk = XM_DEF_MSK;
1457 /* disable GP0 interrupt bit for external Phy */
1458 msk |= XM_IS_INP_ASS;
1459
1460 xm_write16(hw, port, XM_IMSK, msk);
1461 xm_read16(hw, port, XM_ISRC);
1462
1463 /* get MMU Command Reg. */
1464 cmd = xm_read16(hw, port, XM_MMU_CMD);
1465 if (skge->duplex == DUPLEX_FULL)
1466 cmd |= XM_MMU_GMII_FD;
1467
1468 /*
1469 * Workaround BCOM Errata (#10523) for all BCom Phys
1470 * Enable Power Management after link up
1471 */
1472 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1473 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1474 & ~PHY_B_AC_DIS_PM);
1475 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1476
1477 /* enable Rx/Tx */
1478 xm_write16(hw, port, XM_MMU_CMD,
1479 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1480 skge_link_up(skge);
1481 }
1482
1483
1484 static inline void bcom_phy_intr(struct skge_port *skge)
1485 {
1486 struct skge_hw *hw = skge->hw;
1487 int port = skge->port;
1488 u16 isrc;
1489
1490 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1491 if (netif_msg_intr(skge))
1492 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1493 skge->netdev->name, isrc);
1494
1495 if (isrc & PHY_B_IS_PSE)
1496 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1497 hw->dev[port]->name);
1498
1499 /* Workaround BCom Errata:
1500 * enable and disable loopback mode if "NO HCD" occurs.
1501 */
1502 if (isrc & PHY_B_IS_NO_HDCL) {
1503 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1504 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1505 ctrl | PHY_CT_LOOP);
1506 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1507 ctrl & ~PHY_CT_LOOP);
1508 }
1509
1510 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1511 bcom_check_link(hw, port);
1512
1513 }
1514
1515 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1516 {
1517 int i;
1518
1519 gma_write16(hw, port, GM_SMI_DATA, val);
1520 gma_write16(hw, port, GM_SMI_CTRL,
1521 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1522 for (i = 0; i < PHY_RETRIES; i++) {
1523 udelay(1);
1524
1525 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1526 return 0;
1527 }
1528
1529 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1530 hw->dev[port]->name);
1531 return -EIO;
1532 }
1533
1534 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1535 {
1536 int i;
1537
1538 gma_write16(hw, port, GM_SMI_CTRL,
1539 GM_SMI_CT_PHY_AD(hw->phy_addr)
1540 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1541
1542 for (i = 0; i < PHY_RETRIES; i++) {
1543 udelay(1);
1544 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1545 goto ready;
1546 }
1547
1548 return -ETIMEDOUT;
1549 ready:
1550 *val = gma_read16(hw, port, GM_SMI_DATA);
1551 return 0;
1552 }
1553
1554 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1555 {
1556 u16 v = 0;
1557 if (__gm_phy_read(hw, port, reg, &v))
1558 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1559 hw->dev[port]->name);
1560 return v;
1561 }
1562
1563 /* Marvell Phy Initialization */
1564 static void yukon_init(struct skge_hw *hw, int port)
1565 {
1566 struct skge_port *skge = netdev_priv(hw->dev[port]);
1567 u16 ctrl, ct1000, adv;
1568
1569 if (skge->autoneg == AUTONEG_ENABLE) {
1570 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1571
1572 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1573 PHY_M_EC_MAC_S_MSK);
1574 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1575
1576 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1577
1578 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1579 }
1580
1581 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1582 if (skge->autoneg == AUTONEG_DISABLE)
1583 ctrl &= ~PHY_CT_ANE;
1584
1585 ctrl |= PHY_CT_RESET;
1586 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1587
1588 ctrl = 0;
1589 ct1000 = 0;
1590 adv = PHY_AN_CSMA;
1591
1592 if (skge->autoneg == AUTONEG_ENABLE) {
1593 if (hw->copper) {
1594 if (skge->advertising & ADVERTISED_1000baseT_Full)
1595 ct1000 |= PHY_M_1000C_AFD;
1596 if (skge->advertising & ADVERTISED_1000baseT_Half)
1597 ct1000 |= PHY_M_1000C_AHD;
1598 if (skge->advertising & ADVERTISED_100baseT_Full)
1599 adv |= PHY_M_AN_100_FD;
1600 if (skge->advertising & ADVERTISED_100baseT_Half)
1601 adv |= PHY_M_AN_100_HD;
1602 if (skge->advertising & ADVERTISED_10baseT_Full)
1603 adv |= PHY_M_AN_10_FD;
1604 if (skge->advertising & ADVERTISED_10baseT_Half)
1605 adv |= PHY_M_AN_10_HD;
1606 } else /* special defines for FIBER (88E1011S only) */
1607 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1608
1609 /* Set Flow-control capabilities */
1610 adv |= phy_pause_map[skge->flow_control];
1611
1612 /* Restart Auto-negotiation */
1613 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1614 } else {
1615 /* forced speed/duplex settings */
1616 ct1000 = PHY_M_1000C_MSE;
1617
1618 if (skge->duplex == DUPLEX_FULL)
1619 ctrl |= PHY_CT_DUP_MD;
1620
1621 switch (skge->speed) {
1622 case SPEED_1000:
1623 ctrl |= PHY_CT_SP1000;
1624 break;
1625 case SPEED_100:
1626 ctrl |= PHY_CT_SP100;
1627 break;
1628 }
1629
1630 ctrl |= PHY_CT_RESET;
1631 }
1632
1633 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1634
1635 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1636 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1637
1638 /* Enable phy interrupt on autonegotiation complete (or link up) */
1639 if (skge->autoneg == AUTONEG_ENABLE)
1640 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1641 else
1642 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1643 }
1644
1645 static void yukon_reset(struct skge_hw *hw, int port)
1646 {
1647 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1648 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1649 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1650 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1651 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1652
1653 gma_write16(hw, port, GM_RX_CTRL,
1654 gma_read16(hw, port, GM_RX_CTRL)
1655 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1656 }
1657
1658 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1659 static int is_yukon_lite_a0(struct skge_hw *hw)
1660 {
1661 u32 reg;
1662 int ret;
1663
1664 if (hw->chip_id != CHIP_ID_YUKON)
1665 return 0;
1666
1667 reg = skge_read32(hw, B2_FAR);
1668 skge_write8(hw, B2_FAR + 3, 0xff);
1669 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1670 skge_write32(hw, B2_FAR, reg);
1671 return ret;
1672 }
1673
1674 static void yukon_mac_init(struct skge_hw *hw, int port)
1675 {
1676 struct skge_port *skge = netdev_priv(hw->dev[port]);
1677 int i;
1678 u32 reg;
1679 const u8 *addr = hw->dev[port]->dev_addr;
1680
1681 /* WA code for COMA mode -- set PHY reset */
1682 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1683 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1684 reg = skge_read32(hw, B2_GP_IO);
1685 reg |= GP_DIR_9 | GP_IO_9;
1686 skge_write32(hw, B2_GP_IO, reg);
1687 }
1688
1689 /* hard reset */
1690 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1691 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1692
1693 /* WA code for COMA mode -- clear PHY reset */
1694 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1695 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1696 reg = skge_read32(hw, B2_GP_IO);
1697 reg |= GP_DIR_9;
1698 reg &= ~GP_IO_9;
1699 skge_write32(hw, B2_GP_IO, reg);
1700 }
1701
1702 /* Set hardware config mode */
1703 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1704 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1705 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1706
1707 /* Clear GMC reset */
1708 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1709 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1710 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1711
1712 if (skge->autoneg == AUTONEG_DISABLE) {
1713 reg = GM_GPCR_AU_ALL_DIS;
1714 gma_write16(hw, port, GM_GP_CTRL,
1715 gma_read16(hw, port, GM_GP_CTRL) | reg);
1716
1717 switch (skge->speed) {
1718 case SPEED_1000:
1719 reg &= ~GM_GPCR_SPEED_100;
1720 reg |= GM_GPCR_SPEED_1000;
1721 break;
1722 case SPEED_100:
1723 reg &= ~GM_GPCR_SPEED_1000;
1724 reg |= GM_GPCR_SPEED_100;
1725 break;
1726 case SPEED_10:
1727 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1728 break;
1729 }
1730
1731 if (skge->duplex == DUPLEX_FULL)
1732 reg |= GM_GPCR_DUP_FULL;
1733 } else
1734 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1735
1736 switch (skge->flow_control) {
1737 case FLOW_MODE_NONE:
1738 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1739 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1740 break;
1741 case FLOW_MODE_LOC_SEND:
1742 /* disable Rx flow-control */
1743 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1744 }
1745
1746 gma_write16(hw, port, GM_GP_CTRL, reg);
1747 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1748
1749 yukon_init(hw, port);
1750
1751 /* MIB clear */
1752 reg = gma_read16(hw, port, GM_PHY_ADDR);
1753 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1754
1755 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1756 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1757 gma_write16(hw, port, GM_PHY_ADDR, reg);
1758
1759 /* transmit control */
1760 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1761
1762 /* receive control reg: unicast + multicast + no FCS */
1763 gma_write16(hw, port, GM_RX_CTRL,
1764 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1765
1766 /* transmit flow control */
1767 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1768
1769 /* transmit parameter */
1770 gma_write16(hw, port, GM_TX_PARAM,
1771 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1772 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1773 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1774
1775 /* serial mode register */
1776 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1777 if (hw->dev[port]->mtu > 1500)
1778 reg |= GM_SMOD_JUMBO_ENA;
1779
1780 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1781
1782 /* physical address: used for pause frames */
1783 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1784 /* virtual address for data */
1785 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1786
1787 /* enable interrupt mask for counter overflows */
1788 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1789 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1790 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1791
1792 /* Initialize Mac Fifo */
1793
1794 /* Configure Rx MAC FIFO */
1795 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1796 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1797
1798 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1799 if (is_yukon_lite_a0(hw))
1800 reg &= ~GMF_RX_F_FL_ON;
1801
1802 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1803 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1804 /*
1805 * because Pause Packet Truncation in GMAC is not working
1806 * we have to increase the Flush Threshold to 64 bytes
1807 * in order to flush pause packets in Rx FIFO on Yukon-1
1808 */
1809 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1810
1811 /* Configure Tx MAC FIFO */
1812 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1813 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1814 }
1815
1816 /* Go into power down mode */
1817 static void yukon_suspend(struct skge_hw *hw, int port)
1818 {
1819 u16 ctrl;
1820
1821 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1822 ctrl |= PHY_M_PC_POL_R_DIS;
1823 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1824
1825 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1826 ctrl |= PHY_CT_RESET;
1827 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1828
1829 /* switch IEEE compatible power down mode on */
1830 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1831 ctrl |= PHY_CT_PDOWN;
1832 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1833 }
1834
1835 static void yukon_stop(struct skge_port *skge)
1836 {
1837 struct skge_hw *hw = skge->hw;
1838 int port = skge->port;
1839
1840 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1841 yukon_reset(hw, port);
1842
1843 gma_write16(hw, port, GM_GP_CTRL,
1844 gma_read16(hw, port, GM_GP_CTRL)
1845 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1846 gma_read16(hw, port, GM_GP_CTRL);
1847
1848 yukon_suspend(hw, port);
1849
1850 /* set GPHY Control reset */
1851 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1852 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1853 }
1854
1855 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1856 {
1857 struct skge_hw *hw = skge->hw;
1858 int port = skge->port;
1859 int i;
1860
1861 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1862 | gma_read32(hw, port, GM_TXO_OK_LO);
1863 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1864 | gma_read32(hw, port, GM_RXO_OK_LO);
1865
1866 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1867 data[i] = gma_read32(hw, port,
1868 skge_stats[i].gma_offset);
1869 }
1870
1871 static void yukon_mac_intr(struct skge_hw *hw, int port)
1872 {
1873 struct net_device *dev = hw->dev[port];
1874 struct skge_port *skge = netdev_priv(dev);
1875 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1876
1877 if (netif_msg_intr(skge))
1878 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1879 dev->name, status);
1880
1881 if (status & GM_IS_RX_FF_OR) {
1882 ++skge->net_stats.rx_fifo_errors;
1883 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1884 }
1885
1886 if (status & GM_IS_TX_FF_UR) {
1887 ++skge->net_stats.tx_fifo_errors;
1888 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1889 }
1890
1891 }
1892
1893 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1894 {
1895 switch (aux & PHY_M_PS_SPEED_MSK) {
1896 case PHY_M_PS_SPEED_1000:
1897 return SPEED_1000;
1898 case PHY_M_PS_SPEED_100:
1899 return SPEED_100;
1900 default:
1901 return SPEED_10;
1902 }
1903 }
1904
1905 static void yukon_link_up(struct skge_port *skge)
1906 {
1907 struct skge_hw *hw = skge->hw;
1908 int port = skge->port;
1909 u16 reg;
1910
1911 /* Enable Transmit FIFO Underrun */
1912 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1913
1914 reg = gma_read16(hw, port, GM_GP_CTRL);
1915 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1916 reg |= GM_GPCR_DUP_FULL;
1917
1918 /* enable Rx/Tx */
1919 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1920 gma_write16(hw, port, GM_GP_CTRL, reg);
1921
1922 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1923 skge_link_up(skge);
1924 }
1925
1926 static void yukon_link_down(struct skge_port *skge)
1927 {
1928 struct skge_hw *hw = skge->hw;
1929 int port = skge->port;
1930 u16 ctrl;
1931
1932 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1933
1934 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1935 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1936 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1937
1938 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1939 /* restore Asymmetric Pause bit */
1940 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1941 gm_phy_read(hw, port,
1942 PHY_MARV_AUNE_ADV)
1943 | PHY_M_AN_ASP);
1944
1945 }
1946
1947 yukon_reset(hw, port);
1948 skge_link_down(skge);
1949
1950 yukon_init(hw, port);
1951 }
1952
1953 static void yukon_phy_intr(struct skge_port *skge)
1954 {
1955 struct skge_hw *hw = skge->hw;
1956 int port = skge->port;
1957 const char *reason = NULL;
1958 u16 istatus, phystat;
1959
1960 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1961 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1962
1963 if (netif_msg_intr(skge))
1964 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1965 skge->netdev->name, istatus, phystat);
1966
1967 if (istatus & PHY_M_IS_AN_COMPL) {
1968 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1969 & PHY_M_AN_RF) {
1970 reason = "remote fault";
1971 goto failed;
1972 }
1973
1974 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1975 reason = "master/slave fault";
1976 goto failed;
1977 }
1978
1979 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1980 reason = "speed/duplex";
1981 goto failed;
1982 }
1983
1984 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1985 ? DUPLEX_FULL : DUPLEX_HALF;
1986 skge->speed = yukon_speed(hw, phystat);
1987
1988 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1989 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1990 case PHY_M_PS_PAUSE_MSK:
1991 skge->flow_control = FLOW_MODE_SYMMETRIC;
1992 break;
1993 case PHY_M_PS_RX_P_EN:
1994 skge->flow_control = FLOW_MODE_REM_SEND;
1995 break;
1996 case PHY_M_PS_TX_P_EN:
1997 skge->flow_control = FLOW_MODE_LOC_SEND;
1998 break;
1999 default:
2000 skge->flow_control = FLOW_MODE_NONE;
2001 }
2002
2003 if (skge->flow_control == FLOW_MODE_NONE ||
2004 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2005 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2006 else
2007 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2008 yukon_link_up(skge);
2009 return;
2010 }
2011
2012 if (istatus & PHY_M_IS_LSP_CHANGE)
2013 skge->speed = yukon_speed(hw, phystat);
2014
2015 if (istatus & PHY_M_IS_DUP_CHANGE)
2016 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2017 if (istatus & PHY_M_IS_LST_CHANGE) {
2018 if (phystat & PHY_M_PS_LINK_UP)
2019 yukon_link_up(skge);
2020 else
2021 yukon_link_down(skge);
2022 }
2023 return;
2024 failed:
2025 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2026 skge->netdev->name, reason);
2027
2028 /* XXX restart autonegotiation? */
2029 }
2030
2031 static void skge_phy_reset(struct skge_port *skge)
2032 {
2033 struct skge_hw *hw = skge->hw;
2034 int port = skge->port;
2035
2036 netif_stop_queue(skge->netdev);
2037 netif_carrier_off(skge->netdev);
2038
2039 mutex_lock(&hw->phy_mutex);
2040 if (hw->chip_id == CHIP_ID_GENESIS) {
2041 genesis_reset(hw, port);
2042 genesis_mac_init(hw, port);
2043 } else {
2044 yukon_reset(hw, port);
2045 yukon_init(hw, port);
2046 }
2047 mutex_unlock(&hw->phy_mutex);
2048 }
2049
2050 /* Basic MII support */
2051 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2052 {
2053 struct mii_ioctl_data *data = if_mii(ifr);
2054 struct skge_port *skge = netdev_priv(dev);
2055 struct skge_hw *hw = skge->hw;
2056 int err = -EOPNOTSUPP;
2057
2058 if (!netif_running(dev))
2059 return -ENODEV; /* Phy still in reset */
2060
2061 switch(cmd) {
2062 case SIOCGMIIPHY:
2063 data->phy_id = hw->phy_addr;
2064
2065 /* fallthru */
2066 case SIOCGMIIREG: {
2067 u16 val = 0;
2068 mutex_lock(&hw->phy_mutex);
2069 if (hw->chip_id == CHIP_ID_GENESIS)
2070 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2071 else
2072 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2073 mutex_unlock(&hw->phy_mutex);
2074 data->val_out = val;
2075 break;
2076 }
2077
2078 case SIOCSMIIREG:
2079 if (!capable(CAP_NET_ADMIN))
2080 return -EPERM;
2081
2082 mutex_lock(&hw->phy_mutex);
2083 if (hw->chip_id == CHIP_ID_GENESIS)
2084 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2085 data->val_in);
2086 else
2087 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2088 data->val_in);
2089 mutex_unlock(&hw->phy_mutex);
2090 break;
2091 }
2092 return err;
2093 }
2094
2095 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2096 {
2097 u32 end;
2098
2099 start /= 8;
2100 len /= 8;
2101 end = start + len - 1;
2102
2103 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2104 skge_write32(hw, RB_ADDR(q, RB_START), start);
2105 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2106 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2107 skge_write32(hw, RB_ADDR(q, RB_END), end);
2108
2109 if (q == Q_R1 || q == Q_R2) {
2110 /* Set thresholds on receive queue's */
2111 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2112 start + (2*len)/3);
2113 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2114 start + (len/3));
2115 } else {
2116 /* Enable store & forward on Tx queue's because
2117 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2118 */
2119 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2120 }
2121
2122 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2123 }
2124
2125 /* Setup Bus Memory Interface */
2126 static void skge_qset(struct skge_port *skge, u16 q,
2127 const struct skge_element *e)
2128 {
2129 struct skge_hw *hw = skge->hw;
2130 u32 watermark = 0x600;
2131 u64 base = skge->dma + (e->desc - skge->mem);
2132
2133 /* optimization to reduce window on 32bit/33mhz */
2134 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2135 watermark /= 2;
2136
2137 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2138 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2139 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2140 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2141 }
2142
2143 static int skge_up(struct net_device *dev)
2144 {
2145 struct skge_port *skge = netdev_priv(dev);
2146 struct skge_hw *hw = skge->hw;
2147 int port = skge->port;
2148 u32 chunk, ram_addr;
2149 size_t rx_size, tx_size;
2150 int err;
2151
2152 if (netif_msg_ifup(skge))
2153 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2154
2155 if (dev->mtu > RX_BUF_SIZE)
2156 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2157 else
2158 skge->rx_buf_size = RX_BUF_SIZE;
2159
2160
2161 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2162 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2163 skge->mem_size = tx_size + rx_size;
2164 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2165 if (!skge->mem)
2166 return -ENOMEM;
2167
2168 BUG_ON(skge->dma & 7);
2169
2170 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2171 printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
2172 err = -EINVAL;
2173 goto free_pci_mem;
2174 }
2175
2176 memset(skge->mem, 0, skge->mem_size);
2177
2178 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2179 if (err)
2180 goto free_pci_mem;
2181
2182 err = skge_rx_fill(skge);
2183 if (err)
2184 goto free_rx_ring;
2185
2186 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2187 skge->dma + rx_size);
2188 if (err)
2189 goto free_rx_ring;
2190
2191 /* Initialize MAC */
2192 mutex_lock(&hw->phy_mutex);
2193 if (hw->chip_id == CHIP_ID_GENESIS)
2194 genesis_mac_init(hw, port);
2195 else
2196 yukon_mac_init(hw, port);
2197 mutex_unlock(&hw->phy_mutex);
2198
2199 /* Configure RAMbuffers */
2200 chunk = hw->ram_size / ((hw->ports + 1)*2);
2201 ram_addr = hw->ram_offset + 2 * chunk * port;
2202
2203 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2204 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2205
2206 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2207 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2208 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2209
2210 /* Start receiver BMU */
2211 wmb();
2212 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2213 skge_led(skge, LED_MODE_ON);
2214
2215 netif_poll_enable(dev);
2216 return 0;
2217
2218 free_rx_ring:
2219 skge_rx_clean(skge);
2220 kfree(skge->rx_ring.start);
2221 free_pci_mem:
2222 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2223 skge->mem = NULL;
2224
2225 return err;
2226 }
2227
2228 static int skge_down(struct net_device *dev)
2229 {
2230 struct skge_port *skge = netdev_priv(dev);
2231 struct skge_hw *hw = skge->hw;
2232 int port = skge->port;
2233
2234 if (skge->mem == NULL)
2235 return 0;
2236
2237 if (netif_msg_ifdown(skge))
2238 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2239
2240 netif_stop_queue(dev);
2241
2242 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2243 if (hw->chip_id == CHIP_ID_GENESIS)
2244 genesis_stop(skge);
2245 else
2246 yukon_stop(skge);
2247
2248 /* Stop transmitter */
2249 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2250 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2251 RB_RST_SET|RB_DIS_OP_MD);
2252
2253
2254 /* Disable Force Sync bit and Enable Alloc bit */
2255 skge_write8(hw, SK_REG(port, TXA_CTRL),
2256 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2257
2258 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2259 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2260 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2261
2262 /* Reset PCI FIFO */
2263 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2264 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2265
2266 /* Reset the RAM Buffer async Tx queue */
2267 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2268 /* stop receiver */
2269 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2270 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2271 RB_RST_SET|RB_DIS_OP_MD);
2272 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2273
2274 if (hw->chip_id == CHIP_ID_GENESIS) {
2275 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2276 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2277 } else {
2278 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2279 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2280 }
2281
2282 skge_led(skge, LED_MODE_OFF);
2283
2284 netif_poll_disable(dev);
2285 skge_tx_clean(skge);
2286 skge_rx_clean(skge);
2287
2288 kfree(skge->rx_ring.start);
2289 kfree(skge->tx_ring.start);
2290 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2291 skge->mem = NULL;
2292 return 0;
2293 }
2294
2295 static inline int skge_avail(const struct skge_ring *ring)
2296 {
2297 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2298 + (ring->to_clean - ring->to_use) - 1;
2299 }
2300
2301 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2302 {
2303 struct skge_port *skge = netdev_priv(dev);
2304 struct skge_hw *hw = skge->hw;
2305 struct skge_element *e;
2306 struct skge_tx_desc *td;
2307 int i;
2308 u32 control, len;
2309 u64 map;
2310 unsigned long flags;
2311
2312 if (skb_padto(skb, ETH_ZLEN))
2313 return NETDEV_TX_OK;
2314
2315 if (!spin_trylock_irqsave(&skge->tx_lock, flags))
2316 /* Collision - tell upper layer to requeue */
2317 return NETDEV_TX_LOCKED;
2318
2319 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1)) {
2320 if (!netif_queue_stopped(dev)) {
2321 netif_stop_queue(dev);
2322
2323 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2324 dev->name);
2325 }
2326 spin_unlock_irqrestore(&skge->tx_lock, flags);
2327 return NETDEV_TX_BUSY;
2328 }
2329
2330 e = skge->tx_ring.to_use;
2331 td = e->desc;
2332 BUG_ON(td->control & BMU_OWN);
2333 e->skb = skb;
2334 len = skb_headlen(skb);
2335 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2336 pci_unmap_addr_set(e, mapaddr, map);
2337 pci_unmap_len_set(e, maplen, len);
2338
2339 td->dma_lo = map;
2340 td->dma_hi = map >> 32;
2341
2342 if (skb->ip_summed == CHECKSUM_HW) {
2343 int offset = skb->h.raw - skb->data;
2344
2345 /* This seems backwards, but it is what the sk98lin
2346 * does. Looks like hardware is wrong?
2347 */
2348 if (skb->h.ipiph->protocol == IPPROTO_UDP
2349 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2350 control = BMU_TCP_CHECK;
2351 else
2352 control = BMU_UDP_CHECK;
2353
2354 td->csum_offs = 0;
2355 td->csum_start = offset;
2356 td->csum_write = offset + skb->csum;
2357 } else
2358 control = BMU_CHECK;
2359
2360 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2361 control |= BMU_EOF| BMU_IRQ_EOF;
2362 else {
2363 struct skge_tx_desc *tf = td;
2364
2365 control |= BMU_STFWD;
2366 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2367 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2368
2369 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2370 frag->size, PCI_DMA_TODEVICE);
2371
2372 e = e->next;
2373 e->skb = skb;
2374 tf = e->desc;
2375 BUG_ON(tf->control & BMU_OWN);
2376
2377 tf->dma_lo = map;
2378 tf->dma_hi = (u64) map >> 32;
2379 pci_unmap_addr_set(e, mapaddr, map);
2380 pci_unmap_len_set(e, maplen, frag->size);
2381
2382 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2383 }
2384 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2385 }
2386 /* Make sure all the descriptors written */
2387 wmb();
2388 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2389 wmb();
2390
2391 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2392
2393 if (unlikely(netif_msg_tx_queued(skge)))
2394 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2395 dev->name, e - skge->tx_ring.start, skb->len);
2396
2397 skge->tx_ring.to_use = e->next;
2398 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2399 pr_debug("%s: transmit queue full\n", dev->name);
2400 netif_stop_queue(dev);
2401 }
2402
2403 spin_unlock_irqrestore(&skge->tx_lock, flags);
2404
2405 dev->trans_start = jiffies;
2406
2407 return NETDEV_TX_OK;
2408 }
2409
2410
2411 /* Free resources associated with this reing element */
2412 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2413 u32 control)
2414 {
2415 struct pci_dev *pdev = skge->hw->pdev;
2416
2417 BUG_ON(!e->skb);
2418
2419 /* skb header vs. fragment */
2420 if (control & BMU_STF)
2421 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2422 pci_unmap_len(e, maplen),
2423 PCI_DMA_TODEVICE);
2424 else
2425 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2426 pci_unmap_len(e, maplen),
2427 PCI_DMA_TODEVICE);
2428
2429 if (control & BMU_EOF) {
2430 if (unlikely(netif_msg_tx_done(skge)))
2431 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2432 skge->netdev->name, e - skge->tx_ring.start);
2433
2434 dev_kfree_skb_any(e->skb);
2435 }
2436 e->skb = NULL;
2437 }
2438
2439 /* Free all buffers in transmit ring */
2440 static void skge_tx_clean(struct skge_port *skge)
2441 {
2442 struct skge_element *e;
2443 unsigned long flags;
2444
2445 spin_lock_irqsave(&skge->tx_lock, flags);
2446 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2447 struct skge_tx_desc *td = e->desc;
2448 skge_tx_free(skge, e, td->control);
2449 td->control = 0;
2450 }
2451
2452 skge->tx_ring.to_clean = e;
2453 netif_wake_queue(skge->netdev);
2454 spin_unlock_irqrestore(&skge->tx_lock, flags);
2455 }
2456
2457 static void skge_tx_timeout(struct net_device *dev)
2458 {
2459 struct skge_port *skge = netdev_priv(dev);
2460
2461 if (netif_msg_timer(skge))
2462 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2463
2464 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2465 skge_tx_clean(skge);
2466 }
2467
2468 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2469 {
2470 int err;
2471
2472 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2473 return -EINVAL;
2474
2475 if (!netif_running(dev)) {
2476 dev->mtu = new_mtu;
2477 return 0;
2478 }
2479
2480 skge_down(dev);
2481
2482 dev->mtu = new_mtu;
2483
2484 err = skge_up(dev);
2485 if (err)
2486 dev_close(dev);
2487
2488 return err;
2489 }
2490
2491 static void genesis_set_multicast(struct net_device *dev)
2492 {
2493 struct skge_port *skge = netdev_priv(dev);
2494 struct skge_hw *hw = skge->hw;
2495 int port = skge->port;
2496 int i, count = dev->mc_count;
2497 struct dev_mc_list *list = dev->mc_list;
2498 u32 mode;
2499 u8 filter[8];
2500
2501 mode = xm_read32(hw, port, XM_MODE);
2502 mode |= XM_MD_ENA_HASH;
2503 if (dev->flags & IFF_PROMISC)
2504 mode |= XM_MD_ENA_PROM;
2505 else
2506 mode &= ~XM_MD_ENA_PROM;
2507
2508 if (dev->flags & IFF_ALLMULTI)
2509 memset(filter, 0xff, sizeof(filter));
2510 else {
2511 memset(filter, 0, sizeof(filter));
2512 for (i = 0; list && i < count; i++, list = list->next) {
2513 u32 crc, bit;
2514 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2515 bit = ~crc & 0x3f;
2516 filter[bit/8] |= 1 << (bit%8);
2517 }
2518 }
2519
2520 xm_write32(hw, port, XM_MODE, mode);
2521 xm_outhash(hw, port, XM_HSM, filter);
2522 }
2523
2524 static void yukon_set_multicast(struct net_device *dev)
2525 {
2526 struct skge_port *skge = netdev_priv(dev);
2527 struct skge_hw *hw = skge->hw;
2528 int port = skge->port;
2529 struct dev_mc_list *list = dev->mc_list;
2530 u16 reg;
2531 u8 filter[8];
2532
2533 memset(filter, 0, sizeof(filter));
2534
2535 reg = gma_read16(hw, port, GM_RX_CTRL);
2536 reg |= GM_RXCR_UCF_ENA;
2537
2538 if (dev->flags & IFF_PROMISC) /* promiscuous */
2539 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2540 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2541 memset(filter, 0xff, sizeof(filter));
2542 else if (dev->mc_count == 0) /* no multicast */
2543 reg &= ~GM_RXCR_MCF_ENA;
2544 else {
2545 int i;
2546 reg |= GM_RXCR_MCF_ENA;
2547
2548 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2549 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2550 filter[bit/8] |= 1 << (bit%8);
2551 }
2552 }
2553
2554
2555 gma_write16(hw, port, GM_MC_ADDR_H1,
2556 (u16)filter[0] | ((u16)filter[1] << 8));
2557 gma_write16(hw, port, GM_MC_ADDR_H2,
2558 (u16)filter[2] | ((u16)filter[3] << 8));
2559 gma_write16(hw, port, GM_MC_ADDR_H3,
2560 (u16)filter[4] | ((u16)filter[5] << 8));
2561 gma_write16(hw, port, GM_MC_ADDR_H4,
2562 (u16)filter[6] | ((u16)filter[7] << 8));
2563
2564 gma_write16(hw, port, GM_RX_CTRL, reg);
2565 }
2566
2567 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2568 {
2569 if (hw->chip_id == CHIP_ID_GENESIS)
2570 return status >> XMR_FS_LEN_SHIFT;
2571 else
2572 return status >> GMR_FS_LEN_SHIFT;
2573 }
2574
2575 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2576 {
2577 if (hw->chip_id == CHIP_ID_GENESIS)
2578 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2579 else
2580 return (status & GMR_FS_ANY_ERR) ||
2581 (status & GMR_FS_RX_OK) == 0;
2582 }
2583
2584
2585 /* Get receive buffer from descriptor.
2586 * Handles copy of small buffers and reallocation failures
2587 */
2588 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2589 struct skge_element *e,
2590 u32 control, u32 status, u16 csum)
2591 {
2592 struct sk_buff *skb;
2593 u16 len = control & BMU_BBC;
2594
2595 if (unlikely(netif_msg_rx_status(skge)))
2596 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2597 skge->netdev->name, e - skge->rx_ring.start,
2598 status, len);
2599
2600 if (len > skge->rx_buf_size)
2601 goto error;
2602
2603 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2604 goto error;
2605
2606 if (bad_phy_status(skge->hw, status))
2607 goto error;
2608
2609 if (phy_length(skge->hw, status) != len)
2610 goto error;
2611
2612 if (len < RX_COPY_THRESHOLD) {
2613 skb = dev_alloc_skb(len + 2);
2614 if (!skb)
2615 goto resubmit;
2616
2617 skb_reserve(skb, 2);
2618 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2619 pci_unmap_addr(e, mapaddr),
2620 len, PCI_DMA_FROMDEVICE);
2621 memcpy(skb->data, e->skb->data, len);
2622 pci_dma_sync_single_for_device(skge->hw->pdev,
2623 pci_unmap_addr(e, mapaddr),
2624 len, PCI_DMA_FROMDEVICE);
2625 skge_rx_reuse(e, skge->rx_buf_size);
2626 } else {
2627 struct sk_buff *nskb;
2628 nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
2629 if (!nskb)
2630 goto resubmit;
2631
2632 skb_reserve(nskb, NET_IP_ALIGN);
2633 pci_unmap_single(skge->hw->pdev,
2634 pci_unmap_addr(e, mapaddr),
2635 pci_unmap_len(e, maplen),
2636 PCI_DMA_FROMDEVICE);
2637 skb = e->skb;
2638 prefetch(skb->data);
2639 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2640 }
2641
2642 skb_put(skb, len);
2643 skb->dev = skge->netdev;
2644 if (skge->rx_csum) {
2645 skb->csum = csum;
2646 skb->ip_summed = CHECKSUM_HW;
2647 }
2648
2649 skb->protocol = eth_type_trans(skb, skge->netdev);
2650
2651 return skb;
2652 error:
2653
2654 if (netif_msg_rx_err(skge))
2655 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2656 skge->netdev->name, e - skge->rx_ring.start,
2657 control, status);
2658
2659 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2660 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2661 skge->net_stats.rx_length_errors++;
2662 if (status & XMR_FS_FRA_ERR)
2663 skge->net_stats.rx_frame_errors++;
2664 if (status & XMR_FS_FCS_ERR)
2665 skge->net_stats.rx_crc_errors++;
2666 } else {
2667 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2668 skge->net_stats.rx_length_errors++;
2669 if (status & GMR_FS_FRAGMENT)
2670 skge->net_stats.rx_frame_errors++;
2671 if (status & GMR_FS_CRC_ERR)
2672 skge->net_stats.rx_crc_errors++;
2673 }
2674
2675 resubmit:
2676 skge_rx_reuse(e, skge->rx_buf_size);
2677 return NULL;
2678 }
2679
2680 /* Free all buffers in Tx ring which are no longer owned by device */
2681 static void skge_txirq(struct net_device *dev)
2682 {
2683 struct skge_port *skge = netdev_priv(dev);
2684 struct skge_ring *ring = &skge->tx_ring;
2685 struct skge_element *e;
2686
2687 rmb();
2688
2689 spin_lock(&skge->tx_lock);
2690 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2691 struct skge_tx_desc *td = e->desc;
2692
2693 if (td->control & BMU_OWN)
2694 break;
2695
2696 skge_tx_free(skge, e, td->control);
2697 }
2698 skge->tx_ring.to_clean = e;
2699
2700 if (netif_queue_stopped(skge->netdev)
2701 && skge_avail(&skge->tx_ring) > TX_LOW_WATER)
2702 netif_wake_queue(skge->netdev);
2703
2704 spin_unlock(&skge->tx_lock);
2705 }
2706
2707 static int skge_poll(struct net_device *dev, int *budget)
2708 {
2709 struct skge_port *skge = netdev_priv(dev);
2710 struct skge_hw *hw = skge->hw;
2711 struct skge_ring *ring = &skge->rx_ring;
2712 struct skge_element *e;
2713 int to_do = min(dev->quota, *budget);
2714 int work_done = 0;
2715
2716 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2717 struct skge_rx_desc *rd = e->desc;
2718 struct sk_buff *skb;
2719 u32 control;
2720
2721 rmb();
2722 control = rd->control;
2723 if (control & BMU_OWN)
2724 break;
2725
2726 skb = skge_rx_get(skge, e, control, rd->status, rd->csum2);
2727 if (likely(skb)) {
2728 dev->last_rx = jiffies;
2729 netif_receive_skb(skb);
2730
2731 ++work_done;
2732 }
2733 }
2734 ring->to_clean = e;
2735
2736 /* restart receiver */
2737 wmb();
2738 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
2739
2740 *budget -= work_done;
2741 dev->quota -= work_done;
2742
2743 if (work_done >= to_do)
2744 return 1; /* not done */
2745
2746 netif_rx_complete(dev);
2747
2748 spin_lock_irq(&hw->hw_lock);
2749 hw->intr_mask |= rxirqmask[skge->port];
2750 skge_write32(hw, B0_IMSK, hw->intr_mask);
2751 skge_read32(hw, B0_IMSK);
2752 spin_unlock_irq(&hw->hw_lock);
2753
2754 return 0;
2755 }
2756
2757 /* Parity errors seem to happen when Genesis is connected to a switch
2758 * with no other ports present. Heartbeat error??
2759 */
2760 static void skge_mac_parity(struct skge_hw *hw, int port)
2761 {
2762 struct net_device *dev = hw->dev[port];
2763
2764 if (dev) {
2765 struct skge_port *skge = netdev_priv(dev);
2766 ++skge->net_stats.tx_heartbeat_errors;
2767 }
2768
2769 if (hw->chip_id == CHIP_ID_GENESIS)
2770 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2771 MFF_CLR_PERR);
2772 else
2773 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2774 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2775 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2776 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2777 }
2778
2779 static void skge_mac_intr(struct skge_hw *hw, int port)
2780 {
2781 if (hw->chip_id == CHIP_ID_GENESIS)
2782 genesis_mac_intr(hw, port);
2783 else
2784 yukon_mac_intr(hw, port);
2785 }
2786
2787 /* Handle device specific framing and timeout interrupts */
2788 static void skge_error_irq(struct skge_hw *hw)
2789 {
2790 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2791
2792 if (hw->chip_id == CHIP_ID_GENESIS) {
2793 /* clear xmac errors */
2794 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2795 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2796 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2797 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2798 } else {
2799 /* Timestamp (unused) overflow */
2800 if (hwstatus & IS_IRQ_TIST_OV)
2801 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2802 }
2803
2804 if (hwstatus & IS_RAM_RD_PAR) {
2805 printk(KERN_ERR PFX "Ram read data parity error\n");
2806 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2807 }
2808
2809 if (hwstatus & IS_RAM_WR_PAR) {
2810 printk(KERN_ERR PFX "Ram write data parity error\n");
2811 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2812 }
2813
2814 if (hwstatus & IS_M1_PAR_ERR)
2815 skge_mac_parity(hw, 0);
2816
2817 if (hwstatus & IS_M2_PAR_ERR)
2818 skge_mac_parity(hw, 1);
2819
2820 if (hwstatus & IS_R1_PAR_ERR) {
2821 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2822 hw->dev[0]->name);
2823 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2824 }
2825
2826 if (hwstatus & IS_R2_PAR_ERR) {
2827 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2828 hw->dev[1]->name);
2829 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2830 }
2831
2832 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2833 u16 pci_status, pci_cmd;
2834
2835 pci_read_config_word(hw->pdev, PCI_COMMAND, &pci_cmd);
2836 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
2837
2838 printk(KERN_ERR PFX "%s: PCI error cmd=%#x status=%#x\n",
2839 pci_name(hw->pdev), pci_cmd, pci_status);
2840
2841 /* Write the error bits back to clear them. */
2842 pci_status &= PCI_STATUS_ERROR_BITS;
2843 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2844 pci_write_config_word(hw->pdev, PCI_COMMAND,
2845 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2846 pci_write_config_word(hw->pdev, PCI_STATUS, pci_status);
2847 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2848
2849 /* if error still set then just ignore it */
2850 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2851 if (hwstatus & IS_IRQ_STAT) {
2852 printk(KERN_INFO PFX "unable to clear error (so ignoring them)\n");
2853 hw->intr_mask &= ~IS_HW_ERR;
2854 }
2855 }
2856 }
2857
2858 /*
2859 * Interrupt from PHY are handled in work queue
2860 * because accessing phy registers requires spin wait which might
2861 * cause excess interrupt latency.
2862 */
2863 static void skge_extirq(void *arg)
2864 {
2865 struct skge_hw *hw = arg;
2866 int port;
2867
2868 mutex_lock(&hw->phy_mutex);
2869 for (port = 0; port < hw->ports; port++) {
2870 struct net_device *dev = hw->dev[port];
2871 struct skge_port *skge = netdev_priv(dev);
2872
2873 if (netif_running(dev)) {
2874 if (hw->chip_id != CHIP_ID_GENESIS)
2875 yukon_phy_intr(skge);
2876 else
2877 bcom_phy_intr(skge);
2878 }
2879 }
2880 mutex_unlock(&hw->phy_mutex);
2881
2882 spin_lock_irq(&hw->hw_lock);
2883 hw->intr_mask |= IS_EXT_REG;
2884 skge_write32(hw, B0_IMSK, hw->intr_mask);
2885 skge_read32(hw, B0_IMSK);
2886 spin_unlock_irq(&hw->hw_lock);
2887 }
2888
2889 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2890 {
2891 struct skge_hw *hw = dev_id;
2892 u32 status;
2893
2894 /* Reading this register masks IRQ */
2895 status = skge_read32(hw, B0_SP_ISRC);
2896 if (status == 0)
2897 return IRQ_NONE;
2898
2899 spin_lock(&hw->hw_lock);
2900 status &= hw->intr_mask;
2901 if (status & IS_EXT_REG) {
2902 hw->intr_mask &= ~IS_EXT_REG;
2903 schedule_work(&hw->phy_work);
2904 }
2905
2906 if (status & IS_XA1_F) {
2907 skge_write8(hw, Q_ADDR(Q_XA1, Q_CSR), CSR_IRQ_CL_F);
2908 skge_txirq(hw->dev[0]);
2909 }
2910
2911 if (status & IS_R1_F) {
2912 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
2913 hw->intr_mask &= ~IS_R1_F;
2914 netif_rx_schedule(hw->dev[0]);
2915 }
2916
2917 if (status & IS_PA_TO_TX1)
2918 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2919
2920 if (status & IS_PA_TO_RX1) {
2921 struct skge_port *skge = netdev_priv(hw->dev[0]);
2922
2923 ++skge->net_stats.rx_over_errors;
2924 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2925 }
2926
2927
2928 if (status & IS_MAC1)
2929 skge_mac_intr(hw, 0);
2930
2931 if (hw->dev[1]) {
2932 if (status & IS_XA2_F) {
2933 skge_write8(hw, Q_ADDR(Q_XA2, Q_CSR), CSR_IRQ_CL_F);
2934 skge_txirq(hw->dev[1]);
2935 }
2936
2937 if (status & IS_R2_F) {
2938 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
2939 hw->intr_mask &= ~IS_R2_F;
2940 netif_rx_schedule(hw->dev[1]);
2941 }
2942
2943 if (status & IS_PA_TO_RX2) {
2944 struct skge_port *skge = netdev_priv(hw->dev[1]);
2945 ++skge->net_stats.rx_over_errors;
2946 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2947 }
2948
2949 if (status & IS_PA_TO_TX2)
2950 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2951
2952 if (status & IS_MAC2)
2953 skge_mac_intr(hw, 1);
2954 }
2955
2956 if (status & IS_HW_ERR)
2957 skge_error_irq(hw);
2958
2959 skge_write32(hw, B0_IMSK, hw->intr_mask);
2960 skge_read32(hw, B0_IMSK);
2961 spin_unlock(&hw->hw_lock);
2962
2963 return IRQ_HANDLED;
2964 }
2965
2966 #ifdef CONFIG_NET_POLL_CONTROLLER
2967 static void skge_netpoll(struct net_device *dev)
2968 {
2969 struct skge_port *skge = netdev_priv(dev);
2970
2971 disable_irq(dev->irq);
2972 skge_intr(dev->irq, skge->hw, NULL);
2973 enable_irq(dev->irq);
2974 }
2975 #endif
2976
2977 static int skge_set_mac_address(struct net_device *dev, void *p)
2978 {
2979 struct skge_port *skge = netdev_priv(dev);
2980 struct skge_hw *hw = skge->hw;
2981 unsigned port = skge->port;
2982 const struct sockaddr *addr = p;
2983
2984 if (!is_valid_ether_addr(addr->sa_data))
2985 return -EADDRNOTAVAIL;
2986
2987 mutex_lock(&hw->phy_mutex);
2988 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2989 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
2990 dev->dev_addr, ETH_ALEN);
2991 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
2992 dev->dev_addr, ETH_ALEN);
2993
2994 if (hw->chip_id == CHIP_ID_GENESIS)
2995 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2996 else {
2997 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2998 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2999 }
3000 mutex_unlock(&hw->phy_mutex);
3001
3002 return 0;
3003 }
3004
3005 static const struct {
3006 u8 id;
3007 const char *name;
3008 } skge_chips[] = {
3009 { CHIP_ID_GENESIS, "Genesis" },
3010 { CHIP_ID_YUKON, "Yukon" },
3011 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3012 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3013 };
3014
3015 static const char *skge_board_name(const struct skge_hw *hw)
3016 {
3017 int i;
3018 static char buf[16];
3019
3020 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3021 if (skge_chips[i].id == hw->chip_id)
3022 return skge_chips[i].name;
3023
3024 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3025 return buf;
3026 }
3027
3028
3029 /*
3030 * Setup the board data structure, but don't bring up
3031 * the port(s)
3032 */
3033 static int skge_reset(struct skge_hw *hw)
3034 {
3035 u32 reg;
3036 u16 ctst, pci_status;
3037 u8 t8, mac_cfg, pmd_type, phy_type;
3038 int i;
3039
3040 ctst = skge_read16(hw, B0_CTST);
3041
3042 /* do a SW reset */
3043 skge_write8(hw, B0_CTST, CS_RST_SET);
3044 skge_write8(hw, B0_CTST, CS_RST_CLR);
3045
3046 /* clear PCI errors, if any */
3047 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3048 skge_write8(hw, B2_TST_CTRL2, 0);
3049
3050 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3051 pci_write_config_word(hw->pdev, PCI_STATUS,
3052 pci_status | PCI_STATUS_ERROR_BITS);
3053 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3054 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3055
3056 /* restore CLK_RUN bits (for Yukon-Lite) */
3057 skge_write16(hw, B0_CTST,
3058 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3059
3060 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3061 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3062 pmd_type = skge_read8(hw, B2_PMD_TYP);
3063 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3064
3065 switch (hw->chip_id) {
3066 case CHIP_ID_GENESIS:
3067 switch (phy_type) {
3068 case SK_PHY_BCOM:
3069 hw->phy_addr = PHY_ADDR_BCOM;
3070 break;
3071 default:
3072 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
3073 pci_name(hw->pdev), phy_type);
3074 return -EOPNOTSUPP;
3075 }
3076 break;
3077
3078 case CHIP_ID_YUKON:
3079 case CHIP_ID_YUKON_LITE:
3080 case CHIP_ID_YUKON_LP:
3081 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3082 hw->copper = 1;
3083
3084 hw->phy_addr = PHY_ADDR_MARV;
3085 break;
3086
3087 default:
3088 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3089 pci_name(hw->pdev), hw->chip_id);
3090 return -EOPNOTSUPP;
3091 }
3092
3093 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3094 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3095 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3096
3097 /* read the adapters RAM size */
3098 t8 = skge_read8(hw, B2_E_0);
3099 if (hw->chip_id == CHIP_ID_GENESIS) {
3100 if (t8 == 3) {
3101 /* special case: 4 x 64k x 36, offset = 0x80000 */
3102 hw->ram_size = 0x100000;
3103 hw->ram_offset = 0x80000;
3104 } else
3105 hw->ram_size = t8 * 512;
3106 }
3107 else if (t8 == 0)
3108 hw->ram_size = 0x20000;
3109 else
3110 hw->ram_size = t8 * 4096;
3111
3112 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
3113 if (hw->ports > 1)
3114 hw->intr_mask |= IS_PORT_2;
3115
3116 if (hw->chip_id == CHIP_ID_GENESIS)
3117 genesis_init(hw);
3118 else {
3119 /* switch power to VCC (WA for VAUX problem) */
3120 skge_write8(hw, B0_POWER_CTRL,
3121 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3122
3123 /* avoid boards with stuck Hardware error bits */
3124 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3125 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3126 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3127 hw->intr_mask &= ~IS_HW_ERR;
3128 }
3129
3130 /* Clear PHY COMA */
3131 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3132 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3133 reg &= ~PCI_PHY_COMA;
3134 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3135 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3136
3137
3138 for (i = 0; i < hw->ports; i++) {
3139 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3140 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3141 }
3142 }
3143
3144 /* turn off hardware timer (unused) */
3145 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3146 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3147 skge_write8(hw, B0_LED, LED_STAT_ON);
3148
3149 /* enable the Tx Arbiters */
3150 for (i = 0; i < hw->ports; i++)
3151 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3152
3153 /* Initialize ram interface */
3154 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3155
3156 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3157 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3158 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3159 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3160 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3161 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3162 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3163 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3164 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3165 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3166 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3167 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3168
3169 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3170
3171 /* Set interrupt moderation for Transmit only
3172 * Receive interrupts avoided by NAPI
3173 */
3174 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3175 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3176 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3177
3178 skge_write32(hw, B0_IMSK, hw->intr_mask);
3179
3180 mutex_lock(&hw->phy_mutex);
3181 for (i = 0; i < hw->ports; i++) {
3182 if (hw->chip_id == CHIP_ID_GENESIS)
3183 genesis_reset(hw, i);
3184 else
3185 yukon_reset(hw, i);
3186 }
3187 mutex_unlock(&hw->phy_mutex);
3188
3189 return 0;
3190 }
3191
3192 /* Initialize network device */
3193 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3194 int highmem)
3195 {
3196 struct skge_port *skge;
3197 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3198
3199 if (!dev) {
3200 printk(KERN_ERR "skge etherdev alloc failed");
3201 return NULL;
3202 }
3203
3204 SET_MODULE_OWNER(dev);
3205 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3206 dev->open = skge_up;
3207 dev->stop = skge_down;
3208 dev->do_ioctl = skge_ioctl;
3209 dev->hard_start_xmit = skge_xmit_frame;
3210 dev->get_stats = skge_get_stats;
3211 if (hw->chip_id == CHIP_ID_GENESIS)
3212 dev->set_multicast_list = genesis_set_multicast;
3213 else
3214 dev->set_multicast_list = yukon_set_multicast;
3215
3216 dev->set_mac_address = skge_set_mac_address;
3217 dev->change_mtu = skge_change_mtu;
3218 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3219 dev->tx_timeout = skge_tx_timeout;
3220 dev->watchdog_timeo = TX_WATCHDOG;
3221 dev->poll = skge_poll;
3222 dev->weight = NAPI_WEIGHT;
3223 #ifdef CONFIG_NET_POLL_CONTROLLER
3224 dev->poll_controller = skge_netpoll;
3225 #endif
3226 dev->irq = hw->pdev->irq;
3227 dev->features = NETIF_F_LLTX;
3228 if (highmem)
3229 dev->features |= NETIF_F_HIGHDMA;
3230
3231 skge = netdev_priv(dev);
3232 skge->netdev = dev;
3233 skge->hw = hw;
3234 skge->msg_enable = netif_msg_init(debug, default_msg);
3235 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3236 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3237
3238 /* Auto speed and flow control */
3239 skge->autoneg = AUTONEG_ENABLE;
3240 skge->flow_control = FLOW_MODE_SYMMETRIC;
3241 skge->duplex = -1;
3242 skge->speed = -1;
3243 skge->advertising = skge_supported_modes(hw);
3244
3245 hw->dev[port] = dev;
3246
3247 skge->port = port;
3248
3249 spin_lock_init(&skge->tx_lock);
3250
3251 if (hw->chip_id != CHIP_ID_GENESIS) {
3252 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3253 skge->rx_csum = 1;
3254 }
3255
3256 /* read the mac address */
3257 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3258 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3259
3260 /* device is off until link detection */
3261 netif_carrier_off(dev);
3262 netif_stop_queue(dev);
3263
3264 return dev;
3265 }
3266
3267 static void __devinit skge_show_addr(struct net_device *dev)
3268 {
3269 const struct skge_port *skge = netdev_priv(dev);
3270
3271 if (netif_msg_probe(skge))
3272 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3273 dev->name,
3274 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3275 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3276 }
3277
3278 static int __devinit skge_probe(struct pci_dev *pdev,
3279 const struct pci_device_id *ent)
3280 {
3281 struct net_device *dev, *dev1;
3282 struct skge_hw *hw;
3283 int err, using_dac = 0;
3284
3285 err = pci_enable_device(pdev);
3286 if (err) {
3287 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3288 pci_name(pdev));
3289 goto err_out;
3290 }
3291
3292 err = pci_request_regions(pdev, DRV_NAME);
3293 if (err) {
3294 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3295 pci_name(pdev));
3296 goto err_out_disable_pdev;
3297 }
3298
3299 pci_set_master(pdev);
3300
3301 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3302 using_dac = 1;
3303 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3304 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3305 using_dac = 0;
3306 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3307 }
3308
3309 if (err) {
3310 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3311 pci_name(pdev));
3312 goto err_out_free_regions;
3313 }
3314
3315 #ifdef __BIG_ENDIAN
3316 /* byte swap descriptors in hardware */
3317 {
3318 u32 reg;
3319
3320 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3321 reg |= PCI_REV_DESC;
3322 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3323 }
3324 #endif
3325
3326 err = -ENOMEM;
3327 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3328 if (!hw) {
3329 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3330 pci_name(pdev));
3331 goto err_out_free_regions;
3332 }
3333
3334 hw->pdev = pdev;
3335 mutex_init(&hw->phy_mutex);
3336 INIT_WORK(&hw->phy_work, skge_extirq, hw);
3337 spin_lock_init(&hw->hw_lock);
3338
3339 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3340 if (!hw->regs) {
3341 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3342 pci_name(pdev));
3343 goto err_out_free_hw;
3344 }
3345
3346 err = skge_reset(hw);
3347 if (err)
3348 goto err_out_iounmap;
3349
3350 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3351 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3352 skge_board_name(hw), hw->chip_rev);
3353
3354 dev = skge_devinit(hw, 0, using_dac);
3355 if (!dev)
3356 goto err_out_led_off;
3357
3358 if (!is_valid_ether_addr(dev->dev_addr)) {
3359 printk(KERN_ERR PFX "%s: bad (zero?) ethernet address in rom\n",
3360 pci_name(pdev));
3361 err = -EIO;
3362 goto err_out_free_netdev;
3363 }
3364
3365 err = register_netdev(dev);
3366 if (err) {
3367 printk(KERN_ERR PFX "%s: cannot register net device\n",
3368 pci_name(pdev));
3369 goto err_out_free_netdev;
3370 }
3371
3372 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3373 if (err) {
3374 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3375 dev->name, pdev->irq);
3376 goto err_out_unregister;
3377 }
3378 skge_show_addr(dev);
3379
3380 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3381 if (register_netdev(dev1) == 0)
3382 skge_show_addr(dev1);
3383 else {
3384 /* Failure to register second port need not be fatal */
3385 printk(KERN_WARNING PFX "register of second port failed\n");
3386 hw->dev[1] = NULL;
3387 free_netdev(dev1);
3388 }
3389 }
3390 pci_set_drvdata(pdev, hw);
3391
3392 return 0;
3393
3394 err_out_unregister:
3395 unregister_netdev(dev);
3396 err_out_free_netdev:
3397 free_netdev(dev);
3398 err_out_led_off:
3399 skge_write16(hw, B0_LED, LED_STAT_OFF);
3400 err_out_iounmap:
3401 iounmap(hw->regs);
3402 err_out_free_hw:
3403 kfree(hw);
3404 err_out_free_regions:
3405 pci_release_regions(pdev);
3406 err_out_disable_pdev:
3407 pci_disable_device(pdev);
3408 pci_set_drvdata(pdev, NULL);
3409 err_out:
3410 return err;
3411 }
3412
3413 static void __devexit skge_remove(struct pci_dev *pdev)
3414 {
3415 struct skge_hw *hw = pci_get_drvdata(pdev);
3416 struct net_device *dev0, *dev1;
3417
3418 if (!hw)
3419 return;
3420
3421 if ((dev1 = hw->dev[1]))
3422 unregister_netdev(dev1);
3423 dev0 = hw->dev[0];
3424 unregister_netdev(dev0);
3425
3426 spin_lock_irq(&hw->hw_lock);
3427 hw->intr_mask = 0;
3428 skge_write32(hw, B0_IMSK, 0);
3429 skge_read32(hw, B0_IMSK);
3430 spin_unlock_irq(&hw->hw_lock);
3431
3432 skge_write16(hw, B0_LED, LED_STAT_OFF);
3433 skge_write8(hw, B0_CTST, CS_RST_SET);
3434
3435 flush_scheduled_work();
3436
3437 free_irq(pdev->irq, hw);
3438 pci_release_regions(pdev);
3439 pci_disable_device(pdev);
3440 if (dev1)
3441 free_netdev(dev1);
3442 free_netdev(dev0);
3443
3444 iounmap(hw->regs);
3445 kfree(hw);
3446 pci_set_drvdata(pdev, NULL);
3447 }
3448
3449 #ifdef CONFIG_PM
3450 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3451 {
3452 struct skge_hw *hw = pci_get_drvdata(pdev);
3453 int i, wol = 0;
3454
3455 pci_save_state(pdev);
3456 for (i = 0; i < hw->ports; i++) {
3457 struct net_device *dev = hw->dev[i];
3458
3459 if (netif_running(dev)) {
3460 struct skge_port *skge = netdev_priv(dev);
3461
3462 netif_carrier_off(dev);
3463 if (skge->wol)
3464 netif_stop_queue(dev);
3465 else
3466 skge_down(dev);
3467 wol |= skge->wol;
3468 }
3469 netif_device_detach(dev);
3470 }
3471
3472 skge_write32(hw, B0_IMSK, 0);
3473 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3474 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3475
3476 return 0;
3477 }
3478
3479 static int skge_resume(struct pci_dev *pdev)
3480 {
3481 struct skge_hw *hw = pci_get_drvdata(pdev);
3482 int i, err;
3483
3484 pci_set_power_state(pdev, PCI_D0);
3485 pci_restore_state(pdev);
3486 pci_enable_wake(pdev, PCI_D0, 0);
3487
3488 err = skge_reset(hw);
3489 if (err)
3490 goto out;
3491
3492 for (i = 0; i < hw->ports; i++) {
3493 struct net_device *dev = hw->dev[i];
3494
3495 netif_device_attach(dev);
3496 if (netif_running(dev)) {
3497 err = skge_up(dev);
3498
3499 if (err) {
3500 printk(KERN_ERR PFX "%s: could not up: %d\n",
3501 dev->name, err);
3502 dev_close(dev);
3503 goto out;
3504 }
3505 }
3506 }
3507 out:
3508 return err;
3509 }
3510 #endif
3511
3512 static struct pci_driver skge_driver = {
3513 .name = DRV_NAME,
3514 .id_table = skge_id_table,
3515 .probe = skge_probe,
3516 .remove = __devexit_p(skge_remove),
3517 #ifdef CONFIG_PM
3518 .suspend = skge_suspend,
3519 .resume = skge_resume,
3520 #endif
3521 };
3522
3523 static int __init skge_init_module(void)
3524 {
3525 return pci_register_driver(&skge_driver);
3526 }
3527
3528 static void __exit skge_cleanup_module(void)
3529 {
3530 pci_unregister_driver(&skge_driver);
3531 }
3532
3533 module_init(skge_init_module);
3534 module_exit(skge_cleanup_module);
Support for the Chinese Samsung S3C2440 based development boards