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PCI: Include PCI domain in PCI bus names on x86/x86_64
[linux-2.6/mini2440.git] / drivers / pci / probe.c
blob07d5c7424b0198947023101021b8f1cef7802b88
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include "pci.h"
13
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
18
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
22
23
24 static int find_anything(struct device *dev, void *data)
25 {
26 return 1;
27 }
28
29 /*
30 * Some device drivers need know if pci is initiated.
31 * Basically, we think pci is not initiated when there
32 * is no device to be found on the pci_bus_type.
33 */
34 int no_pci_devices(void)
35 {
36 struct device *dev;
37 int no_devices;
38
39 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
40 no_devices = (dev == NULL);
41 put_device(dev);
42 return no_devices;
43 }
44 EXPORT_SYMBOL(no_pci_devices);
45
46 #ifdef HAVE_PCI_LEGACY
47 /**
48 * pci_create_legacy_files - create legacy I/O port and memory files
49 * @b: bus to create files under
50 *
51 * Some platforms allow access to legacy I/O port and ISA memory space on
52 * a per-bus basis. This routine creates the files and ties them into
53 * their associated read, write and mmap files from pci-sysfs.c
54 */
55 static void pci_create_legacy_files(struct pci_bus *b)
56 {
57 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
58 GFP_ATOMIC);
59 if (b->legacy_io) {
60 b->legacy_io->attr.name = "legacy_io";
61 b->legacy_io->size = 0xffff;
62 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
63 b->legacy_io->read = pci_read_legacy_io;
64 b->legacy_io->write = pci_write_legacy_io;
65 device_create_bin_file(&b->dev, b->legacy_io);
66
67 /* Allocated above after the legacy_io struct */
68 b->legacy_mem = b->legacy_io + 1;
69 b->legacy_mem->attr.name = "legacy_mem";
70 b->legacy_mem->size = 1024*1024;
71 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
72 b->legacy_mem->mmap = pci_mmap_legacy_mem;
73 device_create_bin_file(&b->dev, b->legacy_mem);
74 }
75 }
76
77 void pci_remove_legacy_files(struct pci_bus *b)
78 {
79 if (b->legacy_io) {
80 device_remove_bin_file(&b->dev, b->legacy_io);
81 device_remove_bin_file(&b->dev, b->legacy_mem);
82 kfree(b->legacy_io); /* both are allocated here */
83 }
84 }
85 #else /* !HAVE_PCI_LEGACY */
86 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
87 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
88 #endif /* HAVE_PCI_LEGACY */
89
90 /*
91 * PCI Bus Class Devices
92 */
93 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
94 struct device_attribute *attr,
95 char *buf)
96 {
97 int ret;
98 cpumask_t cpumask;
99
100 cpumask = pcibus_to_cpumask(to_pci_bus(dev));
101 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
102 if (ret < PAGE_SIZE)
103 buf[ret++] = '\n';
104 return ret;
105 }
106 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
107
108 /*
109 * PCI Bus Class
110 */
111 static void release_pcibus_dev(struct device *dev)
112 {
113 struct pci_bus *pci_bus = to_pci_bus(dev);
114
115 if (pci_bus->bridge)
116 put_device(pci_bus->bridge);
117 kfree(pci_bus);
118 }
119
120 static struct class pcibus_class = {
121 .name = "pci_bus",
122 .dev_release = &release_pcibus_dev,
123 };
124
125 static int __init pcibus_class_init(void)
126 {
127 return class_register(&pcibus_class);
128 }
129 postcore_initcall(pcibus_class_init);
130
131 /*
132 * Translate the low bits of the PCI base
133 * to the resource type
134 */
135 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
136 {
137 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
138 return IORESOURCE_IO;
139
140 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
141 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
142
143 return IORESOURCE_MEM;
144 }
145
146 /*
147 * Find the extent of a PCI decode..
148 */
149 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
150 {
151 u32 size = mask & maxbase; /* Find the significant bits */
152 if (!size)
153 return 0;
154
155 /* Get the lowest of them to find the decode size, and
156 from that the extent. */
157 size = (size & ~(size-1)) - 1;
158
159 /* base == maxbase can be valid only if the BAR has
160 already been programmed with all 1s. */
161 if (base == maxbase && ((base | size) & mask) != mask)
162 return 0;
163
164 return size;
165 }
166
167 static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
168 {
169 u64 size = mask & maxbase; /* Find the significant bits */
170 if (!size)
171 return 0;
172
173 /* Get the lowest of them to find the decode size, and
174 from that the extent. */
175 size = (size & ~(size-1)) - 1;
176
177 /* base == maxbase can be valid only if the BAR has
178 already been programmed with all 1s. */
179 if (base == maxbase && ((base | size) & mask) != mask)
180 return 0;
181
182 return size;
183 }
184
185 static inline int is_64bit_memory(u32 mask)
186 {
187 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
188 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
189 return 1;
190 return 0;
191 }
192
193 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
194 {
195 unsigned int pos, reg, next;
196 u32 l, sz;
197 struct resource *res;
198
199 for(pos=0; pos<howmany; pos = next) {
200 u64 l64;
201 u64 sz64;
202 u32 raw_sz;
203
204 next = pos+1;
205 res = &dev->resource[pos];
206 res->name = pci_name(dev);
207 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
208 pci_read_config_dword(dev, reg, &l);
209 pci_write_config_dword(dev, reg, ~0);
210 pci_read_config_dword(dev, reg, &sz);
211 pci_write_config_dword(dev, reg, l);
212 if (!sz || sz == 0xffffffff)
213 continue;
214 if (l == 0xffffffff)
215 l = 0;
216 raw_sz = sz;
217 if ((l & PCI_BASE_ADDRESS_SPACE) ==
218 PCI_BASE_ADDRESS_SPACE_MEMORY) {
219 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
220 /*
221 * For 64bit prefetchable memory sz could be 0, if the
222 * real size is bigger than 4G, so we need to check
223 * szhi for that.
224 */
225 if (!is_64bit_memory(l) && !sz)
226 continue;
227 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
228 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
229 } else {
230 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
231 if (!sz)
232 continue;
233 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
234 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
235 }
236 res->end = res->start + (unsigned long) sz;
237 res->flags |= pci_calc_resource_flags(l);
238 if (is_64bit_memory(l)) {
239 u32 szhi, lhi;
240
241 pci_read_config_dword(dev, reg+4, &lhi);
242 pci_write_config_dword(dev, reg+4, ~0);
243 pci_read_config_dword(dev, reg+4, &szhi);
244 pci_write_config_dword(dev, reg+4, lhi);
245 sz64 = ((u64)szhi << 32) | raw_sz;
246 l64 = ((u64)lhi << 32) | l;
247 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
248 next++;
249 #if BITS_PER_LONG == 64
250 if (!sz64) {
251 res->start = 0;
252 res->end = 0;
253 res->flags = 0;
254 continue;
255 }
256 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
257 res->end = res->start + sz64;
258 #else
259 if (sz64 > 0x100000000ULL) {
260 printk(KERN_ERR "PCI: Unable to handle 64-bit "
261 "BAR for device %s\n", pci_name(dev));
262 res->start = 0;
263 res->flags = 0;
264 } else if (lhi) {
265 /* 64-bit wide address, treat as disabled */
266 pci_write_config_dword(dev, reg,
267 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
268 pci_write_config_dword(dev, reg+4, 0);
269 res->start = 0;
270 res->end = sz;
271 }
272 #endif
273 }
274 }
275 if (rom) {
276 dev->rom_base_reg = rom;
277 res = &dev->resource[PCI_ROM_RESOURCE];
278 res->name = pci_name(dev);
279 pci_read_config_dword(dev, rom, &l);
280 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
281 pci_read_config_dword(dev, rom, &sz);
282 pci_write_config_dword(dev, rom, l);
283 if (l == 0xffffffff)
284 l = 0;
285 if (sz && sz != 0xffffffff) {
286 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
287 if (sz) {
288 res->flags = (l & IORESOURCE_ROM_ENABLE) |
289 IORESOURCE_MEM | IORESOURCE_PREFETCH |
290 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
291 res->start = l & PCI_ROM_ADDRESS_MASK;
292 res->end = res->start + (unsigned long) sz;
293 }
294 }
295 }
296 }
297
298 void __devinit pci_read_bridge_bases(struct pci_bus *child)
299 {
300 struct pci_dev *dev = child->self;
301 u8 io_base_lo, io_limit_lo;
302 u16 mem_base_lo, mem_limit_lo;
303 unsigned long base, limit;
304 struct resource *res;
305 int i;
306
307 if (!dev) /* It's a host bus, nothing to read */
308 return;
309
310 if (dev->transparent) {
311 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
312 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
313 child->resource[i] = child->parent->resource[i - 3];
314 }
315
316 for(i=0; i<3; i++)
317 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
318
319 res = child->resource[0];
320 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
321 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
322 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
323 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
324
325 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
326 u16 io_base_hi, io_limit_hi;
327 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
328 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
329 base |= (io_base_hi << 16);
330 limit |= (io_limit_hi << 16);
331 }
332
333 if (base <= limit) {
334 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
335 if (!res->start)
336 res->start = base;
337 if (!res->end)
338 res->end = limit + 0xfff;
339 }
340
341 res = child->resource[1];
342 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
343 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
344 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
345 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
346 if (base <= limit) {
347 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
348 res->start = base;
349 res->end = limit + 0xfffff;
350 }
351
352 res = child->resource[2];
353 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
354 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
355 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
356 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
357
358 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
359 u32 mem_base_hi, mem_limit_hi;
360 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
361 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
362
363 /*
364 * Some bridges set the base > limit by default, and some
365 * (broken) BIOSes do not initialize them. If we find
366 * this, just assume they are not being used.
367 */
368 if (mem_base_hi <= mem_limit_hi) {
369 #if BITS_PER_LONG == 64
370 base |= ((long) mem_base_hi) << 32;
371 limit |= ((long) mem_limit_hi) << 32;
372 #else
373 if (mem_base_hi || mem_limit_hi) {
374 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
375 return;
376 }
377 #endif
378 }
379 }
380 if (base <= limit) {
381 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
382 res->start = base;
383 res->end = limit + 0xfffff;
384 }
385 }
386
387 static struct pci_bus * pci_alloc_bus(void)
388 {
389 struct pci_bus *b;
390
391 b = kzalloc(sizeof(*b), GFP_KERNEL);
392 if (b) {
393 INIT_LIST_HEAD(&b->node);
394 INIT_LIST_HEAD(&b->children);
395 INIT_LIST_HEAD(&b->devices);
396 }
397 return b;
398 }
399
400 static struct pci_bus * __devinit
401 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
402 {
403 struct pci_bus *child;
404 int i;
405
406 /*
407 * Allocate a new bus, and inherit stuff from the parent..
408 */
409 child = pci_alloc_bus();
410 if (!child)
411 return NULL;
412
413 child->self = bridge;
414 child->parent = parent;
415 child->ops = parent->ops;
416 child->sysdata = parent->sysdata;
417 child->bus_flags = parent->bus_flags;
418 child->bridge = get_device(&bridge->dev);
419
420 /* initialize some portions of the bus device, but don't register it
421 * now as the parent is not properly set up yet. This device will get
422 * registered later in pci_bus_add_devices()
423 */
424 child->dev.class = &pcibus_class;
425 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr);
426
427 /*
428 * Set up the primary, secondary and subordinate
429 * bus numbers.
430 */
431 child->number = child->secondary = busnr;
432 child->primary = parent->secondary;
433 child->subordinate = 0xff;
434
435 /* Set up default resource pointers and names.. */
436 for (i = 0; i < 4; i++) {
437 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
438 child->resource[i]->name = child->name;
439 }
440 bridge->subordinate = child;
441
442 return child;
443 }
444
445 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
446 {
447 struct pci_bus *child;
448
449 child = pci_alloc_child_bus(parent, dev, busnr);
450 if (child) {
451 down_write(&pci_bus_sem);
452 list_add_tail(&child->node, &parent->children);
453 up_write(&pci_bus_sem);
454 }
455 return child;
456 }
457
458 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
459 {
460 struct pci_bus *parent = child->parent;
461
462 /* Attempts to fix that up are really dangerous unless
463 we're going to re-assign all bus numbers. */
464 if (!pcibios_assign_all_busses())
465 return;
466
467 while (parent->parent && parent->subordinate < max) {
468 parent->subordinate = max;
469 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
470 parent = parent->parent;
471 }
472 }
473
474 /*
475 * If it's a bridge, configure it and scan the bus behind it.
476 * For CardBus bridges, we don't scan behind as the devices will
477 * be handled by the bridge driver itself.
478 *
479 * We need to process bridges in two passes -- first we scan those
480 * already configured by the BIOS and after we are done with all of
481 * them, we proceed to assigning numbers to the remaining buses in
482 * order to avoid overlaps between old and new bus numbers.
483 */
484 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
485 {
486 struct pci_bus *child;
487 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
488 u32 buses, i, j = 0;
489 u16 bctl;
490
491 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
492
493 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
494 pci_name(dev), buses & 0xffffff, pass);
495
496 /* Disable MasterAbortMode during probing to avoid reporting
497 of bus errors (in some architectures) */
498 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
499 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
500 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
501
502 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
503 unsigned int cmax, busnr;
504 /*
505 * Bus already configured by firmware, process it in the first
506 * pass and just note the configuration.
507 */
508 if (pass)
509 goto out;
510 busnr = (buses >> 8) & 0xFF;
511
512 /*
513 * If we already got to this bus through a different bridge,
514 * ignore it. This can happen with the i450NX chipset.
515 */
516 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
517 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
518 pci_domain_nr(bus), busnr);
519 goto out;
520 }
521
522 child = pci_add_new_bus(bus, dev, busnr);
523 if (!child)
524 goto out;
525 child->primary = buses & 0xFF;
526 child->subordinate = (buses >> 16) & 0xFF;
527 child->bridge_ctl = bctl;
528
529 cmax = pci_scan_child_bus(child);
530 if (cmax > max)
531 max = cmax;
532 if (child->subordinate > max)
533 max = child->subordinate;
534 } else {
535 /*
536 * We need to assign a number to this bus which we always
537 * do in the second pass.
538 */
539 if (!pass) {
540 if (pcibios_assign_all_busses())
541 /* Temporarily disable forwarding of the
542 configuration cycles on all bridges in
543 this bus segment to avoid possible
544 conflicts in the second pass between two
545 bridges programmed with overlapping
546 bus ranges. */
547 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
548 buses & ~0xffffff);
549 goto out;
550 }
551
552 /* Clear errors */
553 pci_write_config_word(dev, PCI_STATUS, 0xffff);
554
555 /* Prevent assigning a bus number that already exists.
556 * This can happen when a bridge is hot-plugged */
557 if (pci_find_bus(pci_domain_nr(bus), max+1))
558 goto out;
559 child = pci_add_new_bus(bus, dev, ++max);
560 buses = (buses & 0xff000000)
561 | ((unsigned int)(child->primary) << 0)
562 | ((unsigned int)(child->secondary) << 8)
563 | ((unsigned int)(child->subordinate) << 16);
564
565 /*
566 * yenta.c forces a secondary latency timer of 176.
567 * Copy that behaviour here.
568 */
569 if (is_cardbus) {
570 buses &= ~0xff000000;
571 buses |= CARDBUS_LATENCY_TIMER << 24;
572 }
573
574 /*
575 * We need to blast all three values with a single write.
576 */
577 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
578
579 if (!is_cardbus) {
580 child->bridge_ctl = bctl;
581 /*
582 * Adjust subordinate busnr in parent buses.
583 * We do this before scanning for children because
584 * some devices may not be detected if the bios
585 * was lazy.
586 */
587 pci_fixup_parent_subordinate_busnr(child, max);
588 /* Now we can scan all subordinate buses... */
589 max = pci_scan_child_bus(child);
590 /*
591 * now fix it up again since we have found
592 * the real value of max.
593 */
594 pci_fixup_parent_subordinate_busnr(child, max);
595 } else {
596 /*
597 * For CardBus bridges, we leave 4 bus numbers
598 * as cards with a PCI-to-PCI bridge can be
599 * inserted later.
600 */
601 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
602 struct pci_bus *parent = bus;
603 if (pci_find_bus(pci_domain_nr(bus),
604 max+i+1))
605 break;
606 while (parent->parent) {
607 if ((!pcibios_assign_all_busses()) &&
608 (parent->subordinate > max) &&
609 (parent->subordinate <= max+i)) {
610 j = 1;
611 }
612 parent = parent->parent;
613 }
614 if (j) {
615 /*
616 * Often, there are two cardbus bridges
617 * -- try to leave one valid bus number
618 * for each one.
619 */
620 i /= 2;
621 break;
622 }
623 }
624 max += i;
625 pci_fixup_parent_subordinate_busnr(child, max);
626 }
627 /*
628 * Set the subordinate bus number to its real value.
629 */
630 child->subordinate = max;
631 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
632 }
633
634 sprintf(child->name,
635 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
636 pci_domain_nr(bus), child->number);
637
638 /* Has only triggered on CardBus, fixup is in yenta_socket */
639 while (bus->parent) {
640 if ((child->subordinate > bus->subordinate) ||
641 (child->number > bus->subordinate) ||
642 (child->number < bus->number) ||
643 (child->subordinate < bus->number)) {
644 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
645 "hidden behind%s bridge #%02x (-#%02x)\n",
646 child->number, child->subordinate,
647 (bus->number > child->subordinate &&
648 bus->subordinate < child->number) ?
649 "wholly" : "partially",
650 bus->self->transparent ? " transparent" : "",
651 bus->number, bus->subordinate);
652 }
653 bus = bus->parent;
654 }
655
656 out:
657 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
658
659 return max;
660 }
661
662 /*
663 * Read interrupt line and base address registers.
664 * The architecture-dependent code can tweak these, of course.
665 */
666 static void pci_read_irq(struct pci_dev *dev)
667 {
668 unsigned char irq;
669
670 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
671 dev->pin = irq;
672 if (irq)
673 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
674 dev->irq = irq;
675 }
676
677 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
678
679 /**
680 * pci_setup_device - fill in class and map information of a device
681 * @dev: the device structure to fill
682 *
683 * Initialize the device structure with information about the device's
684 * vendor,class,memory and IO-space addresses,IRQ lines etc.
685 * Called at initialisation of the PCI subsystem and by CardBus services.
686 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
687 * or CardBus).
688 */
689 static int pci_setup_device(struct pci_dev * dev)
690 {
691 u32 class;
692
693 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
694 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
695
696 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
697 dev->revision = class & 0xff;
698 class >>= 8; /* upper 3 bytes */
699 dev->class = class;
700 class >>= 8;
701
702 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
703 dev->vendor, dev->device, class, dev->hdr_type);
704
705 /* "Unknown power state" */
706 dev->current_state = PCI_UNKNOWN;
707
708 /* Early fixups, before probing the BARs */
709 pci_fixup_device(pci_fixup_early, dev);
710 class = dev->class >> 8;
711
712 switch (dev->hdr_type) { /* header type */
713 case PCI_HEADER_TYPE_NORMAL: /* standard header */
714 if (class == PCI_CLASS_BRIDGE_PCI)
715 goto bad;
716 pci_read_irq(dev);
717 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
718 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
719 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
720
721 /*
722 * Do the ugly legacy mode stuff here rather than broken chip
723 * quirk code. Legacy mode ATA controllers have fixed
724 * addresses. These are not always echoed in BAR0-3, and
725 * BAR0-3 in a few cases contain junk!
726 */
727 if (class == PCI_CLASS_STORAGE_IDE) {
728 u8 progif;
729 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
730 if ((progif & 1) == 0) {
731 dev->resource[0].start = 0x1F0;
732 dev->resource[0].end = 0x1F7;
733 dev->resource[0].flags = LEGACY_IO_RESOURCE;
734 dev->resource[1].start = 0x3F6;
735 dev->resource[1].end = 0x3F6;
736 dev->resource[1].flags = LEGACY_IO_RESOURCE;
737 }
738 if ((progif & 4) == 0) {
739 dev->resource[2].start = 0x170;
740 dev->resource[2].end = 0x177;
741 dev->resource[2].flags = LEGACY_IO_RESOURCE;
742 dev->resource[3].start = 0x376;
743 dev->resource[3].end = 0x376;
744 dev->resource[3].flags = LEGACY_IO_RESOURCE;
745 }
746 }
747 break;
748
749 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
750 if (class != PCI_CLASS_BRIDGE_PCI)
751 goto bad;
752 /* The PCI-to-PCI bridge spec requires that subtractive
753 decoding (i.e. transparent) bridge must have programming
754 interface code of 0x01. */
755 pci_read_irq(dev);
756 dev->transparent = ((dev->class & 0xff) == 1);
757 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
758 break;
759
760 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
761 if (class != PCI_CLASS_BRIDGE_CARDBUS)
762 goto bad;
763 pci_read_irq(dev);
764 pci_read_bases(dev, 1, 0);
765 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
766 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
767 break;
768
769 default: /* unknown header */
770 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
771 pci_name(dev), dev->hdr_type);
772 return -1;
773
774 bad:
775 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
776 pci_name(dev), class, dev->hdr_type);
777 dev->class = PCI_CLASS_NOT_DEFINED;
778 }
779
780 /* We found a fine healthy device, go go go... */
781 return 0;
782 }
783
784 /**
785 * pci_release_dev - free a pci device structure when all users of it are finished.
786 * @dev: device that's been disconnected
787 *
788 * Will be called only by the device core when all users of this pci device are
789 * done.
790 */
791 static void pci_release_dev(struct device *dev)
792 {
793 struct pci_dev *pci_dev;
794
795 pci_dev = to_pci_dev(dev);
796 kfree(pci_dev);
797 }
798
799 static void set_pcie_port_type(struct pci_dev *pdev)
800 {
801 int pos;
802 u16 reg16;
803
804 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
805 if (!pos)
806 return;
807 pdev->is_pcie = 1;
808 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
809 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
810 }
811
812 /**
813 * pci_cfg_space_size - get the configuration space size of the PCI device.
814 * @dev: PCI device
815 *
816 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
817 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
818 * access it. Maybe we don't have a way to generate extended config space
819 * accesses, or the device is behind a reverse Express bridge. So we try
820 * reading the dword at 0x100 which must either be 0 or a valid extended
821 * capability header.
822 */
823 int pci_cfg_space_size(struct pci_dev *dev)
824 {
825 int pos;
826 u32 status;
827
828 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
829 if (!pos) {
830 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
831 if (!pos)
832 goto fail;
833
834 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
835 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
836 goto fail;
837 }
838
839 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
840 goto fail;
841 if (status == 0xffffffff)
842 goto fail;
843
844 return PCI_CFG_SPACE_EXP_SIZE;
845
846 fail:
847 return PCI_CFG_SPACE_SIZE;
848 }
849
850 static void pci_release_bus_bridge_dev(struct device *dev)
851 {
852 kfree(dev);
853 }
854
855 struct pci_dev *alloc_pci_dev(void)
856 {
857 struct pci_dev *dev;
858
859 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
860 if (!dev)
861 return NULL;
862
863 INIT_LIST_HEAD(&dev->bus_list);
864
865 pci_msi_init_pci_dev(dev);
866
867 return dev;
868 }
869 EXPORT_SYMBOL(alloc_pci_dev);
870
871 /*
872 * Read the config data for a PCI device, sanity-check it
873 * and fill in the dev structure...
874 */
875 static struct pci_dev * __devinit
876 pci_scan_device(struct pci_bus *bus, int devfn)
877 {
878 struct pci_dev *dev;
879 u32 l;
880 u8 hdr_type;
881 int delay = 1;
882
883 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
884 return NULL;
885
886 /* some broken boards return 0 or ~0 if a slot is empty: */
887 if (l == 0xffffffff || l == 0x00000000 ||
888 l == 0x0000ffff || l == 0xffff0000)
889 return NULL;
890
891 /* Configuration request Retry Status */
892 while (l == 0xffff0001) {
893 msleep(delay);
894 delay *= 2;
895 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
896 return NULL;
897 /* Card hasn't responded in 60 seconds? Must be stuck. */
898 if (delay > 60 * 1000) {
899 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
900 "responding\n", pci_domain_nr(bus),
901 bus->number, PCI_SLOT(devfn),
902 PCI_FUNC(devfn));
903 return NULL;
904 }
905 }
906
907 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
908 return NULL;
909
910 dev = alloc_pci_dev();
911 if (!dev)
912 return NULL;
913
914 dev->bus = bus;
915 dev->sysdata = bus->sysdata;
916 dev->dev.parent = bus->bridge;
917 dev->dev.bus = &pci_bus_type;
918 dev->devfn = devfn;
919 dev->hdr_type = hdr_type & 0x7f;
920 dev->multifunction = !!(hdr_type & 0x80);
921 dev->vendor = l & 0xffff;
922 dev->device = (l >> 16) & 0xffff;
923 dev->cfg_size = pci_cfg_space_size(dev);
924 dev->error_state = pci_channel_io_normal;
925 set_pcie_port_type(dev);
926
927 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
928 set this higher, assuming the system even supports it. */
929 dev->dma_mask = 0xffffffff;
930 if (pci_setup_device(dev) < 0) {
931 kfree(dev);
932 return NULL;
933 }
934
935 return dev;
936 }
937
938 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
939 {
940 device_initialize(&dev->dev);
941 dev->dev.release = pci_release_dev;
942 pci_dev_get(dev);
943
944 set_dev_node(&dev->dev, pcibus_to_node(bus));
945 dev->dev.dma_mask = &dev->dma_mask;
946 dev->dev.dma_parms = &dev->dma_parms;
947 dev->dev.coherent_dma_mask = 0xffffffffull;
948
949 pci_set_dma_max_seg_size(dev, 65536);
950 pci_set_dma_seg_boundary(dev, 0xffffffff);
951
952 /* Fix up broken headers */
953 pci_fixup_device(pci_fixup_header, dev);
954
955 /*
956 * Add the device to our list of discovered devices
957 * and the bus list for fixup functions, etc.
958 */
959 down_write(&pci_bus_sem);
960 list_add_tail(&dev->bus_list, &bus->devices);
961 up_write(&pci_bus_sem);
962 }
963
964 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
965 {
966 struct pci_dev *dev;
967
968 dev = pci_scan_device(bus, devfn);
969 if (!dev)
970 return NULL;
971
972 pci_device_add(dev, bus);
973
974 return dev;
975 }
976 EXPORT_SYMBOL(pci_scan_single_device);
977
978 /**
979 * pci_scan_slot - scan a PCI slot on a bus for devices.
980 * @bus: PCI bus to scan
981 * @devfn: slot number to scan (must have zero function.)
982 *
983 * Scan a PCI slot on the specified PCI bus for devices, adding
984 * discovered devices to the @bus->devices list. New devices
985 * will not have is_added set.
986 */
987 int pci_scan_slot(struct pci_bus *bus, int devfn)
988 {
989 int func, nr = 0;
990 int scan_all_fns;
991
992 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
993
994 for (func = 0; func < 8; func++, devfn++) {
995 struct pci_dev *dev;
996
997 dev = pci_scan_single_device(bus, devfn);
998 if (dev) {
999 nr++;
1000
1001 /*
1002 * If this is a single function device,
1003 * don't scan past the first function.
1004 */
1005 if (!dev->multifunction) {
1006 if (func > 0) {
1007 dev->multifunction = 1;
1008 } else {
1009 break;
1010 }
1011 }
1012 } else {
1013 if (func == 0 && !scan_all_fns)
1014 break;
1015 }
1016 }
1017 return nr;
1018 }
1019
1020 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1021 {
1022 unsigned int devfn, pass, max = bus->secondary;
1023 struct pci_dev *dev;
1024
1025 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1026
1027 /* Go find them, Rover! */
1028 for (devfn = 0; devfn < 0x100; devfn += 8)
1029 pci_scan_slot(bus, devfn);
1030
1031 /*
1032 * After performing arch-dependent fixup of the bus, look behind
1033 * all PCI-to-PCI bridges on this bus.
1034 */
1035 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1036 pcibios_fixup_bus(bus);
1037 for (pass=0; pass < 2; pass++)
1038 list_for_each_entry(dev, &bus->devices, bus_list) {
1039 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1040 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1041 max = pci_scan_bridge(bus, dev, max, pass);
1042 }
1043
1044 /*
1045 * We've scanned the bus and so we know all about what's on
1046 * the other side of any bridges that may be on this bus plus
1047 * any devices.
1048 *
1049 * Return how far we've got finding sub-buses.
1050 */
1051 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1052 pci_domain_nr(bus), bus->number, max);
1053 return max;
1054 }
1055
1056 struct pci_bus * pci_create_bus(struct device *parent,
1057 int bus, struct pci_ops *ops, void *sysdata)
1058 {
1059 int error;
1060 struct pci_bus *b;
1061 struct device *dev;
1062
1063 b = pci_alloc_bus();
1064 if (!b)
1065 return NULL;
1066
1067 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1068 if (!dev){
1069 kfree(b);
1070 return NULL;
1071 }
1072
1073 b->sysdata = sysdata;
1074 b->ops = ops;
1075
1076 if (pci_find_bus(pci_domain_nr(b), bus)) {
1077 /* If we already got to this bus through a different bridge, ignore it */
1078 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1079 goto err_out;
1080 }
1081
1082 down_write(&pci_bus_sem);
1083 list_add_tail(&b->node, &pci_root_buses);
1084 up_write(&pci_bus_sem);
1085
1086 memset(dev, 0, sizeof(*dev));
1087 dev->parent = parent;
1088 dev->release = pci_release_bus_bridge_dev;
1089 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1090 error = device_register(dev);
1091 if (error)
1092 goto dev_reg_err;
1093 b->bridge = get_device(dev);
1094
1095 b->dev.class = &pcibus_class;
1096 b->dev.parent = b->bridge;
1097 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
1098 error = device_register(&b->dev);
1099 if (error)
1100 goto class_dev_reg_err;
1101 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1102 if (error)
1103 goto dev_create_file_err;
1104
1105 /* Create legacy_io and legacy_mem files for this bus */
1106 pci_create_legacy_files(b);
1107
1108 b->number = b->secondary = bus;
1109 b->resource[0] = &ioport_resource;
1110 b->resource[1] = &iomem_resource;
1111
1112 return b;
1113
1114 dev_create_file_err:
1115 device_unregister(&b->dev);
1116 class_dev_reg_err:
1117 device_unregister(dev);
1118 dev_reg_err:
1119 down_write(&pci_bus_sem);
1120 list_del(&b->node);
1121 up_write(&pci_bus_sem);
1122 err_out:
1123 kfree(dev);
1124 kfree(b);
1125 return NULL;
1126 }
1127
1128 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1129 int bus, struct pci_ops *ops, void *sysdata)
1130 {
1131 struct pci_bus *b;
1132
1133 b = pci_create_bus(parent, bus, ops, sysdata);
1134 if (b)
1135 b->subordinate = pci_scan_child_bus(b);
1136 return b;
1137 }
1138 EXPORT_SYMBOL(pci_scan_bus_parented);
1139
1140 #ifdef CONFIG_HOTPLUG
1141 EXPORT_SYMBOL(pci_add_new_bus);
1142 EXPORT_SYMBOL(pci_scan_slot);
1143 EXPORT_SYMBOL(pci_scan_bridge);
1144 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1145 #endif
1146
1147 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1148 {
1149 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1150 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1151
1152 if (a->bus->number < b->bus->number) return -1;
1153 else if (a->bus->number > b->bus->number) return 1;
1154
1155 if (a->devfn < b->devfn) return -1;
1156 else if (a->devfn > b->devfn) return 1;
1157
1158 return 0;
1159 }
1160
1161 /*
1162 * Yes, this forcably breaks the klist abstraction temporarily. It
1163 * just wants to sort the klist, not change reference counts and
1164 * take/drop locks rapidly in the process. It does all this while
1165 * holding the lock for the list, so objects can't otherwise be
1166 * added/removed while we're swizzling.
1167 */
1168 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1169 {
1170 struct list_head *pos;
1171 struct klist_node *n;
1172 struct device *dev;
1173 struct pci_dev *b;
1174
1175 list_for_each(pos, list) {
1176 n = container_of(pos, struct klist_node, n_node);
1177 dev = container_of(n, struct device, knode_bus);
1178 b = to_pci_dev(dev);
1179 if (pci_sort_bf_cmp(a, b) <= 0) {
1180 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1181 return;
1182 }
1183 }
1184 list_move_tail(&a->dev.knode_bus.n_node, list);
1185 }
1186
1187 void __init pci_sort_breadthfirst(void)
1188 {
1189 LIST_HEAD(sorted_devices);
1190 struct list_head *pos, *tmp;
1191 struct klist_node *n;
1192 struct device *dev;
1193 struct pci_dev *pdev;
1194 struct klist *device_klist;
1195
1196 device_klist = bus_get_device_klist(&pci_bus_type);
1197
1198 spin_lock(&device_klist->k_lock);
1199 list_for_each_safe(pos, tmp, &device_klist->k_list) {
1200 n = container_of(pos, struct klist_node, n_node);
1201 dev = container_of(n, struct device, knode_bus);
1202 pdev = to_pci_dev(dev);
1203 pci_insertion_sort_klist(pdev, &sorted_devices);
1204 }
1205 list_splice(&sorted_devices, &device_klist->k_list);
1206 spin_unlock(&device_klist->k_lock);
1207 }
Support for the Chinese Samsung S3C2440 based development boards