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[PATCH] synclink_gt: add bisync and monosync modes
[linux-2.6/mini2440.git] / drivers / char / synclink_gt.c
blobbd3821679ac86a0353c603cd30e01415fdf93b63
1 /*
2 * $Id: synclink_gt.c,v 4.25 2006/02/06 21:20:33 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink GT serial adapters.
5 *
6 * written by Paul Fulghum for Microgate Corporation
7 * paulkf@microgate.com
8 *
9 * Microgate and SyncLink are trademarks of Microgate Corporation
10 *
11 * This code is released under the GNU General Public License (GPL)
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
17 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
21 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
23 * OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26 /*
27 * DEBUG OUTPUT DEFINITIONS
28 *
29 * uncomment lines below to enable specific types of debug output
30 *
31 * DBGINFO information - most verbose output
32 * DBGERR serious errors
33 * DBGBH bottom half service routine debugging
34 * DBGISR interrupt service routine debugging
35 * DBGDATA output receive and transmit data
36 * DBGTBUF output transmit DMA buffers and registers
37 * DBGRBUF output receive DMA buffers and registers
38 */
39
40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
45 //#define DBGTBUF(info) dump_tbufs(info)
46 //#define DBGRBUF(info) dump_rbufs(info)
47
48
49 #include <linux/module.h>
50 #include <linux/version.h>
51 #include <linux/errno.h>
52 #include <linux/signal.h>
53 #include <linux/sched.h>
54 #include <linux/timer.h>
55 #include <linux/interrupt.h>
56 #include <linux/pci.h>
57 #include <linux/tty.h>
58 #include <linux/tty_flip.h>
59 #include <linux/serial.h>
60 #include <linux/major.h>
61 #include <linux/string.h>
62 #include <linux/fcntl.h>
63 #include <linux/ptrace.h>
64 #include <linux/ioport.h>
65 #include <linux/mm.h>
66 #include <linux/slab.h>
67 #include <linux/netdevice.h>
68 #include <linux/vmalloc.h>
69 #include <linux/init.h>
70 #include <linux/delay.h>
71 #include <linux/ioctl.h>
72 #include <linux/termios.h>
73 #include <linux/bitops.h>
74 #include <linux/workqueue.h>
75 #include <linux/hdlc.h>
76
77 #include <asm/system.h>
78 #include <asm/io.h>
79 #include <asm/irq.h>
80 #include <asm/dma.h>
81 #include <asm/types.h>
82 #include <asm/uaccess.h>
83
84 #include "linux/synclink.h"
85
86 #ifdef CONFIG_HDLC_MODULE
87 #define CONFIG_HDLC 1
88 #endif
89
90 /*
91 * module identification
92 */
93 static char *driver_name = "SyncLink GT";
94 static char *driver_version = "$Revision: 4.25 $";
95 static char *tty_driver_name = "synclink_gt";
96 static char *tty_dev_prefix = "ttySLG";
97 MODULE_LICENSE("GPL");
98 #define MGSL_MAGIC 0x5401
99 #define MAX_DEVICES 12
100
101 static struct pci_device_id pci_table[] = {
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
104 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
105 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
106 {0,}, /* terminate list */
107 };
108 MODULE_DEVICE_TABLE(pci, pci_table);
109
110 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
111 static void remove_one(struct pci_dev *dev);
112 static struct pci_driver pci_driver = {
113 .name = "synclink_gt",
114 .id_table = pci_table,
115 .probe = init_one,
116 .remove = __devexit_p(remove_one),
117 };
118
119 static int pci_registered;
120
121 /*
122 * module configuration and status
123 */
124 static struct slgt_info *slgt_device_list;
125 static int slgt_device_count;
126
127 static int ttymajor;
128 static int debug_level;
129 static int maxframe[MAX_DEVICES];
130 static int dosyncppp[MAX_DEVICES];
131
132 module_param(ttymajor, int, 0);
133 module_param(debug_level, int, 0);
134 module_param_array(maxframe, int, NULL, 0);
135 module_param_array(dosyncppp, int, NULL, 0);
136
137 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
138 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
139 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
140 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
141
142 /*
143 * tty support and callbacks
144 */
145 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
146
147 static struct tty_driver *serial_driver;
148
149 static int open(struct tty_struct *tty, struct file * filp);
150 static void close(struct tty_struct *tty, struct file * filp);
151 static void hangup(struct tty_struct *tty);
152 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
153
154 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
155 static void put_char(struct tty_struct *tty, unsigned char ch);
156 static void send_xchar(struct tty_struct *tty, char ch);
157 static void wait_until_sent(struct tty_struct *tty, int timeout);
158 static int write_room(struct tty_struct *tty);
159 static void flush_chars(struct tty_struct *tty);
160 static void flush_buffer(struct tty_struct *tty);
161 static void tx_hold(struct tty_struct *tty);
162 static void tx_release(struct tty_struct *tty);
163
164 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
165 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
166 static int chars_in_buffer(struct tty_struct *tty);
167 static void throttle(struct tty_struct * tty);
168 static void unthrottle(struct tty_struct * tty);
169 static void set_break(struct tty_struct *tty, int break_state);
170
171 /*
172 * generic HDLC support and callbacks
173 */
174 #ifdef CONFIG_HDLC
175 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
176 static void hdlcdev_tx_done(struct slgt_info *info);
177 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
178 static int hdlcdev_init(struct slgt_info *info);
179 static void hdlcdev_exit(struct slgt_info *info);
180 #endif
181
182
183 /*
184 * device specific structures, macros and functions
185 */
186
187 #define SLGT_MAX_PORTS 4
188 #define SLGT_REG_SIZE 256
189
190 /*
191 * conditional wait facility
192 */
193 struct cond_wait {
194 struct cond_wait *next;
195 wait_queue_head_t q;
196 wait_queue_t wait;
197 unsigned int data;
198 };
199 static void init_cond_wait(struct cond_wait *w, unsigned int data);
200 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
201 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
202 static void flush_cond_wait(struct cond_wait **head);
203
204 /*
205 * DMA buffer descriptor and access macros
206 */
207 struct slgt_desc
208 {
209 unsigned short count;
210 unsigned short status;
211 unsigned int pbuf; /* physical address of data buffer */
212 unsigned int next; /* physical address of next descriptor */
213
214 /* driver book keeping */
215 char *buf; /* virtual address of data buffer */
216 unsigned int pdesc; /* physical address of this descriptor */
217 dma_addr_t buf_dma_addr;
218 };
219
220 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
221 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
222 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
223 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
224 #define desc_count(a) (le16_to_cpu((a).count))
225 #define desc_status(a) (le16_to_cpu((a).status))
226 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
227 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
228 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
229 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
230 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
231
232 struct _input_signal_events {
233 int ri_up;
234 int ri_down;
235 int dsr_up;
236 int dsr_down;
237 int dcd_up;
238 int dcd_down;
239 int cts_up;
240 int cts_down;
241 };
242
243 /*
244 * device instance data structure
245 */
246 struct slgt_info {
247 void *if_ptr; /* General purpose pointer (used by SPPP) */
248
249 struct slgt_info *next_device; /* device list link */
250
251 int magic;
252 int flags;
253
254 char device_name[25];
255 struct pci_dev *pdev;
256
257 int port_count; /* count of ports on adapter */
258 int adapter_num; /* adapter instance number */
259 int port_num; /* port instance number */
260
261 /* array of pointers to port contexts on this adapter */
262 struct slgt_info *port_array[SLGT_MAX_PORTS];
263
264 int count; /* count of opens */
265 int line; /* tty line instance number */
266 unsigned short close_delay;
267 unsigned short closing_wait; /* time to wait before closing */
268
269 struct mgsl_icount icount;
270
271 struct tty_struct *tty;
272 int timeout;
273 int x_char; /* xon/xoff character */
274 int blocked_open; /* # of blocked opens */
275 unsigned int read_status_mask;
276 unsigned int ignore_status_mask;
277
278 wait_queue_head_t open_wait;
279 wait_queue_head_t close_wait;
280
281 wait_queue_head_t status_event_wait_q;
282 wait_queue_head_t event_wait_q;
283 struct timer_list tx_timer;
284 struct timer_list rx_timer;
285
286 unsigned int gpio_present;
287 struct cond_wait *gpio_wait_q;
288
289 spinlock_t lock; /* spinlock for synchronizing with ISR */
290
291 struct work_struct task;
292 u32 pending_bh;
293 int bh_requested;
294 int bh_running;
295
296 int isr_overflow;
297 int irq_requested; /* nonzero if IRQ requested */
298 int irq_occurred; /* for diagnostics use */
299
300 /* device configuration */
301
302 unsigned int bus_type;
303 unsigned int irq_level;
304 unsigned long irq_flags;
305
306 unsigned char __iomem * reg_addr; /* memory mapped registers address */
307 u32 phys_reg_addr;
308 int reg_addr_requested;
309
310 MGSL_PARAMS params; /* communications parameters */
311 u32 idle_mode;
312 u32 max_frame_size; /* as set by device config */
313
314 unsigned int raw_rx_size;
315 unsigned int if_mode;
316
317 /* device status */
318
319 int rx_enabled;
320 int rx_restart;
321
322 int tx_enabled;
323 int tx_active;
324
325 unsigned char signals; /* serial signal states */
326 int init_error; /* initialization error */
327
328 unsigned char *tx_buf;
329 int tx_count;
330
331 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
332 char char_buf[MAX_ASYNC_BUFFER_SIZE];
333 BOOLEAN drop_rts_on_tx_done;
334 struct _input_signal_events input_signal_events;
335
336 int dcd_chkcount; /* check counts to prevent */
337 int cts_chkcount; /* too many IRQs if a signal */
338 int dsr_chkcount; /* is floating */
339 int ri_chkcount;
340
341 char *bufs; /* virtual address of DMA buffer lists */
342 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
343
344 unsigned int rbuf_count;
345 struct slgt_desc *rbufs;
346 unsigned int rbuf_current;
347 unsigned int rbuf_index;
348
349 unsigned int tbuf_count;
350 struct slgt_desc *tbufs;
351 unsigned int tbuf_current;
352 unsigned int tbuf_start;
353
354 unsigned char *tmp_rbuf;
355 unsigned int tmp_rbuf_count;
356
357 /* SPPP/Cisco HDLC device parts */
358
359 int netcount;
360 int dosyncppp;
361 spinlock_t netlock;
362 #ifdef CONFIG_HDLC
363 struct net_device *netdev;
364 #endif
365
366 };
367
368 static MGSL_PARAMS default_params = {
369 .mode = MGSL_MODE_HDLC,
370 .loopback = 0,
371 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
372 .encoding = HDLC_ENCODING_NRZI_SPACE,
373 .clock_speed = 0,
374 .addr_filter = 0xff,
375 .crc_type = HDLC_CRC_16_CCITT,
376 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
377 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
378 .data_rate = 9600,
379 .data_bits = 8,
380 .stop_bits = 1,
381 .parity = ASYNC_PARITY_NONE
382 };
383
384
385 #define BH_RECEIVE 1
386 #define BH_TRANSMIT 2
387 #define BH_STATUS 4
388 #define IO_PIN_SHUTDOWN_LIMIT 100
389
390 #define DMABUFSIZE 256
391 #define DESC_LIST_SIZE 4096
392
393 #define MASK_PARITY BIT1
394 #define MASK_FRAMING BIT0
395 #define MASK_BREAK BIT14
396 #define MASK_OVERRUN BIT4
397
398 #define GSR 0x00 /* global status */
399 #define JCR 0x04 /* JTAG control */
400 #define IODR 0x08 /* GPIO direction */
401 #define IOER 0x0c /* GPIO interrupt enable */
402 #define IOVR 0x10 /* GPIO value */
403 #define IOSR 0x14 /* GPIO interrupt status */
404 #define TDR 0x80 /* tx data */
405 #define RDR 0x80 /* rx data */
406 #define TCR 0x82 /* tx control */
407 #define TIR 0x84 /* tx idle */
408 #define TPR 0x85 /* tx preamble */
409 #define RCR 0x86 /* rx control */
410 #define VCR 0x88 /* V.24 control */
411 #define CCR 0x89 /* clock control */
412 #define BDR 0x8a /* baud divisor */
413 #define SCR 0x8c /* serial control */
414 #define SSR 0x8e /* serial status */
415 #define RDCSR 0x90 /* rx DMA control/status */
416 #define TDCSR 0x94 /* tx DMA control/status */
417 #define RDDAR 0x98 /* rx DMA descriptor address */
418 #define TDDAR 0x9c /* tx DMA descriptor address */
419
420 #define RXIDLE BIT14
421 #define RXBREAK BIT14
422 #define IRQ_TXDATA BIT13
423 #define IRQ_TXIDLE BIT12
424 #define IRQ_TXUNDER BIT11 /* HDLC */
425 #define IRQ_RXDATA BIT10
426 #define IRQ_RXIDLE BIT9 /* HDLC */
427 #define IRQ_RXBREAK BIT9 /* async */
428 #define IRQ_RXOVER BIT8
429 #define IRQ_DSR BIT7
430 #define IRQ_CTS BIT6
431 #define IRQ_DCD BIT5
432 #define IRQ_RI BIT4
433 #define IRQ_ALL 0x3ff0
434 #define IRQ_MASTER BIT0
435
436 #define slgt_irq_on(info, mask) \
437 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
438 #define slgt_irq_off(info, mask) \
439 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
440
441 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
442 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
443 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
444 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
445 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
446 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
447
448 static void msc_set_vcr(struct slgt_info *info);
449
450 static int startup(struct slgt_info *info);
451 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
452 static void shutdown(struct slgt_info *info);
453 static void program_hw(struct slgt_info *info);
454 static void change_params(struct slgt_info *info);
455
456 static int register_test(struct slgt_info *info);
457 static int irq_test(struct slgt_info *info);
458 static int loopback_test(struct slgt_info *info);
459 static int adapter_test(struct slgt_info *info);
460
461 static void reset_adapter(struct slgt_info *info);
462 static void reset_port(struct slgt_info *info);
463 static void async_mode(struct slgt_info *info);
464 static void sync_mode(struct slgt_info *info);
465
466 static void rx_stop(struct slgt_info *info);
467 static void rx_start(struct slgt_info *info);
468 static void reset_rbufs(struct slgt_info *info);
469 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
470 static void rdma_reset(struct slgt_info *info);
471 static int rx_get_frame(struct slgt_info *info);
472 static int rx_get_buf(struct slgt_info *info);
473
474 static void tx_start(struct slgt_info *info);
475 static void tx_stop(struct slgt_info *info);
476 static void tx_set_idle(struct slgt_info *info);
477 static unsigned int free_tbuf_count(struct slgt_info *info);
478 static void reset_tbufs(struct slgt_info *info);
479 static void tdma_reset(struct slgt_info *info);
480 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
481
482 static void get_signals(struct slgt_info *info);
483 static void set_signals(struct slgt_info *info);
484 static void enable_loopback(struct slgt_info *info);
485 static void set_rate(struct slgt_info *info, u32 data_rate);
486
487 static int bh_action(struct slgt_info *info);
488 static void bh_handler(void* context);
489 static void bh_transmit(struct slgt_info *info);
490 static void isr_serial(struct slgt_info *info);
491 static void isr_rdma(struct slgt_info *info);
492 static void isr_txeom(struct slgt_info *info, unsigned short status);
493 static void isr_tdma(struct slgt_info *info);
494 static irqreturn_t slgt_interrupt(int irq, void *dev_id, struct pt_regs * regs);
495
496 static int alloc_dma_bufs(struct slgt_info *info);
497 static void free_dma_bufs(struct slgt_info *info);
498 static int alloc_desc(struct slgt_info *info);
499 static void free_desc(struct slgt_info *info);
500 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
501 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
502
503 static int alloc_tmp_rbuf(struct slgt_info *info);
504 static void free_tmp_rbuf(struct slgt_info *info);
505
506 static void tx_timeout(unsigned long context);
507 static void rx_timeout(unsigned long context);
508
509 /*
510 * ioctl handlers
511 */
512 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
513 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
514 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
515 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
516 static int set_txidle(struct slgt_info *info, int idle_mode);
517 static int tx_enable(struct slgt_info *info, int enable);
518 static int tx_abort(struct slgt_info *info);
519 static int rx_enable(struct slgt_info *info, int enable);
520 static int modem_input_wait(struct slgt_info *info,int arg);
521 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
522 static int tiocmget(struct tty_struct *tty, struct file *file);
523 static int tiocmset(struct tty_struct *tty, struct file *file,
524 unsigned int set, unsigned int clear);
525 static void set_break(struct tty_struct *tty, int break_state);
526 static int get_interface(struct slgt_info *info, int __user *if_mode);
527 static int set_interface(struct slgt_info *info, int if_mode);
528 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
529 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
530 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
531
532 /*
533 * driver functions
534 */
535 static void add_device(struct slgt_info *info);
536 static void device_init(int adapter_num, struct pci_dev *pdev);
537 static int claim_resources(struct slgt_info *info);
538 static void release_resources(struct slgt_info *info);
539
540 /*
541 * DEBUG OUTPUT CODE
542 */
543 #ifndef DBGINFO
544 #define DBGINFO(fmt)
545 #endif
546 #ifndef DBGERR
547 #define DBGERR(fmt)
548 #endif
549 #ifndef DBGBH
550 #define DBGBH(fmt)
551 #endif
552 #ifndef DBGISR
553 #define DBGISR(fmt)
554 #endif
555
556 #ifdef DBGDATA
557 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
558 {
559 int i;
560 int linecount;
561 printk("%s %s data:\n",info->device_name, label);
562 while(count) {
563 linecount = (count > 16) ? 16 : count;
564 for(i=0; i < linecount; i++)
565 printk("%02X ",(unsigned char)data[i]);
566 for(;i<17;i++)
567 printk(" ");
568 for(i=0;i<linecount;i++) {
569 if (data[i]>=040 && data[i]<=0176)
570 printk("%c",data[i]);
571 else
572 printk(".");
573 }
574 printk("\n");
575 data += linecount;
576 count -= linecount;
577 }
578 }
579 #else
580 #define DBGDATA(info, buf, size, label)
581 #endif
582
583 #ifdef DBGTBUF
584 static void dump_tbufs(struct slgt_info *info)
585 {
586 int i;
587 printk("tbuf_current=%d\n", info->tbuf_current);
588 for (i=0 ; i < info->tbuf_count ; i++) {
589 printk("%d: count=%04X status=%04X\n",
590 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
591 }
592 }
593 #else
594 #define DBGTBUF(info)
595 #endif
596
597 #ifdef DBGRBUF
598 static void dump_rbufs(struct slgt_info *info)
599 {
600 int i;
601 printk("rbuf_current=%d\n", info->rbuf_current);
602 for (i=0 ; i < info->rbuf_count ; i++) {
603 printk("%d: count=%04X status=%04X\n",
604 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
605 }
606 }
607 #else
608 #define DBGRBUF(info)
609 #endif
610
611 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
612 {
613 #ifdef SANITY_CHECK
614 if (!info) {
615 printk("null struct slgt_info for (%s) in %s\n", devname, name);
616 return 1;
617 }
618 if (info->magic != MGSL_MAGIC) {
619 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
620 return 1;
621 }
622 #else
623 if (!info)
624 return 1;
625 #endif
626 return 0;
627 }
628
629 /**
630 * line discipline callback wrappers
631 *
632 * The wrappers maintain line discipline references
633 * while calling into the line discipline.
634 *
635 * ldisc_receive_buf - pass receive data to line discipline
636 */
637 static void ldisc_receive_buf(struct tty_struct *tty,
638 const __u8 *data, char *flags, int count)
639 {
640 struct tty_ldisc *ld;
641 if (!tty)
642 return;
643 ld = tty_ldisc_ref(tty);
644 if (ld) {
645 if (ld->receive_buf)
646 ld->receive_buf(tty, data, flags, count);
647 tty_ldisc_deref(ld);
648 }
649 }
650
651 /* tty callbacks */
652
653 static int open(struct tty_struct *tty, struct file *filp)
654 {
655 struct slgt_info *info;
656 int retval, line;
657 unsigned long flags;
658
659 line = tty->index;
660 if ((line < 0) || (line >= slgt_device_count)) {
661 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
662 return -ENODEV;
663 }
664
665 info = slgt_device_list;
666 while(info && info->line != line)
667 info = info->next_device;
668 if (sanity_check(info, tty->name, "open"))
669 return -ENODEV;
670 if (info->init_error) {
671 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
672 return -ENODEV;
673 }
674
675 tty->driver_data = info;
676 info->tty = tty;
677
678 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
679
680 /* If port is closing, signal caller to try again */
681 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
682 if (info->flags & ASYNC_CLOSING)
683 interruptible_sleep_on(&info->close_wait);
684 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
685 -EAGAIN : -ERESTARTSYS);
686 goto cleanup;
687 }
688
689 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
690
691 spin_lock_irqsave(&info->netlock, flags);
692 if (info->netcount) {
693 retval = -EBUSY;
694 spin_unlock_irqrestore(&info->netlock, flags);
695 goto cleanup;
696 }
697 info->count++;
698 spin_unlock_irqrestore(&info->netlock, flags);
699
700 if (info->count == 1) {
701 /* 1st open on this device, init hardware */
702 retval = startup(info);
703 if (retval < 0)
704 goto cleanup;
705 }
706
707 retval = block_til_ready(tty, filp, info);
708 if (retval) {
709 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
710 goto cleanup;
711 }
712
713 retval = 0;
714
715 cleanup:
716 if (retval) {
717 if (tty->count == 1)
718 info->tty = NULL; /* tty layer will release tty struct */
719 if(info->count)
720 info->count--;
721 }
722
723 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
724 return retval;
725 }
726
727 static void close(struct tty_struct *tty, struct file *filp)
728 {
729 struct slgt_info *info = tty->driver_data;
730
731 if (sanity_check(info, tty->name, "close"))
732 return;
733 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
734
735 if (!info->count)
736 return;
737
738 if (tty_hung_up_p(filp))
739 goto cleanup;
740
741 if ((tty->count == 1) && (info->count != 1)) {
742 /*
743 * tty->count is 1 and the tty structure will be freed.
744 * info->count should be one in this case.
745 * if it's not, correct it so that the port is shutdown.
746 */
747 DBGERR(("%s close: bad refcount; tty->count=1, "
748 "info->count=%d\n", info->device_name, info->count));
749 info->count = 1;
750 }
751
752 info->count--;
753
754 /* if at least one open remaining, leave hardware active */
755 if (info->count)
756 goto cleanup;
757
758 info->flags |= ASYNC_CLOSING;
759
760 /* set tty->closing to notify line discipline to
761 * only process XON/XOFF characters. Only the N_TTY
762 * discipline appears to use this (ppp does not).
763 */
764 tty->closing = 1;
765
766 /* wait for transmit data to clear all layers */
767
768 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
769 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
770 tty_wait_until_sent(tty, info->closing_wait);
771 }
772
773 if (info->flags & ASYNC_INITIALIZED)
774 wait_until_sent(tty, info->timeout);
775 if (tty->driver->flush_buffer)
776 tty->driver->flush_buffer(tty);
777 tty_ldisc_flush(tty);
778
779 shutdown(info);
780
781 tty->closing = 0;
782 info->tty = NULL;
783
784 if (info->blocked_open) {
785 if (info->close_delay) {
786 msleep_interruptible(jiffies_to_msecs(info->close_delay));
787 }
788 wake_up_interruptible(&info->open_wait);
789 }
790
791 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
792
793 wake_up_interruptible(&info->close_wait);
794
795 cleanup:
796 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
797 }
798
799 static void hangup(struct tty_struct *tty)
800 {
801 struct slgt_info *info = tty->driver_data;
802
803 if (sanity_check(info, tty->name, "hangup"))
804 return;
805 DBGINFO(("%s hangup\n", info->device_name));
806
807 flush_buffer(tty);
808 shutdown(info);
809
810 info->count = 0;
811 info->flags &= ~ASYNC_NORMAL_ACTIVE;
812 info->tty = NULL;
813
814 wake_up_interruptible(&info->open_wait);
815 }
816
817 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
818 {
819 struct slgt_info *info = tty->driver_data;
820 unsigned long flags;
821
822 DBGINFO(("%s set_termios\n", tty->driver->name));
823
824 /* just return if nothing has changed */
825 if ((tty->termios->c_cflag == old_termios->c_cflag)
826 && (RELEVANT_IFLAG(tty->termios->c_iflag)
827 == RELEVANT_IFLAG(old_termios->c_iflag)))
828 return;
829
830 change_params(info);
831
832 /* Handle transition to B0 status */
833 if (old_termios->c_cflag & CBAUD &&
834 !(tty->termios->c_cflag & CBAUD)) {
835 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
836 spin_lock_irqsave(&info->lock,flags);
837 set_signals(info);
838 spin_unlock_irqrestore(&info->lock,flags);
839 }
840
841 /* Handle transition away from B0 status */
842 if (!(old_termios->c_cflag & CBAUD) &&
843 tty->termios->c_cflag & CBAUD) {
844 info->signals |= SerialSignal_DTR;
845 if (!(tty->termios->c_cflag & CRTSCTS) ||
846 !test_bit(TTY_THROTTLED, &tty->flags)) {
847 info->signals |= SerialSignal_RTS;
848 }
849 spin_lock_irqsave(&info->lock,flags);
850 set_signals(info);
851 spin_unlock_irqrestore(&info->lock,flags);
852 }
853
854 /* Handle turning off CRTSCTS */
855 if (old_termios->c_cflag & CRTSCTS &&
856 !(tty->termios->c_cflag & CRTSCTS)) {
857 tty->hw_stopped = 0;
858 tx_release(tty);
859 }
860 }
861
862 static int write(struct tty_struct *tty,
863 const unsigned char *buf, int count)
864 {
865 int ret = 0;
866 struct slgt_info *info = tty->driver_data;
867 unsigned long flags;
868
869 if (sanity_check(info, tty->name, "write"))
870 goto cleanup;
871 DBGINFO(("%s write count=%d\n", info->device_name, count));
872
873 if (!info->tx_buf)
874 goto cleanup;
875
876 if (count > info->max_frame_size) {
877 ret = -EIO;
878 goto cleanup;
879 }
880
881 if (!count)
882 goto cleanup;
883
884 if (info->params.mode == MGSL_MODE_RAW ||
885 info->params.mode == MGSL_MODE_MONOSYNC ||
886 info->params.mode == MGSL_MODE_BISYNC) {
887 unsigned int bufs_needed = (count/DMABUFSIZE);
888 unsigned int bufs_free = free_tbuf_count(info);
889 if (count % DMABUFSIZE)
890 ++bufs_needed;
891 if (bufs_needed > bufs_free)
892 goto cleanup;
893 } else {
894 if (info->tx_active)
895 goto cleanup;
896 if (info->tx_count) {
897 /* send accumulated data from send_char() calls */
898 /* as frame and wait before accepting more data. */
899 tx_load(info, info->tx_buf, info->tx_count);
900 goto start;
901 }
902 }
903
904 ret = info->tx_count = count;
905 tx_load(info, buf, count);
906 goto start;
907
908 start:
909 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
910 spin_lock_irqsave(&info->lock,flags);
911 if (!info->tx_active)
912 tx_start(info);
913 spin_unlock_irqrestore(&info->lock,flags);
914 }
915
916 cleanup:
917 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
918 return ret;
919 }
920
921 static void put_char(struct tty_struct *tty, unsigned char ch)
922 {
923 struct slgt_info *info = tty->driver_data;
924 unsigned long flags;
925
926 if (sanity_check(info, tty->name, "put_char"))
927 return;
928 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
929 if (!info->tx_buf)
930 return;
931 spin_lock_irqsave(&info->lock,flags);
932 if (!info->tx_active && (info->tx_count < info->max_frame_size))
933 info->tx_buf[info->tx_count++] = ch;
934 spin_unlock_irqrestore(&info->lock,flags);
935 }
936
937 static void send_xchar(struct tty_struct *tty, char ch)
938 {
939 struct slgt_info *info = tty->driver_data;
940 unsigned long flags;
941
942 if (sanity_check(info, tty->name, "send_xchar"))
943 return;
944 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
945 info->x_char = ch;
946 if (ch) {
947 spin_lock_irqsave(&info->lock,flags);
948 if (!info->tx_enabled)
949 tx_start(info);
950 spin_unlock_irqrestore(&info->lock,flags);
951 }
952 }
953
954 static void wait_until_sent(struct tty_struct *tty, int timeout)
955 {
956 struct slgt_info *info = tty->driver_data;
957 unsigned long orig_jiffies, char_time;
958
959 if (!info )
960 return;
961 if (sanity_check(info, tty->name, "wait_until_sent"))
962 return;
963 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
964 if (!(info->flags & ASYNC_INITIALIZED))
965 goto exit;
966
967 orig_jiffies = jiffies;
968
969 /* Set check interval to 1/5 of estimated time to
970 * send a character, and make it at least 1. The check
971 * interval should also be less than the timeout.
972 * Note: use tight timings here to satisfy the NIST-PCTS.
973 */
974
975 if (info->params.data_rate) {
976 char_time = info->timeout/(32 * 5);
977 if (!char_time)
978 char_time++;
979 } else
980 char_time = 1;
981
982 if (timeout)
983 char_time = min_t(unsigned long, char_time, timeout);
984
985 while (info->tx_active) {
986 msleep_interruptible(jiffies_to_msecs(char_time));
987 if (signal_pending(current))
988 break;
989 if (timeout && time_after(jiffies, orig_jiffies + timeout))
990 break;
991 }
992
993 exit:
994 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
995 }
996
997 static int write_room(struct tty_struct *tty)
998 {
999 struct slgt_info *info = tty->driver_data;
1000 int ret;
1001
1002 if (sanity_check(info, tty->name, "write_room"))
1003 return 0;
1004 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1005 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
1006 return ret;
1007 }
1008
1009 static void flush_chars(struct tty_struct *tty)
1010 {
1011 struct slgt_info *info = tty->driver_data;
1012 unsigned long flags;
1013
1014 if (sanity_check(info, tty->name, "flush_chars"))
1015 return;
1016 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1017
1018 if (info->tx_count <= 0 || tty->stopped ||
1019 tty->hw_stopped || !info->tx_buf)
1020 return;
1021
1022 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1023
1024 spin_lock_irqsave(&info->lock,flags);
1025 if (!info->tx_active && info->tx_count) {
1026 tx_load(info, info->tx_buf,info->tx_count);
1027 tx_start(info);
1028 }
1029 spin_unlock_irqrestore(&info->lock,flags);
1030 }
1031
1032 static void flush_buffer(struct tty_struct *tty)
1033 {
1034 struct slgt_info *info = tty->driver_data;
1035 unsigned long flags;
1036
1037 if (sanity_check(info, tty->name, "flush_buffer"))
1038 return;
1039 DBGINFO(("%s flush_buffer\n", info->device_name));
1040
1041 spin_lock_irqsave(&info->lock,flags);
1042 if (!info->tx_active)
1043 info->tx_count = 0;
1044 spin_unlock_irqrestore(&info->lock,flags);
1045
1046 wake_up_interruptible(&tty->write_wait);
1047 tty_wakeup(tty);
1048 }
1049
1050 /*
1051 * throttle (stop) transmitter
1052 */
1053 static void tx_hold(struct tty_struct *tty)
1054 {
1055 struct slgt_info *info = tty->driver_data;
1056 unsigned long flags;
1057
1058 if (sanity_check(info, tty->name, "tx_hold"))
1059 return;
1060 DBGINFO(("%s tx_hold\n", info->device_name));
1061 spin_lock_irqsave(&info->lock,flags);
1062 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1063 tx_stop(info);
1064 spin_unlock_irqrestore(&info->lock,flags);
1065 }
1066
1067 /*
1068 * release (start) transmitter
1069 */
1070 static void tx_release(struct tty_struct *tty)
1071 {
1072 struct slgt_info *info = tty->driver_data;
1073 unsigned long flags;
1074
1075 if (sanity_check(info, tty->name, "tx_release"))
1076 return;
1077 DBGINFO(("%s tx_release\n", info->device_name));
1078 spin_lock_irqsave(&info->lock,flags);
1079 if (!info->tx_active && info->tx_count) {
1080 tx_load(info, info->tx_buf, info->tx_count);
1081 tx_start(info);
1082 }
1083 spin_unlock_irqrestore(&info->lock,flags);
1084 }
1085
1086 /*
1087 * Service an IOCTL request
1088 *
1089 * Arguments
1090 *
1091 * tty pointer to tty instance data
1092 * file pointer to associated file object for device
1093 * cmd IOCTL command code
1094 * arg command argument/context
1095 *
1096 * Return 0 if success, otherwise error code
1097 */
1098 static int ioctl(struct tty_struct *tty, struct file *file,
1099 unsigned int cmd, unsigned long arg)
1100 {
1101 struct slgt_info *info = tty->driver_data;
1102 struct mgsl_icount cnow; /* kernel counter temps */
1103 struct serial_icounter_struct __user *p_cuser; /* user space */
1104 unsigned long flags;
1105 void __user *argp = (void __user *)arg;
1106
1107 if (sanity_check(info, tty->name, "ioctl"))
1108 return -ENODEV;
1109 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1110
1111 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1112 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1113 if (tty->flags & (1 << TTY_IO_ERROR))
1114 return -EIO;
1115 }
1116
1117 switch (cmd) {
1118 case MGSL_IOCGPARAMS:
1119 return get_params(info, argp);
1120 case MGSL_IOCSPARAMS:
1121 return set_params(info, argp);
1122 case MGSL_IOCGTXIDLE:
1123 return get_txidle(info, argp);
1124 case MGSL_IOCSTXIDLE:
1125 return set_txidle(info, (int)arg);
1126 case MGSL_IOCTXENABLE:
1127 return tx_enable(info, (int)arg);
1128 case MGSL_IOCRXENABLE:
1129 return rx_enable(info, (int)arg);
1130 case MGSL_IOCTXABORT:
1131 return tx_abort(info);
1132 case MGSL_IOCGSTATS:
1133 return get_stats(info, argp);
1134 case MGSL_IOCWAITEVENT:
1135 return wait_mgsl_event(info, argp);
1136 case TIOCMIWAIT:
1137 return modem_input_wait(info,(int)arg);
1138 case MGSL_IOCGIF:
1139 return get_interface(info, argp);
1140 case MGSL_IOCSIF:
1141 return set_interface(info,(int)arg);
1142 case MGSL_IOCSGPIO:
1143 return set_gpio(info, argp);
1144 case MGSL_IOCGGPIO:
1145 return get_gpio(info, argp);
1146 case MGSL_IOCWAITGPIO:
1147 return wait_gpio(info, argp);
1148 case TIOCGICOUNT:
1149 spin_lock_irqsave(&info->lock,flags);
1150 cnow = info->icount;
1151 spin_unlock_irqrestore(&info->lock,flags);
1152 p_cuser = argp;
1153 if (put_user(cnow.cts, &p_cuser->cts) ||
1154 put_user(cnow.dsr, &p_cuser->dsr) ||
1155 put_user(cnow.rng, &p_cuser->rng) ||
1156 put_user(cnow.dcd, &p_cuser->dcd) ||
1157 put_user(cnow.rx, &p_cuser->rx) ||
1158 put_user(cnow.tx, &p_cuser->tx) ||
1159 put_user(cnow.frame, &p_cuser->frame) ||
1160 put_user(cnow.overrun, &p_cuser->overrun) ||
1161 put_user(cnow.parity, &p_cuser->parity) ||
1162 put_user(cnow.brk, &p_cuser->brk) ||
1163 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1164 return -EFAULT;
1165 return 0;
1166 default:
1167 return -ENOIOCTLCMD;
1168 }
1169 return 0;
1170 }
1171
1172 /*
1173 * proc fs support
1174 */
1175 static inline int line_info(char *buf, struct slgt_info *info)
1176 {
1177 char stat_buf[30];
1178 int ret;
1179 unsigned long flags;
1180
1181 ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1182 info->device_name, info->phys_reg_addr,
1183 info->irq_level, info->max_frame_size);
1184
1185 /* output current serial signal states */
1186 spin_lock_irqsave(&info->lock,flags);
1187 get_signals(info);
1188 spin_unlock_irqrestore(&info->lock,flags);
1189
1190 stat_buf[0] = 0;
1191 stat_buf[1] = 0;
1192 if (info->signals & SerialSignal_RTS)
1193 strcat(stat_buf, "|RTS");
1194 if (info->signals & SerialSignal_CTS)
1195 strcat(stat_buf, "|CTS");
1196 if (info->signals & SerialSignal_DTR)
1197 strcat(stat_buf, "|DTR");
1198 if (info->signals & SerialSignal_DSR)
1199 strcat(stat_buf, "|DSR");
1200 if (info->signals & SerialSignal_DCD)
1201 strcat(stat_buf, "|CD");
1202 if (info->signals & SerialSignal_RI)
1203 strcat(stat_buf, "|RI");
1204
1205 if (info->params.mode != MGSL_MODE_ASYNC) {
1206 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1207 info->icount.txok, info->icount.rxok);
1208 if (info->icount.txunder)
1209 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1210 if (info->icount.txabort)
1211 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1212 if (info->icount.rxshort)
1213 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1214 if (info->icount.rxlong)
1215 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1216 if (info->icount.rxover)
1217 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1218 if (info->icount.rxcrc)
1219 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1220 } else {
1221 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1222 info->icount.tx, info->icount.rx);
1223 if (info->icount.frame)
1224 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1225 if (info->icount.parity)
1226 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1227 if (info->icount.brk)
1228 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1229 if (info->icount.overrun)
1230 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1231 }
1232
1233 /* Append serial signal status to end */
1234 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1235
1236 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1237 info->tx_active,info->bh_requested,info->bh_running,
1238 info->pending_bh);
1239
1240 return ret;
1241 }
1242
1243 /* Called to print information about devices
1244 */
1245 static int read_proc(char *page, char **start, off_t off, int count,
1246 int *eof, void *data)
1247 {
1248 int len = 0, l;
1249 off_t begin = 0;
1250 struct slgt_info *info;
1251
1252 len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1253
1254 info = slgt_device_list;
1255 while( info ) {
1256 l = line_info(page + len, info);
1257 len += l;
1258 if (len+begin > off+count)
1259 goto done;
1260 if (len+begin < off) {
1261 begin += len;
1262 len = 0;
1263 }
1264 info = info->next_device;
1265 }
1266
1267 *eof = 1;
1268 done:
1269 if (off >= len+begin)
1270 return 0;
1271 *start = page + (off-begin);
1272 return ((count < begin+len-off) ? count : begin+len-off);
1273 }
1274
1275 /*
1276 * return count of bytes in transmit buffer
1277 */
1278 static int chars_in_buffer(struct tty_struct *tty)
1279 {
1280 struct slgt_info *info = tty->driver_data;
1281 if (sanity_check(info, tty->name, "chars_in_buffer"))
1282 return 0;
1283 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1284 return info->tx_count;
1285 }
1286
1287 /*
1288 * signal remote device to throttle send data (our receive data)
1289 */
1290 static void throttle(struct tty_struct * tty)
1291 {
1292 struct slgt_info *info = tty->driver_data;
1293 unsigned long flags;
1294
1295 if (sanity_check(info, tty->name, "throttle"))
1296 return;
1297 DBGINFO(("%s throttle\n", info->device_name));
1298 if (I_IXOFF(tty))
1299 send_xchar(tty, STOP_CHAR(tty));
1300 if (tty->termios->c_cflag & CRTSCTS) {
1301 spin_lock_irqsave(&info->lock,flags);
1302 info->signals &= ~SerialSignal_RTS;
1303 set_signals(info);
1304 spin_unlock_irqrestore(&info->lock,flags);
1305 }
1306 }
1307
1308 /*
1309 * signal remote device to stop throttling send data (our receive data)
1310 */
1311 static void unthrottle(struct tty_struct * tty)
1312 {
1313 struct slgt_info *info = tty->driver_data;
1314 unsigned long flags;
1315
1316 if (sanity_check(info, tty->name, "unthrottle"))
1317 return;
1318 DBGINFO(("%s unthrottle\n", info->device_name));
1319 if (I_IXOFF(tty)) {
1320 if (info->x_char)
1321 info->x_char = 0;
1322 else
1323 send_xchar(tty, START_CHAR(tty));
1324 }
1325 if (tty->termios->c_cflag & CRTSCTS) {
1326 spin_lock_irqsave(&info->lock,flags);
1327 info->signals |= SerialSignal_RTS;
1328 set_signals(info);
1329 spin_unlock_irqrestore(&info->lock,flags);
1330 }
1331 }
1332
1333 /*
1334 * set or clear transmit break condition
1335 * break_state -1=set break condition, 0=clear
1336 */
1337 static void set_break(struct tty_struct *tty, int break_state)
1338 {
1339 struct slgt_info *info = tty->driver_data;
1340 unsigned short value;
1341 unsigned long flags;
1342
1343 if (sanity_check(info, tty->name, "set_break"))
1344 return;
1345 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1346
1347 spin_lock_irqsave(&info->lock,flags);
1348 value = rd_reg16(info, TCR);
1349 if (break_state == -1)
1350 value |= BIT6;
1351 else
1352 value &= ~BIT6;
1353 wr_reg16(info, TCR, value);
1354 spin_unlock_irqrestore(&info->lock,flags);
1355 }
1356
1357 #ifdef CONFIG_HDLC
1358
1359 /**
1360 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1361 * set encoding and frame check sequence (FCS) options
1362 *
1363 * dev pointer to network device structure
1364 * encoding serial encoding setting
1365 * parity FCS setting
1366 *
1367 * returns 0 if success, otherwise error code
1368 */
1369 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1370 unsigned short parity)
1371 {
1372 struct slgt_info *info = dev_to_port(dev);
1373 unsigned char new_encoding;
1374 unsigned short new_crctype;
1375
1376 /* return error if TTY interface open */
1377 if (info->count)
1378 return -EBUSY;
1379
1380 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1381
1382 switch (encoding)
1383 {
1384 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1385 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1386 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1387 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1388 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1389 default: return -EINVAL;
1390 }
1391
1392 switch (parity)
1393 {
1394 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1395 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1396 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1397 default: return -EINVAL;
1398 }
1399
1400 info->params.encoding = new_encoding;
1401 info->params.crc_type = new_crctype;
1402
1403 /* if network interface up, reprogram hardware */
1404 if (info->netcount)
1405 program_hw(info);
1406
1407 return 0;
1408 }
1409
1410 /**
1411 * called by generic HDLC layer to send frame
1412 *
1413 * skb socket buffer containing HDLC frame
1414 * dev pointer to network device structure
1415 *
1416 * returns 0 if success, otherwise error code
1417 */
1418 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1419 {
1420 struct slgt_info *info = dev_to_port(dev);
1421 struct net_device_stats *stats = hdlc_stats(dev);
1422 unsigned long flags;
1423
1424 DBGINFO(("%s hdlc_xmit\n", dev->name));
1425
1426 /* stop sending until this frame completes */
1427 netif_stop_queue(dev);
1428
1429 /* copy data to device buffers */
1430 info->tx_count = skb->len;
1431 tx_load(info, skb->data, skb->len);
1432
1433 /* update network statistics */
1434 stats->tx_packets++;
1435 stats->tx_bytes += skb->len;
1436
1437 /* done with socket buffer, so free it */
1438 dev_kfree_skb(skb);
1439
1440 /* save start time for transmit timeout detection */
1441 dev->trans_start = jiffies;
1442
1443 /* start hardware transmitter if necessary */
1444 spin_lock_irqsave(&info->lock,flags);
1445 if (!info->tx_active)
1446 tx_start(info);
1447 spin_unlock_irqrestore(&info->lock,flags);
1448
1449 return 0;
1450 }
1451
1452 /**
1453 * called by network layer when interface enabled
1454 * claim resources and initialize hardware
1455 *
1456 * dev pointer to network device structure
1457 *
1458 * returns 0 if success, otherwise error code
1459 */
1460 static int hdlcdev_open(struct net_device *dev)
1461 {
1462 struct slgt_info *info = dev_to_port(dev);
1463 int rc;
1464 unsigned long flags;
1465
1466 DBGINFO(("%s hdlcdev_open\n", dev->name));
1467
1468 /* generic HDLC layer open processing */
1469 if ((rc = hdlc_open(dev)))
1470 return rc;
1471
1472 /* arbitrate between network and tty opens */
1473 spin_lock_irqsave(&info->netlock, flags);
1474 if (info->count != 0 || info->netcount != 0) {
1475 DBGINFO(("%s hdlc_open busy\n", dev->name));
1476 spin_unlock_irqrestore(&info->netlock, flags);
1477 return -EBUSY;
1478 }
1479 info->netcount=1;
1480 spin_unlock_irqrestore(&info->netlock, flags);
1481
1482 /* claim resources and init adapter */
1483 if ((rc = startup(info)) != 0) {
1484 spin_lock_irqsave(&info->netlock, flags);
1485 info->netcount=0;
1486 spin_unlock_irqrestore(&info->netlock, flags);
1487 return rc;
1488 }
1489
1490 /* assert DTR and RTS, apply hardware settings */
1491 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1492 program_hw(info);
1493
1494 /* enable network layer transmit */
1495 dev->trans_start = jiffies;
1496 netif_start_queue(dev);
1497
1498 /* inform generic HDLC layer of current DCD status */
1499 spin_lock_irqsave(&info->lock, flags);
1500 get_signals(info);
1501 spin_unlock_irqrestore(&info->lock, flags);
1502 if (info->signals & SerialSignal_DCD)
1503 netif_carrier_on(dev);
1504 else
1505 netif_carrier_off(dev);
1506 return 0;
1507 }
1508
1509 /**
1510 * called by network layer when interface is disabled
1511 * shutdown hardware and release resources
1512 *
1513 * dev pointer to network device structure
1514 *
1515 * returns 0 if success, otherwise error code
1516 */
1517 static int hdlcdev_close(struct net_device *dev)
1518 {
1519 struct slgt_info *info = dev_to_port(dev);
1520 unsigned long flags;
1521
1522 DBGINFO(("%s hdlcdev_close\n", dev->name));
1523
1524 netif_stop_queue(dev);
1525
1526 /* shutdown adapter and release resources */
1527 shutdown(info);
1528
1529 hdlc_close(dev);
1530
1531 spin_lock_irqsave(&info->netlock, flags);
1532 info->netcount=0;
1533 spin_unlock_irqrestore(&info->netlock, flags);
1534
1535 return 0;
1536 }
1537
1538 /**
1539 * called by network layer to process IOCTL call to network device
1540 *
1541 * dev pointer to network device structure
1542 * ifr pointer to network interface request structure
1543 * cmd IOCTL command code
1544 *
1545 * returns 0 if success, otherwise error code
1546 */
1547 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1548 {
1549 const size_t size = sizeof(sync_serial_settings);
1550 sync_serial_settings new_line;
1551 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1552 struct slgt_info *info = dev_to_port(dev);
1553 unsigned int flags;
1554
1555 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1556
1557 /* return error if TTY interface open */
1558 if (info->count)
1559 return -EBUSY;
1560
1561 if (cmd != SIOCWANDEV)
1562 return hdlc_ioctl(dev, ifr, cmd);
1563
1564 switch(ifr->ifr_settings.type) {
1565 case IF_GET_IFACE: /* return current sync_serial_settings */
1566
1567 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1568 if (ifr->ifr_settings.size < size) {
1569 ifr->ifr_settings.size = size; /* data size wanted */
1570 return -ENOBUFS;
1571 }
1572
1573 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1574 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1575 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1576 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1577
1578 switch (flags){
1579 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1580 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1581 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1582 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1583 default: new_line.clock_type = CLOCK_DEFAULT;
1584 }
1585
1586 new_line.clock_rate = info->params.clock_speed;
1587 new_line.loopback = info->params.loopback ? 1:0;
1588
1589 if (copy_to_user(line, &new_line, size))
1590 return -EFAULT;
1591 return 0;
1592
1593 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1594
1595 if(!capable(CAP_NET_ADMIN))
1596 return -EPERM;
1597 if (copy_from_user(&new_line, line, size))
1598 return -EFAULT;
1599
1600 switch (new_line.clock_type)
1601 {
1602 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1603 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1604 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1605 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1606 case CLOCK_DEFAULT: flags = info->params.flags &
1607 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1608 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1609 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1610 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1611 default: return -EINVAL;
1612 }
1613
1614 if (new_line.loopback != 0 && new_line.loopback != 1)
1615 return -EINVAL;
1616
1617 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1618 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1619 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1620 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1621 info->params.flags |= flags;
1622
1623 info->params.loopback = new_line.loopback;
1624
1625 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1626 info->params.clock_speed = new_line.clock_rate;
1627 else
1628 info->params.clock_speed = 0;
1629
1630 /* if network interface up, reprogram hardware */
1631 if (info->netcount)
1632 program_hw(info);
1633 return 0;
1634
1635 default:
1636 return hdlc_ioctl(dev, ifr, cmd);
1637 }
1638 }
1639
1640 /**
1641 * called by network layer when transmit timeout is detected
1642 *
1643 * dev pointer to network device structure
1644 */
1645 static void hdlcdev_tx_timeout(struct net_device *dev)
1646 {
1647 struct slgt_info *info = dev_to_port(dev);
1648 struct net_device_stats *stats = hdlc_stats(dev);
1649 unsigned long flags;
1650
1651 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1652
1653 stats->tx_errors++;
1654 stats->tx_aborted_errors++;
1655
1656 spin_lock_irqsave(&info->lock,flags);
1657 tx_stop(info);
1658 spin_unlock_irqrestore(&info->lock,flags);
1659
1660 netif_wake_queue(dev);
1661 }
1662
1663 /**
1664 * called by device driver when transmit completes
1665 * reenable network layer transmit if stopped
1666 *
1667 * info pointer to device instance information
1668 */
1669 static void hdlcdev_tx_done(struct slgt_info *info)
1670 {
1671 if (netif_queue_stopped(info->netdev))
1672 netif_wake_queue(info->netdev);
1673 }
1674
1675 /**
1676 * called by device driver when frame received
1677 * pass frame to network layer
1678 *
1679 * info pointer to device instance information
1680 * buf pointer to buffer contianing frame data
1681 * size count of data bytes in buf
1682 */
1683 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1684 {
1685 struct sk_buff *skb = dev_alloc_skb(size);
1686 struct net_device *dev = info->netdev;
1687 struct net_device_stats *stats = hdlc_stats(dev);
1688
1689 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1690
1691 if (skb == NULL) {
1692 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1693 stats->rx_dropped++;
1694 return;
1695 }
1696
1697 memcpy(skb_put(skb, size),buf,size);
1698
1699 skb->protocol = hdlc_type_trans(skb, info->netdev);
1700
1701 stats->rx_packets++;
1702 stats->rx_bytes += size;
1703
1704 netif_rx(skb);
1705
1706 info->netdev->last_rx = jiffies;
1707 }
1708
1709 /**
1710 * called by device driver when adding device instance
1711 * do generic HDLC initialization
1712 *
1713 * info pointer to device instance information
1714 *
1715 * returns 0 if success, otherwise error code
1716 */
1717 static int hdlcdev_init(struct slgt_info *info)
1718 {
1719 int rc;
1720 struct net_device *dev;
1721 hdlc_device *hdlc;
1722
1723 /* allocate and initialize network and HDLC layer objects */
1724
1725 if (!(dev = alloc_hdlcdev(info))) {
1726 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1727 return -ENOMEM;
1728 }
1729
1730 /* for network layer reporting purposes only */
1731 dev->mem_start = info->phys_reg_addr;
1732 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1733 dev->irq = info->irq_level;
1734
1735 /* network layer callbacks and settings */
1736 dev->do_ioctl = hdlcdev_ioctl;
1737 dev->open = hdlcdev_open;
1738 dev->stop = hdlcdev_close;
1739 dev->tx_timeout = hdlcdev_tx_timeout;
1740 dev->watchdog_timeo = 10*HZ;
1741 dev->tx_queue_len = 50;
1742
1743 /* generic HDLC layer callbacks and settings */
1744 hdlc = dev_to_hdlc(dev);
1745 hdlc->attach = hdlcdev_attach;
1746 hdlc->xmit = hdlcdev_xmit;
1747
1748 /* register objects with HDLC layer */
1749 if ((rc = register_hdlc_device(dev))) {
1750 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1751 free_netdev(dev);
1752 return rc;
1753 }
1754
1755 info->netdev = dev;
1756 return 0;
1757 }
1758
1759 /**
1760 * called by device driver when removing device instance
1761 * do generic HDLC cleanup
1762 *
1763 * info pointer to device instance information
1764 */
1765 static void hdlcdev_exit(struct slgt_info *info)
1766 {
1767 unregister_hdlc_device(info->netdev);
1768 free_netdev(info->netdev);
1769 info->netdev = NULL;
1770 }
1771
1772 #endif /* ifdef CONFIG_HDLC */
1773
1774 /*
1775 * get async data from rx DMA buffers
1776 */
1777 static void rx_async(struct slgt_info *info)
1778 {
1779 struct tty_struct *tty = info->tty;
1780 struct mgsl_icount *icount = &info->icount;
1781 unsigned int start, end;
1782 unsigned char *p;
1783 unsigned char status;
1784 struct slgt_desc *bufs = info->rbufs;
1785 int i, count;
1786 int chars = 0;
1787 int stat;
1788 unsigned char ch;
1789
1790 start = end = info->rbuf_current;
1791
1792 while(desc_complete(bufs[end])) {
1793 count = desc_count(bufs[end]) - info->rbuf_index;
1794 p = bufs[end].buf + info->rbuf_index;
1795
1796 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1797 DBGDATA(info, p, count, "rx");
1798
1799 for(i=0 ; i < count; i+=2, p+=2) {
1800 ch = *p;
1801 icount->rx++;
1802
1803 stat = 0;
1804
1805 if ((status = *(p+1) & (BIT1 + BIT0))) {
1806 if (status & BIT1)
1807 icount->parity++;
1808 else if (status & BIT0)
1809 icount->frame++;
1810 /* discard char if tty control flags say so */
1811 if (status & info->ignore_status_mask)
1812 continue;
1813 if (status & BIT1)
1814 stat = TTY_PARITY;
1815 else if (status & BIT0)
1816 stat = TTY_FRAME;
1817 }
1818 if (tty) {
1819 tty_insert_flip_char(tty, ch, stat);
1820 chars++;
1821 }
1822 }
1823
1824 if (i < count) {
1825 /* receive buffer not completed */
1826 info->rbuf_index += i;
1827 info->rx_timer.expires = jiffies + 1;
1828 add_timer(&info->rx_timer);
1829 break;
1830 }
1831
1832 info->rbuf_index = 0;
1833 free_rbufs(info, end, end);
1834
1835 if (++end == info->rbuf_count)
1836 end = 0;
1837
1838 /* if entire list searched then no frame available */
1839 if (end == start)
1840 break;
1841 }
1842
1843 if (tty && chars)
1844 tty_flip_buffer_push(tty);
1845 }
1846
1847 /*
1848 * return next bottom half action to perform
1849 */
1850 static int bh_action(struct slgt_info *info)
1851 {
1852 unsigned long flags;
1853 int rc;
1854
1855 spin_lock_irqsave(&info->lock,flags);
1856
1857 if (info->pending_bh & BH_RECEIVE) {
1858 info->pending_bh &= ~BH_RECEIVE;
1859 rc = BH_RECEIVE;
1860 } else if (info->pending_bh & BH_TRANSMIT) {
1861 info->pending_bh &= ~BH_TRANSMIT;
1862 rc = BH_TRANSMIT;
1863 } else if (info->pending_bh & BH_STATUS) {
1864 info->pending_bh &= ~BH_STATUS;
1865 rc = BH_STATUS;
1866 } else {
1867 /* Mark BH routine as complete */
1868 info->bh_running = 0;
1869 info->bh_requested = 0;
1870 rc = 0;
1871 }
1872
1873 spin_unlock_irqrestore(&info->lock,flags);
1874
1875 return rc;
1876 }
1877
1878 /*
1879 * perform bottom half processing
1880 */
1881 static void bh_handler(void* context)
1882 {
1883 struct slgt_info *info = context;
1884 int action;
1885
1886 if (!info)
1887 return;
1888 info->bh_running = 1;
1889
1890 while((action = bh_action(info))) {
1891 switch (action) {
1892 case BH_RECEIVE:
1893 DBGBH(("%s bh receive\n", info->device_name));
1894 switch(info->params.mode) {
1895 case MGSL_MODE_ASYNC:
1896 rx_async(info);
1897 break;
1898 case MGSL_MODE_HDLC:
1899 while(rx_get_frame(info));
1900 break;
1901 case MGSL_MODE_RAW:
1902 case MGSL_MODE_MONOSYNC:
1903 case MGSL_MODE_BISYNC:
1904 while(rx_get_buf(info));
1905 break;
1906 }
1907 /* restart receiver if rx DMA buffers exhausted */
1908 if (info->rx_restart)
1909 rx_start(info);
1910 break;
1911 case BH_TRANSMIT:
1912 bh_transmit(info);
1913 break;
1914 case BH_STATUS:
1915 DBGBH(("%s bh status\n", info->device_name));
1916 info->ri_chkcount = 0;
1917 info->dsr_chkcount = 0;
1918 info->dcd_chkcount = 0;
1919 info->cts_chkcount = 0;
1920 break;
1921 default:
1922 DBGBH(("%s unknown action\n", info->device_name));
1923 break;
1924 }
1925 }
1926 DBGBH(("%s bh_handler exit\n", info->device_name));
1927 }
1928
1929 static void bh_transmit(struct slgt_info *info)
1930 {
1931 struct tty_struct *tty = info->tty;
1932
1933 DBGBH(("%s bh_transmit\n", info->device_name));
1934 if (tty) {
1935 tty_wakeup(tty);
1936 wake_up_interruptible(&tty->write_wait);
1937 }
1938 }
1939
1940 static void dsr_change(struct slgt_info *info)
1941 {
1942 get_signals(info);
1943 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1944 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1945 slgt_irq_off(info, IRQ_DSR);
1946 return;
1947 }
1948 info->icount.dsr++;
1949 if (info->signals & SerialSignal_DSR)
1950 info->input_signal_events.dsr_up++;
1951 else
1952 info->input_signal_events.dsr_down++;
1953 wake_up_interruptible(&info->status_event_wait_q);
1954 wake_up_interruptible(&info->event_wait_q);
1955 info->pending_bh |= BH_STATUS;
1956 }
1957
1958 static void cts_change(struct slgt_info *info)
1959 {
1960 get_signals(info);
1961 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1962 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1963 slgt_irq_off(info, IRQ_CTS);
1964 return;
1965 }
1966 info->icount.cts++;
1967 if (info->signals & SerialSignal_CTS)
1968 info->input_signal_events.cts_up++;
1969 else
1970 info->input_signal_events.cts_down++;
1971 wake_up_interruptible(&info->status_event_wait_q);
1972 wake_up_interruptible(&info->event_wait_q);
1973 info->pending_bh |= BH_STATUS;
1974
1975 if (info->flags & ASYNC_CTS_FLOW) {
1976 if (info->tty) {
1977 if (info->tty->hw_stopped) {
1978 if (info->signals & SerialSignal_CTS) {
1979 info->tty->hw_stopped = 0;
1980 info->pending_bh |= BH_TRANSMIT;
1981 return;
1982 }
1983 } else {
1984 if (!(info->signals & SerialSignal_CTS))
1985 info->tty->hw_stopped = 1;
1986 }
1987 }
1988 }
1989 }
1990
1991 static void dcd_change(struct slgt_info *info)
1992 {
1993 get_signals(info);
1994 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1995 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1996 slgt_irq_off(info, IRQ_DCD);
1997 return;
1998 }
1999 info->icount.dcd++;
2000 if (info->signals & SerialSignal_DCD) {
2001 info->input_signal_events.dcd_up++;
2002 } else {
2003 info->input_signal_events.dcd_down++;
2004 }
2005 #ifdef CONFIG_HDLC
2006 if (info->netcount) {
2007 if (info->signals & SerialSignal_DCD)
2008 netif_carrier_on(info->netdev);
2009 else
2010 netif_carrier_off(info->netdev);
2011 }
2012 #endif
2013 wake_up_interruptible(&info->status_event_wait_q);
2014 wake_up_interruptible(&info->event_wait_q);
2015 info->pending_bh |= BH_STATUS;
2016
2017 if (info->flags & ASYNC_CHECK_CD) {
2018 if (info->signals & SerialSignal_DCD)
2019 wake_up_interruptible(&info->open_wait);
2020 else {
2021 if (info->tty)
2022 tty_hangup(info->tty);
2023 }
2024 }
2025 }
2026
2027 static void ri_change(struct slgt_info *info)
2028 {
2029 get_signals(info);
2030 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2031 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2032 slgt_irq_off(info, IRQ_RI);
2033 return;
2034 }
2035 info->icount.dcd++;
2036 if (info->signals & SerialSignal_RI) {
2037 info->input_signal_events.ri_up++;
2038 } else {
2039 info->input_signal_events.ri_down++;
2040 }
2041 wake_up_interruptible(&info->status_event_wait_q);
2042 wake_up_interruptible(&info->event_wait_q);
2043 info->pending_bh |= BH_STATUS;
2044 }
2045
2046 static void isr_serial(struct slgt_info *info)
2047 {
2048 unsigned short status = rd_reg16(info, SSR);
2049
2050 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2051
2052 wr_reg16(info, SSR, status); /* clear pending */
2053
2054 info->irq_occurred = 1;
2055
2056 if (info->params.mode == MGSL_MODE_ASYNC) {
2057 if (status & IRQ_TXIDLE) {
2058 if (info->tx_count)
2059 isr_txeom(info, status);
2060 }
2061 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2062 info->icount.brk++;
2063 /* process break detection if tty control allows */
2064 if (info->tty) {
2065 if (!(status & info->ignore_status_mask)) {
2066 if (info->read_status_mask & MASK_BREAK) {
2067 tty_insert_flip_char(info->tty, 0, TTY_BREAK);
2068 if (info->flags & ASYNC_SAK)
2069 do_SAK(info->tty);
2070 }
2071 }
2072 }
2073 }
2074 } else {
2075 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2076 isr_txeom(info, status);
2077
2078 if (status & IRQ_RXIDLE) {
2079 if (status & RXIDLE)
2080 info->icount.rxidle++;
2081 else
2082 info->icount.exithunt++;
2083 wake_up_interruptible(&info->event_wait_q);
2084 }
2085
2086 if (status & IRQ_RXOVER)
2087 rx_start(info);
2088 }
2089
2090 if (status & IRQ_DSR)
2091 dsr_change(info);
2092 if (status & IRQ_CTS)
2093 cts_change(info);
2094 if (status & IRQ_DCD)
2095 dcd_change(info);
2096 if (status & IRQ_RI)
2097 ri_change(info);
2098 }
2099
2100 static void isr_rdma(struct slgt_info *info)
2101 {
2102 unsigned int status = rd_reg32(info, RDCSR);
2103
2104 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2105
2106 /* RDCSR (rx DMA control/status)
2107 *
2108 * 31..07 reserved
2109 * 06 save status byte to DMA buffer
2110 * 05 error
2111 * 04 eol (end of list)
2112 * 03 eob (end of buffer)
2113 * 02 IRQ enable
2114 * 01 reset
2115 * 00 enable
2116 */
2117 wr_reg32(info, RDCSR, status); /* clear pending */
2118
2119 if (status & (BIT5 + BIT4)) {
2120 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2121 info->rx_restart = 1;
2122 }
2123 info->pending_bh |= BH_RECEIVE;
2124 }
2125
2126 static void isr_tdma(struct slgt_info *info)
2127 {
2128 unsigned int status = rd_reg32(info, TDCSR);
2129
2130 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2131
2132 /* TDCSR (tx DMA control/status)
2133 *
2134 * 31..06 reserved
2135 * 05 error
2136 * 04 eol (end of list)
2137 * 03 eob (end of buffer)
2138 * 02 IRQ enable
2139 * 01 reset
2140 * 00 enable
2141 */
2142 wr_reg32(info, TDCSR, status); /* clear pending */
2143
2144 if (status & (BIT5 + BIT4 + BIT3)) {
2145 // another transmit buffer has completed
2146 // run bottom half to get more send data from user
2147 info->pending_bh |= BH_TRANSMIT;
2148 }
2149 }
2150
2151 static void isr_txeom(struct slgt_info *info, unsigned short status)
2152 {
2153 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2154
2155 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2156 tdma_reset(info);
2157 reset_tbufs(info);
2158 if (status & IRQ_TXUNDER) {
2159 unsigned short val = rd_reg16(info, TCR);
2160 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2161 wr_reg16(info, TCR, val); /* clear reset bit */
2162 }
2163
2164 if (info->tx_active) {
2165 if (info->params.mode != MGSL_MODE_ASYNC) {
2166 if (status & IRQ_TXUNDER)
2167 info->icount.txunder++;
2168 else if (status & IRQ_TXIDLE)
2169 info->icount.txok++;
2170 }
2171
2172 info->tx_active = 0;
2173 info->tx_count = 0;
2174
2175 del_timer(&info->tx_timer);
2176
2177 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2178 info->signals &= ~SerialSignal_RTS;
2179 info->drop_rts_on_tx_done = 0;
2180 set_signals(info);
2181 }
2182
2183 #ifdef CONFIG_HDLC
2184 if (info->netcount)
2185 hdlcdev_tx_done(info);
2186 else
2187 #endif
2188 {
2189 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2190 tx_stop(info);
2191 return;
2192 }
2193 info->pending_bh |= BH_TRANSMIT;
2194 }
2195 }
2196 }
2197
2198 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2199 {
2200 struct cond_wait *w, *prev;
2201
2202 /* wake processes waiting for specific transitions */
2203 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2204 if (w->data & changed) {
2205 w->data = state;
2206 wake_up_interruptible(&w->q);
2207 if (prev != NULL)
2208 prev->next = w->next;
2209 else
2210 info->gpio_wait_q = w->next;
2211 } else
2212 prev = w;
2213 }
2214 }
2215
2216 /* interrupt service routine
2217 *
2218 * irq interrupt number
2219 * dev_id device ID supplied during interrupt registration
2220 * regs interrupted processor context
2221 */
2222 static irqreturn_t slgt_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2223 {
2224 struct slgt_info *info;
2225 unsigned int gsr;
2226 unsigned int i;
2227
2228 DBGISR(("slgt_interrupt irq=%d entry\n", irq));
2229
2230 info = dev_id;
2231 if (!info)
2232 return IRQ_NONE;
2233
2234 spin_lock(&info->lock);
2235
2236 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2237 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2238 info->irq_occurred = 1;
2239 for(i=0; i < info->port_count ; i++) {
2240 if (info->port_array[i] == NULL)
2241 continue;
2242 if (gsr & (BIT8 << i))
2243 isr_serial(info->port_array[i]);
2244 if (gsr & (BIT16 << (i*2)))
2245 isr_rdma(info->port_array[i]);
2246 if (gsr & (BIT17 << (i*2)))
2247 isr_tdma(info->port_array[i]);
2248 }
2249 }
2250
2251 if (info->gpio_present) {
2252 unsigned int state;
2253 unsigned int changed;
2254 while ((changed = rd_reg32(info, IOSR)) != 0) {
2255 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2256 /* read latched state of GPIO signals */
2257 state = rd_reg32(info, IOVR);
2258 /* clear pending GPIO interrupt bits */
2259 wr_reg32(info, IOSR, changed);
2260 for (i=0 ; i < info->port_count ; i++) {
2261 if (info->port_array[i] != NULL)
2262 isr_gpio(info->port_array[i], changed, state);
2263 }
2264 }
2265 }
2266
2267 for(i=0; i < info->port_count ; i++) {
2268 struct slgt_info *port = info->port_array[i];
2269
2270 if (port && (port->count || port->netcount) &&
2271 port->pending_bh && !port->bh_running &&
2272 !port->bh_requested) {
2273 DBGISR(("%s bh queued\n", port->device_name));
2274 schedule_work(&port->task);
2275 port->bh_requested = 1;
2276 }
2277 }
2278
2279 spin_unlock(&info->lock);
2280
2281 DBGISR(("slgt_interrupt irq=%d exit\n", irq));
2282 return IRQ_HANDLED;
2283 }
2284
2285 static int startup(struct slgt_info *info)
2286 {
2287 DBGINFO(("%s startup\n", info->device_name));
2288
2289 if (info->flags & ASYNC_INITIALIZED)
2290 return 0;
2291
2292 if (!info->tx_buf) {
2293 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2294 if (!info->tx_buf) {
2295 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2296 return -ENOMEM;
2297 }
2298 }
2299
2300 info->pending_bh = 0;
2301
2302 memset(&info->icount, 0, sizeof(info->icount));
2303
2304 /* program hardware for current parameters */
2305 change_params(info);
2306
2307 if (info->tty)
2308 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2309
2310 info->flags |= ASYNC_INITIALIZED;
2311
2312 return 0;
2313 }
2314
2315 /*
2316 * called by close() and hangup() to shutdown hardware
2317 */
2318 static void shutdown(struct slgt_info *info)
2319 {
2320 unsigned long flags;
2321
2322 if (!(info->flags & ASYNC_INITIALIZED))
2323 return;
2324
2325 DBGINFO(("%s shutdown\n", info->device_name));
2326
2327 /* clear status wait queue because status changes */
2328 /* can't happen after shutting down the hardware */
2329 wake_up_interruptible(&info->status_event_wait_q);
2330 wake_up_interruptible(&info->event_wait_q);
2331
2332 del_timer_sync(&info->tx_timer);
2333 del_timer_sync(&info->rx_timer);
2334
2335 kfree(info->tx_buf);
2336 info->tx_buf = NULL;
2337
2338 spin_lock_irqsave(&info->lock,flags);
2339
2340 tx_stop(info);
2341 rx_stop(info);
2342
2343 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2344
2345 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2346 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2347 set_signals(info);
2348 }
2349
2350 flush_cond_wait(&info->gpio_wait_q);
2351
2352 spin_unlock_irqrestore(&info->lock,flags);
2353
2354 if (info->tty)
2355 set_bit(TTY_IO_ERROR, &info->tty->flags);
2356
2357 info->flags &= ~ASYNC_INITIALIZED;
2358 }
2359
2360 static void program_hw(struct slgt_info *info)
2361 {
2362 unsigned long flags;
2363
2364 spin_lock_irqsave(&info->lock,flags);
2365
2366 rx_stop(info);
2367 tx_stop(info);
2368
2369 if (info->params.mode != MGSL_MODE_ASYNC ||
2370 info->netcount)
2371 sync_mode(info);
2372 else
2373 async_mode(info);
2374
2375 set_signals(info);
2376
2377 info->dcd_chkcount = 0;
2378 info->cts_chkcount = 0;
2379 info->ri_chkcount = 0;
2380 info->dsr_chkcount = 0;
2381
2382 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2383 get_signals(info);
2384
2385 if (info->netcount ||
2386 (info->tty && info->tty->termios->c_cflag & CREAD))
2387 rx_start(info);
2388
2389 spin_unlock_irqrestore(&info->lock,flags);
2390 }
2391
2392 /*
2393 * reconfigure adapter based on new parameters
2394 */
2395 static void change_params(struct slgt_info *info)
2396 {
2397 unsigned cflag;
2398 int bits_per_char;
2399
2400 if (!info->tty || !info->tty->termios)
2401 return;
2402 DBGINFO(("%s change_params\n", info->device_name));
2403
2404 cflag = info->tty->termios->c_cflag;
2405
2406 /* if B0 rate (hangup) specified then negate DTR and RTS */
2407 /* otherwise assert DTR and RTS */
2408 if (cflag & CBAUD)
2409 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2410 else
2411 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2412
2413 /* byte size and parity */
2414
2415 switch (cflag & CSIZE) {
2416 case CS5: info->params.data_bits = 5; break;
2417 case CS6: info->params.data_bits = 6; break;
2418 case CS7: info->params.data_bits = 7; break;
2419 case CS8: info->params.data_bits = 8; break;
2420 default: info->params.data_bits = 7; break;
2421 }
2422
2423 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2424
2425 if (cflag & PARENB)
2426 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2427 else
2428 info->params.parity = ASYNC_PARITY_NONE;
2429
2430 /* calculate number of jiffies to transmit a full
2431 * FIFO (32 bytes) at specified data rate
2432 */
2433 bits_per_char = info->params.data_bits +
2434 info->params.stop_bits + 1;
2435
2436 info->params.data_rate = tty_get_baud_rate(info->tty);
2437
2438 if (info->params.data_rate) {
2439 info->timeout = (32*HZ*bits_per_char) /
2440 info->params.data_rate;
2441 }
2442 info->timeout += HZ/50; /* Add .02 seconds of slop */
2443
2444 if (cflag & CRTSCTS)
2445 info->flags |= ASYNC_CTS_FLOW;
2446 else
2447 info->flags &= ~ASYNC_CTS_FLOW;
2448
2449 if (cflag & CLOCAL)
2450 info->flags &= ~ASYNC_CHECK_CD;
2451 else
2452 info->flags |= ASYNC_CHECK_CD;
2453
2454 /* process tty input control flags */
2455
2456 info->read_status_mask = IRQ_RXOVER;
2457 if (I_INPCK(info->tty))
2458 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2459 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2460 info->read_status_mask |= MASK_BREAK;
2461 if (I_IGNPAR(info->tty))
2462 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2463 if (I_IGNBRK(info->tty)) {
2464 info->ignore_status_mask |= MASK_BREAK;
2465 /* If ignoring parity and break indicators, ignore
2466 * overruns too. (For real raw support).
2467 */
2468 if (I_IGNPAR(info->tty))
2469 info->ignore_status_mask |= MASK_OVERRUN;
2470 }
2471
2472 program_hw(info);
2473 }
2474
2475 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2476 {
2477 DBGINFO(("%s get_stats\n", info->device_name));
2478 if (!user_icount) {
2479 memset(&info->icount, 0, sizeof(info->icount));
2480 } else {
2481 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2482 return -EFAULT;
2483 }
2484 return 0;
2485 }
2486
2487 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2488 {
2489 DBGINFO(("%s get_params\n", info->device_name));
2490 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2491 return -EFAULT;
2492 return 0;
2493 }
2494
2495 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2496 {
2497 unsigned long flags;
2498 MGSL_PARAMS tmp_params;
2499
2500 DBGINFO(("%s set_params\n", info->device_name));
2501 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2502 return -EFAULT;
2503
2504 spin_lock_irqsave(&info->lock, flags);
2505 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2506 spin_unlock_irqrestore(&info->lock, flags);
2507
2508 change_params(info);
2509
2510 return 0;
2511 }
2512
2513 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2514 {
2515 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2516 if (put_user(info->idle_mode, idle_mode))
2517 return -EFAULT;
2518 return 0;
2519 }
2520
2521 static int set_txidle(struct slgt_info *info, int idle_mode)
2522 {
2523 unsigned long flags;
2524 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2525 spin_lock_irqsave(&info->lock,flags);
2526 info->idle_mode = idle_mode;
2527 if (info->params.mode != MGSL_MODE_ASYNC)
2528 tx_set_idle(info);
2529 spin_unlock_irqrestore(&info->lock,flags);
2530 return 0;
2531 }
2532
2533 static int tx_enable(struct slgt_info *info, int enable)
2534 {
2535 unsigned long flags;
2536 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2537 spin_lock_irqsave(&info->lock,flags);
2538 if (enable) {
2539 if (!info->tx_enabled)
2540 tx_start(info);
2541 } else {
2542 if (info->tx_enabled)
2543 tx_stop(info);
2544 }
2545 spin_unlock_irqrestore(&info->lock,flags);
2546 return 0;
2547 }
2548
2549 /*
2550 * abort transmit HDLC frame
2551 */
2552 static int tx_abort(struct slgt_info *info)
2553 {
2554 unsigned long flags;
2555 DBGINFO(("%s tx_abort\n", info->device_name));
2556 spin_lock_irqsave(&info->lock,flags);
2557 tdma_reset(info);
2558 spin_unlock_irqrestore(&info->lock,flags);
2559 return 0;
2560 }
2561
2562 static int rx_enable(struct slgt_info *info, int enable)
2563 {
2564 unsigned long flags;
2565 DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2566 spin_lock_irqsave(&info->lock,flags);
2567 if (enable) {
2568 if (!info->rx_enabled)
2569 rx_start(info);
2570 else if (enable == 2) {
2571 /* force hunt mode (write 1 to RCR[3]) */
2572 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2573 }
2574 } else {
2575 if (info->rx_enabled)
2576 rx_stop(info);
2577 }
2578 spin_unlock_irqrestore(&info->lock,flags);
2579 return 0;
2580 }
2581
2582 /*
2583 * wait for specified event to occur
2584 */
2585 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2586 {
2587 unsigned long flags;
2588 int s;
2589 int rc=0;
2590 struct mgsl_icount cprev, cnow;
2591 int events;
2592 int mask;
2593 struct _input_signal_events oldsigs, newsigs;
2594 DECLARE_WAITQUEUE(wait, current);
2595
2596 if (get_user(mask, mask_ptr))
2597 return -EFAULT;
2598
2599 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2600
2601 spin_lock_irqsave(&info->lock,flags);
2602
2603 /* return immediately if state matches requested events */
2604 get_signals(info);
2605 s = info->signals;
2606
2607 events = mask &
2608 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2609 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2610 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2611 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2612 if (events) {
2613 spin_unlock_irqrestore(&info->lock,flags);
2614 goto exit;
2615 }
2616
2617 /* save current irq counts */
2618 cprev = info->icount;
2619 oldsigs = info->input_signal_events;
2620
2621 /* enable hunt and idle irqs if needed */
2622 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2623 unsigned short val = rd_reg16(info, SCR);
2624 if (!(val & IRQ_RXIDLE))
2625 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2626 }
2627
2628 set_current_state(TASK_INTERRUPTIBLE);
2629 add_wait_queue(&info->event_wait_q, &wait);
2630
2631 spin_unlock_irqrestore(&info->lock,flags);
2632
2633 for(;;) {
2634 schedule();
2635 if (signal_pending(current)) {
2636 rc = -ERESTARTSYS;
2637 break;
2638 }
2639
2640 /* get current irq counts */
2641 spin_lock_irqsave(&info->lock,flags);
2642 cnow = info->icount;
2643 newsigs = info->input_signal_events;
2644 set_current_state(TASK_INTERRUPTIBLE);
2645 spin_unlock_irqrestore(&info->lock,flags);
2646
2647 /* if no change, wait aborted for some reason */
2648 if (newsigs.dsr_up == oldsigs.dsr_up &&
2649 newsigs.dsr_down == oldsigs.dsr_down &&
2650 newsigs.dcd_up == oldsigs.dcd_up &&
2651 newsigs.dcd_down == oldsigs.dcd_down &&
2652 newsigs.cts_up == oldsigs.cts_up &&
2653 newsigs.cts_down == oldsigs.cts_down &&
2654 newsigs.ri_up == oldsigs.ri_up &&
2655 newsigs.ri_down == oldsigs.ri_down &&
2656 cnow.exithunt == cprev.exithunt &&
2657 cnow.rxidle == cprev.rxidle) {
2658 rc = -EIO;
2659 break;
2660 }
2661
2662 events = mask &
2663 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2664 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2665 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2666 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2667 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2668 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2669 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2670 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2671 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2672 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2673 if (events)
2674 break;
2675
2676 cprev = cnow;
2677 oldsigs = newsigs;
2678 }
2679
2680 remove_wait_queue(&info->event_wait_q, &wait);
2681 set_current_state(TASK_RUNNING);
2682
2683
2684 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2685 spin_lock_irqsave(&info->lock,flags);
2686 if (!waitqueue_active(&info->event_wait_q)) {
2687 /* disable enable exit hunt mode/idle rcvd IRQs */
2688 wr_reg16(info, SCR,
2689 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2690 }
2691 spin_unlock_irqrestore(&info->lock,flags);
2692 }
2693 exit:
2694 if (rc == 0)
2695 rc = put_user(events, mask_ptr);
2696 return rc;
2697 }
2698
2699 static int get_interface(struct slgt_info *info, int __user *if_mode)
2700 {
2701 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2702 if (put_user(info->if_mode, if_mode))
2703 return -EFAULT;
2704 return 0;
2705 }
2706
2707 static int set_interface(struct slgt_info *info, int if_mode)
2708 {
2709 unsigned long flags;
2710 unsigned short val;
2711
2712 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2713 spin_lock_irqsave(&info->lock,flags);
2714 info->if_mode = if_mode;
2715
2716 msc_set_vcr(info);
2717
2718 /* TCR (tx control) 07 1=RTS driver control */
2719 val = rd_reg16(info, TCR);
2720 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2721 val |= BIT7;
2722 else
2723 val &= ~BIT7;
2724 wr_reg16(info, TCR, val);
2725
2726 spin_unlock_irqrestore(&info->lock,flags);
2727 return 0;
2728 }
2729
2730 /*
2731 * set general purpose IO pin state and direction
2732 *
2733 * user_gpio fields:
2734 * state each bit indicates a pin state
2735 * smask set bit indicates pin state to set
2736 * dir each bit indicates a pin direction (0=input, 1=output)
2737 * dmask set bit indicates pin direction to set
2738 */
2739 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2740 {
2741 unsigned long flags;
2742 struct gpio_desc gpio;
2743 __u32 data;
2744
2745 if (!info->gpio_present)
2746 return -EINVAL;
2747 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2748 return -EFAULT;
2749 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2750 info->device_name, gpio.state, gpio.smask,
2751 gpio.dir, gpio.dmask));
2752
2753 spin_lock_irqsave(&info->lock,flags);
2754 if (gpio.dmask) {
2755 data = rd_reg32(info, IODR);
2756 data |= gpio.dmask & gpio.dir;
2757 data &= ~(gpio.dmask & ~gpio.dir);
2758 wr_reg32(info, IODR, data);
2759 }
2760 if (gpio.smask) {
2761 data = rd_reg32(info, IOVR);
2762 data |= gpio.smask & gpio.state;
2763 data &= ~(gpio.smask & ~gpio.state);
2764 wr_reg32(info, IOVR, data);
2765 }
2766 spin_unlock_irqrestore(&info->lock,flags);
2767
2768 return 0;
2769 }
2770
2771 /*
2772 * get general purpose IO pin state and direction
2773 */
2774 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2775 {
2776 struct gpio_desc gpio;
2777 if (!info->gpio_present)
2778 return -EINVAL;
2779 gpio.state = rd_reg32(info, IOVR);
2780 gpio.smask = 0xffffffff;
2781 gpio.dir = rd_reg32(info, IODR);
2782 gpio.dmask = 0xffffffff;
2783 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2784 return -EFAULT;
2785 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2786 info->device_name, gpio.state, gpio.dir));
2787 return 0;
2788 }
2789
2790 /*
2791 * conditional wait facility
2792 */
2793 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2794 {
2795 init_waitqueue_head(&w->q);
2796 init_waitqueue_entry(&w->wait, current);
2797 w->data = data;
2798 }
2799
2800 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2801 {
2802 set_current_state(TASK_INTERRUPTIBLE);
2803 add_wait_queue(&w->q, &w->wait);
2804 w->next = *head;
2805 *head = w;
2806 }
2807
2808 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2809 {
2810 struct cond_wait *w, *prev;
2811 remove_wait_queue(&cw->q, &cw->wait);
2812 set_current_state(TASK_RUNNING);
2813 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2814 if (w == cw) {
2815 if (prev != NULL)
2816 prev->next = w->next;
2817 else
2818 *head = w->next;
2819 break;
2820 }
2821 }
2822 }
2823
2824 static void flush_cond_wait(struct cond_wait **head)
2825 {
2826 while (*head != NULL) {
2827 wake_up_interruptible(&(*head)->q);
2828 *head = (*head)->next;
2829 }
2830 }
2831
2832 /*
2833 * wait for general purpose I/O pin(s) to enter specified state
2834 *
2835 * user_gpio fields:
2836 * state - bit indicates target pin state
2837 * smask - set bit indicates watched pin
2838 *
2839 * The wait ends when at least one watched pin enters the specified
2840 * state. When 0 (no error) is returned, user_gpio->state is set to the
2841 * state of all GPIO pins when the wait ends.
2842 *
2843 * Note: Each pin may be a dedicated input, dedicated output, or
2844 * configurable input/output. The number and configuration of pins
2845 * varies with the specific adapter model. Only input pins (dedicated
2846 * or configured) can be monitored with this function.
2847 */
2848 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2849 {
2850 unsigned long flags;
2851 int rc = 0;
2852 struct gpio_desc gpio;
2853 struct cond_wait wait;
2854 u32 state;
2855
2856 if (!info->gpio_present)
2857 return -EINVAL;
2858 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2859 return -EFAULT;
2860 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2861 info->device_name, gpio.state, gpio.smask));
2862 /* ignore output pins identified by set IODR bit */
2863 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2864 return -EINVAL;
2865 init_cond_wait(&wait, gpio.smask);
2866
2867 spin_lock_irqsave(&info->lock, flags);
2868 /* enable interrupts for watched pins */
2869 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2870 /* get current pin states */
2871 state = rd_reg32(info, IOVR);
2872
2873 if (gpio.smask & ~(state ^ gpio.state)) {
2874 /* already in target state */
2875 gpio.state = state;
2876 } else {
2877 /* wait for target state */
2878 add_cond_wait(&info->gpio_wait_q, &wait);
2879 spin_unlock_irqrestore(&info->lock, flags);
2880 schedule();
2881 if (signal_pending(current))
2882 rc = -ERESTARTSYS;
2883 else
2884 gpio.state = wait.data;
2885 spin_lock_irqsave(&info->lock, flags);
2886 remove_cond_wait(&info->gpio_wait_q, &wait);
2887 }
2888
2889 /* disable all GPIO interrupts if no waiting processes */
2890 if (info->gpio_wait_q == NULL)
2891 wr_reg32(info, IOER, 0);
2892 spin_unlock_irqrestore(&info->lock,flags);
2893
2894 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2895 rc = -EFAULT;
2896 return rc;
2897 }
2898
2899 static int modem_input_wait(struct slgt_info *info,int arg)
2900 {
2901 unsigned long flags;
2902 int rc;
2903 struct mgsl_icount cprev, cnow;
2904 DECLARE_WAITQUEUE(wait, current);
2905
2906 /* save current irq counts */
2907 spin_lock_irqsave(&info->lock,flags);
2908 cprev = info->icount;
2909 add_wait_queue(&info->status_event_wait_q, &wait);
2910 set_current_state(TASK_INTERRUPTIBLE);
2911 spin_unlock_irqrestore(&info->lock,flags);
2912
2913 for(;;) {
2914 schedule();
2915 if (signal_pending(current)) {
2916 rc = -ERESTARTSYS;
2917 break;
2918 }
2919
2920 /* get new irq counts */
2921 spin_lock_irqsave(&info->lock,flags);
2922 cnow = info->icount;
2923 set_current_state(TASK_INTERRUPTIBLE);
2924 spin_unlock_irqrestore(&info->lock,flags);
2925
2926 /* if no change, wait aborted for some reason */
2927 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2928 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2929 rc = -EIO;
2930 break;
2931 }
2932
2933 /* check for change in caller specified modem input */
2934 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2935 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2936 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2937 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2938 rc = 0;
2939 break;
2940 }
2941
2942 cprev = cnow;
2943 }
2944 remove_wait_queue(&info->status_event_wait_q, &wait);
2945 set_current_state(TASK_RUNNING);
2946 return rc;
2947 }
2948
2949 /*
2950 * return state of serial control and status signals
2951 */
2952 static int tiocmget(struct tty_struct *tty, struct file *file)
2953 {
2954 struct slgt_info *info = tty->driver_data;
2955 unsigned int result;
2956 unsigned long flags;
2957
2958 spin_lock_irqsave(&info->lock,flags);
2959 get_signals(info);
2960 spin_unlock_irqrestore(&info->lock,flags);
2961
2962 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2963 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2964 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2965 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2966 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2967 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2968
2969 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
2970 return result;
2971 }
2972
2973 /*
2974 * set modem control signals (DTR/RTS)
2975 *
2976 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
2977 * TIOCMSET = set/clear signal values
2978 * value bit mask for command
2979 */
2980 static int tiocmset(struct tty_struct *tty, struct file *file,
2981 unsigned int set, unsigned int clear)
2982 {
2983 struct slgt_info *info = tty->driver_data;
2984 unsigned long flags;
2985
2986 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
2987
2988 if (set & TIOCM_RTS)
2989 info->signals |= SerialSignal_RTS;
2990 if (set & TIOCM_DTR)
2991 info->signals |= SerialSignal_DTR;
2992 if (clear & TIOCM_RTS)
2993 info->signals &= ~SerialSignal_RTS;
2994 if (clear & TIOCM_DTR)
2995 info->signals &= ~SerialSignal_DTR;
2996
2997 spin_lock_irqsave(&info->lock,flags);
2998 set_signals(info);
2999 spin_unlock_irqrestore(&info->lock,flags);
3000 return 0;
3001 }
3002
3003 /*
3004 * block current process until the device is ready to open
3005 */
3006 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3007 struct slgt_info *info)
3008 {
3009 DECLARE_WAITQUEUE(wait, current);
3010 int retval;
3011 int do_clocal = 0, extra_count = 0;
3012 unsigned long flags;
3013
3014 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3015
3016 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3017 /* nonblock mode is set or port is not enabled */
3018 info->flags |= ASYNC_NORMAL_ACTIVE;
3019 return 0;
3020 }
3021
3022 if (tty->termios->c_cflag & CLOCAL)
3023 do_clocal = 1;
3024
3025 /* Wait for carrier detect and the line to become
3026 * free (i.e., not in use by the callout). While we are in
3027 * this loop, info->count is dropped by one, so that
3028 * close() knows when to free things. We restore it upon
3029 * exit, either normal or abnormal.
3030 */
3031
3032 retval = 0;
3033 add_wait_queue(&info->open_wait, &wait);
3034
3035 spin_lock_irqsave(&info->lock, flags);
3036 if (!tty_hung_up_p(filp)) {
3037 extra_count = 1;
3038 info->count--;
3039 }
3040 spin_unlock_irqrestore(&info->lock, flags);
3041 info->blocked_open++;
3042
3043 while (1) {
3044 if ((tty->termios->c_cflag & CBAUD)) {
3045 spin_lock_irqsave(&info->lock,flags);
3046 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3047 set_signals(info);
3048 spin_unlock_irqrestore(&info->lock,flags);
3049 }
3050
3051 set_current_state(TASK_INTERRUPTIBLE);
3052
3053 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3054 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3055 -EAGAIN : -ERESTARTSYS;
3056 break;
3057 }
3058
3059 spin_lock_irqsave(&info->lock,flags);
3060 get_signals(info);
3061 spin_unlock_irqrestore(&info->lock,flags);
3062
3063 if (!(info->flags & ASYNC_CLOSING) &&
3064 (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3065 break;
3066 }
3067
3068 if (signal_pending(current)) {
3069 retval = -ERESTARTSYS;
3070 break;
3071 }
3072
3073 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3074 schedule();
3075 }
3076
3077 set_current_state(TASK_RUNNING);
3078 remove_wait_queue(&info->open_wait, &wait);
3079
3080 if (extra_count)
3081 info->count++;
3082 info->blocked_open--;
3083
3084 if (!retval)
3085 info->flags |= ASYNC_NORMAL_ACTIVE;
3086
3087 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3088 return retval;
3089 }
3090
3091 static int alloc_tmp_rbuf(struct slgt_info *info)
3092 {
3093 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3094 if (info->tmp_rbuf == NULL)
3095 return -ENOMEM;
3096 return 0;
3097 }
3098
3099 static void free_tmp_rbuf(struct slgt_info *info)
3100 {
3101 kfree(info->tmp_rbuf);
3102 info->tmp_rbuf = NULL;
3103 }
3104
3105 /*
3106 * allocate DMA descriptor lists.
3107 */
3108 static int alloc_desc(struct slgt_info *info)
3109 {
3110 unsigned int i;
3111 unsigned int pbufs;
3112
3113 /* allocate memory to hold descriptor lists */
3114 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3115 if (info->bufs == NULL)
3116 return -ENOMEM;
3117
3118 memset(info->bufs, 0, DESC_LIST_SIZE);
3119
3120 info->rbufs = (struct slgt_desc*)info->bufs;
3121 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3122
3123 pbufs = (unsigned int)info->bufs_dma_addr;
3124
3125 /*
3126 * Build circular lists of descriptors
3127 */
3128
3129 for (i=0; i < info->rbuf_count; i++) {
3130 /* physical address of this descriptor */
3131 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3132
3133 /* physical address of next descriptor */
3134 if (i == info->rbuf_count - 1)
3135 info->rbufs[i].next = cpu_to_le32(pbufs);
3136 else
3137 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3138 set_desc_count(info->rbufs[i], DMABUFSIZE);
3139 }
3140
3141 for (i=0; i < info->tbuf_count; i++) {
3142 /* physical address of this descriptor */
3143 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3144
3145 /* physical address of next descriptor */
3146 if (i == info->tbuf_count - 1)
3147 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3148 else
3149 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3150 }
3151
3152 return 0;
3153 }
3154
3155 static void free_desc(struct slgt_info *info)
3156 {
3157 if (info->bufs != NULL) {
3158 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3159 info->bufs = NULL;
3160 info->rbufs = NULL;
3161 info->tbufs = NULL;
3162 }
3163 }
3164
3165 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3166 {
3167 int i;
3168 for (i=0; i < count; i++) {
3169 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3170 return -ENOMEM;
3171 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3172 }
3173 return 0;
3174 }
3175
3176 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3177 {
3178 int i;
3179 for (i=0; i < count; i++) {
3180 if (bufs[i].buf == NULL)
3181 continue;
3182 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3183 bufs[i].buf = NULL;
3184 }
3185 }
3186
3187 static int alloc_dma_bufs(struct slgt_info *info)
3188 {
3189 info->rbuf_count = 32;
3190 info->tbuf_count = 32;
3191
3192 if (alloc_desc(info) < 0 ||
3193 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3194 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3195 alloc_tmp_rbuf(info) < 0) {
3196 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3197 return -ENOMEM;
3198 }
3199 reset_rbufs(info);
3200 return 0;
3201 }
3202
3203 static void free_dma_bufs(struct slgt_info *info)
3204 {
3205 if (info->bufs) {
3206 free_bufs(info, info->rbufs, info->rbuf_count);
3207 free_bufs(info, info->tbufs, info->tbuf_count);
3208 free_desc(info);
3209 }
3210 free_tmp_rbuf(info);
3211 }
3212
3213 static int claim_resources(struct slgt_info *info)
3214 {
3215 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3216 DBGERR(("%s reg addr conflict, addr=%08X\n",
3217 info->device_name, info->phys_reg_addr));
3218 info->init_error = DiagStatus_AddressConflict;
3219 goto errout;
3220 }
3221 else
3222 info->reg_addr_requested = 1;
3223
3224 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3225 if (!info->reg_addr) {
3226 DBGERR(("%s cant map device registers, addr=%08X\n",
3227 info->device_name, info->phys_reg_addr));
3228 info->init_error = DiagStatus_CantAssignPciResources;
3229 goto errout;
3230 }
3231 return 0;
3232
3233 errout:
3234 release_resources(info);
3235 return -ENODEV;
3236 }
3237
3238 static void release_resources(struct slgt_info *info)
3239 {
3240 if (info->irq_requested) {
3241 free_irq(info->irq_level, info);
3242 info->irq_requested = 0;
3243 }
3244
3245 if (info->reg_addr_requested) {
3246 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3247 info->reg_addr_requested = 0;
3248 }
3249
3250 if (info->reg_addr) {
3251 iounmap(info->reg_addr);
3252 info->reg_addr = NULL;
3253 }
3254 }
3255
3256 /* Add the specified device instance data structure to the
3257 * global linked list of devices and increment the device count.
3258 */
3259 static void add_device(struct slgt_info *info)
3260 {
3261 char *devstr;
3262
3263 info->next_device = NULL;
3264 info->line = slgt_device_count;
3265 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3266
3267 if (info->line < MAX_DEVICES) {
3268 if (maxframe[info->line])
3269 info->max_frame_size = maxframe[info->line];
3270 info->dosyncppp = dosyncppp[info->line];
3271 }
3272
3273 slgt_device_count++;
3274
3275 if (!slgt_device_list)
3276 slgt_device_list = info;
3277 else {
3278 struct slgt_info *current_dev = slgt_device_list;
3279 while(current_dev->next_device)
3280 current_dev = current_dev->next_device;
3281 current_dev->next_device = info;
3282 }
3283
3284 if (info->max_frame_size < 4096)
3285 info->max_frame_size = 4096;
3286 else if (info->max_frame_size > 65535)
3287 info->max_frame_size = 65535;
3288
3289 switch(info->pdev->device) {
3290 case SYNCLINK_GT_DEVICE_ID:
3291 devstr = "GT";
3292 break;
3293 case SYNCLINK_GT2_DEVICE_ID:
3294 devstr = "GT2";
3295 break;
3296 case SYNCLINK_GT4_DEVICE_ID:
3297 devstr = "GT4";
3298 break;
3299 case SYNCLINK_AC_DEVICE_ID:
3300 devstr = "AC";
3301 info->params.mode = MGSL_MODE_ASYNC;
3302 break;
3303 default:
3304 devstr = "(unknown model)";
3305 }
3306 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3307 devstr, info->device_name, info->phys_reg_addr,
3308 info->irq_level, info->max_frame_size);
3309
3310 #ifdef CONFIG_HDLC
3311 hdlcdev_init(info);
3312 #endif
3313 }
3314
3315 /*
3316 * allocate device instance structure, return NULL on failure
3317 */
3318 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3319 {
3320 struct slgt_info *info;
3321
3322 info = kmalloc(sizeof(struct slgt_info), GFP_KERNEL);
3323
3324 if (!info) {
3325 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3326 driver_name, adapter_num, port_num));
3327 } else {
3328 memset(info, 0, sizeof(struct slgt_info));
3329 info->magic = MGSL_MAGIC;
3330 INIT_WORK(&info->task, bh_handler, info);
3331 info->max_frame_size = 4096;
3332 info->raw_rx_size = DMABUFSIZE;
3333 info->close_delay = 5*HZ/10;
3334 info->closing_wait = 30*HZ;
3335 init_waitqueue_head(&info->open_wait);
3336 init_waitqueue_head(&info->close_wait);
3337 init_waitqueue_head(&info->status_event_wait_q);
3338 init_waitqueue_head(&info->event_wait_q);
3339 spin_lock_init(&info->netlock);
3340 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3341 info->idle_mode = HDLC_TXIDLE_FLAGS;
3342 info->adapter_num = adapter_num;
3343 info->port_num = port_num;
3344
3345 init_timer(&info->tx_timer);
3346 info->tx_timer.data = (unsigned long)info;
3347 info->tx_timer.function = tx_timeout;
3348
3349 init_timer(&info->rx_timer);
3350 info->rx_timer.data = (unsigned long)info;
3351 info->rx_timer.function = rx_timeout;
3352
3353 /* Copy configuration info to device instance data */
3354 info->pdev = pdev;
3355 info->irq_level = pdev->irq;
3356 info->phys_reg_addr = pci_resource_start(pdev,0);
3357
3358 info->bus_type = MGSL_BUS_TYPE_PCI;
3359 info->irq_flags = IRQF_SHARED;
3360
3361 info->init_error = -1; /* assume error, set to 0 on successful init */
3362 }
3363
3364 return info;
3365 }
3366
3367 static void device_init(int adapter_num, struct pci_dev *pdev)
3368 {
3369 struct slgt_info *port_array[SLGT_MAX_PORTS];
3370 int i;
3371 int port_count = 1;
3372
3373 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3374 port_count = 2;
3375 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3376 port_count = 4;
3377
3378 /* allocate device instances for all ports */
3379 for (i=0; i < port_count; ++i) {
3380 port_array[i] = alloc_dev(adapter_num, i, pdev);
3381 if (port_array[i] == NULL) {
3382 for (--i; i >= 0; --i)
3383 kfree(port_array[i]);
3384 return;
3385 }
3386 }
3387
3388 /* give copy of port_array to all ports and add to device list */
3389 for (i=0; i < port_count; ++i) {
3390 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3391 add_device(port_array[i]);
3392 port_array[i]->port_count = port_count;
3393 spin_lock_init(&port_array[i]->lock);
3394 }
3395
3396 /* Allocate and claim adapter resources */
3397 if (!claim_resources(port_array[0])) {
3398
3399 alloc_dma_bufs(port_array[0]);
3400
3401 /* copy resource information from first port to others */
3402 for (i = 1; i < port_count; ++i) {
3403 port_array[i]->lock = port_array[0]->lock;
3404 port_array[i]->irq_level = port_array[0]->irq_level;
3405 port_array[i]->reg_addr = port_array[0]->reg_addr;
3406 alloc_dma_bufs(port_array[i]);
3407 }
3408
3409 if (request_irq(port_array[0]->irq_level,
3410 slgt_interrupt,
3411 port_array[0]->irq_flags,
3412 port_array[0]->device_name,
3413 port_array[0]) < 0) {
3414 DBGERR(("%s request_irq failed IRQ=%d\n",
3415 port_array[0]->device_name,
3416 port_array[0]->irq_level));
3417 } else {
3418 port_array[0]->irq_requested = 1;
3419 adapter_test(port_array[0]);
3420 for (i=1 ; i < port_count ; i++) {
3421 port_array[i]->init_error = port_array[0]->init_error;
3422 port_array[i]->gpio_present = port_array[0]->gpio_present;
3423 }
3424 }
3425 }
3426 }
3427
3428 static int __devinit init_one(struct pci_dev *dev,
3429 const struct pci_device_id *ent)
3430 {
3431 if (pci_enable_device(dev)) {
3432 printk("error enabling pci device %p\n", dev);
3433 return -EIO;
3434 }
3435 pci_set_master(dev);
3436 device_init(slgt_device_count, dev);
3437 return 0;
3438 }
3439
3440 static void __devexit remove_one(struct pci_dev *dev)
3441 {
3442 }
3443
3444 static struct tty_operations ops = {
3445 .open = open,
3446 .close = close,
3447 .write = write,
3448 .put_char = put_char,
3449 .flush_chars = flush_chars,
3450 .write_room = write_room,
3451 .chars_in_buffer = chars_in_buffer,
3452 .flush_buffer = flush_buffer,
3453 .ioctl = ioctl,
3454 .throttle = throttle,
3455 .unthrottle = unthrottle,
3456 .send_xchar = send_xchar,
3457 .break_ctl = set_break,
3458 .wait_until_sent = wait_until_sent,
3459 .read_proc = read_proc,
3460 .set_termios = set_termios,
3461 .stop = tx_hold,
3462 .start = tx_release,
3463 .hangup = hangup,
3464 .tiocmget = tiocmget,
3465 .tiocmset = tiocmset,
3466 };
3467
3468 static void slgt_cleanup(void)
3469 {
3470 int rc;
3471 struct slgt_info *info;
3472 struct slgt_info *tmp;
3473
3474 printk("unload %s %s\n", driver_name, driver_version);
3475
3476 if (serial_driver) {
3477 if ((rc = tty_unregister_driver(serial_driver)))
3478 DBGERR(("tty_unregister_driver error=%d\n", rc));
3479 put_tty_driver(serial_driver);
3480 }
3481
3482 /* reset devices */
3483 info = slgt_device_list;
3484 while(info) {
3485 reset_port(info);
3486 info = info->next_device;
3487 }
3488
3489 /* release devices */
3490 info = slgt_device_list;
3491 while(info) {
3492 #ifdef CONFIG_HDLC
3493 hdlcdev_exit(info);
3494 #endif
3495 free_dma_bufs(info);
3496 free_tmp_rbuf(info);
3497 if (info->port_num == 0)
3498 release_resources(info);
3499 tmp = info;
3500 info = info->next_device;
3501 kfree(tmp);
3502 }
3503
3504 if (pci_registered)
3505 pci_unregister_driver(&pci_driver);
3506 }
3507
3508 /*
3509 * Driver initialization entry point.
3510 */
3511 static int __init slgt_init(void)
3512 {
3513 int rc;
3514
3515 printk("%s %s\n", driver_name, driver_version);
3516
3517 slgt_device_count = 0;
3518 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3519 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3520 return rc;
3521 }
3522 pci_registered = 1;
3523
3524 if (!slgt_device_list) {
3525 printk("%s no devices found\n",driver_name);
3526 return -ENODEV;
3527 }
3528
3529 serial_driver = alloc_tty_driver(MAX_DEVICES);
3530 if (!serial_driver) {
3531 rc = -ENOMEM;
3532 goto error;
3533 }
3534
3535 /* Initialize the tty_driver structure */
3536
3537 serial_driver->owner = THIS_MODULE;
3538 serial_driver->driver_name = tty_driver_name;
3539 serial_driver->name = tty_dev_prefix;
3540 serial_driver->major = ttymajor;
3541 serial_driver->minor_start = 64;
3542 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3543 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3544 serial_driver->init_termios = tty_std_termios;
3545 serial_driver->init_termios.c_cflag =
3546 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3547 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3548 tty_set_operations(serial_driver, &ops);
3549 if ((rc = tty_register_driver(serial_driver)) < 0) {
3550 DBGERR(("%s can't register serial driver\n", driver_name));
3551 put_tty_driver(serial_driver);
3552 serial_driver = NULL;
3553 goto error;
3554 }
3555
3556 printk("%s %s, tty major#%d\n",
3557 driver_name, driver_version,
3558 serial_driver->major);
3559
3560 return 0;
3561
3562 error:
3563 slgt_cleanup();
3564 return rc;
3565 }
3566
3567 static void __exit slgt_exit(void)
3568 {
3569 slgt_cleanup();
3570 }
3571
3572 module_init(slgt_init);
3573 module_exit(slgt_exit);
3574
3575 /*
3576 * register access routines
3577 */
3578
3579 #define CALC_REGADDR() \
3580 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3581 if (addr >= 0x80) \
3582 reg_addr += (info->port_num) * 32;
3583
3584 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3585 {
3586 CALC_REGADDR();
3587 return readb((void __iomem *)reg_addr);
3588 }
3589
3590 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3591 {
3592 CALC_REGADDR();
3593 writeb(value, (void __iomem *)reg_addr);
3594 }
3595
3596 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3597 {
3598 CALC_REGADDR();
3599 return readw((void __iomem *)reg_addr);
3600 }
3601
3602 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3603 {
3604 CALC_REGADDR();
3605 writew(value, (void __iomem *)reg_addr);
3606 }
3607
3608 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3609 {
3610 CALC_REGADDR();
3611 return readl((void __iomem *)reg_addr);
3612 }
3613
3614 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3615 {
3616 CALC_REGADDR();
3617 writel(value, (void __iomem *)reg_addr);
3618 }
3619
3620 static void rdma_reset(struct slgt_info *info)
3621 {
3622 unsigned int i;
3623
3624 /* set reset bit */
3625 wr_reg32(info, RDCSR, BIT1);
3626
3627 /* wait for enable bit cleared */
3628 for(i=0 ; i < 1000 ; i++)
3629 if (!(rd_reg32(info, RDCSR) & BIT0))
3630 break;
3631 }
3632
3633 static void tdma_reset(struct slgt_info *info)
3634 {
3635 unsigned int i;
3636
3637 /* set reset bit */
3638 wr_reg32(info, TDCSR, BIT1);
3639
3640 /* wait for enable bit cleared */
3641 for(i=0 ; i < 1000 ; i++)
3642 if (!(rd_reg32(info, TDCSR) & BIT0))
3643 break;
3644 }
3645
3646 /*
3647 * enable internal loopback
3648 * TxCLK and RxCLK are generated from BRG
3649 * and TxD is looped back to RxD internally.
3650 */
3651 static void enable_loopback(struct slgt_info *info)
3652 {
3653 /* SCR (serial control) BIT2=looopback enable */
3654 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3655
3656 if (info->params.mode != MGSL_MODE_ASYNC) {
3657 /* CCR (clock control)
3658 * 07..05 tx clock source (010 = BRG)
3659 * 04..02 rx clock source (010 = BRG)
3660 * 01 auxclk enable (0 = disable)
3661 * 00 BRG enable (1 = enable)
3662 *
3663 * 0100 1001
3664 */
3665 wr_reg8(info, CCR, 0x49);
3666
3667 /* set speed if available, otherwise use default */
3668 if (info->params.clock_speed)
3669 set_rate(info, info->params.clock_speed);
3670 else
3671 set_rate(info, 3686400);
3672 }
3673 }
3674
3675 /*
3676 * set baud rate generator to specified rate
3677 */
3678 static void set_rate(struct slgt_info *info, u32 rate)
3679 {
3680 unsigned int div;
3681 static unsigned int osc = 14745600;
3682
3683 /* div = osc/rate - 1
3684 *
3685 * Round div up if osc/rate is not integer to
3686 * force to next slowest rate.
3687 */
3688
3689 if (rate) {
3690 div = osc/rate;
3691 if (!(osc % rate) && div)
3692 div--;
3693 wr_reg16(info, BDR, (unsigned short)div);
3694 }
3695 }
3696
3697 static void rx_stop(struct slgt_info *info)
3698 {
3699 unsigned short val;
3700
3701 /* disable and reset receiver */
3702 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3703 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3704 wr_reg16(info, RCR, val); /* clear reset bit */
3705
3706 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3707
3708 /* clear pending rx interrupts */
3709 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3710
3711 rdma_reset(info);
3712
3713 info->rx_enabled = 0;
3714 info->rx_restart = 0;
3715 }
3716
3717 static void rx_start(struct slgt_info *info)
3718 {
3719 unsigned short val;
3720
3721 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3722
3723 /* clear pending rx overrun IRQ */
3724 wr_reg16(info, SSR, IRQ_RXOVER);
3725
3726 /* reset and disable receiver */
3727 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3728 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3729 wr_reg16(info, RCR, val); /* clear reset bit */
3730
3731 rdma_reset(info);
3732 reset_rbufs(info);
3733
3734 /* set 1st descriptor address */
3735 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3736
3737 if (info->params.mode != MGSL_MODE_ASYNC) {
3738 /* enable rx DMA and DMA interrupt */
3739 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3740 } else {
3741 /* enable saving of rx status, rx DMA and DMA interrupt */
3742 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3743 }
3744
3745 slgt_irq_on(info, IRQ_RXOVER);
3746
3747 /* enable receiver */
3748 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3749
3750 info->rx_restart = 0;
3751 info->rx_enabled = 1;
3752 }
3753
3754 static void tx_start(struct slgt_info *info)
3755 {
3756 if (!info->tx_enabled) {
3757 wr_reg16(info, TCR,
3758 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3759 info->tx_enabled = TRUE;
3760 }
3761
3762 if (info->tx_count) {
3763 info->drop_rts_on_tx_done = 0;
3764
3765 if (info->params.mode != MGSL_MODE_ASYNC) {
3766 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3767 get_signals(info);
3768 if (!(info->signals & SerialSignal_RTS)) {
3769 info->signals |= SerialSignal_RTS;
3770 set_signals(info);
3771 info->drop_rts_on_tx_done = 1;
3772 }
3773 }
3774
3775 slgt_irq_off(info, IRQ_TXDATA);
3776 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3777 /* clear tx idle and underrun status bits */
3778 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3779
3780 if (!(rd_reg32(info, TDCSR) & BIT0)) {
3781 /* tx DMA stopped, restart tx DMA */
3782 tdma_reset(info);
3783 /* set 1st descriptor address */
3784 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3785 switch(info->params.mode) {
3786 case MGSL_MODE_RAW:
3787 case MGSL_MODE_MONOSYNC:
3788 case MGSL_MODE_BISYNC:
3789 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3790 break;
3791 default:
3792 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3793 }
3794 }
3795
3796 if (info->params.mode == MGSL_MODE_HDLC) {
3797 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
3798 add_timer(&info->tx_timer);
3799 }
3800 } else {
3801 tdma_reset(info);
3802 /* set 1st descriptor address */
3803 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3804
3805 slgt_irq_off(info, IRQ_TXDATA);
3806 slgt_irq_on(info, IRQ_TXIDLE);
3807 /* clear tx idle status bit */
3808 wr_reg16(info, SSR, IRQ_TXIDLE);
3809
3810 /* enable tx DMA */
3811 wr_reg32(info, TDCSR, BIT0);
3812 }
3813
3814 info->tx_active = 1;
3815 }
3816 }
3817
3818 static void tx_stop(struct slgt_info *info)
3819 {
3820 unsigned short val;
3821
3822 del_timer(&info->tx_timer);
3823
3824 tdma_reset(info);
3825
3826 /* reset and disable transmitter */
3827 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3828 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3829
3830 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3831
3832 /* clear tx idle and underrun status bit */
3833 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3834
3835 reset_tbufs(info);
3836
3837 info->tx_enabled = 0;
3838 info->tx_active = 0;
3839 }
3840
3841 static void reset_port(struct slgt_info *info)
3842 {
3843 if (!info->reg_addr)
3844 return;
3845
3846 tx_stop(info);
3847 rx_stop(info);
3848
3849 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3850 set_signals(info);
3851
3852 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3853 }
3854
3855 static void reset_adapter(struct slgt_info *info)
3856 {
3857 int i;
3858 for (i=0; i < info->port_count; ++i) {
3859 if (info->port_array[i])
3860 reset_port(info->port_array[i]);
3861 }
3862 }
3863
3864 static void async_mode(struct slgt_info *info)
3865 {
3866 unsigned short val;
3867
3868 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3869 tx_stop(info);
3870 rx_stop(info);
3871
3872 /* TCR (tx control)
3873 *
3874 * 15..13 mode, 010=async
3875 * 12..10 encoding, 000=NRZ
3876 * 09 parity enable
3877 * 08 1=odd parity, 0=even parity
3878 * 07 1=RTS driver control
3879 * 06 1=break enable
3880 * 05..04 character length
3881 * 00=5 bits
3882 * 01=6 bits
3883 * 10=7 bits
3884 * 11=8 bits
3885 * 03 0=1 stop bit, 1=2 stop bits
3886 * 02 reset
3887 * 01 enable
3888 * 00 auto-CTS enable
3889 */
3890 val = 0x4000;
3891
3892 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3893 val |= BIT7;
3894
3895 if (info->params.parity != ASYNC_PARITY_NONE) {
3896 val |= BIT9;
3897 if (info->params.parity == ASYNC_PARITY_ODD)
3898 val |= BIT8;
3899 }
3900
3901 switch (info->params.data_bits)
3902 {
3903 case 6: val |= BIT4; break;
3904 case 7: val |= BIT5; break;
3905 case 8: val |= BIT5 + BIT4; break;
3906 }
3907
3908 if (info->params.stop_bits != 1)
3909 val |= BIT3;
3910
3911 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
3912 val |= BIT0;
3913
3914 wr_reg16(info, TCR, val);
3915
3916 /* RCR (rx control)
3917 *
3918 * 15..13 mode, 010=async
3919 * 12..10 encoding, 000=NRZ
3920 * 09 parity enable
3921 * 08 1=odd parity, 0=even parity
3922 * 07..06 reserved, must be 0
3923 * 05..04 character length
3924 * 00=5 bits
3925 * 01=6 bits
3926 * 10=7 bits
3927 * 11=8 bits
3928 * 03 reserved, must be zero
3929 * 02 reset
3930 * 01 enable
3931 * 00 auto-DCD enable
3932 */
3933 val = 0x4000;
3934
3935 if (info->params.parity != ASYNC_PARITY_NONE) {
3936 val |= BIT9;
3937 if (info->params.parity == ASYNC_PARITY_ODD)
3938 val |= BIT8;
3939 }
3940
3941 switch (info->params.data_bits)
3942 {
3943 case 6: val |= BIT4; break;
3944 case 7: val |= BIT5; break;
3945 case 8: val |= BIT5 + BIT4; break;
3946 }
3947
3948 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
3949 val |= BIT0;
3950
3951 wr_reg16(info, RCR, val);
3952
3953 /* CCR (clock control)
3954 *
3955 * 07..05 011 = tx clock source is BRG/16
3956 * 04..02 010 = rx clock source is BRG
3957 * 01 0 = auxclk disabled
3958 * 00 1 = BRG enabled
3959 *
3960 * 0110 1001
3961 */
3962 wr_reg8(info, CCR, 0x69);
3963
3964 msc_set_vcr(info);
3965
3966 /* SCR (serial control)
3967 *
3968 * 15 1=tx req on FIFO half empty
3969 * 14 1=rx req on FIFO half full
3970 * 13 tx data IRQ enable
3971 * 12 tx idle IRQ enable
3972 * 11 rx break on IRQ enable
3973 * 10 rx data IRQ enable
3974 * 09 rx break off IRQ enable
3975 * 08 overrun IRQ enable
3976 * 07 DSR IRQ enable
3977 * 06 CTS IRQ enable
3978 * 05 DCD IRQ enable
3979 * 04 RI IRQ enable
3980 * 03 reserved, must be zero
3981 * 02 1=txd->rxd internal loopback enable
3982 * 01 reserved, must be zero
3983 * 00 1=master IRQ enable
3984 */
3985 val = BIT15 + BIT14 + BIT0;
3986 wr_reg16(info, SCR, val);
3987
3988 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
3989
3990 set_rate(info, info->params.data_rate * 16);
3991
3992 if (info->params.loopback)
3993 enable_loopback(info);
3994 }
3995
3996 static void sync_mode(struct slgt_info *info)
3997 {
3998 unsigned short val;
3999
4000 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4001 tx_stop(info);
4002 rx_stop(info);
4003
4004 /* TCR (tx control)
4005 *
4006 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4007 * 12..10 encoding
4008 * 09 CRC enable
4009 * 08 CRC32
4010 * 07 1=RTS driver control
4011 * 06 preamble enable
4012 * 05..04 preamble length
4013 * 03 share open/close flag
4014 * 02 reset
4015 * 01 enable
4016 * 00 auto-CTS enable
4017 */
4018 val = 0;
4019
4020 switch(info->params.mode) {
4021 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4022 case MGSL_MODE_BISYNC: val |= BIT15; break;
4023 case MGSL_MODE_RAW: val |= BIT13; break;
4024 }
4025 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4026 val |= BIT7;
4027
4028 switch(info->params.encoding)
4029 {
4030 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4031 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4032 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4033 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4034 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4035 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4036 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4037 }
4038
4039 switch (info->params.crc_type & HDLC_CRC_MASK)
4040 {
4041 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4042 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4043 }
4044
4045 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4046 val |= BIT6;
4047
4048 switch (info->params.preamble_length)
4049 {
4050 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4051 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4052 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4053 }
4054
4055 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4056 val |= BIT0;
4057
4058 wr_reg16(info, TCR, val);
4059
4060 /* TPR (transmit preamble) */
4061
4062 switch (info->params.preamble)
4063 {
4064 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4065 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4066 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4067 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4068 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4069 default: val = 0x7e; break;
4070 }
4071 wr_reg8(info, TPR, (unsigned char)val);
4072
4073 /* RCR (rx control)
4074 *
4075 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4076 * 12..10 encoding
4077 * 09 CRC enable
4078 * 08 CRC32
4079 * 07..03 reserved, must be 0
4080 * 02 reset
4081 * 01 enable
4082 * 00 auto-DCD enable
4083 */
4084 val = 0;
4085
4086 switch(info->params.mode) {
4087 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4088 case MGSL_MODE_BISYNC: val |= BIT15; break;
4089 case MGSL_MODE_RAW: val |= BIT13; break;
4090 }
4091
4092 switch(info->params.encoding)
4093 {
4094 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4095 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4096 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4097 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4098 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4099 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4100 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4101 }
4102
4103 switch (info->params.crc_type & HDLC_CRC_MASK)
4104 {
4105 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4106 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4107 }
4108
4109 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4110 val |= BIT0;
4111
4112 wr_reg16(info, RCR, val);
4113
4114 /* CCR (clock control)
4115 *
4116 * 07..05 tx clock source
4117 * 04..02 rx clock source
4118 * 01 auxclk enable
4119 * 00 BRG enable
4120 */
4121 val = 0;
4122
4123 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4124 {
4125 // when RxC source is DPLL, BRG generates 16X DPLL
4126 // reference clock, so take TxC from BRG/16 to get
4127 // transmit clock at actual data rate
4128 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4129 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4130 else
4131 val |= BIT6; /* 010, txclk = BRG */
4132 }
4133 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4134 val |= BIT7; /* 100, txclk = DPLL Input */
4135 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4136 val |= BIT5; /* 001, txclk = RXC Input */
4137
4138 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4139 val |= BIT3; /* 010, rxclk = BRG */
4140 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4141 val |= BIT4; /* 100, rxclk = DPLL */
4142 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4143 val |= BIT2; /* 001, rxclk = TXC Input */
4144
4145 if (info->params.clock_speed)
4146 val |= BIT1 + BIT0;
4147
4148 wr_reg8(info, CCR, (unsigned char)val);
4149
4150 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4151 {
4152 // program DPLL mode
4153 switch(info->params.encoding)
4154 {
4155 case HDLC_ENCODING_BIPHASE_MARK:
4156 case HDLC_ENCODING_BIPHASE_SPACE:
4157 val = BIT7; break;
4158 case HDLC_ENCODING_BIPHASE_LEVEL:
4159 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4160 val = BIT7 + BIT6; break;
4161 default: val = BIT6; // NRZ encodings
4162 }
4163 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4164
4165 // DPLL requires a 16X reference clock from BRG
4166 set_rate(info, info->params.clock_speed * 16);
4167 }
4168 else
4169 set_rate(info, info->params.clock_speed);
4170
4171 tx_set_idle(info);
4172
4173 msc_set_vcr(info);
4174
4175 /* SCR (serial control)
4176 *
4177 * 15 1=tx req on FIFO half empty
4178 * 14 1=rx req on FIFO half full
4179 * 13 tx data IRQ enable
4180 * 12 tx idle IRQ enable
4181 * 11 underrun IRQ enable
4182 * 10 rx data IRQ enable
4183 * 09 rx idle IRQ enable
4184 * 08 overrun IRQ enable
4185 * 07 DSR IRQ enable
4186 * 06 CTS IRQ enable
4187 * 05 DCD IRQ enable
4188 * 04 RI IRQ enable
4189 * 03 reserved, must be zero
4190 * 02 1=txd->rxd internal loopback enable
4191 * 01 reserved, must be zero
4192 * 00 1=master IRQ enable
4193 */
4194 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4195
4196 if (info->params.loopback)
4197 enable_loopback(info);
4198 }
4199
4200 /*
4201 * set transmit idle mode
4202 */
4203 static void tx_set_idle(struct slgt_info *info)
4204 {
4205 unsigned char val;
4206 unsigned short tcr;
4207
4208 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4209 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4210 */
4211 tcr = rd_reg16(info, TCR);
4212 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4213 /* disable preamble, set idle size to 16 bits */
4214 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4215 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4216 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4217 } else if (!(tcr & BIT6)) {
4218 /* preamble is disabled, set idle size to 8 bits */
4219 tcr &= ~(BIT5 + BIT4);
4220 }
4221 wr_reg16(info, TCR, tcr);
4222
4223 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4224 /* LSB of custom tx idle specified in tx idle register */
4225 val = (unsigned char)(info->idle_mode & 0xff);
4226 } else {
4227 /* standard 8 bit idle patterns */
4228 switch(info->idle_mode)
4229 {
4230 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4231 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4232 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4233 case HDLC_TXIDLE_ZEROS:
4234 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4235 default: val = 0xff;
4236 }
4237 }
4238
4239 wr_reg8(info, TIR, val);
4240 }
4241
4242 /*
4243 * get state of V24 status (input) signals
4244 */
4245 static void get_signals(struct slgt_info *info)
4246 {
4247 unsigned short status = rd_reg16(info, SSR);
4248
4249 /* clear all serial signals except DTR and RTS */
4250 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4251
4252 if (status & BIT3)
4253 info->signals |= SerialSignal_DSR;
4254 if (status & BIT2)
4255 info->signals |= SerialSignal_CTS;
4256 if (status & BIT1)
4257 info->signals |= SerialSignal_DCD;
4258 if (status & BIT0)
4259 info->signals |= SerialSignal_RI;
4260 }
4261
4262 /*
4263 * set V.24 Control Register based on current configuration
4264 */
4265 static void msc_set_vcr(struct slgt_info *info)
4266 {
4267 unsigned char val = 0;
4268
4269 /* VCR (V.24 control)
4270 *
4271 * 07..04 serial IF select
4272 * 03 DTR
4273 * 02 RTS
4274 * 01 LL
4275 * 00 RL
4276 */
4277
4278 switch(info->if_mode & MGSL_INTERFACE_MASK)
4279 {
4280 case MGSL_INTERFACE_RS232:
4281 val |= BIT5; /* 0010 */
4282 break;
4283 case MGSL_INTERFACE_V35:
4284 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4285 break;
4286 case MGSL_INTERFACE_RS422:
4287 val |= BIT6; /* 0100 */
4288 break;
4289 }
4290
4291 if (info->signals & SerialSignal_DTR)
4292 val |= BIT3;
4293 if (info->signals & SerialSignal_RTS)
4294 val |= BIT2;
4295 if (info->if_mode & MGSL_INTERFACE_LL)
4296 val |= BIT1;
4297 if (info->if_mode & MGSL_INTERFACE_RL)
4298 val |= BIT0;
4299 wr_reg8(info, VCR, val);
4300 }
4301
4302 /*
4303 * set state of V24 control (output) signals
4304 */
4305 static void set_signals(struct slgt_info *info)
4306 {
4307 unsigned char val = rd_reg8(info, VCR);
4308 if (info->signals & SerialSignal_DTR)
4309 val |= BIT3;
4310 else
4311 val &= ~BIT3;
4312 if (info->signals & SerialSignal_RTS)
4313 val |= BIT2;
4314 else
4315 val &= ~BIT2;
4316 wr_reg8(info, VCR, val);
4317 }
4318
4319 /*
4320 * free range of receive DMA buffers (i to last)
4321 */
4322 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4323 {
4324 int done = 0;
4325
4326 while(!done) {
4327 /* reset current buffer for reuse */
4328 info->rbufs[i].status = 0;
4329 switch(info->params.mode) {
4330 case MGSL_MODE_RAW:
4331 case MGSL_MODE_MONOSYNC:
4332 case MGSL_MODE_BISYNC:
4333 set_desc_count(info->rbufs[i], info->raw_rx_size);
4334 break;
4335 default:
4336 set_desc_count(info->rbufs[i], DMABUFSIZE);
4337 }
4338
4339 if (i == last)
4340 done = 1;
4341 if (++i == info->rbuf_count)
4342 i = 0;
4343 }
4344 info->rbuf_current = i;
4345 }
4346
4347 /*
4348 * mark all receive DMA buffers as free
4349 */
4350 static void reset_rbufs(struct slgt_info *info)
4351 {
4352 free_rbufs(info, 0, info->rbuf_count - 1);
4353 }
4354
4355 /*
4356 * pass receive HDLC frame to upper layer
4357 *
4358 * return 1 if frame available, otherwise 0
4359 */
4360 static int rx_get_frame(struct slgt_info *info)
4361 {
4362 unsigned int start, end;
4363 unsigned short status;
4364 unsigned int framesize = 0;
4365 int rc = 0;
4366 unsigned long flags;
4367 struct tty_struct *tty = info->tty;
4368 unsigned char addr_field = 0xff;
4369 unsigned int crc_size = 0;
4370
4371 switch (info->params.crc_type & HDLC_CRC_MASK) {
4372 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4373 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4374 }
4375
4376 check_again:
4377
4378 framesize = 0;
4379 addr_field = 0xff;
4380 start = end = info->rbuf_current;
4381
4382 for (;;) {
4383 if (!desc_complete(info->rbufs[end]))
4384 goto cleanup;
4385
4386 if (framesize == 0 && info->params.addr_filter != 0xff)
4387 addr_field = info->rbufs[end].buf[0];
4388
4389 framesize += desc_count(info->rbufs[end]);
4390
4391 if (desc_eof(info->rbufs[end]))
4392 break;
4393
4394 if (++end == info->rbuf_count)
4395 end = 0;
4396
4397 if (end == info->rbuf_current) {
4398 if (info->rx_enabled){
4399 spin_lock_irqsave(&info->lock,flags);
4400 rx_start(info);
4401 spin_unlock_irqrestore(&info->lock,flags);
4402 }
4403 goto cleanup;
4404 }
4405 }
4406
4407 /* status
4408 *
4409 * 15 buffer complete
4410 * 14..06 reserved
4411 * 05..04 residue
4412 * 02 eof (end of frame)
4413 * 01 CRC error
4414 * 00 abort
4415 */
4416 status = desc_status(info->rbufs[end]);
4417
4418 /* ignore CRC bit if not using CRC (bit is undefined) */
4419 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4420 status &= ~BIT1;
4421
4422 if (framesize == 0 ||
4423 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4424 free_rbufs(info, start, end);
4425 goto check_again;
4426 }
4427
4428 if (framesize < (2 + crc_size) || status & BIT0) {
4429 info->icount.rxshort++;
4430 framesize = 0;
4431 } else if (status & BIT1) {
4432 info->icount.rxcrc++;
4433 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4434 framesize = 0;
4435 }
4436
4437 #ifdef CONFIG_HDLC
4438 if (framesize == 0) {
4439 struct net_device_stats *stats = hdlc_stats(info->netdev);
4440 stats->rx_errors++;
4441 stats->rx_frame_errors++;
4442 }
4443 #endif
4444
4445 DBGBH(("%s rx frame status=%04X size=%d\n",
4446 info->device_name, status, framesize));
4447 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4448
4449 if (framesize) {
4450 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4451 framesize -= crc_size;
4452 crc_size = 0;
4453 }
4454
4455 if (framesize > info->max_frame_size + crc_size)
4456 info->icount.rxlong++;
4457 else {
4458 /* copy dma buffer(s) to contiguous temp buffer */
4459 int copy_count = framesize;
4460 int i = start;
4461 unsigned char *p = info->tmp_rbuf;
4462 info->tmp_rbuf_count = framesize;
4463
4464 info->icount.rxok++;
4465
4466 while(copy_count) {
4467 int partial_count = min(copy_count, DMABUFSIZE);
4468 memcpy(p, info->rbufs[i].buf, partial_count);
4469 p += partial_count;
4470 copy_count -= partial_count;
4471 if (++i == info->rbuf_count)
4472 i = 0;
4473 }
4474
4475 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4476 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4477 framesize++;
4478 }
4479
4480 #ifdef CONFIG_HDLC
4481 if (info->netcount)
4482 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4483 else
4484 #endif
4485 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4486 }
4487 }
4488 free_rbufs(info, start, end);
4489 rc = 1;
4490
4491 cleanup:
4492 return rc;
4493 }
4494
4495 /*
4496 * pass receive buffer (RAW synchronous mode) to tty layer
4497 * return 1 if buffer available, otherwise 0
4498 */
4499 static int rx_get_buf(struct slgt_info *info)
4500 {
4501 unsigned int i = info->rbuf_current;
4502 unsigned int count;
4503
4504 if (!desc_complete(info->rbufs[i]))
4505 return 0;
4506 count = desc_count(info->rbufs[i]);
4507 switch(info->params.mode) {
4508 case MGSL_MODE_MONOSYNC:
4509 case MGSL_MODE_BISYNC:
4510 /* ignore residue in byte synchronous modes */
4511 if (desc_residue(info->rbufs[i]))
4512 count--;
4513 break;
4514 }
4515 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4516 DBGINFO(("rx_get_buf size=%d\n", count));
4517 if (count)
4518 ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4519 info->flag_buf, count);
4520 free_rbufs(info, i, i);
4521 return 1;
4522 }
4523
4524 static void reset_tbufs(struct slgt_info *info)
4525 {
4526 unsigned int i;
4527 info->tbuf_current = 0;
4528 for (i=0 ; i < info->tbuf_count ; i++) {
4529 info->tbufs[i].status = 0;
4530 info->tbufs[i].count = 0;
4531 }
4532 }
4533
4534 /*
4535 * return number of free transmit DMA buffers
4536 */
4537 static unsigned int free_tbuf_count(struct slgt_info *info)
4538 {
4539 unsigned int count = 0;
4540 unsigned int i = info->tbuf_current;
4541
4542 do
4543 {
4544 if (desc_count(info->tbufs[i]))
4545 break; /* buffer in use */
4546 ++count;
4547 if (++i == info->tbuf_count)
4548 i=0;
4549 } while (i != info->tbuf_current);
4550
4551 /* last buffer with zero count may be in use, assume it is */
4552 if (count)
4553 --count;
4554
4555 return count;
4556 }
4557
4558 /*
4559 * load transmit DMA buffer(s) with data
4560 */
4561 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4562 {
4563 unsigned short count;
4564 unsigned int i;
4565 struct slgt_desc *d;
4566
4567 if (size == 0)
4568 return;
4569
4570 DBGDATA(info, buf, size, "tx");
4571
4572 info->tbuf_start = i = info->tbuf_current;
4573
4574 while (size) {
4575 d = &info->tbufs[i];
4576 if (++i == info->tbuf_count)
4577 i = 0;
4578
4579 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4580 memcpy(d->buf, buf, count);
4581
4582 size -= count;
4583 buf += count;
4584
4585 /*
4586 * set EOF bit for last buffer of HDLC frame or
4587 * for every buffer in raw mode
4588 */
4589 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4590 info->params.mode == MGSL_MODE_RAW)
4591 set_desc_eof(*d, 1);
4592 else
4593 set_desc_eof(*d, 0);
4594
4595 set_desc_count(*d, count);
4596 }
4597
4598 info->tbuf_current = i;
4599 }
4600
4601 static int register_test(struct slgt_info *info)
4602 {
4603 static unsigned short patterns[] =
4604 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4605 static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4606 unsigned int i;
4607 int rc = 0;
4608
4609 for (i=0 ; i < count ; i++) {
4610 wr_reg16(info, TIR, patterns[i]);
4611 wr_reg16(info, BDR, patterns[(i+1)%count]);
4612 if ((rd_reg16(info, TIR) != patterns[i]) ||
4613 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4614 rc = -ENODEV;
4615 break;
4616 }
4617 }
4618 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4619 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4620 return rc;
4621 }
4622
4623 static int irq_test(struct slgt_info *info)
4624 {
4625 unsigned long timeout;
4626 unsigned long flags;
4627 struct tty_struct *oldtty = info->tty;
4628 u32 speed = info->params.data_rate;
4629
4630 info->params.data_rate = 921600;
4631 info->tty = NULL;
4632
4633 spin_lock_irqsave(&info->lock, flags);
4634 async_mode(info);
4635 slgt_irq_on(info, IRQ_TXIDLE);
4636
4637 /* enable transmitter */
4638 wr_reg16(info, TCR,
4639 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4640
4641 /* write one byte and wait for tx idle */
4642 wr_reg16(info, TDR, 0);
4643
4644 /* assume failure */
4645 info->init_error = DiagStatus_IrqFailure;
4646 info->irq_occurred = FALSE;
4647
4648 spin_unlock_irqrestore(&info->lock, flags);
4649
4650 timeout=100;
4651 while(timeout-- && !info->irq_occurred)
4652 msleep_interruptible(10);
4653
4654 spin_lock_irqsave(&info->lock,flags);
4655 reset_port(info);
4656 spin_unlock_irqrestore(&info->lock,flags);
4657
4658 info->params.data_rate = speed;
4659 info->tty = oldtty;
4660
4661 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4662 return info->irq_occurred ? 0 : -ENODEV;
4663 }
4664
4665 static int loopback_test_rx(struct slgt_info *info)
4666 {
4667 unsigned char *src, *dest;
4668 int count;
4669
4670 if (desc_complete(info->rbufs[0])) {
4671 count = desc_count(info->rbufs[0]);
4672 src = info->rbufs[0].buf;
4673 dest = info->tmp_rbuf;
4674
4675 for( ; count ; count-=2, src+=2) {
4676 /* src=data byte (src+1)=status byte */
4677 if (!(*(src+1) & (BIT9 + BIT8))) {
4678 *dest = *src;
4679 dest++;
4680 info->tmp_rbuf_count++;
4681 }
4682 }
4683 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4684 return 1;
4685 }
4686 return 0;
4687 }
4688
4689 static int loopback_test(struct slgt_info *info)
4690 {
4691 #define TESTFRAMESIZE 20
4692
4693 unsigned long timeout;
4694 u16 count = TESTFRAMESIZE;
4695 unsigned char buf[TESTFRAMESIZE];
4696 int rc = -ENODEV;
4697 unsigned long flags;
4698
4699 struct tty_struct *oldtty = info->tty;
4700 MGSL_PARAMS params;
4701
4702 memcpy(&params, &info->params, sizeof(params));
4703
4704 info->params.mode = MGSL_MODE_ASYNC;
4705 info->params.data_rate = 921600;
4706 info->params.loopback = 1;
4707 info->tty = NULL;
4708
4709 /* build and send transmit frame */
4710 for (count = 0; count < TESTFRAMESIZE; ++count)
4711 buf[count] = (unsigned char)count;
4712
4713 info->tmp_rbuf_count = 0;
4714 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4715
4716 /* program hardware for HDLC and enabled receiver */
4717 spin_lock_irqsave(&info->lock,flags);
4718 async_mode(info);
4719 rx_start(info);
4720 info->tx_count = count;
4721 tx_load(info, buf, count);
4722 tx_start(info);
4723 spin_unlock_irqrestore(&info->lock, flags);
4724
4725 /* wait for receive complete */
4726 for (timeout = 100; timeout; --timeout) {
4727 msleep_interruptible(10);
4728 if (loopback_test_rx(info)) {
4729 rc = 0;
4730 break;
4731 }
4732 }
4733
4734 /* verify received frame length and contents */
4735 if (!rc && (info->tmp_rbuf_count != count ||
4736 memcmp(buf, info->tmp_rbuf, count))) {
4737 rc = -ENODEV;
4738 }
4739
4740 spin_lock_irqsave(&info->lock,flags);
4741 reset_adapter(info);
4742 spin_unlock_irqrestore(&info->lock,flags);
4743
4744 memcpy(&info->params, &params, sizeof(info->params));
4745 info->tty = oldtty;
4746
4747 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4748 return rc;
4749 }
4750
4751 static int adapter_test(struct slgt_info *info)
4752 {
4753 DBGINFO(("testing %s\n", info->device_name));
4754 if (register_test(info) < 0) {
4755 printk("register test failure %s addr=%08X\n",
4756 info->device_name, info->phys_reg_addr);
4757 } else if (irq_test(info) < 0) {
4758 printk("IRQ test failure %s IRQ=%d\n",
4759 info->device_name, info->irq_level);
4760 } else if (loopback_test(info) < 0) {
4761 printk("loopback test failure %s\n", info->device_name);
4762 }
4763 return info->init_error;
4764 }
4765
4766 /*
4767 * transmit timeout handler
4768 */
4769 static void tx_timeout(unsigned long context)
4770 {
4771 struct slgt_info *info = (struct slgt_info*)context;
4772 unsigned long flags;
4773
4774 DBGINFO(("%s tx_timeout\n", info->device_name));
4775 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4776 info->icount.txtimeout++;
4777 }
4778 spin_lock_irqsave(&info->lock,flags);
4779 info->tx_active = 0;
4780 info->tx_count = 0;
4781 spin_unlock_irqrestore(&info->lock,flags);
4782
4783 #ifdef CONFIG_HDLC
4784 if (info->netcount)
4785 hdlcdev_tx_done(info);
4786 else
4787 #endif
4788 bh_transmit(info);
4789 }
4790
4791 /*
4792 * receive buffer polling timer
4793 */
4794 static void rx_timeout(unsigned long context)
4795 {
4796 struct slgt_info *info = (struct slgt_info*)context;
4797 unsigned long flags;
4798
4799 DBGINFO(("%s rx_timeout\n", info->device_name));
4800 spin_lock_irqsave(&info->lock, flags);
4801 info->pending_bh |= BH_RECEIVE;
4802 spin_unlock_irqrestore(&info->lock, flags);
4803 bh_handler(info);
4804 }
4805
Support for the Chinese Samsung S3C2440 based development boards