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crypto: hash - Fixed digest size check
[linux-2.6/mini2440.git] / drivers / net / r6040.c
blob504a48ff73c83e5cbac2eaa96c25bdc754bbd40e
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/version.h>
28 #include <linux/moduleparam.h>
29 #include <linux/string.h>
30 #include <linux/timer.h>
31 #include <linux/errno.h>
32 #include <linux/ioport.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/mii.h>
42 #include <linux/ethtool.h>
43 #include <linux/crc32.h>
44 #include <linux/spinlock.h>
45 #include <linux/bitops.h>
46 #include <linux/io.h>
47 #include <linux/irq.h>
48 #include <linux/uaccess.h>
49
50 #include <asm/processor.h>
51
52 #define DRV_NAME "r6040"
53 #define DRV_VERSION "0.16"
54 #define DRV_RELDATE "10Nov2007"
55
56 /* PHY CHIP Address */
57 #define PHY1_ADDR 1 /* For MAC1 */
58 #define PHY2_ADDR 2 /* For MAC2 */
59 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
60 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
61
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT (6000 * HZ / 1000)
64
65 /* RDC MAC I/O Size */
66 #define R6040_IO_SIZE 256
67
68 /* MAX RDC MAC */
69 #define MAX_MAC 2
70
71 /* MAC registers */
72 #define MCR0 0x00 /* Control register 0 */
73 #define MCR1 0x04 /* Control register 1 */
74 #define MAC_RST 0x0001 /* Reset the MAC */
75 #define MBCR 0x08 /* Bus control */
76 #define MT_ICR 0x0C /* TX interrupt control */
77 #define MR_ICR 0x10 /* RX interrupt control */
78 #define MTPR 0x14 /* TX poll command register */
79 #define MR_BSR 0x18 /* RX buffer size */
80 #define MR_DCR 0x1A /* RX descriptor control */
81 #define MLSR 0x1C /* Last status */
82 #define MMDIO 0x20 /* MDIO control register */
83 #define MDIO_WRITE 0x4000 /* MDIO write */
84 #define MDIO_READ 0x2000 /* MDIO read */
85 #define MMRD 0x24 /* MDIO read data register */
86 #define MMWD 0x28 /* MDIO write data register */
87 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
88 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
89 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
90 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
91 #define MISR 0x3C /* Status register */
92 #define MIER 0x40 /* INT enable register */
93 #define MSK_INT 0x0000 /* Mask off interrupts */
94 #define ME_CISR 0x44 /* Event counter INT status */
95 #define ME_CIER 0x48 /* Event counter INT enable */
96 #define MR_CNT 0x50 /* Successfully received packet counter */
97 #define ME_CNT0 0x52 /* Event counter 0 */
98 #define ME_CNT1 0x54 /* Event counter 1 */
99 #define ME_CNT2 0x56 /* Event counter 2 */
100 #define ME_CNT3 0x58 /* Event counter 3 */
101 #define MT_CNT 0x5A /* Successfully transmit packet counter */
102 #define ME_CNT4 0x5C /* Event counter 4 */
103 #define MP_CNT 0x5E /* Pause frame counter register */
104 #define MAR0 0x60 /* Hash table 0 */
105 #define MAR1 0x62 /* Hash table 1 */
106 #define MAR2 0x64 /* Hash table 2 */
107 #define MAR3 0x66 /* Hash table 3 */
108 #define MID_0L 0x68 /* Multicast address MID0 Low */
109 #define MID_0M 0x6A /* Multicast address MID0 Medium */
110 #define MID_0H 0x6C /* Multicast address MID0 High */
111 #define MID_1L 0x70 /* MID1 Low */
112 #define MID_1M 0x72 /* MID1 Medium */
113 #define MID_1H 0x74 /* MID1 High */
114 #define MID_2L 0x78 /* MID2 Low */
115 #define MID_2M 0x7A /* MID2 Medium */
116 #define MID_2H 0x7C /* MID2 High */
117 #define MID_3L 0x80 /* MID3 Low */
118 #define MID_3M 0x82 /* MID3 Medium */
119 #define MID_3H 0x84 /* MID3 High */
120 #define PHY_CC 0x88 /* PHY status change configuration register */
121 #define PHY_ST 0x8A /* PHY status register */
122 #define MAC_SM 0xAC /* MAC status machine */
123 #define MAC_ID 0xBE /* Identifier register */
124
125 #define TX_DCNT 0x80 /* TX descriptor count */
126 #define RX_DCNT 0x80 /* RX descriptor count */
127 #define MAX_BUF_SIZE 0x600
128 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
129 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
130 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
131 #define MCAST_MAX 4 /* Max number multicast addresses to filter */
132
133 /* PHY settings */
134 #define ICPLUS_PHY_ID 0x0243
135
136 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
137 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
138 "Florian Fainelli <florian@openwrt.org>");
139 MODULE_LICENSE("GPL");
140 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
141
142 #define RX_INT 0x0001
143 #define TX_INT 0x0010
144 #define RX_NO_DESC_INT 0x0002
145 #define INT_MASK (RX_INT | TX_INT)
146
147 struct r6040_descriptor {
148 u16 status, len; /* 0-3 */
149 __le32 buf; /* 4-7 */
150 __le32 ndesc; /* 8-B */
151 u32 rev1; /* C-F */
152 char *vbufp; /* 10-13 */
153 struct r6040_descriptor *vndescp; /* 14-17 */
154 struct sk_buff *skb_ptr; /* 18-1B */
155 u32 rev2; /* 1C-1F */
156 } __attribute__((aligned(32)));
157
158 struct r6040_private {
159 spinlock_t lock; /* driver lock */
160 struct timer_list timer;
161 struct pci_dev *pdev;
162 struct r6040_descriptor *rx_insert_ptr;
163 struct r6040_descriptor *rx_remove_ptr;
164 struct r6040_descriptor *tx_insert_ptr;
165 struct r6040_descriptor *tx_remove_ptr;
166 struct r6040_descriptor *rx_ring;
167 struct r6040_descriptor *tx_ring;
168 dma_addr_t rx_ring_dma;
169 dma_addr_t tx_ring_dma;
170 u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode;
171 u16 mcr0, mcr1;
172 u16 switch_sig;
173 struct net_device *dev;
174 struct mii_if_info mii_if;
175 struct napi_struct napi;
176 void __iomem *base;
177 };
178
179 static char version[] __devinitdata = KERN_INFO DRV_NAME
180 ": RDC R6040 NAPI net driver,"
181 "version "DRV_VERSION " (" DRV_RELDATE ")\n";
182
183 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
184
185 /* Read a word data from PHY Chip */
186 static int phy_read(void __iomem *ioaddr, int phy_addr, int reg)
187 {
188 int limit = 2048;
189 u16 cmd;
190
191 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
192 /* Wait for the read bit to be cleared */
193 while (limit--) {
194 cmd = ioread16(ioaddr + MMDIO);
195 if (cmd & MDIO_READ)
196 break;
197 }
198
199 return ioread16(ioaddr + MMRD);
200 }
201
202 /* Write a word data from PHY Chip */
203 static void phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
204 {
205 int limit = 2048;
206 u16 cmd;
207
208 iowrite16(val, ioaddr + MMWD);
209 /* Write the command to the MDIO bus */
210 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
211 /* Wait for the write bit to be cleared */
212 while (limit--) {
213 cmd = ioread16(ioaddr + MMDIO);
214 if (cmd & MDIO_WRITE)
215 break;
216 }
217 }
218
219 static int mdio_read(struct net_device *dev, int mii_id, int reg)
220 {
221 struct r6040_private *lp = netdev_priv(dev);
222 void __iomem *ioaddr = lp->base;
223
224 return (phy_read(ioaddr, lp->phy_addr, reg));
225 }
226
227 static void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
228 {
229 struct r6040_private *lp = netdev_priv(dev);
230 void __iomem *ioaddr = lp->base;
231
232 phy_write(ioaddr, lp->phy_addr, reg, val);
233 }
234
235 static void r6040_free_txbufs(struct net_device *dev)
236 {
237 struct r6040_private *lp = netdev_priv(dev);
238 int i;
239
240 for (i = 0; i < TX_DCNT; i++) {
241 if (lp->tx_insert_ptr->skb_ptr) {
242 pci_unmap_single(lp->pdev,
243 le32_to_cpu(lp->tx_insert_ptr->buf),
244 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
245 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
246 lp->rx_insert_ptr->skb_ptr = NULL;
247 }
248 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
249 }
250 }
251
252 static void r6040_free_rxbufs(struct net_device *dev)
253 {
254 struct r6040_private *lp = netdev_priv(dev);
255 int i;
256
257 for (i = 0; i < RX_DCNT; i++) {
258 if (lp->rx_insert_ptr->skb_ptr) {
259 pci_unmap_single(lp->pdev,
260 le32_to_cpu(lp->rx_insert_ptr->buf),
261 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
262 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
263 lp->rx_insert_ptr->skb_ptr = NULL;
264 }
265 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
266 }
267 }
268
269 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
270 dma_addr_t desc_dma, int size)
271 {
272 struct r6040_descriptor *desc = desc_ring;
273 dma_addr_t mapping = desc_dma;
274
275 while (size-- > 0) {
276 mapping += sizeof(*desc);
277 desc->ndesc = cpu_to_le32(mapping);
278 desc->vndescp = desc + 1;
279 desc++;
280 }
281 desc--;
282 desc->ndesc = cpu_to_le32(desc_dma);
283 desc->vndescp = desc_ring;
284 }
285
286 /* Allocate skb buffer for rx descriptor */
287 static void rx_buf_alloc(struct r6040_private *lp, struct net_device *dev)
288 {
289 struct r6040_descriptor *descptr;
290 void __iomem *ioaddr = lp->base;
291
292 descptr = lp->rx_insert_ptr;
293 while (lp->rx_free_desc < RX_DCNT) {
294 descptr->skb_ptr = netdev_alloc_skb(dev, MAX_BUF_SIZE);
295
296 if (!descptr->skb_ptr)
297 break;
298 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
299 descptr->skb_ptr->data,
300 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
301 descptr->status = 0x8000;
302 descptr = descptr->vndescp;
303 lp->rx_free_desc++;
304 /* Trigger RX DMA */
305 iowrite16(lp->mcr0 | 0x0002, ioaddr);
306 }
307 lp->rx_insert_ptr = descptr;
308 }
309
310 static void r6040_alloc_txbufs(struct net_device *dev)
311 {
312 struct r6040_private *lp = netdev_priv(dev);
313 void __iomem *ioaddr = lp->base;
314
315 lp->tx_free_desc = TX_DCNT;
316
317 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
318 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
319
320 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
321 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
322 }
323
324 static void r6040_alloc_rxbufs(struct net_device *dev)
325 {
326 struct r6040_private *lp = netdev_priv(dev);
327 void __iomem *ioaddr = lp->base;
328
329 lp->rx_free_desc = 0;
330
331 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
332 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
333
334 rx_buf_alloc(lp, dev);
335
336 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
337 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
338 }
339
340 static void r6040_tx_timeout(struct net_device *dev)
341 {
342 struct r6040_private *priv = netdev_priv(dev);
343 void __iomem *ioaddr = priv->base;
344
345 printk(KERN_WARNING "%s: transmit timed out, status %4.4x, PHY status "
346 "%4.4x\n",
347 dev->name, ioread16(ioaddr + MIER),
348 mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
349
350 disable_irq(dev->irq);
351 napi_disable(&priv->napi);
352 spin_lock(&priv->lock);
353 /* Clear all descriptors */
354 r6040_free_txbufs(dev);
355 r6040_free_rxbufs(dev);
356 r6040_alloc_txbufs(dev);
357 r6040_alloc_rxbufs(dev);
358
359 /* Reset MAC */
360 iowrite16(MAC_RST, ioaddr + MCR1);
361 spin_unlock(&priv->lock);
362 enable_irq(dev->irq);
363
364 dev->stats.tx_errors++;
365 netif_wake_queue(dev);
366 }
367
368 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
369 {
370 struct r6040_private *priv = netdev_priv(dev);
371 void __iomem *ioaddr = priv->base;
372 unsigned long flags;
373
374 spin_lock_irqsave(&priv->lock, flags);
375 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
376 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
377 spin_unlock_irqrestore(&priv->lock, flags);
378
379 return &dev->stats;
380 }
381
382 /* Stop RDC MAC and Free the allocated resource */
383 static void r6040_down(struct net_device *dev)
384 {
385 struct r6040_private *lp = netdev_priv(dev);
386 void __iomem *ioaddr = lp->base;
387 struct pci_dev *pdev = lp->pdev;
388 int limit = 2048;
389 u16 *adrp;
390 u16 cmd;
391
392 /* Stop MAC */
393 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
394 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
395 while (limit--) {
396 cmd = ioread16(ioaddr + MCR1);
397 if (cmd & 0x1)
398 break;
399 }
400
401 /* Restore MAC Address to MIDx */
402 adrp = (u16 *) dev->dev_addr;
403 iowrite16(adrp[0], ioaddr + MID_0L);
404 iowrite16(adrp[1], ioaddr + MID_0M);
405 iowrite16(adrp[2], ioaddr + MID_0H);
406 free_irq(dev->irq, dev);
407
408 /* Free RX buffer */
409 r6040_free_rxbufs(dev);
410
411 /* Free TX buffer */
412 r6040_free_txbufs(dev);
413
414 /* Free Descriptor memory */
415 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
416 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
417 }
418
419 static int r6040_close(struct net_device *dev)
420 {
421 struct r6040_private *lp = netdev_priv(dev);
422
423 /* deleted timer */
424 del_timer_sync(&lp->timer);
425
426 spin_lock_irq(&lp->lock);
427 netif_stop_queue(dev);
428 r6040_down(dev);
429 spin_unlock_irq(&lp->lock);
430
431 return 0;
432 }
433
434 /* Status of PHY CHIP */
435 static int phy_mode_chk(struct net_device *dev)
436 {
437 struct r6040_private *lp = netdev_priv(dev);
438 void __iomem *ioaddr = lp->base;
439 int phy_dat;
440
441 /* PHY Link Status Check */
442 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
443 if (!(phy_dat & 0x4))
444 phy_dat = 0x8000; /* Link Failed, full duplex */
445
446 /* PHY Chip Auto-Negotiation Status */
447 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
448 if (phy_dat & 0x0020) {
449 /* Auto Negotiation Mode */
450 phy_dat = phy_read(ioaddr, lp->phy_addr, 5);
451 phy_dat &= phy_read(ioaddr, lp->phy_addr, 4);
452 if (phy_dat & 0x140)
453 /* Force full duplex */
454 phy_dat = 0x8000;
455 else
456 phy_dat = 0;
457 } else {
458 /* Force Mode */
459 phy_dat = phy_read(ioaddr, lp->phy_addr, 0);
460 if (phy_dat & 0x100)
461 phy_dat = 0x8000;
462 else
463 phy_dat = 0x0000;
464 }
465
466 return phy_dat;
467 };
468
469 static void r6040_set_carrier(struct mii_if_info *mii)
470 {
471 if (phy_mode_chk(mii->dev)) {
472 /* autoneg is off: Link is always assumed to be up */
473 if (!netif_carrier_ok(mii->dev))
474 netif_carrier_on(mii->dev);
475 } else
476 phy_mode_chk(mii->dev);
477 }
478
479 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
480 {
481 struct r6040_private *lp = netdev_priv(dev);
482 struct mii_ioctl_data *data = if_mii(rq);
483 int rc;
484
485 if (!netif_running(dev))
486 return -EINVAL;
487 spin_lock_irq(&lp->lock);
488 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
489 spin_unlock_irq(&lp->lock);
490 r6040_set_carrier(&lp->mii_if);
491 return rc;
492 }
493
494 static int r6040_rx(struct net_device *dev, int limit)
495 {
496 struct r6040_private *priv = netdev_priv(dev);
497 int count;
498 void __iomem *ioaddr = priv->base;
499 u16 err;
500
501 for (count = 0; count < limit; ++count) {
502 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
503 struct sk_buff *skb_ptr;
504
505 /* Disable RX interrupt */
506 iowrite16(ioread16(ioaddr + MIER) & (~RX_INT), ioaddr + MIER);
507 descptr = priv->rx_remove_ptr;
508
509 /* Check for errors */
510 err = ioread16(ioaddr + MLSR);
511 if (err & 0x0400)
512 dev->stats.rx_errors++;
513 /* RX FIFO over-run */
514 if (err & 0x8000)
515 dev->stats.rx_fifo_errors++;
516 /* RX descriptor unavailable */
517 if (err & 0x0080)
518 dev->stats.rx_frame_errors++;
519 /* Received packet with length over buffer lenght */
520 if (err & 0x0020)
521 dev->stats.rx_over_errors++;
522 /* Received packet with too long or short */
523 if (err & (0x0010 | 0x0008))
524 dev->stats.rx_length_errors++;
525 /* Received packet with CRC errors */
526 if (err & 0x0004) {
527 spin_lock(&priv->lock);
528 dev->stats.rx_crc_errors++;
529 spin_unlock(&priv->lock);
530 }
531
532 while (priv->rx_free_desc) {
533 /* No RX packet */
534 if (descptr->status & 0x8000)
535 break;
536 skb_ptr = descptr->skb_ptr;
537 if (!skb_ptr) {
538 printk(KERN_ERR "%s: Inconsistent RX"
539 "descriptor chain\n",
540 dev->name);
541 break;
542 }
543 descptr->skb_ptr = NULL;
544 skb_ptr->dev = priv->dev;
545 /* Do not count the CRC */
546 skb_put(skb_ptr, descptr->len - 4);
547 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
548 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
549 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
550 /* Send to upper layer */
551 netif_receive_skb(skb_ptr);
552 dev->last_rx = jiffies;
553 dev->stats.rx_packets++;
554 dev->stats.rx_bytes += descptr->len;
555 /* To next descriptor */
556 descptr = descptr->vndescp;
557 priv->rx_free_desc--;
558 }
559 priv->rx_remove_ptr = descptr;
560 }
561 /* Allocate new RX buffer */
562 if (priv->rx_free_desc < RX_DCNT)
563 rx_buf_alloc(priv, priv->dev);
564
565 return count;
566 }
567
568 static void r6040_tx(struct net_device *dev)
569 {
570 struct r6040_private *priv = netdev_priv(dev);
571 struct r6040_descriptor *descptr;
572 void __iomem *ioaddr = priv->base;
573 struct sk_buff *skb_ptr;
574 u16 err;
575
576 spin_lock(&priv->lock);
577 descptr = priv->tx_remove_ptr;
578 while (priv->tx_free_desc < TX_DCNT) {
579 /* Check for errors */
580 err = ioread16(ioaddr + MLSR);
581
582 if (err & 0x0200)
583 dev->stats.rx_fifo_errors++;
584 if (err & (0x2000 | 0x4000))
585 dev->stats.tx_carrier_errors++;
586
587 if (descptr->status & 0x8000)
588 break; /* Not complete */
589 skb_ptr = descptr->skb_ptr;
590 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
591 skb_ptr->len, PCI_DMA_TODEVICE);
592 /* Free buffer */
593 dev_kfree_skb_irq(skb_ptr);
594 descptr->skb_ptr = NULL;
595 /* To next descriptor */
596 descptr = descptr->vndescp;
597 priv->tx_free_desc++;
598 }
599 priv->tx_remove_ptr = descptr;
600
601 if (priv->tx_free_desc)
602 netif_wake_queue(dev);
603 spin_unlock(&priv->lock);
604 }
605
606 static int r6040_poll(struct napi_struct *napi, int budget)
607 {
608 struct r6040_private *priv =
609 container_of(napi, struct r6040_private, napi);
610 struct net_device *dev = priv->dev;
611 void __iomem *ioaddr = priv->base;
612 int work_done;
613
614 work_done = r6040_rx(dev, budget);
615
616 if (work_done < budget) {
617 netif_rx_complete(dev, napi);
618 /* Enable RX interrupt */
619 iowrite16(ioread16(ioaddr + MIER) | RX_INT, ioaddr + MIER);
620 }
621 return work_done;
622 }
623
624 /* The RDC interrupt handler. */
625 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
626 {
627 struct net_device *dev = dev_id;
628 struct r6040_private *lp = netdev_priv(dev);
629 void __iomem *ioaddr = lp->base;
630 u16 status;
631
632 /* Mask off RDC MAC interrupt */
633 iowrite16(MSK_INT, ioaddr + MIER);
634 /* Read MISR status and clear */
635 status = ioread16(ioaddr + MISR);
636
637 if (status == 0x0000 || status == 0xffff)
638 return IRQ_NONE;
639
640 /* RX interrupt request */
641 if (status & 0x01) {
642 netif_rx_schedule(dev, &lp->napi);
643 iowrite16(TX_INT, ioaddr + MIER);
644 }
645
646 /* TX interrupt request */
647 if (status & 0x10)
648 r6040_tx(dev);
649
650 return IRQ_HANDLED;
651 }
652
653 #ifdef CONFIG_NET_POLL_CONTROLLER
654 static void r6040_poll_controller(struct net_device *dev)
655 {
656 disable_irq(dev->irq);
657 r6040_interrupt(dev->irq, dev);
658 enable_irq(dev->irq);
659 }
660 #endif
661
662 /* Init RDC MAC */
663 static void r6040_up(struct net_device *dev)
664 {
665 struct r6040_private *lp = netdev_priv(dev);
666 void __iomem *ioaddr = lp->base;
667
668 /* Initialise and alloc RX/TX buffers */
669 r6040_alloc_txbufs(dev);
670 r6040_alloc_rxbufs(dev);
671
672 /* Buffer Size Register */
673 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
674 /* Read the PHY ID */
675 lp->switch_sig = phy_read(ioaddr, 0, 2);
676
677 if (lp->switch_sig == ICPLUS_PHY_ID) {
678 phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
679 lp->phy_mode = 0x8000;
680 } else {
681 /* PHY Mode Check */
682 phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
683 phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
684
685 if (PHY_MODE == 0x3100)
686 lp->phy_mode = phy_mode_chk(dev);
687 else
688 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
689 }
690 /* MAC Bus Control Register */
691 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
692
693 /* MAC TX/RX Enable */
694 lp->mcr0 |= lp->phy_mode;
695 iowrite16(lp->mcr0, ioaddr);
696
697 /* set interrupt waiting time and packet numbers */
698 iowrite16(0x0F06, ioaddr + MT_ICR);
699 iowrite16(0x0F06, ioaddr + MR_ICR);
700
701 /* improve performance (by RDC guys) */
702 phy_write(ioaddr, 30, 17, (phy_read(ioaddr, 30, 17) | 0x4000));
703 phy_write(ioaddr, 30, 17, ~((~phy_read(ioaddr, 30, 17)) | 0x2000));
704 phy_write(ioaddr, 0, 19, 0x0000);
705 phy_write(ioaddr, 0, 30, 0x01F0);
706
707 /* Interrupt Mask Register */
708 iowrite16(INT_MASK, ioaddr + MIER);
709 }
710
711 /*
712 A periodic timer routine
713 Polling PHY Chip Link Status
714 */
715 static void r6040_timer(unsigned long data)
716 {
717 struct net_device *dev = (struct net_device *)data;
718 struct r6040_private *lp = netdev_priv(dev);
719 void __iomem *ioaddr = lp->base;
720 u16 phy_mode;
721
722 /* Polling PHY Chip Status */
723 if (PHY_MODE == 0x3100)
724 phy_mode = phy_mode_chk(dev);
725 else
726 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
727
728 if (phy_mode != lp->phy_mode) {
729 lp->phy_mode = phy_mode;
730 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
731 iowrite16(lp->mcr0, ioaddr);
732 printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
733 }
734
735 /* Timer active again */
736 mod_timer(&lp->timer, round_jiffies(jiffies + HZ));
737 }
738
739 /* Read/set MAC address routines */
740 static void r6040_mac_address(struct net_device *dev)
741 {
742 struct r6040_private *lp = netdev_priv(dev);
743 void __iomem *ioaddr = lp->base;
744 u16 *adrp;
745
746 /* MAC operation register */
747 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
748 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
749 iowrite16(0, ioaddr + MAC_SM);
750 udelay(5000);
751
752 /* Restore MAC Address */
753 adrp = (u16 *) dev->dev_addr;
754 iowrite16(adrp[0], ioaddr + MID_0L);
755 iowrite16(adrp[1], ioaddr + MID_0M);
756 iowrite16(adrp[2], ioaddr + MID_0H);
757 }
758
759 static int r6040_open(struct net_device *dev)
760 {
761 struct r6040_private *lp = netdev_priv(dev);
762 int ret;
763
764 /* Request IRQ and Register interrupt handler */
765 ret = request_irq(dev->irq, &r6040_interrupt,
766 IRQF_SHARED, dev->name, dev);
767 if (ret)
768 return ret;
769
770 /* Set MAC address */
771 r6040_mac_address(dev);
772
773 /* Allocate Descriptor memory */
774 lp->rx_ring =
775 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
776 if (!lp->rx_ring)
777 return -ENOMEM;
778
779 lp->tx_ring =
780 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
781 if (!lp->tx_ring) {
782 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
783 lp->rx_ring_dma);
784 return -ENOMEM;
785 }
786
787 r6040_up(dev);
788
789 napi_enable(&lp->napi);
790 netif_start_queue(dev);
791
792 /* set and active a timer process */
793 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
794 if (lp->switch_sig != ICPLUS_PHY_ID)
795 mod_timer(&lp->timer, jiffies + HZ);
796 return 0;
797 }
798
799 static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
800 {
801 struct r6040_private *lp = netdev_priv(dev);
802 struct r6040_descriptor *descptr;
803 void __iomem *ioaddr = lp->base;
804 unsigned long flags;
805 int ret = NETDEV_TX_OK;
806
807 /* Critical Section */
808 spin_lock_irqsave(&lp->lock, flags);
809
810 /* TX resource check */
811 if (!lp->tx_free_desc) {
812 spin_unlock_irqrestore(&lp->lock, flags);
813 netif_stop_queue(dev);
814 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
815 ret = NETDEV_TX_BUSY;
816 return ret;
817 }
818
819 /* Statistic Counter */
820 dev->stats.tx_packets++;
821 dev->stats.tx_bytes += skb->len;
822 /* Set TX descriptor & Transmit it */
823 lp->tx_free_desc--;
824 descptr = lp->tx_insert_ptr;
825 if (skb->len < MISR)
826 descptr->len = MISR;
827 else
828 descptr->len = skb->len;
829
830 descptr->skb_ptr = skb;
831 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
832 skb->data, skb->len, PCI_DMA_TODEVICE));
833 descptr->status = 0x8000;
834 /* Trigger the MAC to check the TX descriptor */
835 iowrite16(0x01, ioaddr + MTPR);
836 lp->tx_insert_ptr = descptr->vndescp;
837
838 /* If no tx resource, stop */
839 if (!lp->tx_free_desc)
840 netif_stop_queue(dev);
841
842 dev->trans_start = jiffies;
843 spin_unlock_irqrestore(&lp->lock, flags);
844 return ret;
845 }
846
847 static void r6040_multicast_list(struct net_device *dev)
848 {
849 struct r6040_private *lp = netdev_priv(dev);
850 void __iomem *ioaddr = lp->base;
851 u16 *adrp;
852 u16 reg;
853 unsigned long flags;
854 struct dev_mc_list *dmi = dev->mc_list;
855 int i;
856
857 /* MAC Address */
858 adrp = (u16 *)dev->dev_addr;
859 iowrite16(adrp[0], ioaddr + MID_0L);
860 iowrite16(adrp[1], ioaddr + MID_0M);
861 iowrite16(adrp[2], ioaddr + MID_0H);
862
863 /* Promiscous Mode */
864 spin_lock_irqsave(&lp->lock, flags);
865
866 /* Clear AMCP & PROM bits */
867 reg = ioread16(ioaddr) & ~0x0120;
868 if (dev->flags & IFF_PROMISC) {
869 reg |= 0x0020;
870 lp->mcr0 |= 0x0020;
871 }
872 /* Too many multicast addresses
873 * accept all traffic */
874 else if ((dev->mc_count > MCAST_MAX)
875 || (dev->flags & IFF_ALLMULTI))
876 reg |= 0x0020;
877
878 iowrite16(reg, ioaddr);
879 spin_unlock_irqrestore(&lp->lock, flags);
880
881 /* Build the hash table */
882 if (dev->mc_count > MCAST_MAX) {
883 u16 hash_table[4];
884 u32 crc;
885
886 for (i = 0; i < 4; i++)
887 hash_table[i] = 0;
888
889 for (i = 0; i < dev->mc_count; i++) {
890 char *addrs = dmi->dmi_addr;
891
892 dmi = dmi->next;
893
894 if (!(*addrs & 1))
895 continue;
896
897 crc = ether_crc_le(6, addrs);
898 crc >>= 26;
899 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
900 }
901 /* Write the index of the hash table */
902 for (i = 0; i < 4; i++)
903 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
904 /* Fill the MAC hash tables with their values */
905 iowrite16(hash_table[0], ioaddr + MAR0);
906 iowrite16(hash_table[1], ioaddr + MAR1);
907 iowrite16(hash_table[2], ioaddr + MAR2);
908 iowrite16(hash_table[3], ioaddr + MAR3);
909 }
910 /* Multicast Address 1~4 case */
911 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
912 adrp = (u16 *)dmi->dmi_addr;
913 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
914 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
915 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
916 dmi = dmi->next;
917 }
918 for (i = dev->mc_count; i < MCAST_MAX; i++) {
919 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
920 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
921 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
922 }
923 }
924
925 static void netdev_get_drvinfo(struct net_device *dev,
926 struct ethtool_drvinfo *info)
927 {
928 struct r6040_private *rp = netdev_priv(dev);
929
930 strcpy(info->driver, DRV_NAME);
931 strcpy(info->version, DRV_VERSION);
932 strcpy(info->bus_info, pci_name(rp->pdev));
933 }
934
935 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
936 {
937 struct r6040_private *rp = netdev_priv(dev);
938 int rc;
939
940 spin_lock_irq(&rp->lock);
941 rc = mii_ethtool_gset(&rp->mii_if, cmd);
942 spin_unlock_irq(&rp->lock);
943
944 return rc;
945 }
946
947 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
948 {
949 struct r6040_private *rp = netdev_priv(dev);
950 int rc;
951
952 spin_lock_irq(&rp->lock);
953 rc = mii_ethtool_sset(&rp->mii_if, cmd);
954 spin_unlock_irq(&rp->lock);
955 r6040_set_carrier(&rp->mii_if);
956
957 return rc;
958 }
959
960 static u32 netdev_get_link(struct net_device *dev)
961 {
962 struct r6040_private *rp = netdev_priv(dev);
963
964 return mii_link_ok(&rp->mii_if);
965 }
966
967 static struct ethtool_ops netdev_ethtool_ops = {
968 .get_drvinfo = netdev_get_drvinfo,
969 .get_settings = netdev_get_settings,
970 .set_settings = netdev_set_settings,
971 .get_link = netdev_get_link,
972 };
973
974 static int __devinit r6040_init_one(struct pci_dev *pdev,
975 const struct pci_device_id *ent)
976 {
977 struct net_device *dev;
978 struct r6040_private *lp;
979 void __iomem *ioaddr;
980 int err, io_size = R6040_IO_SIZE;
981 static int card_idx = -1;
982 int bar = 0;
983 long pioaddr;
984 u16 *adrp;
985
986 printk(KERN_INFO "%s\n", version);
987
988 err = pci_enable_device(pdev);
989 if (err)
990 return err;
991
992 /* this should always be supported */
993 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
994 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
995 "not supported by the card\n");
996 return -ENODEV;
997 }
998 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
999 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
1000 "not supported by the card\n");
1001 return -ENODEV;
1002 }
1003
1004 /* IO Size check */
1005 if (pci_resource_len(pdev, 0) < io_size) {
1006 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
1007 return -EIO;
1008 }
1009
1010 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
1011 pci_set_master(pdev);
1012
1013 dev = alloc_etherdev(sizeof(struct r6040_private));
1014 if (!dev) {
1015 printk(KERN_ERR "Failed to allocate etherdev\n");
1016 return -ENOMEM;
1017 }
1018 SET_NETDEV_DEV(dev, &pdev->dev);
1019 lp = netdev_priv(dev);
1020 lp->pdev = pdev;
1021
1022 if (pci_request_regions(pdev, DRV_NAME)) {
1023 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
1024 err = -ENODEV;
1025 goto err_out_disable;
1026 }
1027
1028 ioaddr = pci_iomap(pdev, bar, io_size);
1029 if (!ioaddr) {
1030 printk(KERN_ERR "ioremap failed for device %s\n",
1031 pci_name(pdev));
1032 return -EIO;
1033 }
1034
1035 /* Init system & device */
1036 lp->base = ioaddr;
1037 dev->irq = pdev->irq;
1038
1039 spin_lock_init(&lp->lock);
1040 pci_set_drvdata(pdev, dev);
1041
1042 /* Set MAC address */
1043 card_idx++;
1044
1045 adrp = (u16 *)dev->dev_addr;
1046 adrp[0] = ioread16(ioaddr + MID_0L);
1047 adrp[1] = ioread16(ioaddr + MID_0M);
1048 adrp[2] = ioread16(ioaddr + MID_0H);
1049
1050 /* Link new device into r6040_root_dev */
1051 lp->pdev = pdev;
1052
1053 /* Init RDC private data */
1054 lp->mcr0 = 0x1002;
1055 lp->phy_addr = phy_table[card_idx];
1056 lp->switch_sig = 0;
1057
1058 /* The RDC-specific entries in the device structure. */
1059 dev->open = &r6040_open;
1060 dev->hard_start_xmit = &r6040_start_xmit;
1061 dev->stop = &r6040_close;
1062 dev->get_stats = r6040_get_stats;
1063 dev->set_multicast_list = &r6040_multicast_list;
1064 dev->do_ioctl = &r6040_ioctl;
1065 dev->ethtool_ops = &netdev_ethtool_ops;
1066 dev->tx_timeout = &r6040_tx_timeout;
1067 dev->watchdog_timeo = TX_TIMEOUT;
1068 #ifdef CONFIG_NET_POLL_CONTROLLER
1069 dev->poll_controller = r6040_poll_controller;
1070 #endif
1071 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1072 lp->mii_if.dev = dev;
1073 lp->mii_if.mdio_read = mdio_read;
1074 lp->mii_if.mdio_write = mdio_write;
1075 lp->mii_if.phy_id = lp->phy_addr;
1076 lp->mii_if.phy_id_mask = 0x1f;
1077 lp->mii_if.reg_num_mask = 0x1f;
1078
1079 /* Register net device. After this dev->name assign */
1080 err = register_netdev(dev);
1081 if (err) {
1082 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1083 goto err_out_res;
1084 }
1085 return 0;
1086
1087 err_out_res:
1088 pci_release_regions(pdev);
1089 err_out_disable:
1090 pci_disable_device(pdev);
1091 pci_set_drvdata(pdev, NULL);
1092 free_netdev(dev);
1093
1094 return err;
1095 }
1096
1097 static void __devexit r6040_remove_one(struct pci_dev *pdev)
1098 {
1099 struct net_device *dev = pci_get_drvdata(pdev);
1100
1101 unregister_netdev(dev);
1102 pci_release_regions(pdev);
1103 free_netdev(dev);
1104 pci_disable_device(pdev);
1105 pci_set_drvdata(pdev, NULL);
1106 }
1107
1108
1109 static struct pci_device_id r6040_pci_tbl[] = {
1110 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1111 { 0 }
1112 };
1113 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1114
1115 static struct pci_driver r6040_driver = {
1116 .name = DRV_NAME,
1117 .id_table = r6040_pci_tbl,
1118 .probe = r6040_init_one,
1119 .remove = __devexit_p(r6040_remove_one),
1120 };
1121
1122
1123 static int __init r6040_init(void)
1124 {
1125 return pci_register_driver(&r6040_driver);
1126 }
1127
1128
1129 static void __exit r6040_cleanup(void)
1130 {
1131 pci_unregister_driver(&r6040_driver);
1132 }
1133
1134 module_init(r6040_init);
1135 module_exit(r6040_cleanup);
Support for the Chinese Samsung S3C2440 based development boards