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r8169: WakeOnLan fix for the 8168
[linux-2.6/mini2440.git] / drivers / net / gianfar.c
blobf8ffcbf0bc39551eac65f4f8cb969edf61908ee8
1 /*
2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
10 * Maintainer: Kumar Gala
11 *
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
27 *
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
77 #include <linux/mm.h>
78 #include <linux/of_mdio.h>
79 #include <linux/of_platform.h>
80 #include <linux/ip.h>
81 #include <linux/tcp.h>
82 #include <linux/udp.h>
83 #include <linux/in.h>
84
85 #include <asm/io.h>
86 #include <asm/irq.h>
87 #include <asm/uaccess.h>
88 #include <linux/module.h>
89 #include <linux/dma-mapping.h>
90 #include <linux/crc32.h>
91 #include <linux/mii.h>
92 #include <linux/phy.h>
93 #include <linux/phy_fixed.h>
94 #include <linux/of.h>
95
96 #include "gianfar.h"
97 #include "fsl_pq_mdio.h"
98
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
102
103 const char gfar_driver_name[] = "Gianfar Ethernet";
104 const char gfar_driver_version[] = "1.3";
105
106 static int gfar_enet_open(struct net_device *dev);
107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
108 static void gfar_reset_task(struct work_struct *work);
109 static void gfar_timeout(struct net_device *dev);
110 static int gfar_close(struct net_device *dev);
111 struct sk_buff *gfar_new_skb(struct net_device *dev);
112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
113 struct sk_buff *skb);
114 static int gfar_set_mac_address(struct net_device *dev);
115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
116 static irqreturn_t gfar_error(int irq, void *dev_id);
117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
119 static void adjust_link(struct net_device *dev);
120 static void init_registers(struct net_device *dev);
121 static int init_phy(struct net_device *dev);
122 static int gfar_probe(struct of_device *ofdev,
123 const struct of_device_id *match);
124 static int gfar_remove(struct of_device *ofdev);
125 static void free_skb_resources(struct gfar_private *priv);
126 static void gfar_set_multi(struct net_device *dev);
127 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
128 static void gfar_configure_serdes(struct net_device *dev);
129 static int gfar_poll(struct napi_struct *napi, int budget);
130 #ifdef CONFIG_NET_POLL_CONTROLLER
131 static void gfar_netpoll(struct net_device *dev);
132 #endif
133 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
134 static int gfar_clean_tx_ring(struct net_device *dev);
135 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
136 int amount_pull);
137 static void gfar_vlan_rx_register(struct net_device *netdev,
138 struct vlan_group *grp);
139 void gfar_halt(struct net_device *dev);
140 static void gfar_halt_nodisable(struct net_device *dev);
141 void gfar_start(struct net_device *dev);
142 static void gfar_clear_exact_match(struct net_device *dev);
143 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
145
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
149
150 static const struct net_device_ops gfar_netdev_ops = {
151 .ndo_open = gfar_enet_open,
152 .ndo_start_xmit = gfar_start_xmit,
153 .ndo_stop = gfar_close,
154 .ndo_change_mtu = gfar_change_mtu,
155 .ndo_set_multicast_list = gfar_set_multi,
156 .ndo_tx_timeout = gfar_timeout,
157 .ndo_do_ioctl = gfar_ioctl,
158 .ndo_vlan_rx_register = gfar_vlan_rx_register,
159 .ndo_set_mac_address = eth_mac_addr,
160 .ndo_validate_addr = eth_validate_addr,
161 #ifdef CONFIG_NET_POLL_CONTROLLER
162 .ndo_poll_controller = gfar_netpoll,
163 #endif
164 };
165
166 /* Returns 1 if incoming frames use an FCB */
167 static inline int gfar_uses_fcb(struct gfar_private *priv)
168 {
169 return priv->vlgrp || priv->rx_csum_enable;
170 }
171
172 static int gfar_of_init(struct net_device *dev)
173 {
174 const char *model;
175 const char *ctype;
176 const void *mac_addr;
177 u64 addr, size;
178 int err = 0;
179 struct gfar_private *priv = netdev_priv(dev);
180 struct device_node *np = priv->node;
181 const u32 *stash;
182 const u32 *stash_len;
183 const u32 *stash_idx;
184
185 if (!np || !of_device_is_available(np))
186 return -ENODEV;
187
188 /* get a pointer to the register memory */
189 addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
190 priv->regs = ioremap(addr, size);
191
192 if (priv->regs == NULL)
193 return -ENOMEM;
194
195 priv->interruptTransmit = irq_of_parse_and_map(np, 0);
196
197 model = of_get_property(np, "model", NULL);
198
199 /* If we aren't the FEC we have multiple interrupts */
200 if (model && strcasecmp(model, "FEC")) {
201 priv->interruptReceive = irq_of_parse_and_map(np, 1);
202
203 priv->interruptError = irq_of_parse_and_map(np, 2);
204
205 if (priv->interruptTransmit < 0 ||
206 priv->interruptReceive < 0 ||
207 priv->interruptError < 0) {
208 err = -EINVAL;
209 goto err_out;
210 }
211 }
212
213 stash = of_get_property(np, "bd-stash", NULL);
214
215 if(stash) {
216 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
217 priv->bd_stash_en = 1;
218 }
219
220 stash_len = of_get_property(np, "rx-stash-len", NULL);
221
222 if (stash_len)
223 priv->rx_stash_size = *stash_len;
224
225 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
226
227 if (stash_idx)
228 priv->rx_stash_index = *stash_idx;
229
230 if (stash_len || stash_idx)
231 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
232
233 mac_addr = of_get_mac_address(np);
234 if (mac_addr)
235 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
236
237 if (model && !strcasecmp(model, "TSEC"))
238 priv->device_flags =
239 FSL_GIANFAR_DEV_HAS_GIGABIT |
240 FSL_GIANFAR_DEV_HAS_COALESCE |
241 FSL_GIANFAR_DEV_HAS_RMON |
242 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
243 if (model && !strcasecmp(model, "eTSEC"))
244 priv->device_flags =
245 FSL_GIANFAR_DEV_HAS_GIGABIT |
246 FSL_GIANFAR_DEV_HAS_COALESCE |
247 FSL_GIANFAR_DEV_HAS_RMON |
248 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
249 FSL_GIANFAR_DEV_HAS_PADDING |
250 FSL_GIANFAR_DEV_HAS_CSUM |
251 FSL_GIANFAR_DEV_HAS_VLAN |
252 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
253 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
254
255 ctype = of_get_property(np, "phy-connection-type", NULL);
256
257 /* We only care about rgmii-id. The rest are autodetected */
258 if (ctype && !strcmp(ctype, "rgmii-id"))
259 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
260 else
261 priv->interface = PHY_INTERFACE_MODE_MII;
262
263 if (of_get_property(np, "fsl,magic-packet", NULL))
264 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
265
266 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
267
268 /* Find the TBI PHY. If it's not there, we don't support SGMII */
269 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
270
271 return 0;
272
273 err_out:
274 iounmap(priv->regs);
275 return err;
276 }
277
278 /* Ioctl MII Interface */
279 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
280 {
281 struct gfar_private *priv = netdev_priv(dev);
282
283 if (!netif_running(dev))
284 return -EINVAL;
285
286 if (!priv->phydev)
287 return -ENODEV;
288
289 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
290 }
291
292 /* Set up the ethernet device structure, private data,
293 * and anything else we need before we start */
294 static int gfar_probe(struct of_device *ofdev,
295 const struct of_device_id *match)
296 {
297 u32 tempval;
298 struct net_device *dev = NULL;
299 struct gfar_private *priv = NULL;
300 DECLARE_MAC_BUF(mac);
301 int err = 0;
302 int len_devname;
303
304 /* Create an ethernet device instance */
305 dev = alloc_etherdev(sizeof (*priv));
306
307 if (NULL == dev)
308 return -ENOMEM;
309
310 priv = netdev_priv(dev);
311 priv->ndev = dev;
312 priv->ofdev = ofdev;
313 priv->node = ofdev->node;
314 SET_NETDEV_DEV(dev, &ofdev->dev);
315
316 err = gfar_of_init(dev);
317
318 if (err)
319 goto regs_fail;
320
321 spin_lock_init(&priv->txlock);
322 spin_lock_init(&priv->rxlock);
323 spin_lock_init(&priv->bflock);
324 INIT_WORK(&priv->reset_task, gfar_reset_task);
325
326 dev_set_drvdata(&ofdev->dev, priv);
327
328 /* Stop the DMA engine now, in case it was running before */
329 /* (The firmware could have used it, and left it running). */
330 gfar_halt(dev);
331
332 /* Reset MAC layer */
333 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
334
335 /* We need to delay at least 3 TX clocks */
336 udelay(2);
337
338 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
339 gfar_write(&priv->regs->maccfg1, tempval);
340
341 /* Initialize MACCFG2. */
342 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
343
344 /* Initialize ECNTRL */
345 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
346
347 /* Set the dev->base_addr to the gfar reg region */
348 dev->base_addr = (unsigned long) (priv->regs);
349
350 SET_NETDEV_DEV(dev, &ofdev->dev);
351
352 /* Fill in the dev structure */
353 dev->watchdog_timeo = TX_TIMEOUT;
354 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
355 dev->mtu = 1500;
356
357 dev->netdev_ops = &gfar_netdev_ops;
358 dev->ethtool_ops = &gfar_ethtool_ops;
359
360 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
361 priv->rx_csum_enable = 1;
362 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
363 } else
364 priv->rx_csum_enable = 0;
365
366 priv->vlgrp = NULL;
367
368 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
369 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
370
371 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
372 priv->extended_hash = 1;
373 priv->hash_width = 9;
374
375 priv->hash_regs[0] = &priv->regs->igaddr0;
376 priv->hash_regs[1] = &priv->regs->igaddr1;
377 priv->hash_regs[2] = &priv->regs->igaddr2;
378 priv->hash_regs[3] = &priv->regs->igaddr3;
379 priv->hash_regs[4] = &priv->regs->igaddr4;
380 priv->hash_regs[5] = &priv->regs->igaddr5;
381 priv->hash_regs[6] = &priv->regs->igaddr6;
382 priv->hash_regs[7] = &priv->regs->igaddr7;
383 priv->hash_regs[8] = &priv->regs->gaddr0;
384 priv->hash_regs[9] = &priv->regs->gaddr1;
385 priv->hash_regs[10] = &priv->regs->gaddr2;
386 priv->hash_regs[11] = &priv->regs->gaddr3;
387 priv->hash_regs[12] = &priv->regs->gaddr4;
388 priv->hash_regs[13] = &priv->regs->gaddr5;
389 priv->hash_regs[14] = &priv->regs->gaddr6;
390 priv->hash_regs[15] = &priv->regs->gaddr7;
391
392 } else {
393 priv->extended_hash = 0;
394 priv->hash_width = 8;
395
396 priv->hash_regs[0] = &priv->regs->gaddr0;
397 priv->hash_regs[1] = &priv->regs->gaddr1;
398 priv->hash_regs[2] = &priv->regs->gaddr2;
399 priv->hash_regs[3] = &priv->regs->gaddr3;
400 priv->hash_regs[4] = &priv->regs->gaddr4;
401 priv->hash_regs[5] = &priv->regs->gaddr5;
402 priv->hash_regs[6] = &priv->regs->gaddr6;
403 priv->hash_regs[7] = &priv->regs->gaddr7;
404 }
405
406 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
407 priv->padding = DEFAULT_PADDING;
408 else
409 priv->padding = 0;
410
411 if (dev->features & NETIF_F_IP_CSUM)
412 dev->hard_header_len += GMAC_FCB_LEN;
413
414 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
415 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
416 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
417 priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
418
419 priv->txcoalescing = DEFAULT_TX_COALESCE;
420 priv->txic = DEFAULT_TXIC;
421 priv->rxcoalescing = DEFAULT_RX_COALESCE;
422 priv->rxic = DEFAULT_RXIC;
423
424 /* Enable most messages by default */
425 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
426
427 /* Carrier starts down, phylib will bring it up */
428 netif_carrier_off(dev);
429
430 err = register_netdev(dev);
431
432 if (err) {
433 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
434 dev->name);
435 goto register_fail;
436 }
437
438 device_init_wakeup(&dev->dev,
439 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
440
441 /* fill out IRQ number and name fields */
442 len_devname = strlen(dev->name);
443 strncpy(&priv->int_name_tx[0], dev->name, len_devname);
444 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
445 strncpy(&priv->int_name_tx[len_devname],
446 "_tx", sizeof("_tx") + 1);
447
448 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
449 strncpy(&priv->int_name_rx[len_devname],
450 "_rx", sizeof("_rx") + 1);
451
452 strncpy(&priv->int_name_er[0], dev->name, len_devname);
453 strncpy(&priv->int_name_er[len_devname],
454 "_er", sizeof("_er") + 1);
455 } else
456 priv->int_name_tx[len_devname] = '\0';
457
458 /* Create all the sysfs files */
459 gfar_init_sysfs(dev);
460
461 /* Print out the device info */
462 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
463
464 /* Even more device info helps when determining which kernel */
465 /* provided which set of benchmarks. */
466 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
467 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
468 dev->name, priv->rx_ring_size, priv->tx_ring_size);
469
470 return 0;
471
472 register_fail:
473 iounmap(priv->regs);
474 regs_fail:
475 if (priv->phy_node)
476 of_node_put(priv->phy_node);
477 if (priv->tbi_node)
478 of_node_put(priv->tbi_node);
479 free_netdev(dev);
480 return err;
481 }
482
483 static int gfar_remove(struct of_device *ofdev)
484 {
485 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
486
487 if (priv->phy_node)
488 of_node_put(priv->phy_node);
489 if (priv->tbi_node)
490 of_node_put(priv->tbi_node);
491
492 dev_set_drvdata(&ofdev->dev, NULL);
493
494 iounmap(priv->regs);
495 free_netdev(priv->ndev);
496
497 return 0;
498 }
499
500 #ifdef CONFIG_PM
501 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
502 {
503 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
504 struct net_device *dev = priv->ndev;
505 unsigned long flags;
506 u32 tempval;
507
508 int magic_packet = priv->wol_en &&
509 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
510
511 netif_device_detach(dev);
512
513 if (netif_running(dev)) {
514 spin_lock_irqsave(&priv->txlock, flags);
515 spin_lock(&priv->rxlock);
516
517 gfar_halt_nodisable(dev);
518
519 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
520 tempval = gfar_read(&priv->regs->maccfg1);
521
522 tempval &= ~MACCFG1_TX_EN;
523
524 if (!magic_packet)
525 tempval &= ~MACCFG1_RX_EN;
526
527 gfar_write(&priv->regs->maccfg1, tempval);
528
529 spin_unlock(&priv->rxlock);
530 spin_unlock_irqrestore(&priv->txlock, flags);
531
532 napi_disable(&priv->napi);
533
534 if (magic_packet) {
535 /* Enable interrupt on Magic Packet */
536 gfar_write(&priv->regs->imask, IMASK_MAG);
537
538 /* Enable Magic Packet mode */
539 tempval = gfar_read(&priv->regs->maccfg2);
540 tempval |= MACCFG2_MPEN;
541 gfar_write(&priv->regs->maccfg2, tempval);
542 } else {
543 phy_stop(priv->phydev);
544 }
545 }
546
547 return 0;
548 }
549
550 static int gfar_resume(struct of_device *ofdev)
551 {
552 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
553 struct net_device *dev = priv->ndev;
554 unsigned long flags;
555 u32 tempval;
556 int magic_packet = priv->wol_en &&
557 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
558
559 if (!netif_running(dev)) {
560 netif_device_attach(dev);
561 return 0;
562 }
563
564 if (!magic_packet && priv->phydev)
565 phy_start(priv->phydev);
566
567 /* Disable Magic Packet mode, in case something
568 * else woke us up.
569 */
570
571 spin_lock_irqsave(&priv->txlock, flags);
572 spin_lock(&priv->rxlock);
573
574 tempval = gfar_read(&priv->regs->maccfg2);
575 tempval &= ~MACCFG2_MPEN;
576 gfar_write(&priv->regs->maccfg2, tempval);
577
578 gfar_start(dev);
579
580 spin_unlock(&priv->rxlock);
581 spin_unlock_irqrestore(&priv->txlock, flags);
582
583 netif_device_attach(dev);
584
585 napi_enable(&priv->napi);
586
587 return 0;
588 }
589 #else
590 #define gfar_suspend NULL
591 #define gfar_resume NULL
592 #endif
593
594 /* Reads the controller's registers to determine what interface
595 * connects it to the PHY.
596 */
597 static phy_interface_t gfar_get_interface(struct net_device *dev)
598 {
599 struct gfar_private *priv = netdev_priv(dev);
600 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
601
602 if (ecntrl & ECNTRL_SGMII_MODE)
603 return PHY_INTERFACE_MODE_SGMII;
604
605 if (ecntrl & ECNTRL_TBI_MODE) {
606 if (ecntrl & ECNTRL_REDUCED_MODE)
607 return PHY_INTERFACE_MODE_RTBI;
608 else
609 return PHY_INTERFACE_MODE_TBI;
610 }
611
612 if (ecntrl & ECNTRL_REDUCED_MODE) {
613 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
614 return PHY_INTERFACE_MODE_RMII;
615 else {
616 phy_interface_t interface = priv->interface;
617
618 /*
619 * This isn't autodetected right now, so it must
620 * be set by the device tree or platform code.
621 */
622 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
623 return PHY_INTERFACE_MODE_RGMII_ID;
624
625 return PHY_INTERFACE_MODE_RGMII;
626 }
627 }
628
629 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
630 return PHY_INTERFACE_MODE_GMII;
631
632 return PHY_INTERFACE_MODE_MII;
633 }
634
635
636 /* Initializes driver's PHY state, and attaches to the PHY.
637 * Returns 0 on success.
638 */
639 static int init_phy(struct net_device *dev)
640 {
641 struct gfar_private *priv = netdev_priv(dev);
642 uint gigabit_support =
643 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
644 SUPPORTED_1000baseT_Full : 0;
645 phy_interface_t interface;
646
647 priv->oldlink = 0;
648 priv->oldspeed = 0;
649 priv->oldduplex = -1;
650
651 interface = gfar_get_interface(dev);
652
653 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
654 interface);
655 if (!priv->phydev)
656 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
657 interface);
658 if (!priv->phydev) {
659 dev_err(&dev->dev, "could not attach to PHY\n");
660 return -ENODEV;
661 }
662
663 if (interface == PHY_INTERFACE_MODE_SGMII)
664 gfar_configure_serdes(dev);
665
666 /* Remove any features not supported by the controller */
667 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
668 priv->phydev->advertising = priv->phydev->supported;
669
670 return 0;
671 }
672
673 /*
674 * Initialize TBI PHY interface for communicating with the
675 * SERDES lynx PHY on the chip. We communicate with this PHY
676 * through the MDIO bus on each controller, treating it as a
677 * "normal" PHY at the address found in the TBIPA register. We assume
678 * that the TBIPA register is valid. Either the MDIO bus code will set
679 * it to a value that doesn't conflict with other PHYs on the bus, or the
680 * value doesn't matter, as there are no other PHYs on the bus.
681 */
682 static void gfar_configure_serdes(struct net_device *dev)
683 {
684 struct gfar_private *priv = netdev_priv(dev);
685 struct phy_device *tbiphy;
686
687 if (!priv->tbi_node) {
688 dev_warn(&dev->dev, "error: SGMII mode requires that the "
689 "device tree specify a tbi-handle\n");
690 return;
691 }
692
693 tbiphy = of_phy_find_device(priv->tbi_node);
694 if (!tbiphy) {
695 dev_err(&dev->dev, "error: Could not get TBI device\n");
696 return;
697 }
698
699 /*
700 * If the link is already up, we must already be ok, and don't need to
701 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
702 * everything for us? Resetting it takes the link down and requires
703 * several seconds for it to come back.
704 */
705 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
706 return;
707
708 /* Single clk mode, mii mode off(for serdes communication) */
709 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
710
711 phy_write(tbiphy, MII_ADVERTISE,
712 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
713 ADVERTISE_1000XPSE_ASYM);
714
715 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
716 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
717 }
718
719 static void init_registers(struct net_device *dev)
720 {
721 struct gfar_private *priv = netdev_priv(dev);
722
723 /* Clear IEVENT */
724 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
725
726 /* Initialize IMASK */
727 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
728
729 /* Init hash registers to zero */
730 gfar_write(&priv->regs->igaddr0, 0);
731 gfar_write(&priv->regs->igaddr1, 0);
732 gfar_write(&priv->regs->igaddr2, 0);
733 gfar_write(&priv->regs->igaddr3, 0);
734 gfar_write(&priv->regs->igaddr4, 0);
735 gfar_write(&priv->regs->igaddr5, 0);
736 gfar_write(&priv->regs->igaddr6, 0);
737 gfar_write(&priv->regs->igaddr7, 0);
738
739 gfar_write(&priv->regs->gaddr0, 0);
740 gfar_write(&priv->regs->gaddr1, 0);
741 gfar_write(&priv->regs->gaddr2, 0);
742 gfar_write(&priv->regs->gaddr3, 0);
743 gfar_write(&priv->regs->gaddr4, 0);
744 gfar_write(&priv->regs->gaddr5, 0);
745 gfar_write(&priv->regs->gaddr6, 0);
746 gfar_write(&priv->regs->gaddr7, 0);
747
748 /* Zero out the rmon mib registers if it has them */
749 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
750 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
751
752 /* Mask off the CAM interrupts */
753 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
754 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
755 }
756
757 /* Initialize the max receive buffer length */
758 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
759
760 /* Initialize the Minimum Frame Length Register */
761 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
762 }
763
764
765 /* Halt the receive and transmit queues */
766 static void gfar_halt_nodisable(struct net_device *dev)
767 {
768 struct gfar_private *priv = netdev_priv(dev);
769 struct gfar __iomem *regs = priv->regs;
770 u32 tempval;
771
772 /* Mask all interrupts */
773 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
774
775 /* Clear all interrupts */
776 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
777
778 /* Stop the DMA, and wait for it to stop */
779 tempval = gfar_read(&priv->regs->dmactrl);
780 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
781 != (DMACTRL_GRS | DMACTRL_GTS)) {
782 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
783 gfar_write(&priv->regs->dmactrl, tempval);
784
785 while (!(gfar_read(&priv->regs->ievent) &
786 (IEVENT_GRSC | IEVENT_GTSC)))
787 cpu_relax();
788 }
789 }
790
791 /* Halt the receive and transmit queues */
792 void gfar_halt(struct net_device *dev)
793 {
794 struct gfar_private *priv = netdev_priv(dev);
795 struct gfar __iomem *regs = priv->regs;
796 u32 tempval;
797
798 gfar_halt_nodisable(dev);
799
800 /* Disable Rx and Tx */
801 tempval = gfar_read(&regs->maccfg1);
802 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
803 gfar_write(&regs->maccfg1, tempval);
804 }
805
806 void stop_gfar(struct net_device *dev)
807 {
808 struct gfar_private *priv = netdev_priv(dev);
809 struct gfar __iomem *regs = priv->regs;
810 unsigned long flags;
811
812 phy_stop(priv->phydev);
813
814 /* Lock it down */
815 spin_lock_irqsave(&priv->txlock, flags);
816 spin_lock(&priv->rxlock);
817
818 gfar_halt(dev);
819
820 spin_unlock(&priv->rxlock);
821 spin_unlock_irqrestore(&priv->txlock, flags);
822
823 /* Free the IRQs */
824 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
825 free_irq(priv->interruptError, dev);
826 free_irq(priv->interruptTransmit, dev);
827 free_irq(priv->interruptReceive, dev);
828 } else {
829 free_irq(priv->interruptTransmit, dev);
830 }
831
832 free_skb_resources(priv);
833
834 dma_free_coherent(&priv->ofdev->dev,
835 sizeof(struct txbd8)*priv->tx_ring_size
836 + sizeof(struct rxbd8)*priv->rx_ring_size,
837 priv->tx_bd_base,
838 gfar_read(&regs->tbase0));
839 }
840
841 /* If there are any tx skbs or rx skbs still around, free them.
842 * Then free tx_skbuff and rx_skbuff */
843 static void free_skb_resources(struct gfar_private *priv)
844 {
845 struct rxbd8 *rxbdp;
846 struct txbd8 *txbdp;
847 int i, j;
848
849 /* Go through all the buffer descriptors and free their data buffers */
850 txbdp = priv->tx_bd_base;
851
852 for (i = 0; i < priv->tx_ring_size; i++) {
853 if (!priv->tx_skbuff[i])
854 continue;
855
856 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
857 txbdp->length, DMA_TO_DEVICE);
858 txbdp->lstatus = 0;
859 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
860 txbdp++;
861 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
862 txbdp->length, DMA_TO_DEVICE);
863 }
864 txbdp++;
865 dev_kfree_skb_any(priv->tx_skbuff[i]);
866 priv->tx_skbuff[i] = NULL;
867 }
868
869 kfree(priv->tx_skbuff);
870
871 rxbdp = priv->rx_bd_base;
872
873 /* rx_skbuff is not guaranteed to be allocated, so only
874 * free it and its contents if it is allocated */
875 if(priv->rx_skbuff != NULL) {
876 for (i = 0; i < priv->rx_ring_size; i++) {
877 if (priv->rx_skbuff[i]) {
878 dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
879 priv->rx_buffer_size,
880 DMA_FROM_DEVICE);
881
882 dev_kfree_skb_any(priv->rx_skbuff[i]);
883 priv->rx_skbuff[i] = NULL;
884 }
885
886 rxbdp->lstatus = 0;
887 rxbdp->bufPtr = 0;
888
889 rxbdp++;
890 }
891
892 kfree(priv->rx_skbuff);
893 }
894 }
895
896 void gfar_start(struct net_device *dev)
897 {
898 struct gfar_private *priv = netdev_priv(dev);
899 struct gfar __iomem *regs = priv->regs;
900 u32 tempval;
901
902 /* Enable Rx and Tx in MACCFG1 */
903 tempval = gfar_read(&regs->maccfg1);
904 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
905 gfar_write(&regs->maccfg1, tempval);
906
907 /* Initialize DMACTRL to have WWR and WOP */
908 tempval = gfar_read(&priv->regs->dmactrl);
909 tempval |= DMACTRL_INIT_SETTINGS;
910 gfar_write(&priv->regs->dmactrl, tempval);
911
912 /* Make sure we aren't stopped */
913 tempval = gfar_read(&priv->regs->dmactrl);
914 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
915 gfar_write(&priv->regs->dmactrl, tempval);
916
917 /* Clear THLT/RHLT, so that the DMA starts polling now */
918 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
919 gfar_write(&regs->rstat, RSTAT_CLEAR_RHALT);
920
921 /* Unmask the interrupts we look for */
922 gfar_write(&regs->imask, IMASK_DEFAULT);
923
924 dev->trans_start = jiffies;
925 }
926
927 /* Bring the controller up and running */
928 int startup_gfar(struct net_device *dev)
929 {
930 struct txbd8 *txbdp;
931 struct rxbd8 *rxbdp;
932 dma_addr_t addr = 0;
933 unsigned long vaddr;
934 int i;
935 struct gfar_private *priv = netdev_priv(dev);
936 struct gfar __iomem *regs = priv->regs;
937 int err = 0;
938 u32 rctrl = 0;
939 u32 attrs = 0;
940
941 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
942
943 /* Allocate memory for the buffer descriptors */
944 vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev,
945 sizeof (struct txbd8) * priv->tx_ring_size +
946 sizeof (struct rxbd8) * priv->rx_ring_size,
947 &addr, GFP_KERNEL);
948
949 if (vaddr == 0) {
950 if (netif_msg_ifup(priv))
951 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
952 dev->name);
953 return -ENOMEM;
954 }
955
956 priv->tx_bd_base = (struct txbd8 *) vaddr;
957
958 /* enet DMA only understands physical addresses */
959 gfar_write(&regs->tbase0, addr);
960
961 /* Start the rx descriptor ring where the tx ring leaves off */
962 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
963 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
964 priv->rx_bd_base = (struct rxbd8 *) vaddr;
965 gfar_write(&regs->rbase0, addr);
966
967 /* Setup the skbuff rings */
968 priv->tx_skbuff =
969 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
970 priv->tx_ring_size, GFP_KERNEL);
971
972 if (NULL == priv->tx_skbuff) {
973 if (netif_msg_ifup(priv))
974 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
975 dev->name);
976 err = -ENOMEM;
977 goto tx_skb_fail;
978 }
979
980 for (i = 0; i < priv->tx_ring_size; i++)
981 priv->tx_skbuff[i] = NULL;
982
983 priv->rx_skbuff =
984 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
985 priv->rx_ring_size, GFP_KERNEL);
986
987 if (NULL == priv->rx_skbuff) {
988 if (netif_msg_ifup(priv))
989 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
990 dev->name);
991 err = -ENOMEM;
992 goto rx_skb_fail;
993 }
994
995 for (i = 0; i < priv->rx_ring_size; i++)
996 priv->rx_skbuff[i] = NULL;
997
998 /* Initialize some variables in our dev structure */
999 priv->num_txbdfree = priv->tx_ring_size;
1000 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
1001 priv->cur_rx = priv->rx_bd_base;
1002 priv->skb_curtx = priv->skb_dirtytx = 0;
1003 priv->skb_currx = 0;
1004
1005 /* Initialize Transmit Descriptor Ring */
1006 txbdp = priv->tx_bd_base;
1007 for (i = 0; i < priv->tx_ring_size; i++) {
1008 txbdp->lstatus = 0;
1009 txbdp->bufPtr = 0;
1010 txbdp++;
1011 }
1012
1013 /* Set the last descriptor in the ring to indicate wrap */
1014 txbdp--;
1015 txbdp->status |= TXBD_WRAP;
1016
1017 rxbdp = priv->rx_bd_base;
1018 for (i = 0; i < priv->rx_ring_size; i++) {
1019 struct sk_buff *skb;
1020
1021 skb = gfar_new_skb(dev);
1022
1023 if (!skb) {
1024 printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1025 dev->name);
1026
1027 goto err_rxalloc_fail;
1028 }
1029
1030 priv->rx_skbuff[i] = skb;
1031
1032 gfar_new_rxbdp(dev, rxbdp, skb);
1033
1034 rxbdp++;
1035 }
1036
1037 /* Set the last descriptor in the ring to wrap */
1038 rxbdp--;
1039 rxbdp->status |= RXBD_WRAP;
1040
1041 /* If the device has multiple interrupts, register for
1042 * them. Otherwise, only register for the one */
1043 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1044 /* Install our interrupt handlers for Error,
1045 * Transmit, and Receive */
1046 if (request_irq(priv->interruptError, gfar_error,
1047 0, priv->int_name_er, dev) < 0) {
1048 if (netif_msg_intr(priv))
1049 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1050 dev->name, priv->interruptError);
1051
1052 err = -1;
1053 goto err_irq_fail;
1054 }
1055
1056 if (request_irq(priv->interruptTransmit, gfar_transmit,
1057 0, priv->int_name_tx, dev) < 0) {
1058 if (netif_msg_intr(priv))
1059 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1060 dev->name, priv->interruptTransmit);
1061
1062 err = -1;
1063
1064 goto tx_irq_fail;
1065 }
1066
1067 if (request_irq(priv->interruptReceive, gfar_receive,
1068 0, priv->int_name_rx, dev) < 0) {
1069 if (netif_msg_intr(priv))
1070 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1071 dev->name, priv->interruptReceive);
1072
1073 err = -1;
1074 goto rx_irq_fail;
1075 }
1076 } else {
1077 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1078 0, priv->int_name_tx, dev) < 0) {
1079 if (netif_msg_intr(priv))
1080 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1081 dev->name, priv->interruptTransmit);
1082
1083 err = -1;
1084 goto err_irq_fail;
1085 }
1086 }
1087
1088 phy_start(priv->phydev);
1089
1090 /* Configure the coalescing support */
1091 gfar_write(&regs->txic, 0);
1092 if (priv->txcoalescing)
1093 gfar_write(&regs->txic, priv->txic);
1094
1095 gfar_write(&regs->rxic, 0);
1096 if (priv->rxcoalescing)
1097 gfar_write(&regs->rxic, priv->rxic);
1098
1099 if (priv->rx_csum_enable)
1100 rctrl |= RCTRL_CHECKSUMMING;
1101
1102 if (priv->extended_hash) {
1103 rctrl |= RCTRL_EXTHASH;
1104
1105 gfar_clear_exact_match(dev);
1106 rctrl |= RCTRL_EMEN;
1107 }
1108
1109 if (priv->padding) {
1110 rctrl &= ~RCTRL_PAL_MASK;
1111 rctrl |= RCTRL_PADDING(priv->padding);
1112 }
1113
1114 /* Init rctrl based on our settings */
1115 gfar_write(&priv->regs->rctrl, rctrl);
1116
1117 if (dev->features & NETIF_F_IP_CSUM)
1118 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1119
1120 /* Set the extraction length and index */
1121 attrs = ATTRELI_EL(priv->rx_stash_size) |
1122 ATTRELI_EI(priv->rx_stash_index);
1123
1124 gfar_write(&priv->regs->attreli, attrs);
1125
1126 /* Start with defaults, and add stashing or locking
1127 * depending on the approprate variables */
1128 attrs = ATTR_INIT_SETTINGS;
1129
1130 if (priv->bd_stash_en)
1131 attrs |= ATTR_BDSTASH;
1132
1133 if (priv->rx_stash_size != 0)
1134 attrs |= ATTR_BUFSTASH;
1135
1136 gfar_write(&priv->regs->attr, attrs);
1137
1138 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1139 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1140 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1141
1142 /* Start the controller */
1143 gfar_start(dev);
1144
1145 return 0;
1146
1147 rx_irq_fail:
1148 free_irq(priv->interruptTransmit, dev);
1149 tx_irq_fail:
1150 free_irq(priv->interruptError, dev);
1151 err_irq_fail:
1152 err_rxalloc_fail:
1153 rx_skb_fail:
1154 free_skb_resources(priv);
1155 tx_skb_fail:
1156 dma_free_coherent(&priv->ofdev->dev,
1157 sizeof(struct txbd8)*priv->tx_ring_size
1158 + sizeof(struct rxbd8)*priv->rx_ring_size,
1159 priv->tx_bd_base,
1160 gfar_read(&regs->tbase0));
1161
1162 return err;
1163 }
1164
1165 /* Called when something needs to use the ethernet device */
1166 /* Returns 0 for success. */
1167 static int gfar_enet_open(struct net_device *dev)
1168 {
1169 struct gfar_private *priv = netdev_priv(dev);
1170 int err;
1171
1172 napi_enable(&priv->napi);
1173
1174 skb_queue_head_init(&priv->rx_recycle);
1175
1176 /* Initialize a bunch of registers */
1177 init_registers(dev);
1178
1179 gfar_set_mac_address(dev);
1180
1181 err = init_phy(dev);
1182
1183 if(err) {
1184 napi_disable(&priv->napi);
1185 return err;
1186 }
1187
1188 err = startup_gfar(dev);
1189 if (err) {
1190 napi_disable(&priv->napi);
1191 return err;
1192 }
1193
1194 netif_start_queue(dev);
1195
1196 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1197
1198 return err;
1199 }
1200
1201 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1202 {
1203 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1204
1205 memset(fcb, 0, GMAC_FCB_LEN);
1206
1207 return fcb;
1208 }
1209
1210 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1211 {
1212 u8 flags = 0;
1213
1214 /* If we're here, it's a IP packet with a TCP or UDP
1215 * payload. We set it to checksum, using a pseudo-header
1216 * we provide
1217 */
1218 flags = TXFCB_DEFAULT;
1219
1220 /* Tell the controller what the protocol is */
1221 /* And provide the already calculated phcs */
1222 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1223 flags |= TXFCB_UDP;
1224 fcb->phcs = udp_hdr(skb)->check;
1225 } else
1226 fcb->phcs = tcp_hdr(skb)->check;
1227
1228 /* l3os is the distance between the start of the
1229 * frame (skb->data) and the start of the IP hdr.
1230 * l4os is the distance between the start of the
1231 * l3 hdr and the l4 hdr */
1232 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1233 fcb->l4os = skb_network_header_len(skb);
1234
1235 fcb->flags = flags;
1236 }
1237
1238 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1239 {
1240 fcb->flags |= TXFCB_VLN;
1241 fcb->vlctl = vlan_tx_tag_get(skb);
1242 }
1243
1244 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1245 struct txbd8 *base, int ring_size)
1246 {
1247 struct txbd8 *new_bd = bdp + stride;
1248
1249 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1250 }
1251
1252 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1253 int ring_size)
1254 {
1255 return skip_txbd(bdp, 1, base, ring_size);
1256 }
1257
1258 /* This is called by the kernel when a frame is ready for transmission. */
1259 /* It is pointed to by the dev->hard_start_xmit function pointer */
1260 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1261 {
1262 struct gfar_private *priv = netdev_priv(dev);
1263 struct txfcb *fcb = NULL;
1264 struct txbd8 *txbdp, *txbdp_start, *base;
1265 u32 lstatus;
1266 int i;
1267 u32 bufaddr;
1268 unsigned long flags;
1269 unsigned int nr_frags, length;
1270
1271 base = priv->tx_bd_base;
1272
1273 /* make space for additional header when fcb is needed */
1274 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1275 (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1276 (skb_headroom(skb) < GMAC_FCB_LEN)) {
1277 struct sk_buff *skb_new;
1278
1279 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1280 if (!skb_new) {
1281 dev->stats.tx_errors++;
1282 kfree_skb(skb);
1283 return NETDEV_TX_OK;
1284 }
1285 kfree_skb(skb);
1286 skb = skb_new;
1287 }
1288
1289 /* total number of fragments in the SKB */
1290 nr_frags = skb_shinfo(skb)->nr_frags;
1291
1292 spin_lock_irqsave(&priv->txlock, flags);
1293
1294 /* check if there is space to queue this packet */
1295 if ((nr_frags+1) > priv->num_txbdfree) {
1296 /* no space, stop the queue */
1297 netif_stop_queue(dev);
1298 dev->stats.tx_fifo_errors++;
1299 spin_unlock_irqrestore(&priv->txlock, flags);
1300 return NETDEV_TX_BUSY;
1301 }
1302
1303 /* Update transmit stats */
1304 dev->stats.tx_bytes += skb->len;
1305
1306 txbdp = txbdp_start = priv->cur_tx;
1307
1308 if (nr_frags == 0) {
1309 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1310 } else {
1311 /* Place the fragment addresses and lengths into the TxBDs */
1312 for (i = 0; i < nr_frags; i++) {
1313 /* Point at the next BD, wrapping as needed */
1314 txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1315
1316 length = skb_shinfo(skb)->frags[i].size;
1317
1318 lstatus = txbdp->lstatus | length |
1319 BD_LFLAG(TXBD_READY);
1320
1321 /* Handle the last BD specially */
1322 if (i == nr_frags - 1)
1323 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1324
1325 bufaddr = dma_map_page(&priv->ofdev->dev,
1326 skb_shinfo(skb)->frags[i].page,
1327 skb_shinfo(skb)->frags[i].page_offset,
1328 length,
1329 DMA_TO_DEVICE);
1330
1331 /* set the TxBD length and buffer pointer */
1332 txbdp->bufPtr = bufaddr;
1333 txbdp->lstatus = lstatus;
1334 }
1335
1336 lstatus = txbdp_start->lstatus;
1337 }
1338
1339 /* Set up checksumming */
1340 if (CHECKSUM_PARTIAL == skb->ip_summed) {
1341 fcb = gfar_add_fcb(skb);
1342 lstatus |= BD_LFLAG(TXBD_TOE);
1343 gfar_tx_checksum(skb, fcb);
1344 }
1345
1346 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1347 if (unlikely(NULL == fcb)) {
1348 fcb = gfar_add_fcb(skb);
1349 lstatus |= BD_LFLAG(TXBD_TOE);
1350 }
1351
1352 gfar_tx_vlan(skb, fcb);
1353 }
1354
1355 /* setup the TxBD length and buffer pointer for the first BD */
1356 priv->tx_skbuff[priv->skb_curtx] = skb;
1357 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1358 skb_headlen(skb), DMA_TO_DEVICE);
1359
1360 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1361
1362 /*
1363 * The powerpc-specific eieio() is used, as wmb() has too strong
1364 * semantics (it requires synchronization between cacheable and
1365 * uncacheable mappings, which eieio doesn't provide and which we
1366 * don't need), thus requiring a more expensive sync instruction. At
1367 * some point, the set of architecture-independent barrier functions
1368 * should be expanded to include weaker barriers.
1369 */
1370 eieio();
1371
1372 txbdp_start->lstatus = lstatus;
1373
1374 /* Update the current skb pointer to the next entry we will use
1375 * (wrapping if necessary) */
1376 priv->skb_curtx = (priv->skb_curtx + 1) &
1377 TX_RING_MOD_MASK(priv->tx_ring_size);
1378
1379 priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1380
1381 /* reduce TxBD free count */
1382 priv->num_txbdfree -= (nr_frags + 1);
1383
1384 dev->trans_start = jiffies;
1385
1386 /* If the next BD still needs to be cleaned up, then the bds
1387 are full. We need to tell the kernel to stop sending us stuff. */
1388 if (!priv->num_txbdfree) {
1389 netif_stop_queue(dev);
1390
1391 dev->stats.tx_fifo_errors++;
1392 }
1393
1394 /* Tell the DMA to go go go */
1395 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1396
1397 /* Unlock priv */
1398 spin_unlock_irqrestore(&priv->txlock, flags);
1399
1400 return NETDEV_TX_OK;
1401 }
1402
1403 /* Stops the kernel queue, and halts the controller */
1404 static int gfar_close(struct net_device *dev)
1405 {
1406 struct gfar_private *priv = netdev_priv(dev);
1407
1408 napi_disable(&priv->napi);
1409
1410 skb_queue_purge(&priv->rx_recycle);
1411 cancel_work_sync(&priv->reset_task);
1412 stop_gfar(dev);
1413
1414 /* Disconnect from the PHY */
1415 phy_disconnect(priv->phydev);
1416 priv->phydev = NULL;
1417
1418 netif_stop_queue(dev);
1419
1420 return 0;
1421 }
1422
1423 /* Changes the mac address if the controller is not running. */
1424 static int gfar_set_mac_address(struct net_device *dev)
1425 {
1426 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1427
1428 return 0;
1429 }
1430
1431
1432 /* Enables and disables VLAN insertion/extraction */
1433 static void gfar_vlan_rx_register(struct net_device *dev,
1434 struct vlan_group *grp)
1435 {
1436 struct gfar_private *priv = netdev_priv(dev);
1437 unsigned long flags;
1438 u32 tempval;
1439
1440 spin_lock_irqsave(&priv->rxlock, flags);
1441
1442 priv->vlgrp = grp;
1443
1444 if (grp) {
1445 /* Enable VLAN tag insertion */
1446 tempval = gfar_read(&priv->regs->tctrl);
1447 tempval |= TCTRL_VLINS;
1448
1449 gfar_write(&priv->regs->tctrl, tempval);
1450
1451 /* Enable VLAN tag extraction */
1452 tempval = gfar_read(&priv->regs->rctrl);
1453 tempval |= RCTRL_VLEX;
1454 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1455 gfar_write(&priv->regs->rctrl, tempval);
1456 } else {
1457 /* Disable VLAN tag insertion */
1458 tempval = gfar_read(&priv->regs->tctrl);
1459 tempval &= ~TCTRL_VLINS;
1460 gfar_write(&priv->regs->tctrl, tempval);
1461
1462 /* Disable VLAN tag extraction */
1463 tempval = gfar_read(&priv->regs->rctrl);
1464 tempval &= ~RCTRL_VLEX;
1465 /* If parse is no longer required, then disable parser */
1466 if (tempval & RCTRL_REQ_PARSER)
1467 tempval |= RCTRL_PRSDEP_INIT;
1468 else
1469 tempval &= ~RCTRL_PRSDEP_INIT;
1470 gfar_write(&priv->regs->rctrl, tempval);
1471 }
1472
1473 gfar_change_mtu(dev, dev->mtu);
1474
1475 spin_unlock_irqrestore(&priv->rxlock, flags);
1476 }
1477
1478 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1479 {
1480 int tempsize, tempval;
1481 struct gfar_private *priv = netdev_priv(dev);
1482 int oldsize = priv->rx_buffer_size;
1483 int frame_size = new_mtu + ETH_HLEN;
1484
1485 if (priv->vlgrp)
1486 frame_size += VLAN_HLEN;
1487
1488 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1489 if (netif_msg_drv(priv))
1490 printk(KERN_ERR "%s: Invalid MTU setting\n",
1491 dev->name);
1492 return -EINVAL;
1493 }
1494
1495 if (gfar_uses_fcb(priv))
1496 frame_size += GMAC_FCB_LEN;
1497
1498 frame_size += priv->padding;
1499
1500 tempsize =
1501 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1502 INCREMENTAL_BUFFER_SIZE;
1503
1504 /* Only stop and start the controller if it isn't already
1505 * stopped, and we changed something */
1506 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1507 stop_gfar(dev);
1508
1509 priv->rx_buffer_size = tempsize;
1510
1511 dev->mtu = new_mtu;
1512
1513 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1514 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1515
1516 /* If the mtu is larger than the max size for standard
1517 * ethernet frames (ie, a jumbo frame), then set maccfg2
1518 * to allow huge frames, and to check the length */
1519 tempval = gfar_read(&priv->regs->maccfg2);
1520
1521 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1522 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1523 else
1524 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1525
1526 gfar_write(&priv->regs->maccfg2, tempval);
1527
1528 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1529 startup_gfar(dev);
1530
1531 return 0;
1532 }
1533
1534 /* gfar_reset_task gets scheduled when a packet has not been
1535 * transmitted after a set amount of time.
1536 * For now, assume that clearing out all the structures, and
1537 * starting over will fix the problem.
1538 */
1539 static void gfar_reset_task(struct work_struct *work)
1540 {
1541 struct gfar_private *priv = container_of(work, struct gfar_private,
1542 reset_task);
1543 struct net_device *dev = priv->ndev;
1544
1545 if (dev->flags & IFF_UP) {
1546 netif_stop_queue(dev);
1547 stop_gfar(dev);
1548 startup_gfar(dev);
1549 netif_start_queue(dev);
1550 }
1551
1552 netif_tx_schedule_all(dev);
1553 }
1554
1555 static void gfar_timeout(struct net_device *dev)
1556 {
1557 struct gfar_private *priv = netdev_priv(dev);
1558
1559 dev->stats.tx_errors++;
1560 schedule_work(&priv->reset_task);
1561 }
1562
1563 /* Interrupt Handler for Transmit complete */
1564 static int gfar_clean_tx_ring(struct net_device *dev)
1565 {
1566 struct gfar_private *priv = netdev_priv(dev);
1567 struct txbd8 *bdp;
1568 struct txbd8 *lbdp = NULL;
1569 struct txbd8 *base = priv->tx_bd_base;
1570 struct sk_buff *skb;
1571 int skb_dirtytx;
1572 int tx_ring_size = priv->tx_ring_size;
1573 int frags = 0;
1574 int i;
1575 int howmany = 0;
1576 u32 lstatus;
1577
1578 bdp = priv->dirty_tx;
1579 skb_dirtytx = priv->skb_dirtytx;
1580
1581 while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1582 frags = skb_shinfo(skb)->nr_frags;
1583 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1584
1585 lstatus = lbdp->lstatus;
1586
1587 /* Only clean completed frames */
1588 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1589 (lstatus & BD_LENGTH_MASK))
1590 break;
1591
1592 dma_unmap_single(&priv->ofdev->dev,
1593 bdp->bufPtr,
1594 bdp->length,
1595 DMA_TO_DEVICE);
1596
1597 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1598 bdp = next_txbd(bdp, base, tx_ring_size);
1599
1600 for (i = 0; i < frags; i++) {
1601 dma_unmap_page(&priv->ofdev->dev,
1602 bdp->bufPtr,
1603 bdp->length,
1604 DMA_TO_DEVICE);
1605 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1606 bdp = next_txbd(bdp, base, tx_ring_size);
1607 }
1608
1609 /*
1610 * If there's room in the queue (limit it to rx_buffer_size)
1611 * we add this skb back into the pool, if it's the right size
1612 */
1613 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1614 skb_recycle_check(skb, priv->rx_buffer_size +
1615 RXBUF_ALIGNMENT))
1616 __skb_queue_head(&priv->rx_recycle, skb);
1617 else
1618 dev_kfree_skb_any(skb);
1619
1620 priv->tx_skbuff[skb_dirtytx] = NULL;
1621
1622 skb_dirtytx = (skb_dirtytx + 1) &
1623 TX_RING_MOD_MASK(tx_ring_size);
1624
1625 howmany++;
1626 priv->num_txbdfree += frags + 1;
1627 }
1628
1629 /* If we freed a buffer, we can restart transmission, if necessary */
1630 if (netif_queue_stopped(dev) && priv->num_txbdfree)
1631 netif_wake_queue(dev);
1632
1633 /* Update dirty indicators */
1634 priv->skb_dirtytx = skb_dirtytx;
1635 priv->dirty_tx = bdp;
1636
1637 dev->stats.tx_packets += howmany;
1638
1639 return howmany;
1640 }
1641
1642 static void gfar_schedule_cleanup(struct net_device *dev)
1643 {
1644 struct gfar_private *priv = netdev_priv(dev);
1645 unsigned long flags;
1646
1647 spin_lock_irqsave(&priv->txlock, flags);
1648 spin_lock(&priv->rxlock);
1649
1650 if (napi_schedule_prep(&priv->napi)) {
1651 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1652 __napi_schedule(&priv->napi);
1653 } else {
1654 /*
1655 * Clear IEVENT, so interrupts aren't called again
1656 * because of the packets that have already arrived.
1657 */
1658 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1659 }
1660
1661 spin_unlock(&priv->rxlock);
1662 spin_unlock_irqrestore(&priv->txlock, flags);
1663 }
1664
1665 /* Interrupt Handler for Transmit complete */
1666 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1667 {
1668 gfar_schedule_cleanup((struct net_device *)dev_id);
1669 return IRQ_HANDLED;
1670 }
1671
1672 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1673 struct sk_buff *skb)
1674 {
1675 struct gfar_private *priv = netdev_priv(dev);
1676 u32 lstatus;
1677
1678 bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1679 priv->rx_buffer_size, DMA_FROM_DEVICE);
1680
1681 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1682
1683 if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1684 lstatus |= BD_LFLAG(RXBD_WRAP);
1685
1686 eieio();
1687
1688 bdp->lstatus = lstatus;
1689 }
1690
1691
1692 struct sk_buff * gfar_new_skb(struct net_device *dev)
1693 {
1694 unsigned int alignamount;
1695 struct gfar_private *priv = netdev_priv(dev);
1696 struct sk_buff *skb = NULL;
1697
1698 skb = __skb_dequeue(&priv->rx_recycle);
1699 if (!skb)
1700 skb = netdev_alloc_skb(dev,
1701 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1702
1703 if (!skb)
1704 return NULL;
1705
1706 alignamount = RXBUF_ALIGNMENT -
1707 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1708
1709 /* We need the data buffer to be aligned properly. We will reserve
1710 * as many bytes as needed to align the data properly
1711 */
1712 skb_reserve(skb, alignamount);
1713
1714 return skb;
1715 }
1716
1717 static inline void count_errors(unsigned short status, struct net_device *dev)
1718 {
1719 struct gfar_private *priv = netdev_priv(dev);
1720 struct net_device_stats *stats = &dev->stats;
1721 struct gfar_extra_stats *estats = &priv->extra_stats;
1722
1723 /* If the packet was truncated, none of the other errors
1724 * matter */
1725 if (status & RXBD_TRUNCATED) {
1726 stats->rx_length_errors++;
1727
1728 estats->rx_trunc++;
1729
1730 return;
1731 }
1732 /* Count the errors, if there were any */
1733 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1734 stats->rx_length_errors++;
1735
1736 if (status & RXBD_LARGE)
1737 estats->rx_large++;
1738 else
1739 estats->rx_short++;
1740 }
1741 if (status & RXBD_NONOCTET) {
1742 stats->rx_frame_errors++;
1743 estats->rx_nonoctet++;
1744 }
1745 if (status & RXBD_CRCERR) {
1746 estats->rx_crcerr++;
1747 stats->rx_crc_errors++;
1748 }
1749 if (status & RXBD_OVERRUN) {
1750 estats->rx_overrun++;
1751 stats->rx_crc_errors++;
1752 }
1753 }
1754
1755 irqreturn_t gfar_receive(int irq, void *dev_id)
1756 {
1757 gfar_schedule_cleanup((struct net_device *)dev_id);
1758 return IRQ_HANDLED;
1759 }
1760
1761 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1762 {
1763 /* If valid headers were found, and valid sums
1764 * were verified, then we tell the kernel that no
1765 * checksumming is necessary. Otherwise, it is */
1766 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1767 skb->ip_summed = CHECKSUM_UNNECESSARY;
1768 else
1769 skb->ip_summed = CHECKSUM_NONE;
1770 }
1771
1772
1773 /* gfar_process_frame() -- handle one incoming packet if skb
1774 * isn't NULL. */
1775 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1776 int amount_pull)
1777 {
1778 struct gfar_private *priv = netdev_priv(dev);
1779 struct rxfcb *fcb = NULL;
1780
1781 int ret;
1782
1783 /* fcb is at the beginning if exists */
1784 fcb = (struct rxfcb *)skb->data;
1785
1786 /* Remove the FCB from the skb */
1787 /* Remove the padded bytes, if there are any */
1788 if (amount_pull)
1789 skb_pull(skb, amount_pull);
1790
1791 if (priv->rx_csum_enable)
1792 gfar_rx_checksum(skb, fcb);
1793
1794 /* Tell the skb what kind of packet this is */
1795 skb->protocol = eth_type_trans(skb, dev);
1796
1797 /* Send the packet up the stack */
1798 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1799 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1800 else
1801 ret = netif_receive_skb(skb);
1802
1803 if (NET_RX_DROP == ret)
1804 priv->extra_stats.kernel_dropped++;
1805
1806 return 0;
1807 }
1808
1809 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1810 * until the budget/quota has been reached. Returns the number
1811 * of frames handled
1812 */
1813 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1814 {
1815 struct rxbd8 *bdp, *base;
1816 struct sk_buff *skb;
1817 int pkt_len;
1818 int amount_pull;
1819 int howmany = 0;
1820 struct gfar_private *priv = netdev_priv(dev);
1821
1822 /* Get the first full descriptor */
1823 bdp = priv->cur_rx;
1824 base = priv->rx_bd_base;
1825
1826 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1827 priv->padding;
1828
1829 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1830 struct sk_buff *newskb;
1831 rmb();
1832
1833 /* Add another skb for the future */
1834 newskb = gfar_new_skb(dev);
1835
1836 skb = priv->rx_skbuff[priv->skb_currx];
1837
1838 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1839 priv->rx_buffer_size, DMA_FROM_DEVICE);
1840
1841 /* We drop the frame if we failed to allocate a new buffer */
1842 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1843 bdp->status & RXBD_ERR)) {
1844 count_errors(bdp->status, dev);
1845
1846 if (unlikely(!newskb))
1847 newskb = skb;
1848 else if (skb) {
1849 /*
1850 * We need to reset ->data to what it
1851 * was before gfar_new_skb() re-aligned
1852 * it to an RXBUF_ALIGNMENT boundary
1853 * before we put the skb back on the
1854 * recycle list.
1855 */
1856 skb->data = skb->head + NET_SKB_PAD;
1857 __skb_queue_head(&priv->rx_recycle, skb);
1858 }
1859 } else {
1860 /* Increment the number of packets */
1861 dev->stats.rx_packets++;
1862 howmany++;
1863
1864 if (likely(skb)) {
1865 pkt_len = bdp->length - ETH_FCS_LEN;
1866 /* Remove the FCS from the packet length */
1867 skb_put(skb, pkt_len);
1868 dev->stats.rx_bytes += pkt_len;
1869
1870 if (in_irq() || irqs_disabled())
1871 printk("Interrupt problem!\n");
1872 gfar_process_frame(dev, skb, amount_pull);
1873
1874 } else {
1875 if (netif_msg_rx_err(priv))
1876 printk(KERN_WARNING
1877 "%s: Missing skb!\n", dev->name);
1878 dev->stats.rx_dropped++;
1879 priv->extra_stats.rx_skbmissing++;
1880 }
1881
1882 }
1883
1884 priv->rx_skbuff[priv->skb_currx] = newskb;
1885
1886 /* Setup the new bdp */
1887 gfar_new_rxbdp(dev, bdp, newskb);
1888
1889 /* Update to the next pointer */
1890 bdp = next_bd(bdp, base, priv->rx_ring_size);
1891
1892 /* update to point at the next skb */
1893 priv->skb_currx =
1894 (priv->skb_currx + 1) &
1895 RX_RING_MOD_MASK(priv->rx_ring_size);
1896 }
1897
1898 /* Update the current rxbd pointer to be the next one */
1899 priv->cur_rx = bdp;
1900
1901 return howmany;
1902 }
1903
1904 static int gfar_poll(struct napi_struct *napi, int budget)
1905 {
1906 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1907 struct net_device *dev = priv->ndev;
1908 int tx_cleaned = 0;
1909 int rx_cleaned = 0;
1910 unsigned long flags;
1911
1912 /* Clear IEVENT, so interrupts aren't called again
1913 * because of the packets that have already arrived */
1914 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1915
1916 /* If we fail to get the lock, don't bother with the TX BDs */
1917 if (spin_trylock_irqsave(&priv->txlock, flags)) {
1918 tx_cleaned = gfar_clean_tx_ring(dev);
1919 spin_unlock_irqrestore(&priv->txlock, flags);
1920 }
1921
1922 rx_cleaned = gfar_clean_rx_ring(dev, budget);
1923
1924 if (tx_cleaned)
1925 return budget;
1926
1927 if (rx_cleaned < budget) {
1928 napi_complete(napi);
1929
1930 /* Clear the halt bit in RSTAT */
1931 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1932
1933 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1934
1935 /* If we are coalescing interrupts, update the timer */
1936 /* Otherwise, clear it */
1937 if (likely(priv->rxcoalescing)) {
1938 gfar_write(&priv->regs->rxic, 0);
1939 gfar_write(&priv->regs->rxic, priv->rxic);
1940 }
1941 if (likely(priv->txcoalescing)) {
1942 gfar_write(&priv->regs->txic, 0);
1943 gfar_write(&priv->regs->txic, priv->txic);
1944 }
1945 }
1946
1947 return rx_cleaned;
1948 }
1949
1950 #ifdef CONFIG_NET_POLL_CONTROLLER
1951 /*
1952 * Polling 'interrupt' - used by things like netconsole to send skbs
1953 * without having to re-enable interrupts. It's not called while
1954 * the interrupt routine is executing.
1955 */
1956 static void gfar_netpoll(struct net_device *dev)
1957 {
1958 struct gfar_private *priv = netdev_priv(dev);
1959
1960 /* If the device has multiple interrupts, run tx/rx */
1961 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1962 disable_irq(priv->interruptTransmit);
1963 disable_irq(priv->interruptReceive);
1964 disable_irq(priv->interruptError);
1965 gfar_interrupt(priv->interruptTransmit, dev);
1966 enable_irq(priv->interruptError);
1967 enable_irq(priv->interruptReceive);
1968 enable_irq(priv->interruptTransmit);
1969 } else {
1970 disable_irq(priv->interruptTransmit);
1971 gfar_interrupt(priv->interruptTransmit, dev);
1972 enable_irq(priv->interruptTransmit);
1973 }
1974 }
1975 #endif
1976
1977 /* The interrupt handler for devices with one interrupt */
1978 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1979 {
1980 struct net_device *dev = dev_id;
1981 struct gfar_private *priv = netdev_priv(dev);
1982
1983 /* Save ievent for future reference */
1984 u32 events = gfar_read(&priv->regs->ievent);
1985
1986 /* Check for reception */
1987 if (events & IEVENT_RX_MASK)
1988 gfar_receive(irq, dev_id);
1989
1990 /* Check for transmit completion */
1991 if (events & IEVENT_TX_MASK)
1992 gfar_transmit(irq, dev_id);
1993
1994 /* Check for errors */
1995 if (events & IEVENT_ERR_MASK)
1996 gfar_error(irq, dev_id);
1997
1998 return IRQ_HANDLED;
1999 }
2000
2001 /* Called every time the controller might need to be made
2002 * aware of new link state. The PHY code conveys this
2003 * information through variables in the phydev structure, and this
2004 * function converts those variables into the appropriate
2005 * register values, and can bring down the device if needed.
2006 */
2007 static void adjust_link(struct net_device *dev)
2008 {
2009 struct gfar_private *priv = netdev_priv(dev);
2010 struct gfar __iomem *regs = priv->regs;
2011 unsigned long flags;
2012 struct phy_device *phydev = priv->phydev;
2013 int new_state = 0;
2014
2015 spin_lock_irqsave(&priv->txlock, flags);
2016 if (phydev->link) {
2017 u32 tempval = gfar_read(&regs->maccfg2);
2018 u32 ecntrl = gfar_read(&regs->ecntrl);
2019
2020 /* Now we make sure that we can be in full duplex mode.
2021 * If not, we operate in half-duplex mode. */
2022 if (phydev->duplex != priv->oldduplex) {
2023 new_state = 1;
2024 if (!(phydev->duplex))
2025 tempval &= ~(MACCFG2_FULL_DUPLEX);
2026 else
2027 tempval |= MACCFG2_FULL_DUPLEX;
2028
2029 priv->oldduplex = phydev->duplex;
2030 }
2031
2032 if (phydev->speed != priv->oldspeed) {
2033 new_state = 1;
2034 switch (phydev->speed) {
2035 case 1000:
2036 tempval =
2037 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2038
2039 ecntrl &= ~(ECNTRL_R100);
2040 break;
2041 case 100:
2042 case 10:
2043 tempval =
2044 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2045
2046 /* Reduced mode distinguishes
2047 * between 10 and 100 */
2048 if (phydev->speed == SPEED_100)
2049 ecntrl |= ECNTRL_R100;
2050 else
2051 ecntrl &= ~(ECNTRL_R100);
2052 break;
2053 default:
2054 if (netif_msg_link(priv))
2055 printk(KERN_WARNING
2056 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2057 dev->name, phydev->speed);
2058 break;
2059 }
2060
2061 priv->oldspeed = phydev->speed;
2062 }
2063
2064 gfar_write(&regs->maccfg2, tempval);
2065 gfar_write(&regs->ecntrl, ecntrl);
2066
2067 if (!priv->oldlink) {
2068 new_state = 1;
2069 priv->oldlink = 1;
2070 }
2071 } else if (priv->oldlink) {
2072 new_state = 1;
2073 priv->oldlink = 0;
2074 priv->oldspeed = 0;
2075 priv->oldduplex = -1;
2076 }
2077
2078 if (new_state && netif_msg_link(priv))
2079 phy_print_status(phydev);
2080
2081 spin_unlock_irqrestore(&priv->txlock, flags);
2082 }
2083
2084 /* Update the hash table based on the current list of multicast
2085 * addresses we subscribe to. Also, change the promiscuity of
2086 * the device based on the flags (this function is called
2087 * whenever dev->flags is changed */
2088 static void gfar_set_multi(struct net_device *dev)
2089 {
2090 struct dev_mc_list *mc_ptr;
2091 struct gfar_private *priv = netdev_priv(dev);
2092 struct gfar __iomem *regs = priv->regs;
2093 u32 tempval;
2094
2095 if(dev->flags & IFF_PROMISC) {
2096 /* Set RCTRL to PROM */
2097 tempval = gfar_read(&regs->rctrl);
2098 tempval |= RCTRL_PROM;
2099 gfar_write(&regs->rctrl, tempval);
2100 } else {
2101 /* Set RCTRL to not PROM */
2102 tempval = gfar_read(&regs->rctrl);
2103 tempval &= ~(RCTRL_PROM);
2104 gfar_write(&regs->rctrl, tempval);
2105 }
2106
2107 if(dev->flags & IFF_ALLMULTI) {
2108 /* Set the hash to rx all multicast frames */
2109 gfar_write(&regs->igaddr0, 0xffffffff);
2110 gfar_write(&regs->igaddr1, 0xffffffff);
2111 gfar_write(&regs->igaddr2, 0xffffffff);
2112 gfar_write(&regs->igaddr3, 0xffffffff);
2113 gfar_write(&regs->igaddr4, 0xffffffff);
2114 gfar_write(&regs->igaddr5, 0xffffffff);
2115 gfar_write(&regs->igaddr6, 0xffffffff);
2116 gfar_write(&regs->igaddr7, 0xffffffff);
2117 gfar_write(&regs->gaddr0, 0xffffffff);
2118 gfar_write(&regs->gaddr1, 0xffffffff);
2119 gfar_write(&regs->gaddr2, 0xffffffff);
2120 gfar_write(&regs->gaddr3, 0xffffffff);
2121 gfar_write(&regs->gaddr4, 0xffffffff);
2122 gfar_write(&regs->gaddr5, 0xffffffff);
2123 gfar_write(&regs->gaddr6, 0xffffffff);
2124 gfar_write(&regs->gaddr7, 0xffffffff);
2125 } else {
2126 int em_num;
2127 int idx;
2128
2129 /* zero out the hash */
2130 gfar_write(&regs->igaddr0, 0x0);
2131 gfar_write(&regs->igaddr1, 0x0);
2132 gfar_write(&regs->igaddr2, 0x0);
2133 gfar_write(&regs->igaddr3, 0x0);
2134 gfar_write(&regs->igaddr4, 0x0);
2135 gfar_write(&regs->igaddr5, 0x0);
2136 gfar_write(&regs->igaddr6, 0x0);
2137 gfar_write(&regs->igaddr7, 0x0);
2138 gfar_write(&regs->gaddr0, 0x0);
2139 gfar_write(&regs->gaddr1, 0x0);
2140 gfar_write(&regs->gaddr2, 0x0);
2141 gfar_write(&regs->gaddr3, 0x0);
2142 gfar_write(&regs->gaddr4, 0x0);
2143 gfar_write(&regs->gaddr5, 0x0);
2144 gfar_write(&regs->gaddr6, 0x0);
2145 gfar_write(&regs->gaddr7, 0x0);
2146
2147 /* If we have extended hash tables, we need to
2148 * clear the exact match registers to prepare for
2149 * setting them */
2150 if (priv->extended_hash) {
2151 em_num = GFAR_EM_NUM + 1;
2152 gfar_clear_exact_match(dev);
2153 idx = 1;
2154 } else {
2155 idx = 0;
2156 em_num = 0;
2157 }
2158
2159 if(dev->mc_count == 0)
2160 return;
2161
2162 /* Parse the list, and set the appropriate bits */
2163 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2164 if (idx < em_num) {
2165 gfar_set_mac_for_addr(dev, idx,
2166 mc_ptr->dmi_addr);
2167 idx++;
2168 } else
2169 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2170 }
2171 }
2172
2173 return;
2174 }
2175
2176
2177 /* Clears each of the exact match registers to zero, so they
2178 * don't interfere with normal reception */
2179 static void gfar_clear_exact_match(struct net_device *dev)
2180 {
2181 int idx;
2182 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2183
2184 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2185 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2186 }
2187
2188 /* Set the appropriate hash bit for the given addr */
2189 /* The algorithm works like so:
2190 * 1) Take the Destination Address (ie the multicast address), and
2191 * do a CRC on it (little endian), and reverse the bits of the
2192 * result.
2193 * 2) Use the 8 most significant bits as a hash into a 256-entry
2194 * table. The table is controlled through 8 32-bit registers:
2195 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2196 * gaddr7. This means that the 3 most significant bits in the
2197 * hash index which gaddr register to use, and the 5 other bits
2198 * indicate which bit (assuming an IBM numbering scheme, which
2199 * for PowerPC (tm) is usually the case) in the register holds
2200 * the entry. */
2201 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2202 {
2203 u32 tempval;
2204 struct gfar_private *priv = netdev_priv(dev);
2205 u32 result = ether_crc(MAC_ADDR_LEN, addr);
2206 int width = priv->hash_width;
2207 u8 whichbit = (result >> (32 - width)) & 0x1f;
2208 u8 whichreg = result >> (32 - width + 5);
2209 u32 value = (1 << (31-whichbit));
2210
2211 tempval = gfar_read(priv->hash_regs[whichreg]);
2212 tempval |= value;
2213 gfar_write(priv->hash_regs[whichreg], tempval);
2214
2215 return;
2216 }
2217
2218
2219 /* There are multiple MAC Address register pairs on some controllers
2220 * This function sets the numth pair to a given address
2221 */
2222 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2223 {
2224 struct gfar_private *priv = netdev_priv(dev);
2225 int idx;
2226 char tmpbuf[MAC_ADDR_LEN];
2227 u32 tempval;
2228 u32 __iomem *macptr = &priv->regs->macstnaddr1;
2229
2230 macptr += num*2;
2231
2232 /* Now copy it into the mac registers backwards, cuz */
2233 /* little endian is silly */
2234 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2235 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2236
2237 gfar_write(macptr, *((u32 *) (tmpbuf)));
2238
2239 tempval = *((u32 *) (tmpbuf + 4));
2240
2241 gfar_write(macptr+1, tempval);
2242 }
2243
2244 /* GFAR error interrupt handler */
2245 static irqreturn_t gfar_error(int irq, void *dev_id)
2246 {
2247 struct net_device *dev = dev_id;
2248 struct gfar_private *priv = netdev_priv(dev);
2249
2250 /* Save ievent for future reference */
2251 u32 events = gfar_read(&priv->regs->ievent);
2252
2253 /* Clear IEVENT */
2254 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2255
2256 /* Magic Packet is not an error. */
2257 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2258 (events & IEVENT_MAG))
2259 events &= ~IEVENT_MAG;
2260
2261 /* Hmm... */
2262 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2263 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2264 dev->name, events, gfar_read(&priv->regs->imask));
2265
2266 /* Update the error counters */
2267 if (events & IEVENT_TXE) {
2268 dev->stats.tx_errors++;
2269
2270 if (events & IEVENT_LC)
2271 dev->stats.tx_window_errors++;
2272 if (events & IEVENT_CRL)
2273 dev->stats.tx_aborted_errors++;
2274 if (events & IEVENT_XFUN) {
2275 if (netif_msg_tx_err(priv))
2276 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2277 "packet dropped.\n", dev->name);
2278 dev->stats.tx_dropped++;
2279 priv->extra_stats.tx_underrun++;
2280
2281 /* Reactivate the Tx Queues */
2282 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2283 }
2284 if (netif_msg_tx_err(priv))
2285 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2286 }
2287 if (events & IEVENT_BSY) {
2288 dev->stats.rx_errors++;
2289 priv->extra_stats.rx_bsy++;
2290
2291 gfar_receive(irq, dev_id);
2292
2293 if (netif_msg_rx_err(priv))
2294 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2295 dev->name, gfar_read(&priv->regs->rstat));
2296 }
2297 if (events & IEVENT_BABR) {
2298 dev->stats.rx_errors++;
2299 priv->extra_stats.rx_babr++;
2300
2301 if (netif_msg_rx_err(priv))
2302 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2303 }
2304 if (events & IEVENT_EBERR) {
2305 priv->extra_stats.eberr++;
2306 if (netif_msg_rx_err(priv))
2307 printk(KERN_DEBUG "%s: bus error\n", dev->name);
2308 }
2309 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2310 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2311
2312 if (events & IEVENT_BABT) {
2313 priv->extra_stats.tx_babt++;
2314 if (netif_msg_tx_err(priv))
2315 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2316 }
2317 return IRQ_HANDLED;
2318 }
2319
2320 /* work with hotplug and coldplug */
2321 MODULE_ALIAS("platform:fsl-gianfar");
2322
2323 static struct of_device_id gfar_match[] =
2324 {
2325 {
2326 .type = "network",
2327 .compatible = "gianfar",
2328 },
2329 {},
2330 };
2331
2332 /* Structure for a device driver */
2333 static struct of_platform_driver gfar_driver = {
2334 .name = "fsl-gianfar",
2335 .match_table = gfar_match,
2336
2337 .probe = gfar_probe,
2338 .remove = gfar_remove,
2339 .suspend = gfar_suspend,
2340 .resume = gfar_resume,
2341 };
2342
2343 static int __init gfar_init(void)
2344 {
2345 return of_register_platform_driver(&gfar_driver);
2346 }
2347
2348 static void __exit gfar_exit(void)
2349 {
2350 of_unregister_platform_driver(&gfar_driver);
2351 }
2352
2353 module_init(gfar_init);
2354 module_exit(gfar_exit);
2355
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