1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
37 /* General customization:
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
51 #define I915_NUM_PIPE 2
56 * 1.2: Add Power Management
57 * 1.3: Add vblank support
58 * 1.4: Fix cmdbuffer path, add heap destroy
59 * 1.5: Add vblank pipe configuration
60 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
61 * - Support vertical blank on secondary display pipe
63 #define DRIVER_MAJOR 1
64 #define DRIVER_MINOR 6
65 #define DRIVER_PATCHLEVEL 0
67 #define WATCH_COHERENCY 0
72 #define WATCH_INACTIVE 0
73 #define WATCH_PWRITE 0
75 #define I915_GEM_PHYS_CURSOR_0 1
76 #define I915_GEM_PHYS_CURSOR_1 2
77 #define I915_GEM_PHYS_OVERLAY_REGS 3
78 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
80 struct drm_i915_gem_phys_object
{
82 struct page
**page_list
;
83 drm_dma_handle_t
*handle
;
84 struct drm_gem_object
*cur_obj
;
87 typedef struct _drm_i915_ring_buffer
{
95 struct drm_gem_object
*ring_obj
;
96 } drm_i915_ring_buffer_t
;
99 struct mem_block
*next
;
100 struct mem_block
*prev
;
103 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
106 struct opregion_header
;
107 struct opregion_acpi
;
108 struct opregion_swsci
;
109 struct opregion_asle
;
111 struct intel_opregion
{
112 struct opregion_header
*header
;
113 struct opregion_acpi
*acpi
;
114 struct opregion_swsci
*swsci
;
115 struct opregion_asle
*asle
;
119 struct drm_i915_master_private
{
120 drm_local_map_t
*sarea
;
121 struct _drm_i915_sarea
*sarea_priv
;
123 #define I915_FENCE_REG_NONE -1
125 struct drm_i915_fence_reg
{
126 struct drm_gem_object
*obj
;
129 typedef struct drm_i915_private
{
130 struct drm_device
*dev
;
136 drm_i915_ring_buffer_t ring
;
138 drm_dma_handle_t
*status_page_dmah
;
139 void *hw_status_page
;
140 dma_addr_t dma_status_page
;
142 unsigned int status_gfx_addr
;
143 drm_local_map_t hws_map
;
144 struct drm_gem_object
*hws_obj
;
152 wait_queue_head_t irq_queue
;
153 atomic_t irq_received
;
154 /** Protects user_irq_refcount and irq_mask_reg */
155 spinlock_t user_irq_lock
;
156 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
157 int user_irq_refcount
;
158 /** Cached value of IMR to avoid reads in updating the bitfield */
162 u32 hotplug_supported_mask
;
163 struct work_struct hotplug_work
;
165 int tex_lru_log_granularity
;
166 int allow_batchbuffer
;
167 struct mem_block
*agp_heap
;
168 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
171 bool cursor_needs_physical
;
177 struct intel_opregion opregion
;
180 int backlight_duty_cycle
; /* restore backlight to this value */
181 bool panel_wants_dither
;
182 struct drm_display_mode
*panel_fixed_mode
;
183 struct drm_display_mode
*vbt_mode
; /* if any */
185 /* Feature bits from the VBIOS */
186 unsigned int int_tv_support
:1;
187 unsigned int lvds_dither
:1;
188 unsigned int lvds_vbt
:1;
189 unsigned int int_crt_support
:1;
190 unsigned int lvds_use_ssc
:1;
193 struct drm_i915_fence_reg fence_regs
[16]; /* assume 965 */
194 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
195 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
202 u32 saveRENDERSTANDBY
;
226 u32 savePFIT_PGM_RATIOS
;
228 u32 saveBLC_PWM_CTL2
;
253 u32 savePP_ON_DELAYS
;
254 u32 savePP_OFF_DELAYS
;
262 u32 savePFIT_CONTROL
;
263 u32 save_palette_a
[256];
264 u32 save_palette_b
[256];
265 u32 saveFBC_CFB_BASE
;
268 u32 saveFBC_CONTROL2
;
272 u32 saveCACHE_MODE_0
;
275 u32 saveMI_ARB_STATE
;
286 uint64_t saveFENCE
[16];
289 struct drm_mm gtt_space
;
291 struct io_mapping
*gtt_mapping
;
295 * List of objects currently involved in rendering from the
298 * Includes buffers having the contents of their GPU caches
299 * flushed, not necessarily primitives. last_rendering_seqno
300 * represents when the rendering involved will be completed.
302 * A reference is held on the buffer while on this list.
304 spinlock_t active_list_lock
;
305 struct list_head active_list
;
308 * List of objects which are not in the ringbuffer but which
309 * still have a write_domain which needs to be flushed before
312 * last_rendering_seqno is 0 while an object is in this list.
314 * A reference is held on the buffer while on this list.
316 struct list_head flushing_list
;
319 * LRU list of objects which are not in the ringbuffer and
320 * are ready to unbind, but are still in the GTT.
322 * last_rendering_seqno is 0 while an object is in this list.
324 * A reference is not held on the buffer while on this list,
325 * as merely being GTT-bound shouldn't prevent its being
326 * freed, and we'll pull it off the list in the free path.
328 struct list_head inactive_list
;
331 * List of breadcrumbs associated with GPU requests currently
334 struct list_head request_list
;
337 * We leave the user IRQ off as much as possible,
338 * but this means that requests will finish and never
339 * be retired once the system goes idle. Set a timer to
340 * fire periodically while the ring is running. When it
341 * fires, go retire requests.
343 struct delayed_work retire_work
;
345 uint32_t next_gem_seqno
;
348 * Waiting sequence number, if any
350 uint32_t waiting_gem_seqno
;
353 * Last seq seen at irq time
355 uint32_t irq_gem_seqno
;
358 * Flag if the X Server, and thus DRM, is not currently in
359 * control of the device.
361 * This is set between LeaveVT and EnterVT. It needs to be
362 * replaced with a semaphore. It also needs to be
363 * transitioned away from for kernel modesetting.
368 * Flag if the hardware appears to be wedged.
370 * This is set when attempts to idle the device timeout.
371 * It prevents command submission from occuring and makes
372 * every pending request fail
376 /** Bit 6 swizzling required for X tiling */
377 uint32_t bit_6_swizzle_x
;
378 /** Bit 6 swizzling required for Y tiling */
379 uint32_t bit_6_swizzle_y
;
381 /* storage for physical objects */
382 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
384 } drm_i915_private_t
;
386 /** driver private structure attached to each drm_gem_object */
387 struct drm_i915_gem_object
{
388 struct drm_gem_object
*obj
;
390 /** Current space allocated to this object in the GTT, if any. */
391 struct drm_mm_node
*gtt_space
;
393 /** This object's place on the active/flushing/inactive lists */
394 struct list_head list
;
397 * This is set if the object is on the active or flushing lists
398 * (has pending rendering), and is not set if it's on inactive (ready
404 * This is set if the object has been written to since last bound
409 /** AGP memory structure for our GTT binding. */
410 DRM_AGP_MEM
*agp_mem
;
416 * Current offset of the object in GTT space.
418 * This is the same as gtt_space->start
422 * Required alignment for the object
424 uint32_t gtt_alignment
;
426 * Fake offset for use by mmap(2)
428 uint64_t mmap_offset
;
431 * Fence register bits (if any) for this object. Will be set
432 * as needed when mapped into the GTT.
433 * Protected by dev->struct_mutex.
437 /** Boolean whether this object has a valid gtt offset. */
440 /** How many users have pinned this object in GTT space */
443 /** Breadcrumb of last rendering to the buffer. */
444 uint32_t last_rendering_seqno
;
446 /** Current tiling mode for the object. */
447 uint32_t tiling_mode
;
450 /** Record of address bit 17 of each page at last unbind. */
453 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
457 * If present, while GEM_DOMAIN_CPU is in the read domain this array
458 * flags which individual pages are valid.
460 uint8_t *page_cpu_valid
;
462 /** User space pin count and filp owning the pin */
463 uint32_t user_pin_count
;
464 struct drm_file
*pin_filp
;
466 /** for phy allocated objects */
467 struct drm_i915_gem_phys_object
*phys_obj
;
470 * Used for checking the object doesn't appear more than once
471 * in an execbuffer object list.
477 * Request queue structure.
479 * The request queue allows us to note sequence numbers that have been emitted
480 * and may be associated with active buffers to be retired.
482 * By keeping this list, we can avoid having to do questionable
483 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
484 * an emission time with seqnos for tracking how far ahead of the GPU we are.
486 struct drm_i915_gem_request
{
487 /** GEM sequence number associated with this request. */
490 /** Time at which this request was emitted, in jiffies. */
491 unsigned long emitted_jiffies
;
493 struct list_head list
;
496 struct drm_i915_file_private
{
498 uint32_t last_gem_seqno
;
499 uint32_t last_gem_throttle_seqno
;
503 enum intel_chip_family
{
510 extern struct drm_ioctl_desc i915_ioctls
[];
511 extern int i915_max_ioctl
;
512 extern unsigned int i915_fbpercrtc
;
514 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
515 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
518 extern void i915_kernel_lost_context(struct drm_device
* dev
);
519 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
520 extern int i915_driver_unload(struct drm_device
*);
521 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
522 extern void i915_driver_lastclose(struct drm_device
* dev
);
523 extern void i915_driver_preclose(struct drm_device
*dev
,
524 struct drm_file
*file_priv
);
525 extern void i915_driver_postclose(struct drm_device
*dev
,
526 struct drm_file
*file_priv
);
527 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
528 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
530 extern int i915_emit_box(struct drm_device
*dev
,
531 struct drm_clip_rect
*boxes
,
532 int i
, int DR1
, int DR4
);
535 extern int i915_irq_emit(struct drm_device
*dev
, void *data
,
536 struct drm_file
*file_priv
);
537 extern int i915_irq_wait(struct drm_device
*dev
, void *data
,
538 struct drm_file
*file_priv
);
539 void i915_user_irq_get(struct drm_device
*dev
);
540 void i915_user_irq_put(struct drm_device
*dev
);
541 extern void i915_enable_interrupt (struct drm_device
*dev
);
543 extern irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
);
544 extern void i915_driver_irq_preinstall(struct drm_device
* dev
);
545 extern int i915_driver_irq_postinstall(struct drm_device
*dev
);
546 extern void i915_driver_irq_uninstall(struct drm_device
* dev
);
547 extern int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
548 struct drm_file
*file_priv
);
549 extern int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
550 struct drm_file
*file_priv
);
551 extern int i915_enable_vblank(struct drm_device
*dev
, int crtc
);
552 extern void i915_disable_vblank(struct drm_device
*dev
, int crtc
);
553 extern u32
i915_get_vblank_counter(struct drm_device
*dev
, int crtc
);
554 extern u32
gm45_get_vblank_counter(struct drm_device
*dev
, int crtc
);
555 extern int i915_vblank_swap(struct drm_device
*dev
, void *data
,
556 struct drm_file
*file_priv
);
557 extern void i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
560 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
563 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
567 extern int i915_mem_alloc(struct drm_device
*dev
, void *data
,
568 struct drm_file
*file_priv
);
569 extern int i915_mem_free(struct drm_device
*dev
, void *data
,
570 struct drm_file
*file_priv
);
571 extern int i915_mem_init_heap(struct drm_device
*dev
, void *data
,
572 struct drm_file
*file_priv
);
573 extern int i915_mem_destroy_heap(struct drm_device
*dev
, void *data
,
574 struct drm_file
*file_priv
);
575 extern void i915_mem_takedown(struct mem_block
**heap
);
576 extern void i915_mem_release(struct drm_device
* dev
,
577 struct drm_file
*file_priv
, struct mem_block
*heap
);
579 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
580 struct drm_file
*file_priv
);
581 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
582 struct drm_file
*file_priv
);
583 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
584 struct drm_file
*file_priv
);
585 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
586 struct drm_file
*file_priv
);
587 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
588 struct drm_file
*file_priv
);
589 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
590 struct drm_file
*file_priv
);
591 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
592 struct drm_file
*file_priv
);
593 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
594 struct drm_file
*file_priv
);
595 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
596 struct drm_file
*file_priv
);
597 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
598 struct drm_file
*file_priv
);
599 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
600 struct drm_file
*file_priv
);
601 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
602 struct drm_file
*file_priv
);
603 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
604 struct drm_file
*file_priv
);
605 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
606 struct drm_file
*file_priv
);
607 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
608 struct drm_file
*file_priv
);
609 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
610 struct drm_file
*file_priv
);
611 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
612 struct drm_file
*file_priv
);
613 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
614 struct drm_file
*file_priv
);
615 void i915_gem_load(struct drm_device
*dev
);
616 int i915_gem_init_object(struct drm_gem_object
*obj
);
617 void i915_gem_free_object(struct drm_gem_object
*obj
);
618 int i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
);
619 void i915_gem_object_unpin(struct drm_gem_object
*obj
);
620 int i915_gem_object_unbind(struct drm_gem_object
*obj
);
621 void i915_gem_lastclose(struct drm_device
*dev
);
622 uint32_t i915_get_gem_seqno(struct drm_device
*dev
);
623 void i915_gem_retire_requests(struct drm_device
*dev
);
624 void i915_gem_retire_work_handler(struct work_struct
*work
);
625 void i915_gem_clflush_object(struct drm_gem_object
*obj
);
626 int i915_gem_object_set_domain(struct drm_gem_object
*obj
,
627 uint32_t read_domains
,
628 uint32_t write_domain
);
629 int i915_gem_init_ringbuffer(struct drm_device
*dev
);
630 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
631 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
633 int i915_gem_idle(struct drm_device
*dev
);
634 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
635 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
,
637 int i915_gem_attach_phys_object(struct drm_device
*dev
,
638 struct drm_gem_object
*obj
, int id
);
639 void i915_gem_detach_phys_object(struct drm_device
*dev
,
640 struct drm_gem_object
*obj
);
641 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
642 int i915_gem_object_get_pages(struct drm_gem_object
*obj
);
643 void i915_gem_object_put_pages(struct drm_gem_object
*obj
);
645 /* i915_gem_tiling.c */
646 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
647 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object
*obj
);
648 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object
*obj
);
650 /* i915_gem_debug.c */
651 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
652 const char *where
, uint32_t mark
);
654 void i915_verify_inactive(struct drm_device
*dev
, char *file
, int line
);
656 #define i915_verify_inactive(dev, file, line)
658 void i915_gem_object_check_coherency(struct drm_gem_object
*obj
, int handle
);
659 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
660 const char *where
, uint32_t mark
);
661 void i915_dump_lru(struct drm_device
*dev
, const char *where
);
664 int i915_gem_debugfs_init(struct drm_minor
*minor
);
665 void i915_gem_debugfs_cleanup(struct drm_minor
*minor
);
668 extern int i915_save_state(struct drm_device
*dev
);
669 extern int i915_restore_state(struct drm_device
*dev
);
672 extern int i915_save_state(struct drm_device
*dev
);
673 extern int i915_restore_state(struct drm_device
*dev
);
676 /* i915_opregion.c */
677 extern int intel_opregion_init(struct drm_device
*dev
, int resume
);
678 extern void intel_opregion_free(struct drm_device
*dev
, int suspend
);
679 extern void opregion_asle_intr(struct drm_device
*dev
);
680 extern void opregion_enable_asle(struct drm_device
*dev
);
682 static inline int intel_opregion_init(struct drm_device
*dev
, int resume
) { return 0; }
683 static inline void intel_opregion_free(struct drm_device
*dev
, int suspend
) { return; }
684 static inline void opregion_asle_intr(struct drm_device
*dev
) { return; }
685 static inline void opregion_enable_asle(struct drm_device
*dev
) { return; }
689 extern void intel_modeset_init(struct drm_device
*dev
);
690 extern void intel_modeset_cleanup(struct drm_device
*dev
);
693 * Lock test for when it's just for synchronization of ring access.
695 * In that case, we don't need to do it when GEM is initialized as nobody else
696 * has access to the ring.
698 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
699 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
700 LOCK_TEST_WITH_RETURN(dev, file_priv); \
703 #define I915_READ(reg) readl(dev_priv->regs + (reg))
704 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
705 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
706 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
707 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
708 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
709 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
710 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
711 #define POSTING_READ(reg) (void)I915_READ(reg)
713 #define I915_VERBOSE 0
715 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
718 #define BEGIN_LP_RING(n) do { \
720 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
721 if (dev_priv->ring.space < (n)*4) \
722 i915_wait_ring(dev, (n)*4, __func__); \
724 outring = dev_priv->ring.tail; \
725 ringmask = dev_priv->ring.tail_mask; \
726 virt = dev_priv->ring.virtual_start; \
729 #define OUT_RING(n) do { \
730 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
731 *(volatile unsigned int *)(virt + outring) = (n); \
734 outring &= ringmask; \
737 #define ADVANCE_LP_RING() do { \
738 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
739 dev_priv->ring.tail = outring; \
740 dev_priv->ring.space -= outcount * 4; \
741 I915_WRITE(PRB0_TAIL, outring); \
745 * Reads a dword out of the status page, which is written to from the command
746 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
749 * The following dwords have a reserved meaning:
750 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
751 * 0x04: ring 0 head pointer
752 * 0x05: ring 1 head pointer (915-class)
753 * 0x06: ring 2 head pointer (915-class)
754 * 0x10-0x1b: Context status DWords (GM45)
755 * 0x1f: Last written status offset. (GM45)
757 * The area from dword 0x20 to 0x3ff is available for driver usage.
759 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
760 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
761 #define I915_GEM_HWS_INDEX 0x20
762 #define I915_BREADCRUMB_INDEX 0x21
764 extern int i915_wait_ring(struct drm_device
* dev
, int n
, const char *caller
);
766 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
767 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
768 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
769 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
770 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
772 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
773 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
774 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
775 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
776 (dev)->pci_device == 0x27AE)
777 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
778 (dev)->pci_device == 0x2982 || \
779 (dev)->pci_device == 0x2992 || \
780 (dev)->pci_device == 0x29A2 || \
781 (dev)->pci_device == 0x2A02 || \
782 (dev)->pci_device == 0x2A12 || \
783 (dev)->pci_device == 0x2A42 || \
784 (dev)->pci_device == 0x2E02 || \
785 (dev)->pci_device == 0x2E12 || \
786 (dev)->pci_device == 0x2E22 || \
787 (dev)->pci_device == 0x2E32)
789 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
790 (dev)->pci_device == 0x2A12)
792 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
794 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
795 (dev)->pci_device == 0x2E12 || \
796 (dev)->pci_device == 0x2E22 || \
797 (dev)->pci_device == 0x2E32 || \
800 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
801 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
802 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
804 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
805 (dev)->pci_device == 0x29B2 || \
806 (dev)->pci_device == 0x29D2 || \
809 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
810 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
812 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
813 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
816 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
817 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
818 * rows, which changed the alignment requirements and fence programming.
820 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
822 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev))
823 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
825 #define PRIMARY_RINGBUFFER_SIZE (128*1024)