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rt2x00: Cleanup indirect register access
[linux-2.6/mini2440.git] / drivers / net / wireless / rt2x00 / rt73usb.c
blobb4ca8488beffe6bc500ad1c7daa5946135cefbd2
1 /*
2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/usb.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00usb.h"
37 #include "rt73usb.h"
38
39 /*
40 * Allow hardware encryption to be disabled.
41 */
42 static int modparam_nohwcrypt = 0;
43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
46 /*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt73usb_register_read and rt73usb_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60 static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
61 const unsigned int offset, u32 *value)
62 {
63 __le32 reg;
64 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
65 USB_VENDOR_REQUEST_IN, offset,
66 &reg, sizeof(reg), REGISTER_TIMEOUT);
67 *value = le32_to_cpu(reg);
68 }
69
70 static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
71 const unsigned int offset, u32 *value)
72 {
73 __le32 reg;
74 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
75 USB_VENDOR_REQUEST_IN, offset,
76 &reg, sizeof(reg), REGISTER_TIMEOUT);
77 *value = le32_to_cpu(reg);
78 }
79
80 static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
81 const unsigned int offset,
82 void *value, const u32 length)
83 {
84 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
85 USB_VENDOR_REQUEST_IN, offset,
86 value, length,
87 REGISTER_TIMEOUT32(length));
88 }
89
90 static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
91 const unsigned int offset, u32 value)
92 {
93 __le32 reg = cpu_to_le32(value);
94 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
95 USB_VENDOR_REQUEST_OUT, offset,
96 &reg, sizeof(reg), REGISTER_TIMEOUT);
97 }
98
99 static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
100 const unsigned int offset, u32 value)
101 {
102 __le32 reg = cpu_to_le32(value);
103 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
104 USB_VENDOR_REQUEST_OUT, offset,
105 &reg, sizeof(reg), REGISTER_TIMEOUT);
106 }
107
108 static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
109 const unsigned int offset,
110 void *value, const u32 length)
111 {
112 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
113 USB_VENDOR_REQUEST_OUT, offset,
114 value, length,
115 REGISTER_TIMEOUT32(length));
116 }
117
118 static int rt73usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
119 const unsigned int offset,
120 struct rt2x00_field32 field,
121 u32 *reg)
122 {
123 unsigned int i;
124
125 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
126 rt73usb_register_read_lock(rt2x00dev, offset, reg);
127 if (!rt2x00_get_field32(*reg, field))
128 return 1;
129 udelay(REGISTER_BUSY_DELAY);
130 }
131
132 ERROR(rt2x00dev, "Indirect register access failed: "
133 "offset=0x%.08x, value=0x%.08x\n", offset, *reg);
134 *reg = ~0;
135
136 return 0;
137 }
138
139 #define WAIT_FOR_BBP(__dev, __reg) \
140 rt73usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
141 #define WAIT_FOR_RF(__dev, __reg) \
142 rt73usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
143
144 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
146 {
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the BBP becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
158 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
159 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
160 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
161
162 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
170 {
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the BBP becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
186 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
187 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
188
189 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
190
191 WAIT_FOR_BBP(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
201 {
202 u32 reg;
203
204 if (!word)
205 return;
206
207 mutex_lock(&rt2x00dev->csr_mutex);
208
209 /*
210 * Wait until the RF becomes available, afterwards we
211 * can safely write the new data into the register.
212 */
213 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
214 reg = 0;
215 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
216 /*
217 * RF5225 and RF2527 contain 21 bits per RF register value,
218 * all others contain 20 bits.
219 */
220 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
221 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
222 rt2x00_rf(&rt2x00dev->chip, RF2527)));
223 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
224 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
225
226 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
227 rt2x00_rf_write(rt2x00dev, word, value);
228 }
229
230 mutex_unlock(&rt2x00dev->csr_mutex);
231 }
232
233 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
234 static const struct rt2x00debug rt73usb_rt2x00debug = {
235 .owner = THIS_MODULE,
236 .csr = {
237 .read = rt73usb_register_read,
238 .write = rt73usb_register_write,
239 .flags = RT2X00DEBUGFS_OFFSET,
240 .word_base = CSR_REG_BASE,
241 .word_size = sizeof(u32),
242 .word_count = CSR_REG_SIZE / sizeof(u32),
243 },
244 .eeprom = {
245 .read = rt2x00_eeprom_read,
246 .write = rt2x00_eeprom_write,
247 .word_base = EEPROM_BASE,
248 .word_size = sizeof(u16),
249 .word_count = EEPROM_SIZE / sizeof(u16),
250 },
251 .bbp = {
252 .read = rt73usb_bbp_read,
253 .write = rt73usb_bbp_write,
254 .word_base = BBP_BASE,
255 .word_size = sizeof(u8),
256 .word_count = BBP_SIZE / sizeof(u8),
257 },
258 .rf = {
259 .read = rt2x00_rf_read,
260 .write = rt73usb_rf_write,
261 .word_base = RF_BASE,
262 .word_size = sizeof(u32),
263 .word_count = RF_SIZE / sizeof(u32),
264 },
265 };
266 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
267
268 #ifdef CONFIG_RT2X00_LIB_LEDS
269 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
270 enum led_brightness brightness)
271 {
272 struct rt2x00_led *led =
273 container_of(led_cdev, struct rt2x00_led, led_dev);
274 unsigned int enabled = brightness != LED_OFF;
275 unsigned int a_mode =
276 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
277 unsigned int bg_mode =
278 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
279
280 if (led->type == LED_TYPE_RADIO) {
281 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
282 MCU_LEDCS_RADIO_STATUS, enabled);
283
284 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
285 0, led->rt2x00dev->led_mcu_reg,
286 REGISTER_TIMEOUT);
287 } else if (led->type == LED_TYPE_ASSOC) {
288 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
289 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
290 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
291 MCU_LEDCS_LINK_A_STATUS, a_mode);
292
293 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
294 0, led->rt2x00dev->led_mcu_reg,
295 REGISTER_TIMEOUT);
296 } else if (led->type == LED_TYPE_QUALITY) {
297 /*
298 * The brightness is divided into 6 levels (0 - 5),
299 * this means we need to convert the brightness
300 * argument into the matching level within that range.
301 */
302 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
303 brightness / (LED_FULL / 6),
304 led->rt2x00dev->led_mcu_reg,
305 REGISTER_TIMEOUT);
306 }
307 }
308
309 static int rt73usb_blink_set(struct led_classdev *led_cdev,
310 unsigned long *delay_on,
311 unsigned long *delay_off)
312 {
313 struct rt2x00_led *led =
314 container_of(led_cdev, struct rt2x00_led, led_dev);
315 u32 reg;
316
317 rt73usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
318 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
319 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
320 rt73usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
321
322 return 0;
323 }
324
325 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
326 struct rt2x00_led *led,
327 enum led_type type)
328 {
329 led->rt2x00dev = rt2x00dev;
330 led->type = type;
331 led->led_dev.brightness_set = rt73usb_brightness_set;
332 led->led_dev.blink_set = rt73usb_blink_set;
333 led->flags = LED_INITIALIZED;
334 }
335 #endif /* CONFIG_RT2X00_LIB_LEDS */
336
337 /*
338 * Configuration handlers.
339 */
340 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
341 struct rt2x00lib_crypto *crypto,
342 struct ieee80211_key_conf *key)
343 {
344 struct hw_key_entry key_entry;
345 struct rt2x00_field32 field;
346 int timeout;
347 u32 mask;
348 u32 reg;
349
350 if (crypto->cmd == SET_KEY) {
351 /*
352 * rt2x00lib can't determine the correct free
353 * key_idx for shared keys. We have 1 register
354 * with key valid bits. The goal is simple, read
355 * the register, if that is full we have no slots
356 * left.
357 * Note that each BSS is allowed to have up to 4
358 * shared keys, so put a mask over the allowed
359 * entries.
360 */
361 mask = (0xf << crypto->bssidx);
362
363 rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg);
364 reg &= mask;
365
366 if (reg && reg == mask)
367 return -ENOSPC;
368
369 key->hw_key_idx += reg ? ffz(reg) : 0;
370
371 /*
372 * Upload key to hardware
373 */
374 memcpy(key_entry.key, crypto->key,
375 sizeof(key_entry.key));
376 memcpy(key_entry.tx_mic, crypto->tx_mic,
377 sizeof(key_entry.tx_mic));
378 memcpy(key_entry.rx_mic, crypto->rx_mic,
379 sizeof(key_entry.rx_mic));
380
381 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
382 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
383 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
384 USB_VENDOR_REQUEST_OUT, reg,
385 &key_entry,
386 sizeof(key_entry),
387 timeout);
388
389 /*
390 * The cipher types are stored over 2 registers.
391 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
392 * bssidx 1 and 2 keys are stored in SEC_CSR5.
393 * Using the correct defines correctly will cause overhead,
394 * so just calculate the correct offset.
395 */
396 if (key->hw_key_idx < 8) {
397 field.bit_offset = (3 * key->hw_key_idx);
398 field.bit_mask = 0x7 << field.bit_offset;
399
400 rt73usb_register_read(rt2x00dev, SEC_CSR1, &reg);
401 rt2x00_set_field32(&reg, field, crypto->cipher);
402 rt73usb_register_write(rt2x00dev, SEC_CSR1, reg);
403 } else {
404 field.bit_offset = (3 * (key->hw_key_idx - 8));
405 field.bit_mask = 0x7 << field.bit_offset;
406
407 rt73usb_register_read(rt2x00dev, SEC_CSR5, &reg);
408 rt2x00_set_field32(&reg, field, crypto->cipher);
409 rt73usb_register_write(rt2x00dev, SEC_CSR5, reg);
410 }
411
412 /*
413 * The driver does not support the IV/EIV generation
414 * in hardware. However it doesn't support the IV/EIV
415 * inside the ieee80211 frame either, but requires it
416 * to be provided seperately for the descriptor.
417 * rt2x00lib will cut the IV/EIV data out of all frames
418 * given to us by mac80211, but we must tell mac80211
419 * to generate the IV/EIV data.
420 */
421 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
422 }
423
424 /*
425 * SEC_CSR0 contains only single-bit fields to indicate
426 * a particular key is valid. Because using the FIELD32()
427 * defines directly will cause a lot of overhead we use
428 * a calculation to determine the correct bit directly.
429 */
430 mask = 1 << key->hw_key_idx;
431
432 rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg);
433 if (crypto->cmd == SET_KEY)
434 reg |= mask;
435 else if (crypto->cmd == DISABLE_KEY)
436 reg &= ~mask;
437 rt73usb_register_write(rt2x00dev, SEC_CSR0, reg);
438
439 return 0;
440 }
441
442 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
443 struct rt2x00lib_crypto *crypto,
444 struct ieee80211_key_conf *key)
445 {
446 struct hw_pairwise_ta_entry addr_entry;
447 struct hw_key_entry key_entry;
448 int timeout;
449 u32 mask;
450 u32 reg;
451
452 if (crypto->cmd == SET_KEY) {
453 /*
454 * rt2x00lib can't determine the correct free
455 * key_idx for pairwise keys. We have 2 registers
456 * with key valid bits. The goal is simple, read
457 * the first register, if that is full move to
458 * the next register.
459 * When both registers are full, we drop the key,
460 * otherwise we use the first invalid entry.
461 */
462 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg);
463 if (reg && reg == ~0) {
464 key->hw_key_idx = 32;
465 rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg);
466 if (reg && reg == ~0)
467 return -ENOSPC;
468 }
469
470 key->hw_key_idx += reg ? ffz(reg) : 0;
471
472 /*
473 * Upload key to hardware
474 */
475 memcpy(key_entry.key, crypto->key,
476 sizeof(key_entry.key));
477 memcpy(key_entry.tx_mic, crypto->tx_mic,
478 sizeof(key_entry.tx_mic));
479 memcpy(key_entry.rx_mic, crypto->rx_mic,
480 sizeof(key_entry.rx_mic));
481
482 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
483 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
484 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
485 USB_VENDOR_REQUEST_OUT, reg,
486 &key_entry,
487 sizeof(key_entry),
488 timeout);
489
490 /*
491 * Send the address and cipher type to the hardware register.
492 * This data fits within the CSR cache size, so we can use
493 * rt73usb_register_multiwrite() directly.
494 */
495 memset(&addr_entry, 0, sizeof(addr_entry));
496 memcpy(&addr_entry, crypto->address, ETH_ALEN);
497 addr_entry.cipher = crypto->cipher;
498
499 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
500 rt73usb_register_multiwrite(rt2x00dev, reg,
501 &addr_entry, sizeof(addr_entry));
502
503 /*
504 * Enable pairwise lookup table for given BSS idx,
505 * without this received frames will not be decrypted
506 * by the hardware.
507 */
508 rt73usb_register_read(rt2x00dev, SEC_CSR4, &reg);
509 reg |= (1 << crypto->bssidx);
510 rt73usb_register_write(rt2x00dev, SEC_CSR4, reg);
511
512 /*
513 * The driver does not support the IV/EIV generation
514 * in hardware. However it doesn't support the IV/EIV
515 * inside the ieee80211 frame either, but requires it
516 * to be provided seperately for the descriptor.
517 * rt2x00lib will cut the IV/EIV data out of all frames
518 * given to us by mac80211, but we must tell mac80211
519 * to generate the IV/EIV data.
520 */
521 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
522 }
523
524 /*
525 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
526 * a particular key is valid. Because using the FIELD32()
527 * defines directly will cause a lot of overhead we use
528 * a calculation to determine the correct bit directly.
529 */
530 if (key->hw_key_idx < 32) {
531 mask = 1 << key->hw_key_idx;
532
533 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg);
534 if (crypto->cmd == SET_KEY)
535 reg |= mask;
536 else if (crypto->cmd == DISABLE_KEY)
537 reg &= ~mask;
538 rt73usb_register_write(rt2x00dev, SEC_CSR2, reg);
539 } else {
540 mask = 1 << (key->hw_key_idx - 32);
541
542 rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg);
543 if (crypto->cmd == SET_KEY)
544 reg |= mask;
545 else if (crypto->cmd == DISABLE_KEY)
546 reg &= ~mask;
547 rt73usb_register_write(rt2x00dev, SEC_CSR3, reg);
548 }
549
550 return 0;
551 }
552
553 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
554 const unsigned int filter_flags)
555 {
556 u32 reg;
557
558 /*
559 * Start configuration steps.
560 * Note that the version error will always be dropped
561 * and broadcast frames will always be accepted since
562 * there is no filter for it at this time.
563 */
564 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
565 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
566 !(filter_flags & FIF_FCSFAIL));
567 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
568 !(filter_flags & FIF_PLCPFAIL));
569 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
570 !(filter_flags & FIF_CONTROL));
571 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
572 !(filter_flags & FIF_PROMISC_IN_BSS));
573 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
574 !(filter_flags & FIF_PROMISC_IN_BSS) &&
575 !rt2x00dev->intf_ap_count);
576 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
577 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
578 !(filter_flags & FIF_ALLMULTI));
579 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
580 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
581 !(filter_flags & FIF_CONTROL));
582 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
583 }
584
585 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
586 struct rt2x00_intf *intf,
587 struct rt2x00intf_conf *conf,
588 const unsigned int flags)
589 {
590 unsigned int beacon_base;
591 u32 reg;
592
593 if (flags & CONFIG_UPDATE_TYPE) {
594 /*
595 * Clear current synchronisation setup.
596 * For the Beacon base registers we only need to clear
597 * the first byte since that byte contains the VALID and OWNER
598 * bits which (when set to 0) will invalidate the entire beacon.
599 */
600 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
601 rt73usb_register_write(rt2x00dev, beacon_base, 0);
602
603 /*
604 * Enable synchronisation.
605 */
606 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
607 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
608 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
609 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
610 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
611 }
612
613 if (flags & CONFIG_UPDATE_MAC) {
614 reg = le32_to_cpu(conf->mac[1]);
615 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
616 conf->mac[1] = cpu_to_le32(reg);
617
618 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
619 conf->mac, sizeof(conf->mac));
620 }
621
622 if (flags & CONFIG_UPDATE_BSSID) {
623 reg = le32_to_cpu(conf->bssid[1]);
624 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
625 conf->bssid[1] = cpu_to_le32(reg);
626
627 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
628 conf->bssid, sizeof(conf->bssid));
629 }
630 }
631
632 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
633 struct rt2x00lib_erp *erp)
634 {
635 u32 reg;
636
637 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
638 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
639 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
640
641 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
642 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
643 !!erp->short_preamble);
644 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
645
646 rt73usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
647
648 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
649 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
650 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
651
652 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
653 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
654 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
655 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
656 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
657 }
658
659 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
660 struct antenna_setup *ant)
661 {
662 u8 r3;
663 u8 r4;
664 u8 r77;
665 u8 temp;
666
667 rt73usb_bbp_read(rt2x00dev, 3, &r3);
668 rt73usb_bbp_read(rt2x00dev, 4, &r4);
669 rt73usb_bbp_read(rt2x00dev, 77, &r77);
670
671 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
672
673 /*
674 * Configure the RX antenna.
675 */
676 switch (ant->rx) {
677 case ANTENNA_HW_DIVERSITY:
678 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
679 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
680 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
681 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
682 break;
683 case ANTENNA_A:
684 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
685 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
686 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
687 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
688 else
689 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
690 break;
691 case ANTENNA_B:
692 default:
693 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
694 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
695 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
696 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
697 else
698 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
699 break;
700 }
701
702 rt73usb_bbp_write(rt2x00dev, 77, r77);
703 rt73usb_bbp_write(rt2x00dev, 3, r3);
704 rt73usb_bbp_write(rt2x00dev, 4, r4);
705 }
706
707 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
708 struct antenna_setup *ant)
709 {
710 u8 r3;
711 u8 r4;
712 u8 r77;
713
714 rt73usb_bbp_read(rt2x00dev, 3, &r3);
715 rt73usb_bbp_read(rt2x00dev, 4, &r4);
716 rt73usb_bbp_read(rt2x00dev, 77, &r77);
717
718 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
719 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
720 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
721
722 /*
723 * Configure the RX antenna.
724 */
725 switch (ant->rx) {
726 case ANTENNA_HW_DIVERSITY:
727 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
728 break;
729 case ANTENNA_A:
730 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
731 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
732 break;
733 case ANTENNA_B:
734 default:
735 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
736 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
737 break;
738 }
739
740 rt73usb_bbp_write(rt2x00dev, 77, r77);
741 rt73usb_bbp_write(rt2x00dev, 3, r3);
742 rt73usb_bbp_write(rt2x00dev, 4, r4);
743 }
744
745 struct antenna_sel {
746 u8 word;
747 /*
748 * value[0] -> non-LNA
749 * value[1] -> LNA
750 */
751 u8 value[2];
752 };
753
754 static const struct antenna_sel antenna_sel_a[] = {
755 { 96, { 0x58, 0x78 } },
756 { 104, { 0x38, 0x48 } },
757 { 75, { 0xfe, 0x80 } },
758 { 86, { 0xfe, 0x80 } },
759 { 88, { 0xfe, 0x80 } },
760 { 35, { 0x60, 0x60 } },
761 { 97, { 0x58, 0x58 } },
762 { 98, { 0x58, 0x58 } },
763 };
764
765 static const struct antenna_sel antenna_sel_bg[] = {
766 { 96, { 0x48, 0x68 } },
767 { 104, { 0x2c, 0x3c } },
768 { 75, { 0xfe, 0x80 } },
769 { 86, { 0xfe, 0x80 } },
770 { 88, { 0xfe, 0x80 } },
771 { 35, { 0x50, 0x50 } },
772 { 97, { 0x48, 0x48 } },
773 { 98, { 0x48, 0x48 } },
774 };
775
776 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
777 struct antenna_setup *ant)
778 {
779 const struct antenna_sel *sel;
780 unsigned int lna;
781 unsigned int i;
782 u32 reg;
783
784 /*
785 * We should never come here because rt2x00lib is supposed
786 * to catch this and send us the correct antenna explicitely.
787 */
788 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
789 ant->tx == ANTENNA_SW_DIVERSITY);
790
791 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
792 sel = antenna_sel_a;
793 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
794 } else {
795 sel = antenna_sel_bg;
796 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
797 }
798
799 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
800 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
801
802 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
803
804 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
805 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
806 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
807 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
808
809 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
810
811 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
812 rt2x00_rf(&rt2x00dev->chip, RF5225))
813 rt73usb_config_antenna_5x(rt2x00dev, ant);
814 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
815 rt2x00_rf(&rt2x00dev->chip, RF2527))
816 rt73usb_config_antenna_2x(rt2x00dev, ant);
817 }
818
819 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
820 struct rt2x00lib_conf *libconf)
821 {
822 u16 eeprom;
823 short lna_gain = 0;
824
825 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
826 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
827 lna_gain += 14;
828
829 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
830 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
831 } else {
832 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
833 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
834 }
835
836 rt2x00dev->lna_gain = lna_gain;
837 }
838
839 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
840 struct rf_channel *rf, const int txpower)
841 {
842 u8 r3;
843 u8 r94;
844 u8 smart;
845
846 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
847 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
848
849 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
850 rt2x00_rf(&rt2x00dev->chip, RF2527));
851
852 rt73usb_bbp_read(rt2x00dev, 3, &r3);
853 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
854 rt73usb_bbp_write(rt2x00dev, 3, r3);
855
856 r94 = 6;
857 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
858 r94 += txpower - MAX_TXPOWER;
859 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
860 r94 += txpower;
861 rt73usb_bbp_write(rt2x00dev, 94, r94);
862
863 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
864 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
865 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
866 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
867
868 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
869 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
870 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
871 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
872
873 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
874 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
875 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
876 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
877
878 udelay(10);
879 }
880
881 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
882 const int txpower)
883 {
884 struct rf_channel rf;
885
886 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
887 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
888 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
889 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
890
891 rt73usb_config_channel(rt2x00dev, &rf, txpower);
892 }
893
894 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
895 struct rt2x00lib_conf *libconf)
896 {
897 u32 reg;
898
899 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
900 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
901 libconf->conf->long_frame_max_tx_count);
902 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
903 libconf->conf->short_frame_max_tx_count);
904 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
905 }
906
907 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
908 struct rt2x00lib_conf *libconf)
909 {
910 u32 reg;
911
912 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
913 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
914 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
915
916 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
917 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
918 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
919
920 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
921 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
922 libconf->conf->beacon_int * 16);
923 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
924 }
925
926 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
927 struct rt2x00lib_conf *libconf,
928 const unsigned int flags)
929 {
930 /* Always recalculate LNA gain before changing configuration */
931 rt73usb_config_lna_gain(rt2x00dev, libconf);
932
933 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
934 rt73usb_config_channel(rt2x00dev, &libconf->rf,
935 libconf->conf->power_level);
936 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
937 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
938 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
939 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
940 rt73usb_config_retry_limit(rt2x00dev, libconf);
941 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
942 rt73usb_config_duration(rt2x00dev, libconf);
943 }
944
945 /*
946 * Link tuning
947 */
948 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
949 struct link_qual *qual)
950 {
951 u32 reg;
952
953 /*
954 * Update FCS error count from register.
955 */
956 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
957 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
958
959 /*
960 * Update False CCA count from register.
961 */
962 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
963 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
964 }
965
966 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
967 {
968 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
969 rt2x00dev->link.vgc_level = 0x20;
970 }
971
972 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
973 {
974 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
975 u8 r17;
976 u8 up_bound;
977 u8 low_bound;
978
979 rt73usb_bbp_read(rt2x00dev, 17, &r17);
980
981 /*
982 * Determine r17 bounds.
983 */
984 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
985 low_bound = 0x28;
986 up_bound = 0x48;
987
988 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
989 low_bound += 0x10;
990 up_bound += 0x10;
991 }
992 } else {
993 if (rssi > -82) {
994 low_bound = 0x1c;
995 up_bound = 0x40;
996 } else if (rssi > -84) {
997 low_bound = 0x1c;
998 up_bound = 0x20;
999 } else {
1000 low_bound = 0x1c;
1001 up_bound = 0x1c;
1002 }
1003
1004 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1005 low_bound += 0x14;
1006 up_bound += 0x10;
1007 }
1008 }
1009
1010 /*
1011 * If we are not associated, we should go straight to the
1012 * dynamic CCA tuning.
1013 */
1014 if (!rt2x00dev->intf_associated)
1015 goto dynamic_cca_tune;
1016
1017 /*
1018 * Special big-R17 for very short distance
1019 */
1020 if (rssi > -35) {
1021 if (r17 != 0x60)
1022 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
1023 return;
1024 }
1025
1026 /*
1027 * Special big-R17 for short distance
1028 */
1029 if (rssi >= -58) {
1030 if (r17 != up_bound)
1031 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
1032 return;
1033 }
1034
1035 /*
1036 * Special big-R17 for middle-short distance
1037 */
1038 if (rssi >= -66) {
1039 low_bound += 0x10;
1040 if (r17 != low_bound)
1041 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
1042 return;
1043 }
1044
1045 /*
1046 * Special mid-R17 for middle distance
1047 */
1048 if (rssi >= -74) {
1049 if (r17 != (low_bound + 0x10))
1050 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
1051 return;
1052 }
1053
1054 /*
1055 * Special case: Change up_bound based on the rssi.
1056 * Lower up_bound when rssi is weaker then -74 dBm.
1057 */
1058 up_bound -= 2 * (-74 - rssi);
1059 if (low_bound > up_bound)
1060 up_bound = low_bound;
1061
1062 if (r17 > up_bound) {
1063 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
1064 return;
1065 }
1066
1067 dynamic_cca_tune:
1068
1069 /*
1070 * r17 does not yet exceed upper limit, continue and base
1071 * the r17 tuning on the false CCA count.
1072 */
1073 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
1074 r17 += 4;
1075 if (r17 > up_bound)
1076 r17 = up_bound;
1077 rt73usb_bbp_write(rt2x00dev, 17, r17);
1078 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
1079 r17 -= 4;
1080 if (r17 < low_bound)
1081 r17 = low_bound;
1082 rt73usb_bbp_write(rt2x00dev, 17, r17);
1083 }
1084 }
1085
1086 /*
1087 * Firmware functions
1088 */
1089 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1090 {
1091 return FIRMWARE_RT2571;
1092 }
1093
1094 static u16 rt73usb_get_firmware_crc(const void *data, const size_t len)
1095 {
1096 u16 crc;
1097
1098 /*
1099 * Use the crc itu-t algorithm.
1100 * The last 2 bytes in the firmware array are the crc checksum itself,
1101 * this means that we should never pass those 2 bytes to the crc
1102 * algorithm.
1103 */
1104 crc = crc_itu_t(0, data, len - 2);
1105 crc = crc_itu_t_byte(crc, 0);
1106 crc = crc_itu_t_byte(crc, 0);
1107
1108 return crc;
1109 }
1110
1111 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1112 const size_t len)
1113 {
1114 unsigned int i;
1115 int status;
1116 u32 reg;
1117
1118 /*
1119 * Wait for stable hardware.
1120 */
1121 for (i = 0; i < 100; i++) {
1122 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1123 if (reg)
1124 break;
1125 msleep(1);
1126 }
1127
1128 if (!reg) {
1129 ERROR(rt2x00dev, "Unstable hardware.\n");
1130 return -EBUSY;
1131 }
1132
1133 /*
1134 * Write firmware to device.
1135 */
1136 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1137 USB_VENDOR_REQUEST_OUT,
1138 FIRMWARE_IMAGE_BASE,
1139 data, len,
1140 REGISTER_TIMEOUT32(len));
1141
1142 /*
1143 * Send firmware request to device to load firmware,
1144 * we need to specify a long timeout time.
1145 */
1146 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1147 0, USB_MODE_FIRMWARE,
1148 REGISTER_TIMEOUT_FIRMWARE);
1149 if (status < 0) {
1150 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1151 return status;
1152 }
1153
1154 return 0;
1155 }
1156
1157 /*
1158 * Initialization functions.
1159 */
1160 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1161 {
1162 u32 reg;
1163
1164 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1165 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1166 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1167 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1168 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1169
1170 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1171 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1172 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1173 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1174 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1175 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1176 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1177 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1178 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1179 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1180
1181 /*
1182 * CCK TXD BBP registers
1183 */
1184 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1185 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1186 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1187 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1188 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1189 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1190 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1191 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1192 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1193 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1194
1195 /*
1196 * OFDM TXD BBP registers
1197 */
1198 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1199 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1200 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1201 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1202 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1203 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1204 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1205 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1206
1207 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1208 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1209 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1210 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1211 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1212 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1213
1214 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1215 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1216 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1217 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1218 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1219 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1220
1221 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1222 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1223 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1224 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1225 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1226 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1227 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1228 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1229
1230 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1231
1232 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1233 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1234 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
1235
1236 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1237
1238 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1239 return -EBUSY;
1240
1241 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1242
1243 /*
1244 * Invalidate all Shared Keys (SEC_CSR0),
1245 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1246 */
1247 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1248 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1249 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1250
1251 reg = 0x000023b0;
1252 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1253 rt2x00_rf(&rt2x00dev->chip, RF2527))
1254 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1255 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1256
1257 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1258 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1259 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1260
1261 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1262 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1263 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1264
1265 /*
1266 * Clear all beacons
1267 * For the Beacon base registers we only need to clear
1268 * the first byte since that byte contains the VALID and OWNER
1269 * bits which (when set to 0) will invalidate the entire beacon.
1270 */
1271 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1272 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1273 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1274 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1275
1276 /*
1277 * We must clear the error counters.
1278 * These registers are cleared on read,
1279 * so we may pass a useless variable to store the value.
1280 */
1281 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1282 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1283 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1284
1285 /*
1286 * Reset MAC and BBP registers.
1287 */
1288 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1289 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1290 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1291 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1292
1293 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1294 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1295 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1296 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1297
1298 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1299 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1300 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1301
1302 return 0;
1303 }
1304
1305 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1306 {
1307 unsigned int i;
1308 u8 value;
1309
1310 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1311 rt73usb_bbp_read(rt2x00dev, 0, &value);
1312 if ((value != 0xff) && (value != 0x00))
1313 return 0;
1314 udelay(REGISTER_BUSY_DELAY);
1315 }
1316
1317 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1318 return -EACCES;
1319 }
1320
1321 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1322 {
1323 unsigned int i;
1324 u16 eeprom;
1325 u8 reg_id;
1326 u8 value;
1327
1328 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1329 return -EACCES;
1330
1331 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1332 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1333 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1334 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1335 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1336 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1337 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1338 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1339 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1340 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1341 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1342 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1343 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1344 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1345 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1346 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1347 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1348 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1349 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1350 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1351 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1352 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1353 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1354 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1355 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1356
1357 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1358 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1359
1360 if (eeprom != 0xffff && eeprom != 0x0000) {
1361 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1362 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1363 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1364 }
1365 }
1366
1367 return 0;
1368 }
1369
1370 /*
1371 * Device state switch handlers.
1372 */
1373 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1374 enum dev_state state)
1375 {
1376 u32 reg;
1377
1378 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1379 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1380 (state == STATE_RADIO_RX_OFF) ||
1381 (state == STATE_RADIO_RX_OFF_LINK));
1382 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1383 }
1384
1385 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1386 {
1387 /*
1388 * Initialize all registers.
1389 */
1390 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1391 rt73usb_init_bbp(rt2x00dev)))
1392 return -EIO;
1393
1394 return 0;
1395 }
1396
1397 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1398 {
1399 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1400
1401 /*
1402 * Disable synchronisation.
1403 */
1404 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1405
1406 rt2x00usb_disable_radio(rt2x00dev);
1407 }
1408
1409 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1410 {
1411 u32 reg;
1412 unsigned int i;
1413 char put_to_sleep;
1414
1415 put_to_sleep = (state != STATE_AWAKE);
1416
1417 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1418 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1419 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1420 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1421
1422 /*
1423 * Device is not guaranteed to be in the requested state yet.
1424 * We must wait until the register indicates that the
1425 * device has entered the correct state.
1426 */
1427 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1428 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1429 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1430 if (state == !put_to_sleep)
1431 return 0;
1432 msleep(10);
1433 }
1434
1435 return -EBUSY;
1436 }
1437
1438 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1439 enum dev_state state)
1440 {
1441 int retval = 0;
1442
1443 switch (state) {
1444 case STATE_RADIO_ON:
1445 retval = rt73usb_enable_radio(rt2x00dev);
1446 break;
1447 case STATE_RADIO_OFF:
1448 rt73usb_disable_radio(rt2x00dev);
1449 break;
1450 case STATE_RADIO_RX_ON:
1451 case STATE_RADIO_RX_ON_LINK:
1452 case STATE_RADIO_RX_OFF:
1453 case STATE_RADIO_RX_OFF_LINK:
1454 rt73usb_toggle_rx(rt2x00dev, state);
1455 break;
1456 case STATE_RADIO_IRQ_ON:
1457 case STATE_RADIO_IRQ_OFF:
1458 /* No support, but no error either */
1459 break;
1460 case STATE_DEEP_SLEEP:
1461 case STATE_SLEEP:
1462 case STATE_STANDBY:
1463 case STATE_AWAKE:
1464 retval = rt73usb_set_state(rt2x00dev, state);
1465 break;
1466 default:
1467 retval = -ENOTSUPP;
1468 break;
1469 }
1470
1471 if (unlikely(retval))
1472 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1473 state, retval);
1474
1475 return retval;
1476 }
1477
1478 /*
1479 * TX descriptor initialization
1480 */
1481 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1482 struct sk_buff *skb,
1483 struct txentry_desc *txdesc)
1484 {
1485 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1486 __le32 *txd = skbdesc->desc;
1487 u32 word;
1488
1489 /*
1490 * Start writing the descriptor words.
1491 */
1492 rt2x00_desc_read(txd, 1, &word);
1493 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1494 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1495 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1496 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1497 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1498 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1499 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1500 rt2x00_desc_write(txd, 1, word);
1501
1502 rt2x00_desc_read(txd, 2, &word);
1503 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1504 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1505 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1506 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1507 rt2x00_desc_write(txd, 2, word);
1508
1509 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1510 _rt2x00_desc_write(txd, 3, skbdesc->iv);
1511 _rt2x00_desc_write(txd, 4, skbdesc->eiv);
1512 }
1513
1514 rt2x00_desc_read(txd, 5, &word);
1515 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1516 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1517 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1518 rt2x00_desc_write(txd, 5, word);
1519
1520 rt2x00_desc_read(txd, 0, &word);
1521 rt2x00_set_field32(&word, TXD_W0_BURST,
1522 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1523 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1524 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1525 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1526 rt2x00_set_field32(&word, TXD_W0_ACK,
1527 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1528 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1529 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1530 rt2x00_set_field32(&word, TXD_W0_OFDM,
1531 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1532 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1533 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1534 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1535 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1536 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1537 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1538 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1539 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1540 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1541 rt2x00_set_field32(&word, TXD_W0_BURST2,
1542 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1543 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1544 rt2x00_desc_write(txd, 0, word);
1545 }
1546
1547 /*
1548 * TX data initialization
1549 */
1550 static void rt73usb_write_beacon(struct queue_entry *entry)
1551 {
1552 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1553 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1554 unsigned int beacon_base;
1555 u32 reg;
1556
1557 /*
1558 * Add the descriptor in front of the skb.
1559 */
1560 skb_push(entry->skb, entry->queue->desc_size);
1561 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1562 skbdesc->desc = entry->skb->data;
1563
1564 /*
1565 * Disable beaconing while we are reloading the beacon data,
1566 * otherwise we might be sending out invalid data.
1567 */
1568 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1569 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1570 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1571 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1572 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1573
1574 /*
1575 * Write entire beacon with descriptor to register.
1576 */
1577 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1578 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1579 USB_VENDOR_REQUEST_OUT, beacon_base,
1580 entry->skb->data, entry->skb->len,
1581 REGISTER_TIMEOUT32(entry->skb->len));
1582
1583 /*
1584 * Clean up the beacon skb.
1585 */
1586 dev_kfree_skb(entry->skb);
1587 entry->skb = NULL;
1588 }
1589
1590 static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1591 struct sk_buff *skb)
1592 {
1593 int length;
1594
1595 /*
1596 * The length _must_ be a multiple of 4,
1597 * but it must _not_ be a multiple of the USB packet size.
1598 */
1599 length = roundup(skb->len, 4);
1600 length += (4 * !(length % rt2x00dev->usb_maxpacket));
1601
1602 return length;
1603 }
1604
1605 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1606 const enum data_queue_qid queue)
1607 {
1608 u32 reg;
1609
1610 if (queue != QID_BEACON) {
1611 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
1612 return;
1613 }
1614
1615 /*
1616 * For Wi-Fi faily generated beacons between participating stations.
1617 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1618 */
1619 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1620
1621 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1622 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1623 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1624 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1625 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1626 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1627 }
1628 }
1629
1630 /*
1631 * RX control handlers
1632 */
1633 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1634 {
1635 u8 offset = rt2x00dev->lna_gain;
1636 u8 lna;
1637
1638 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1639 switch (lna) {
1640 case 3:
1641 offset += 90;
1642 break;
1643 case 2:
1644 offset += 74;
1645 break;
1646 case 1:
1647 offset += 64;
1648 break;
1649 default:
1650 return 0;
1651 }
1652
1653 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1654 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1655 if (lna == 3 || lna == 2)
1656 offset += 10;
1657 } else {
1658 if (lna == 3)
1659 offset += 6;
1660 else if (lna == 2)
1661 offset += 8;
1662 }
1663 }
1664
1665 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1666 }
1667
1668 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1669 struct rxdone_entry_desc *rxdesc)
1670 {
1671 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1672 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1673 __le32 *rxd = (__le32 *)entry->skb->data;
1674 u32 word0;
1675 u32 word1;
1676
1677 /*
1678 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1679 * frame data in rt2x00usb.
1680 */
1681 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1682 rxd = (__le32 *)skbdesc->desc;
1683
1684 /*
1685 * It is now safe to read the descriptor on all architectures.
1686 */
1687 rt2x00_desc_read(rxd, 0, &word0);
1688 rt2x00_desc_read(rxd, 1, &word1);
1689
1690 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1691 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1692
1693 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1694 rxdesc->cipher =
1695 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1696 rxdesc->cipher_status =
1697 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1698 }
1699
1700 if (rxdesc->cipher != CIPHER_NONE) {
1701 _rt2x00_desc_read(rxd, 2, &rxdesc->iv);
1702 _rt2x00_desc_read(rxd, 3, &rxdesc->eiv);
1703 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1704
1705 /*
1706 * Hardware has stripped IV/EIV data from 802.11 frame during
1707 * decryption. It has provided the data seperately but rt2x00lib
1708 * should decide if it should be reinserted.
1709 */
1710 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1711
1712 /*
1713 * FIXME: Legacy driver indicates that the frame does
1714 * contain the Michael Mic. Unfortunately, in rt2x00
1715 * the MIC seems to be missing completely...
1716 */
1717 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1718
1719 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1720 rxdesc->flags |= RX_FLAG_DECRYPTED;
1721 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1722 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1723 }
1724
1725 /*
1726 * Obtain the status about this packet.
1727 * When frame was received with an OFDM bitrate,
1728 * the signal is the PLCP value. If it was received with
1729 * a CCK bitrate the signal is the rate in 100kbit/s.
1730 */
1731 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1732 rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1733 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1734
1735 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1736 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1737 else
1738 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1739 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1740 rxdesc->dev_flags |= RXDONE_MY_BSS;
1741
1742 /*
1743 * Set skb pointers, and update frame information.
1744 */
1745 skb_pull(entry->skb, entry->queue->desc_size);
1746 skb_trim(entry->skb, rxdesc->size);
1747 }
1748
1749 /*
1750 * Device probe functions.
1751 */
1752 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1753 {
1754 u16 word;
1755 u8 *mac;
1756 s8 value;
1757
1758 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1759
1760 /*
1761 * Start validation of the data that has been read.
1762 */
1763 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1764 if (!is_valid_ether_addr(mac)) {
1765 random_ether_addr(mac);
1766 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1767 }
1768
1769 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1770 if (word == 0xffff) {
1771 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1772 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1773 ANTENNA_B);
1774 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1775 ANTENNA_B);
1776 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1777 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1778 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1779 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1780 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1781 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1782 }
1783
1784 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1785 if (word == 0xffff) {
1786 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1787 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1788 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1789 }
1790
1791 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1792 if (word == 0xffff) {
1793 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1794 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1795 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1796 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1797 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1798 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1799 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1800 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1801 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1802 LED_MODE_DEFAULT);
1803 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1804 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1805 }
1806
1807 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1808 if (word == 0xffff) {
1809 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1810 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1811 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1812 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1813 }
1814
1815 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1816 if (word == 0xffff) {
1817 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1818 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1819 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1820 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1821 } else {
1822 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1823 if (value < -10 || value > 10)
1824 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1825 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1826 if (value < -10 || value > 10)
1827 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1828 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1829 }
1830
1831 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1832 if (word == 0xffff) {
1833 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1834 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1835 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1836 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1837 } else {
1838 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1839 if (value < -10 || value > 10)
1840 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1841 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1842 if (value < -10 || value > 10)
1843 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1844 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1845 }
1846
1847 return 0;
1848 }
1849
1850 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1851 {
1852 u32 reg;
1853 u16 value;
1854 u16 eeprom;
1855
1856 /*
1857 * Read EEPROM word for configuration.
1858 */
1859 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1860
1861 /*
1862 * Identify RF chipset.
1863 */
1864 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1865 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1866 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1867
1868 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1869 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1870 return -ENODEV;
1871 }
1872
1873 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1874 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1875 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1876 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1877 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1878 return -ENODEV;
1879 }
1880
1881 /*
1882 * Identify default antenna configuration.
1883 */
1884 rt2x00dev->default_ant.tx =
1885 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1886 rt2x00dev->default_ant.rx =
1887 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1888
1889 /*
1890 * Read the Frame type.
1891 */
1892 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1893 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1894
1895 /*
1896 * Read frequency offset.
1897 */
1898 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1899 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1900
1901 /*
1902 * Read external LNA informations.
1903 */
1904 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1905
1906 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1907 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1908 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1909 }
1910
1911 /*
1912 * Store led settings, for correct led behaviour.
1913 */
1914 #ifdef CONFIG_RT2X00_LIB_LEDS
1915 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1916
1917 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1918 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1919 if (value == LED_MODE_SIGNAL_STRENGTH)
1920 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1921 LED_TYPE_QUALITY);
1922
1923 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1924 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1925 rt2x00_get_field16(eeprom,
1926 EEPROM_LED_POLARITY_GPIO_0));
1927 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1928 rt2x00_get_field16(eeprom,
1929 EEPROM_LED_POLARITY_GPIO_1));
1930 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1931 rt2x00_get_field16(eeprom,
1932 EEPROM_LED_POLARITY_GPIO_2));
1933 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1934 rt2x00_get_field16(eeprom,
1935 EEPROM_LED_POLARITY_GPIO_3));
1936 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1937 rt2x00_get_field16(eeprom,
1938 EEPROM_LED_POLARITY_GPIO_4));
1939 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1940 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1941 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1942 rt2x00_get_field16(eeprom,
1943 EEPROM_LED_POLARITY_RDY_G));
1944 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1945 rt2x00_get_field16(eeprom,
1946 EEPROM_LED_POLARITY_RDY_A));
1947 #endif /* CONFIG_RT2X00_LIB_LEDS */
1948
1949 return 0;
1950 }
1951
1952 /*
1953 * RF value list for RF2528
1954 * Supports: 2.4 GHz
1955 */
1956 static const struct rf_channel rf_vals_bg_2528[] = {
1957 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1958 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1959 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1960 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1961 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1962 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1963 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1964 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1965 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1966 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1967 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1968 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1969 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1970 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1971 };
1972
1973 /*
1974 * RF value list for RF5226
1975 * Supports: 2.4 GHz & 5.2 GHz
1976 */
1977 static const struct rf_channel rf_vals_5226[] = {
1978 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1979 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1980 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1981 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1982 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1983 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1984 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1985 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1986 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1987 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1988 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1989 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1990 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1991 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1992
1993 /* 802.11 UNI / HyperLan 2 */
1994 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1995 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1996 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1997 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1998 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1999 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
2000 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
2001 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
2002
2003 /* 802.11 HyperLan 2 */
2004 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
2005 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
2006 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
2007 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
2008 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
2009 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
2010 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
2011 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
2012 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
2013 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
2014
2015 /* 802.11 UNII */
2016 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2017 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2018 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2019 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2020 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2021 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2022
2023 /* MMAC(Japan)J52 ch 34,38,42,46 */
2024 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2025 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2026 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2027 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2028 };
2029
2030 /*
2031 * RF value list for RF5225 & RF2527
2032 * Supports: 2.4 GHz & 5.2 GHz
2033 */
2034 static const struct rf_channel rf_vals_5225_2527[] = {
2035 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2036 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2037 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2038 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2039 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2040 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2041 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2042 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2043 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2044 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2045 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2046 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2047 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2048 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2049
2050 /* 802.11 UNI / HyperLan 2 */
2051 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2052 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2053 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2054 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2055 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2056 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2057 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2058 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2059
2060 /* 802.11 HyperLan 2 */
2061 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2062 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2063 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2064 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2065 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2066 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2067 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2068 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2069 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2070 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2071
2072 /* 802.11 UNII */
2073 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2074 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2075 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2076 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2077 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2078 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2079
2080 /* MMAC(Japan)J52 ch 34,38,42,46 */
2081 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2082 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2083 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2084 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2085 };
2086
2087
2088 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2089 {
2090 struct hw_mode_spec *spec = &rt2x00dev->spec;
2091 struct channel_info *info;
2092 char *tx_power;
2093 unsigned int i;
2094
2095 /*
2096 * Initialize all hw fields.
2097 */
2098 rt2x00dev->hw->flags =
2099 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2100 IEEE80211_HW_SIGNAL_DBM;
2101 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
2102
2103 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2104 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2105 rt2x00_eeprom_addr(rt2x00dev,
2106 EEPROM_MAC_ADDR_0));
2107
2108 /*
2109 * Initialize hw_mode information.
2110 */
2111 spec->supported_bands = SUPPORT_BAND_2GHZ;
2112 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2113
2114 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
2115 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2116 spec->channels = rf_vals_bg_2528;
2117 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
2118 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2119 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2120 spec->channels = rf_vals_5226;
2121 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
2122 spec->num_channels = 14;
2123 spec->channels = rf_vals_5225_2527;
2124 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
2125 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2126 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2127 spec->channels = rf_vals_5225_2527;
2128 }
2129
2130 /*
2131 * Create channel information array
2132 */
2133 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2134 if (!info)
2135 return -ENOMEM;
2136
2137 spec->channels_info = info;
2138
2139 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2140 for (i = 0; i < 14; i++)
2141 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2142
2143 if (spec->num_channels > 14) {
2144 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2145 for (i = 14; i < spec->num_channels; i++)
2146 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2147 }
2148
2149 return 0;
2150 }
2151
2152 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2153 {
2154 int retval;
2155
2156 /*
2157 * Allocate eeprom data.
2158 */
2159 retval = rt73usb_validate_eeprom(rt2x00dev);
2160 if (retval)
2161 return retval;
2162
2163 retval = rt73usb_init_eeprom(rt2x00dev);
2164 if (retval)
2165 return retval;
2166
2167 /*
2168 * Initialize hw specifications.
2169 */
2170 retval = rt73usb_probe_hw_mode(rt2x00dev);
2171 if (retval)
2172 return retval;
2173
2174 /*
2175 * This device requires firmware.
2176 */
2177 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2178 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2179 if (!modparam_nohwcrypt)
2180 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2181
2182 /*
2183 * Set the rssi offset.
2184 */
2185 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2186
2187 return 0;
2188 }
2189
2190 /*
2191 * IEEE80211 stack callback functions.
2192 */
2193 static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2194 const struct ieee80211_tx_queue_params *params)
2195 {
2196 struct rt2x00_dev *rt2x00dev = hw->priv;
2197 struct data_queue *queue;
2198 struct rt2x00_field32 field;
2199 int retval;
2200 u32 reg;
2201
2202 /*
2203 * First pass the configuration through rt2x00lib, that will
2204 * update the queue settings and validate the input. After that
2205 * we are free to update the registers based on the value
2206 * in the queue parameter.
2207 */
2208 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2209 if (retval)
2210 return retval;
2211
2212 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2213
2214 /* Update WMM TXOP register */
2215 if (queue_idx < 2) {
2216 field.bit_offset = queue_idx * 16;
2217 field.bit_mask = 0xffff << field.bit_offset;
2218
2219 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
2220 rt2x00_set_field32(&reg, field, queue->txop);
2221 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2222 } else if (queue_idx < 4) {
2223 field.bit_offset = (queue_idx - 2) * 16;
2224 field.bit_mask = 0xffff << field.bit_offset;
2225
2226 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
2227 rt2x00_set_field32(&reg, field, queue->txop);
2228 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2229 }
2230
2231 /* Update WMM registers */
2232 field.bit_offset = queue_idx * 4;
2233 field.bit_mask = 0xf << field.bit_offset;
2234
2235 rt73usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2236 rt2x00_set_field32(&reg, field, queue->aifs);
2237 rt73usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2238
2239 rt73usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2240 rt2x00_set_field32(&reg, field, queue->cw_min);
2241 rt73usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2242
2243 rt73usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2244 rt2x00_set_field32(&reg, field, queue->cw_max);
2245 rt73usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2246
2247 return 0;
2248 }
2249
2250 #if 0
2251 /*
2252 * Mac80211 demands get_tsf must be atomic.
2253 * This is not possible for rt73usb since all register access
2254 * functions require sleeping. Untill mac80211 no longer needs
2255 * get_tsf to be atomic, this function should be disabled.
2256 */
2257 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2258 {
2259 struct rt2x00_dev *rt2x00dev = hw->priv;
2260 u64 tsf;
2261 u32 reg;
2262
2263 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2264 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2265 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2266 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2267
2268 return tsf;
2269 }
2270 #else
2271 #define rt73usb_get_tsf NULL
2272 #endif
2273
2274 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2275 .tx = rt2x00mac_tx,
2276 .start = rt2x00mac_start,
2277 .stop = rt2x00mac_stop,
2278 .add_interface = rt2x00mac_add_interface,
2279 .remove_interface = rt2x00mac_remove_interface,
2280 .config = rt2x00mac_config,
2281 .config_interface = rt2x00mac_config_interface,
2282 .configure_filter = rt2x00mac_configure_filter,
2283 .set_key = rt2x00mac_set_key,
2284 .get_stats = rt2x00mac_get_stats,
2285 .bss_info_changed = rt2x00mac_bss_info_changed,
2286 .conf_tx = rt73usb_conf_tx,
2287 .get_tx_stats = rt2x00mac_get_tx_stats,
2288 .get_tsf = rt73usb_get_tsf,
2289 };
2290
2291 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2292 .probe_hw = rt73usb_probe_hw,
2293 .get_firmware_name = rt73usb_get_firmware_name,
2294 .get_firmware_crc = rt73usb_get_firmware_crc,
2295 .load_firmware = rt73usb_load_firmware,
2296 .initialize = rt2x00usb_initialize,
2297 .uninitialize = rt2x00usb_uninitialize,
2298 .clear_entry = rt2x00usb_clear_entry,
2299 .set_device_state = rt73usb_set_device_state,
2300 .link_stats = rt73usb_link_stats,
2301 .reset_tuner = rt73usb_reset_tuner,
2302 .link_tuner = rt73usb_link_tuner,
2303 .write_tx_desc = rt73usb_write_tx_desc,
2304 .write_tx_data = rt2x00usb_write_tx_data,
2305 .write_beacon = rt73usb_write_beacon,
2306 .get_tx_data_len = rt73usb_get_tx_data_len,
2307 .kick_tx_queue = rt73usb_kick_tx_queue,
2308 .fill_rxdone = rt73usb_fill_rxdone,
2309 .config_shared_key = rt73usb_config_shared_key,
2310 .config_pairwise_key = rt73usb_config_pairwise_key,
2311 .config_filter = rt73usb_config_filter,
2312 .config_intf = rt73usb_config_intf,
2313 .config_erp = rt73usb_config_erp,
2314 .config_ant = rt73usb_config_ant,
2315 .config = rt73usb_config,
2316 };
2317
2318 static const struct data_queue_desc rt73usb_queue_rx = {
2319 .entry_num = RX_ENTRIES,
2320 .data_size = DATA_FRAME_SIZE,
2321 .desc_size = RXD_DESC_SIZE,
2322 .priv_size = sizeof(struct queue_entry_priv_usb),
2323 };
2324
2325 static const struct data_queue_desc rt73usb_queue_tx = {
2326 .entry_num = TX_ENTRIES,
2327 .data_size = DATA_FRAME_SIZE,
2328 .desc_size = TXD_DESC_SIZE,
2329 .priv_size = sizeof(struct queue_entry_priv_usb),
2330 };
2331
2332 static const struct data_queue_desc rt73usb_queue_bcn = {
2333 .entry_num = 4 * BEACON_ENTRIES,
2334 .data_size = MGMT_FRAME_SIZE,
2335 .desc_size = TXINFO_SIZE,
2336 .priv_size = sizeof(struct queue_entry_priv_usb),
2337 };
2338
2339 static const struct rt2x00_ops rt73usb_ops = {
2340 .name = KBUILD_MODNAME,
2341 .max_sta_intf = 1,
2342 .max_ap_intf = 4,
2343 .eeprom_size = EEPROM_SIZE,
2344 .rf_size = RF_SIZE,
2345 .tx_queues = NUM_TX_QUEUES,
2346 .rx = &rt73usb_queue_rx,
2347 .tx = &rt73usb_queue_tx,
2348 .bcn = &rt73usb_queue_bcn,
2349 .lib = &rt73usb_rt2x00_ops,
2350 .hw = &rt73usb_mac80211_ops,
2351 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2352 .debugfs = &rt73usb_rt2x00debug,
2353 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2354 };
2355
2356 /*
2357 * rt73usb module information.
2358 */
2359 static struct usb_device_id rt73usb_device_table[] = {
2360 /* AboCom */
2361 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2362 /* Askey */
2363 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2364 /* ASUS */
2365 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2366 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2367 /* Belkin */
2368 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2369 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2370 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2371 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2372 /* Billionton */
2373 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2374 /* Buffalo */
2375 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2376 /* CNet */
2377 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2378 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2379 /* Conceptronic */
2380 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2381 /* Corega */
2382 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
2383 /* D-Link */
2384 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2385 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2386 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
2387 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2388 /* Gemtek */
2389 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2390 /* Gigabyte */
2391 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2392 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2393 /* Huawei-3Com */
2394 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2395 /* Hercules */
2396 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2397 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2398 /* Linksys */
2399 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2400 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2401 /* MSI */
2402 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2403 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2404 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2405 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2406 /* Ralink */
2407 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2408 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2409 /* Qcom */
2410 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2411 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2412 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2413 /* Senao */
2414 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2415 /* Sitecom */
2416 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2417 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2418 /* Surecom */
2419 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2420 /* Planex */
2421 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2422 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2423 { 0, }
2424 };
2425
2426 MODULE_AUTHOR(DRV_PROJECT);
2427 MODULE_VERSION(DRV_VERSION);
2428 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2429 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2430 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2431 MODULE_FIRMWARE(FIRMWARE_RT2571);
2432 MODULE_LICENSE("GPL");
2433
2434 static struct usb_driver rt73usb_driver = {
2435 .name = KBUILD_MODNAME,
2436 .id_table = rt73usb_device_table,
2437 .probe = rt2x00usb_probe,
2438 .disconnect = rt2x00usb_disconnect,
2439 .suspend = rt2x00usb_suspend,
2440 .resume = rt2x00usb_resume,
2441 };
2442
2443 static int __init rt73usb_init(void)
2444 {
2445 return usb_register(&rt73usb_driver);
2446 }
2447
2448 static void __exit rt73usb_exit(void)
2449 {
2450 usb_deregister(&rt73usb_driver);
2451 }
2452
2453 module_init(rt73usb_init);
2454 module_exit(rt73usb_exit);
Support for the Chinese Samsung S3C2440 based development boards