2 * linux/arch/arm/mach-versatile/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
29 #include <linux/clocksource.h>
30 #include <linux/clockchips.h>
31 #include <linux/cnt32_to_63.h>
34 #include <asm/clkdev.h>
35 #include <asm/system.h>
36 #include <mach/hardware.h>
39 #include <asm/hardware/arm_timer.h>
40 #include <asm/hardware/icst307.h>
41 #include <asm/hardware/vic.h>
42 #include <asm/mach-types.h>
44 #include <asm/mach/arch.h>
45 #include <asm/mach/flash.h>
46 #include <asm/mach/irq.h>
47 #include <asm/mach/time.h>
48 #include <asm/mach/map.h>
49 #include <asm/mach/mmc.h>
55 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
58 * Setup a VA for the Versatile Vectored Interrupt Controller.
60 #define __io_address(n) __io(IO_ADDRESS(n))
61 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
62 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
64 static void sic_mask_irq(unsigned int irq
)
67 writel(1 << irq
, VA_SIC_BASE
+ SIC_IRQ_ENABLE_CLEAR
);
70 static void sic_unmask_irq(unsigned int irq
)
73 writel(1 << irq
, VA_SIC_BASE
+ SIC_IRQ_ENABLE_SET
);
76 static struct irq_chip sic_chip
= {
80 .unmask
= sic_unmask_irq
,
84 sic_handle_irq(unsigned int irq
, struct irq_desc
*desc
)
86 unsigned long status
= readl(VA_SIC_BASE
+ SIC_IRQ_STATUS
);
89 do_bad_IRQ(irq
, desc
);
94 irq
= ffs(status
) - 1;
95 status
&= ~(1 << irq
);
99 generic_handle_irq(irq
);
104 #define IRQ_MMCI0A IRQ_VICSOURCE22
105 #define IRQ_AACI IRQ_VICSOURCE24
106 #define IRQ_ETH IRQ_VICSOURCE25
107 #define PIC_MASK 0xFFD00000
109 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
110 #define IRQ_AACI IRQ_SIC_AACI
111 #define IRQ_ETH IRQ_SIC_ETH
115 void __init
versatile_init_irq(void)
119 vic_init(VA_VIC_BASE
, IRQ_VIC_START
, ~0);
121 set_irq_chained_handler(IRQ_VICSOURCE31
, sic_handle_irq
);
123 /* Do second interrupt controller */
124 writel(~0, VA_SIC_BASE
+ SIC_IRQ_ENABLE_CLEAR
);
126 for (i
= IRQ_SIC_START
; i
<= IRQ_SIC_END
; i
++) {
127 if ((PIC_MASK
& (1 << (i
- IRQ_SIC_START
))) == 0) {
128 set_irq_chip(i
, &sic_chip
);
129 set_irq_handler(i
, handle_level_irq
);
130 set_irq_flags(i
, IRQF_VALID
| IRQF_PROBE
);
135 * Interrupts on secondary controller from 0 to 8 are routed to
137 * Interrupts from 21 to 31 are routed directly to the VIC on
138 * the corresponding number on primary controller. This is controlled
139 * by setting PIC_ENABLEx.
141 writel(PIC_MASK
, VA_SIC_BASE
+ SIC_INT_PIC_ENABLE
);
144 static struct map_desc versatile_io_desc
[] __initdata
= {
146 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE
),
147 .pfn
= __phys_to_pfn(VERSATILE_SYS_BASE
),
151 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE
),
152 .pfn
= __phys_to_pfn(VERSATILE_SIC_BASE
),
156 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE
),
157 .pfn
= __phys_to_pfn(VERSATILE_VIC_BASE
),
161 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE
),
162 .pfn
= __phys_to_pfn(VERSATILE_SCTL_BASE
),
166 #ifdef CONFIG_MACH_VERSATILE_AB
168 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE
),
169 .pfn
= __phys_to_pfn(VERSATILE_GPIO0_BASE
),
173 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE
),
174 .pfn
= __phys_to_pfn(VERSATILE_IB2_BASE
),
179 #ifdef CONFIG_DEBUG_LL
181 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE
),
182 .pfn
= __phys_to_pfn(VERSATILE_UART0_BASE
),
189 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE
),
190 .pfn
= __phys_to_pfn(VERSATILE_PCI_CORE_BASE
),
194 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE
,
195 .pfn
= __phys_to_pfn(VERSATILE_PCI_BASE
),
196 .length
= VERSATILE_PCI_BASE_SIZE
,
199 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE
,
200 .pfn
= __phys_to_pfn(VERSATILE_PCI_CFG_BASE
),
201 .length
= VERSATILE_PCI_CFG_BASE_SIZE
,
206 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0
,
207 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE0
),
211 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1
,
212 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE1
),
216 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2
,
217 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE2
),
225 void __init
versatile_map_io(void)
227 iotable_init(versatile_io_desc
, ARRAY_SIZE(versatile_io_desc
));
230 #define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
233 * This is the Versatile sched_clock implementation. This has
234 * a resolution of 41.7ns, and a maximum value of about 35583 days.
236 * The return value is guaranteed to be monotonic in that range as
237 * long as there is always less than 89 seconds between successive
238 * calls to this function.
240 unsigned long long sched_clock(void)
242 unsigned long long v
= cnt32_to_63(readl(VERSATILE_REFCOUNTER
));
244 /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
252 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
254 static int versatile_flash_init(void)
258 val
= __raw_readl(VERSATILE_FLASHCTRL
);
259 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
260 __raw_writel(val
, VERSATILE_FLASHCTRL
);
265 static void versatile_flash_exit(void)
269 val
= __raw_readl(VERSATILE_FLASHCTRL
);
270 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
271 __raw_writel(val
, VERSATILE_FLASHCTRL
);
274 static void versatile_flash_set_vpp(int on
)
278 val
= __raw_readl(VERSATILE_FLASHCTRL
);
280 val
|= VERSATILE_FLASHPROG_FLVPPEN
;
282 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
283 __raw_writel(val
, VERSATILE_FLASHCTRL
);
286 static struct flash_platform_data versatile_flash_data
= {
287 .map_name
= "cfi_probe",
289 .init
= versatile_flash_init
,
290 .exit
= versatile_flash_exit
,
291 .set_vpp
= versatile_flash_set_vpp
,
294 static struct resource versatile_flash_resource
= {
295 .start
= VERSATILE_FLASH_BASE
,
296 .end
= VERSATILE_FLASH_BASE
+ VERSATILE_FLASH_SIZE
- 1,
297 .flags
= IORESOURCE_MEM
,
300 static struct platform_device versatile_flash_device
= {
304 .platform_data
= &versatile_flash_data
,
307 .resource
= &versatile_flash_resource
,
310 static struct resource smc91x_resources
[] = {
312 .start
= VERSATILE_ETH_BASE
,
313 .end
= VERSATILE_ETH_BASE
+ SZ_64K
- 1,
314 .flags
= IORESOURCE_MEM
,
319 .flags
= IORESOURCE_IRQ
,
323 static struct platform_device smc91x_device
= {
326 .num_resources
= ARRAY_SIZE(smc91x_resources
),
327 .resource
= smc91x_resources
,
330 static struct resource versatile_i2c_resource
= {
331 .start
= VERSATILE_I2C_BASE
,
332 .end
= VERSATILE_I2C_BASE
+ SZ_4K
- 1,
333 .flags
= IORESOURCE_MEM
,
336 static struct platform_device versatile_i2c_device
= {
337 .name
= "versatile-i2c",
340 .resource
= &versatile_i2c_resource
,
343 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
345 unsigned int mmc_status(struct device
*dev
)
347 struct amba_device
*adev
= container_of(dev
, struct amba_device
, dev
);
350 if (adev
->res
.start
== VERSATILE_MMCI0_BASE
)
355 return readl(VERSATILE_SYSMCI
) & mask
;
358 static struct mmc_platform_data mmc0_plat_data
= {
359 .ocr_mask
= MMC_VDD_32_33
|MMC_VDD_33_34
,
360 .status
= mmc_status
,
366 static const struct icst307_params versatile_oscvco_params
= {
375 static void versatile_oscvco_set(struct clk
*clk
, struct icst307_vco vco
)
377 void __iomem
*sys
= __io_address(VERSATILE_SYS_BASE
);
378 void __iomem
*sys_lock
= sys
+ VERSATILE_SYS_LOCK_OFFSET
;
381 val
= readl(sys
+ clk
->oscoff
) & ~0x7ffff;
382 val
|= vco
.v
| (vco
.r
<< 9) | (vco
.s
<< 16);
384 writel(0xa05f, sys_lock
);
385 writel(val
, sys
+ clk
->oscoff
);
389 static struct clk osc4_clk
= {
390 .params
= &versatile_oscvco_params
,
391 .oscoff
= VERSATILE_SYS_OSCCLCD_OFFSET
,
392 .setvco
= versatile_oscvco_set
,
396 * These are fixed clocks.
398 static struct clk ref24_clk
= {
402 static struct clk_lookup lookups
[] __initdata
= {
436 #define SYS_CLCD_MODE_MASK (3 << 0)
437 #define SYS_CLCD_MODE_888 (0 << 0)
438 #define SYS_CLCD_MODE_5551 (1 << 0)
439 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
440 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
441 #define SYS_CLCD_NLCDIOON (1 << 2)
442 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
443 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
444 #define SYS_CLCD_ID_MASK (0x1f << 8)
445 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
446 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
447 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
448 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
449 #define SYS_CLCD_ID_VGA (0x1f << 8)
451 static struct clcd_panel vga
= {
465 .vmode
= FB_VMODE_NONINTERLACED
,
469 .tim2
= TIM2_BCD
| TIM2_IPC
,
470 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
474 static struct clcd_panel sanyo_3_8_in
= {
476 .name
= "Sanyo QVGA",
488 .vmode
= FB_VMODE_NONINTERLACED
,
493 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
497 static struct clcd_panel sanyo_2_5_in
= {
499 .name
= "Sanyo QVGA Portrait",
510 .sync
= FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_VERT_HIGH_ACT
,
511 .vmode
= FB_VMODE_NONINTERLACED
,
515 .tim2
= TIM2_IVS
| TIM2_IHS
| TIM2_IPC
,
516 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
520 static struct clcd_panel epson_2_2_in
= {
522 .name
= "Epson QCIF",
534 .vmode
= FB_VMODE_NONINTERLACED
,
538 .tim2
= TIM2_BCD
| TIM2_IPC
,
539 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
544 * Detect which LCD panel is connected, and return the appropriate
545 * clcd_panel structure. Note: we do not have any information on
546 * the required timings for the 8.4in panel, so we presently assume
549 static struct clcd_panel
*versatile_clcd_panel(void)
551 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
552 struct clcd_panel
*panel
= &vga
;
555 val
= readl(sys_clcd
) & SYS_CLCD_ID_MASK
;
556 if (val
== SYS_CLCD_ID_SANYO_3_8
)
557 panel
= &sanyo_3_8_in
;
558 else if (val
== SYS_CLCD_ID_SANYO_2_5
)
559 panel
= &sanyo_2_5_in
;
560 else if (val
== SYS_CLCD_ID_EPSON_2_2
)
561 panel
= &epson_2_2_in
;
562 else if (val
== SYS_CLCD_ID_VGA
)
565 printk(KERN_ERR
"CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
574 * Disable all display connectors on the interface module.
576 static void versatile_clcd_disable(struct clcd_fb
*fb
)
578 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
581 val
= readl(sys_clcd
);
582 val
&= ~SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
583 writel(val
, sys_clcd
);
585 #ifdef CONFIG_MACH_VERSATILE_AB
587 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
589 if (machine_is_versatile_ab() && fb
->panel
== &sanyo_2_5_in
) {
590 void __iomem
*versatile_ib2_ctrl
= __io_address(VERSATILE_IB2_CTRL
);
593 ctrl
= readl(versatile_ib2_ctrl
);
595 writel(ctrl
, versatile_ib2_ctrl
);
601 * Enable the relevant connector on the interface module.
603 static void versatile_clcd_enable(struct clcd_fb
*fb
)
605 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
608 val
= readl(sys_clcd
);
609 val
&= ~SYS_CLCD_MODE_MASK
;
611 switch (fb
->fb
.var
.green
.length
) {
613 val
|= SYS_CLCD_MODE_5551
;
616 val
|= SYS_CLCD_MODE_565_RLSB
;
619 val
|= SYS_CLCD_MODE_888
;
626 writel(val
, sys_clcd
);
629 * And now enable the PSUs
631 val
|= SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
632 writel(val
, sys_clcd
);
634 #ifdef CONFIG_MACH_VERSATILE_AB
636 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
638 if (machine_is_versatile_ab() && fb
->panel
== &sanyo_2_5_in
) {
639 void __iomem
*versatile_ib2_ctrl
= __io_address(VERSATILE_IB2_CTRL
);
642 ctrl
= readl(versatile_ib2_ctrl
);
644 writel(ctrl
, versatile_ib2_ctrl
);
649 static unsigned long framesize
= SZ_1M
;
651 static int versatile_clcd_setup(struct clcd_fb
*fb
)
655 fb
->panel
= versatile_clcd_panel();
657 fb
->fb
.screen_base
= dma_alloc_writecombine(&fb
->dev
->dev
, framesize
,
659 if (!fb
->fb
.screen_base
) {
660 printk(KERN_ERR
"CLCD: unable to map framebuffer\n");
664 fb
->fb
.fix
.smem_start
= dma
;
665 fb
->fb
.fix
.smem_len
= framesize
;
670 static int versatile_clcd_mmap(struct clcd_fb
*fb
, struct vm_area_struct
*vma
)
672 return dma_mmap_writecombine(&fb
->dev
->dev
, vma
,
674 fb
->fb
.fix
.smem_start
,
675 fb
->fb
.fix
.smem_len
);
678 static void versatile_clcd_remove(struct clcd_fb
*fb
)
680 dma_free_writecombine(&fb
->dev
->dev
, fb
->fb
.fix
.smem_len
,
681 fb
->fb
.screen_base
, fb
->fb
.fix
.smem_start
);
684 static struct clcd_board clcd_plat_data
= {
686 .check
= clcdfb_check
,
687 .decode
= clcdfb_decode
,
688 .disable
= versatile_clcd_disable
,
689 .enable
= versatile_clcd_enable
,
690 .setup
= versatile_clcd_setup
,
691 .mmap
= versatile_clcd_mmap
,
692 .remove
= versatile_clcd_remove
,
695 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
696 #define AACI_DMA { 0x80, 0x81 }
697 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
698 #define MMCI0_DMA { 0x84, 0 }
699 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
700 #define KMI0_DMA { 0, 0 }
701 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
702 #define KMI1_DMA { 0, 0 }
705 * These devices are connected directly to the multi-layer AHB switch
707 #define SMC_IRQ { NO_IRQ, NO_IRQ }
708 #define SMC_DMA { 0, 0 }
709 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
710 #define MPMC_DMA { 0, 0 }
711 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
712 #define CLCD_DMA { 0, 0 }
713 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
714 #define DMAC_DMA { 0, 0 }
717 * These devices are connected via the core APB bridge
719 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
720 #define SCTL_DMA { 0, 0 }
721 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
722 #define WATCHDOG_DMA { 0, 0 }
723 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
724 #define GPIO0_DMA { 0, 0 }
725 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
726 #define GPIO1_DMA { 0, 0 }
727 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
728 #define RTC_DMA { 0, 0 }
731 * These devices are connected via the DMA APB bridge
733 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
734 #define SCI_DMA { 7, 6 }
735 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
736 #define UART0_DMA { 15, 14 }
737 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
738 #define UART1_DMA { 13, 12 }
739 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
740 #define UART2_DMA { 11, 10 }
741 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
742 #define SSP_DMA { 9, 8 }
744 /* FPGA Primecells */
745 AMBA_DEVICE(aaci
, "fpga:04", AACI
, NULL
);
746 AMBA_DEVICE(mmc0
, "fpga:05", MMCI0
, &mmc0_plat_data
);
747 AMBA_DEVICE(kmi0
, "fpga:06", KMI0
, NULL
);
748 AMBA_DEVICE(kmi1
, "fpga:07", KMI1
, NULL
);
750 /* DevChip Primecells */
751 AMBA_DEVICE(smc
, "dev:00", SMC
, NULL
);
752 AMBA_DEVICE(mpmc
, "dev:10", MPMC
, NULL
);
753 AMBA_DEVICE(clcd
, "dev:20", CLCD
, &clcd_plat_data
);
754 AMBA_DEVICE(dmac
, "dev:30", DMAC
, NULL
);
755 AMBA_DEVICE(sctl
, "dev:e0", SCTL
, NULL
);
756 AMBA_DEVICE(wdog
, "dev:e1", WATCHDOG
, NULL
);
757 AMBA_DEVICE(gpio0
, "dev:e4", GPIO0
, NULL
);
758 AMBA_DEVICE(gpio1
, "dev:e5", GPIO1
, NULL
);
759 AMBA_DEVICE(rtc
, "dev:e8", RTC
, NULL
);
760 AMBA_DEVICE(sci0
, "dev:f0", SCI
, NULL
);
761 AMBA_DEVICE(uart0
, "dev:f1", UART0
, NULL
);
762 AMBA_DEVICE(uart1
, "dev:f2", UART1
, NULL
);
763 AMBA_DEVICE(uart2
, "dev:f3", UART2
, NULL
);
764 AMBA_DEVICE(ssp0
, "dev:f4", SSP
, NULL
);
766 static struct amba_device
*amba_devs
[] __initdata
= {
788 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
790 static void versatile_leds_event(led_event_t ledevt
)
795 local_irq_save(flags
);
796 val
= readl(VA_LEDS_BASE
);
800 val
= val
& ~VERSATILE_SYS_LED0
;
804 val
= val
| VERSATILE_SYS_LED0
;
808 val
= val
^ VERSATILE_SYS_LED1
;
819 writel(val
, VA_LEDS_BASE
);
820 local_irq_restore(flags
);
822 #endif /* CONFIG_LEDS */
824 void __init
versatile_init(void)
828 for (i
= 0; i
< ARRAY_SIZE(lookups
); i
++)
829 clkdev_add(&lookups
[i
]);
831 platform_device_register(&versatile_flash_device
);
832 platform_device_register(&versatile_i2c_device
);
833 platform_device_register(&smc91x_device
);
835 for (i
= 0; i
< ARRAY_SIZE(amba_devs
); i
++) {
836 struct amba_device
*d
= amba_devs
[i
];
837 amba_device_register(d
, &iomem_resource
);
841 leds_event
= versatile_leds_event
;
846 * Where is the timer (VA)?
848 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
849 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
850 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
851 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
852 #define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
855 * How long is the timer interval?
857 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
858 #if TIMER_INTERVAL >= 0x100000
859 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
860 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
861 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
862 #elif TIMER_INTERVAL >= 0x10000
863 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
864 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
865 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
867 #define TIMER_RELOAD (TIMER_INTERVAL)
868 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
869 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
872 static void timer_set_mode(enum clock_event_mode mode
,
873 struct clock_event_device
*clk
)
878 case CLOCK_EVT_MODE_PERIODIC
:
879 writel(TIMER_RELOAD
, TIMER0_VA_BASE
+ TIMER_LOAD
);
881 ctrl
= TIMER_CTRL_PERIODIC
;
882 ctrl
|= TIMER_CTRL_32BIT
| TIMER_CTRL_IE
| TIMER_CTRL_ENABLE
;
884 case CLOCK_EVT_MODE_ONESHOT
:
885 /* period set, and timer enabled in 'next_event' hook */
886 ctrl
= TIMER_CTRL_ONESHOT
;
887 ctrl
|= TIMER_CTRL_32BIT
| TIMER_CTRL_IE
;
889 case CLOCK_EVT_MODE_UNUSED
:
890 case CLOCK_EVT_MODE_SHUTDOWN
:
895 writel(ctrl
, TIMER0_VA_BASE
+ TIMER_CTRL
);
898 static int timer_set_next_event(unsigned long evt
,
899 struct clock_event_device
*unused
)
901 unsigned long ctrl
= readl(TIMER0_VA_BASE
+ TIMER_CTRL
);
903 writel(evt
, TIMER0_VA_BASE
+ TIMER_LOAD
);
904 writel(ctrl
| TIMER_CTRL_ENABLE
, TIMER0_VA_BASE
+ TIMER_CTRL
);
909 static struct clock_event_device timer0_clockevent
= {
912 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
913 .set_mode
= timer_set_mode
,
914 .set_next_event
= timer_set_next_event
,
918 * IRQ handler for the timer
920 static irqreturn_t
versatile_timer_interrupt(int irq
, void *dev_id
)
922 struct clock_event_device
*evt
= &timer0_clockevent
;
924 writel(1, TIMER0_VA_BASE
+ TIMER_INTCLR
);
926 evt
->event_handler(evt
);
931 static struct irqaction versatile_timer_irq
= {
932 .name
= "Versatile Timer Tick",
933 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
,
934 .handler
= versatile_timer_interrupt
,
937 static cycle_t
versatile_get_cycles(void)
939 return ~readl(TIMER3_VA_BASE
+ TIMER_VALUE
);
942 static struct clocksource clocksource_versatile
= {
945 .read
= versatile_get_cycles
,
946 .mask
= CLOCKSOURCE_MASK(32),
948 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
951 static int __init
versatile_clocksource_init(void)
953 /* setup timer3 as free-running clocksource */
954 writel(0, TIMER3_VA_BASE
+ TIMER_CTRL
);
955 writel(0xffffffff, TIMER3_VA_BASE
+ TIMER_LOAD
);
956 writel(0xffffffff, TIMER3_VA_BASE
+ TIMER_VALUE
);
957 writel(TIMER_CTRL_32BIT
| TIMER_CTRL_ENABLE
| TIMER_CTRL_PERIODIC
,
958 TIMER3_VA_BASE
+ TIMER_CTRL
);
960 clocksource_versatile
.mult
=
961 clocksource_khz2mult(1000, clocksource_versatile
.shift
);
962 clocksource_register(&clocksource_versatile
);
968 * Set up timer interrupt, and return the current time in seconds.
970 static void __init
versatile_timer_init(void)
975 * set clock frequency:
976 * VERSATILE_REFCLK is 32KHz
977 * VERSATILE_TIMCLK is 1MHz
979 val
= readl(__io_address(VERSATILE_SCTL_BASE
));
980 writel((VERSATILE_TIMCLK
<< VERSATILE_TIMER1_EnSel
) |
981 (VERSATILE_TIMCLK
<< VERSATILE_TIMER2_EnSel
) |
982 (VERSATILE_TIMCLK
<< VERSATILE_TIMER3_EnSel
) |
983 (VERSATILE_TIMCLK
<< VERSATILE_TIMER4_EnSel
) | val
,
984 __io_address(VERSATILE_SCTL_BASE
));
987 * Initialise to a known state (all timers off)
989 writel(0, TIMER0_VA_BASE
+ TIMER_CTRL
);
990 writel(0, TIMER1_VA_BASE
+ TIMER_CTRL
);
991 writel(0, TIMER2_VA_BASE
+ TIMER_CTRL
);
992 writel(0, TIMER3_VA_BASE
+ TIMER_CTRL
);
995 * Make irqs happen for the system timer
997 setup_irq(IRQ_TIMERINT0_1
, &versatile_timer_irq
);
999 versatile_clocksource_init();
1001 timer0_clockevent
.mult
=
1002 div_sc(1000000, NSEC_PER_SEC
, timer0_clockevent
.shift
);
1003 timer0_clockevent
.max_delta_ns
=
1004 clockevent_delta2ns(0xffffffff, &timer0_clockevent
);
1005 timer0_clockevent
.min_delta_ns
=
1006 clockevent_delta2ns(0xf, &timer0_clockevent
);
1008 timer0_clockevent
.cpumask
= cpumask_of(0);
1009 clockevents_register_device(&timer0_clockevent
);
1012 struct sys_timer versatile_timer
= {
1013 .init
= versatile_timer_init
,