include/drm/drm.h

   1 /**
   2  * \file drm.h
   3  * Header for the Direct Rendering Manager
   4  *
   5  * \author Rickard E. (Rik) Faith <faith@valinux.com>
   6  *
   7  * \par Acknowledgments:
   8  * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
   9  */
  10
  11 /*
  12  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  13  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  14  * All rights reserved.
  15  *
  16  * Permission is hereby granted, free of charge, to any person obtaining a
  17  * copy of this software and associated documentation files (the "Software"),
  18  * to deal in the Software without restriction, including without limitation
  19  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  20  * and/or sell copies of the Software, and to permit persons to whom the
  21  * Software is furnished to do so, subject to the following conditions:
  22  *
  23  * The above copyright notice and this permission notice (including the next
  24  * paragraph) shall be included in all copies or substantial portions of the
  25  * Software.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  28  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  29  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  30  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  31  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  32  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  33  * OTHER DEALINGS IN THE SOFTWARE.
  34  */
  35
  36 #ifndef _DRM_H_
  37 #define _DRM_H_
  38
  39 #if defined(__KERNEL__)
  40 #endif
  41 #include <asm/ioctl.h>          /* For _IO* macros */
  42 #define DRM_IOCTL_NR(n)         _IOC_NR(n)
  43 #define DRM_IOC_VOID            _IOC_NONE
  44 #define DRM_IOC_READ            _IOC_READ
  45 #define DRM_IOC_WRITE           _IOC_WRITE
  46 #define DRM_IOC_READWRITE       _IOC_READ|_IOC_WRITE
  47 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
  48
  49 #define DRM_MAJOR       226
  50 #define DRM_MAX_MINOR   15
  51
  52 #define DRM_NAME        "drm"     /**< Name in kernel, /dev, and /proc */
  53 #define DRM_MIN_ORDER   5         /**< At least 2^5 bytes = 32 bytes */
  54 #define DRM_MAX_ORDER   22        /**< Up to 2^22 bytes = 4MB */
  55 #define DRM_RAM_PERCENT 10        /**< How much system ram can we lock? */
  56
  57 #define _DRM_LOCK_HELD  0x80000000U /**< Hardware lock is held */
  58 #define _DRM_LOCK_CONT  0x40000000U /**< Hardware lock is contended */
  59 #define _DRM_LOCK_IS_HELD(lock)    ((lock) & _DRM_LOCK_HELD)
  60 #define _DRM_LOCK_IS_CONT(lock)    ((lock) & _DRM_LOCK_CONT)
  61 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
  62
  63 typedef unsigned int drm_handle_t;
  64 typedef unsigned int drm_context_t;
  65 typedef unsigned int drm_drawable_t;
  66 typedef unsigned int drm_magic_t;
  67
  68 /**
  69  * Cliprect.
  70  *
  71  * \warning: If you change this structure, make sure you change
  72  * XF86DRIClipRectRec in the server as well
  73  *
  74  * \note KW: Actually it's illegal to change either for
  75  * backwards-compatibility reasons.
  76  */
  77 struct drm_clip_rect {
  78         unsigned short x1;
  79         unsigned short y1;
  80         unsigned short x2;
  81         unsigned short y2;
  82 };
  83
  84 /**
  85  * Drawable information.
  86  */
  87 struct drm_drawable_info {
  88         unsigned int num_rects;
  89         struct drm_clip_rect *rects;
  90 };
  91
  92 /**
  93  * Texture region,
  94  */
  95 struct drm_tex_region {
  96         unsigned char next;
  97         unsigned char prev;
  98         unsigned char in_use;
  99         unsigned char padding;
 100         unsigned int age;
 101 };
 102
 103 /**
 104  * Hardware lock.
 105  *
 106  * The lock structure is a simple cache-line aligned integer.  To avoid
 107  * processor bus contention on a multiprocessor system, there should not be any
 108  * other data stored in the same cache line.
 109  */
 110 struct drm_hw_lock {
 111         __volatile__ unsigned int lock;         /**< lock variable */
 112         char padding[60];                       /**< Pad to cache line */
 113 };
 114
 115 /**
 116  * DRM_IOCTL_VERSION ioctl argument type.
 117  *
 118  * \sa drmGetVersion().
 119  */
 120 struct drm_version {
 121         int version_major;        /**< Major version */
 122         int version_minor;        /**< Minor version */
 123         int version_patchlevel;   /**< Patch level */
 124         size_t name_len;          /**< Length of name buffer */
 125         char __user *name;        /**< Name of driver */
 126         size_t date_len;          /**< Length of date buffer */
 127         char __user *date;        /**< User-space buffer to hold date */
 128         size_t desc_len;          /**< Length of desc buffer */
 129         char __user *desc;        /**< User-space buffer to hold desc */
 130 };
 131
 132 /**
 133  * DRM_IOCTL_GET_UNIQUE ioctl argument type.
 134  *
 135  * \sa drmGetBusid() and drmSetBusId().
 136  */
 137 struct drm_unique {
 138         size_t unique_len;        /**< Length of unique */
 139         char __user *unique;      /**< Unique name for driver instantiation */
 140 };
 141
 142 struct drm_list {
 143         int count;                /**< Length of user-space structures */
 144         struct drm_version __user *version;
 145 };
 146
 147 struct drm_block {
 148         int unused;
 149 };
 150
 151 /**
 152  * DRM_IOCTL_CONTROL ioctl argument type.
 153  *
 154  * \sa drmCtlInstHandler() and drmCtlUninstHandler().
 155  */
 156 struct drm_control {
 157         enum {
 158                 DRM_ADD_COMMAND,
 159                 DRM_RM_COMMAND,
 160                 DRM_INST_HANDLER,
 161                 DRM_UNINST_HANDLER
 162         } func;
 163         int irq;
 164 };
 165
 166 /**
 167  * Type of memory to map.
 168  */
 169 enum drm_map_type {
 170         _DRM_FRAME_BUFFER = 0,    /**< WC (no caching), no core dump */
 171         _DRM_REGISTERS = 1,       /**< no caching, no core dump */
 172         _DRM_SHM = 2,             /**< shared, cached */
 173         _DRM_AGP = 3,             /**< AGP/GART */
 174         _DRM_SCATTER_GATHER = 4,  /**< Scatter/gather memory for PCI DMA */
 175         _DRM_CONSISTENT = 5,      /**< Consistent memory for PCI DMA */
 176 };
 177
 178 /**
 179  * Memory mapping flags.
 180  */
 181 enum drm_map_flags {
 182         _DRM_RESTRICTED = 0x01,      /**< Cannot be mapped to user-virtual */
 183         _DRM_READ_ONLY = 0x02,
 184         _DRM_LOCKED = 0x04,          /**< shared, cached, locked */
 185         _DRM_KERNEL = 0x08,          /**< kernel requires access */
 186         _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
 187         _DRM_CONTAINS_LOCK = 0x20,   /**< SHM page that contains lock */
 188         _DRM_REMOVABLE = 0x40,       /**< Removable mapping */
 189         _DRM_DRIVER = 0x80           /**< Managed by driver */
 190 };
 191
 192 struct drm_ctx_priv_map {
 193         unsigned int ctx_id;     /**< Context requesting private mapping */
 194         void *handle;            /**< Handle of map */
 195 };
 196
 197 /**
 198  * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
 199  * argument type.
 200  *
 201  * \sa drmAddMap().
 202  */
 203 struct drm_map {
 204         unsigned long offset;    /**< Requested physical address (0 for SAREA)*/
 205         unsigned long size;      /**< Requested physical size (bytes) */
 206         enum drm_map_type type;  /**< Type of memory to map */
 207         enum drm_map_flags flags;        /**< Flags */
 208         void *handle;            /**< User-space: "Handle" to pass to mmap() */
 209                                  /**< Kernel-space: kernel-virtual address */
 210         int mtrr;                /**< MTRR slot used */
 211         /*   Private data */
 212 };
 213
 214 /**
 215  * DRM_IOCTL_GET_CLIENT ioctl argument type.
 216  */
 217 struct drm_client {
 218         int idx;                /**< Which client desired? */
 219         int auth;               /**< Is client authenticated? */
 220         unsigned long pid;      /**< Process ID */
 221         unsigned long uid;      /**< User ID */
 222         unsigned long magic;    /**< Magic */
 223         unsigned long iocs;     /**< Ioctl count */
 224 };
 225
 226 enum drm_stat_type {
 227         _DRM_STAT_LOCK,
 228         _DRM_STAT_OPENS,
 229         _DRM_STAT_CLOSES,
 230         _DRM_STAT_IOCTLS,
 231         _DRM_STAT_LOCKS,
 232         _DRM_STAT_UNLOCKS,
 233         _DRM_STAT_VALUE,        /**< Generic value */
 234         _DRM_STAT_BYTE,         /**< Generic byte counter (1024bytes/K) */
 235         _DRM_STAT_COUNT,        /**< Generic non-byte counter (1000/k) */
 236
 237         _DRM_STAT_IRQ,          /**< IRQ */
 238         _DRM_STAT_PRIMARY,      /**< Primary DMA bytes */
 239         _DRM_STAT_SECONDARY,    /**< Secondary DMA bytes */
 240         _DRM_STAT_DMA,          /**< DMA */
 241         _DRM_STAT_SPECIAL,      /**< Special DMA (e.g., priority or polled) */
 242         _DRM_STAT_MISSED        /**< Missed DMA opportunity */
 243             /* Add to the *END* of the list */
 244 };
 245
 246 /**
 247  * DRM_IOCTL_GET_STATS ioctl argument type.
 248  */
 249 struct drm_stats {
 250         unsigned long count;
 251         struct {
 252                 unsigned long value;
 253                 enum drm_stat_type type;
 254         } data[15];
 255 };
 256
 257 /**
 258  * Hardware locking flags.
 259  */
 260 enum drm_lock_flags {
 261         _DRM_LOCK_READY = 0x01,      /**< Wait until hardware is ready for DMA */
 262         _DRM_LOCK_QUIESCENT = 0x02,  /**< Wait until hardware quiescent */
 263         _DRM_LOCK_FLUSH = 0x04,      /**< Flush this context's DMA queue first */
 264         _DRM_LOCK_FLUSH_ALL = 0x08,  /**< Flush all DMA queues first */
 265         /* These *HALT* flags aren't supported yet
 266            -- they will be used to support the
 267            full-screen DGA-like mode. */
 268         _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
 269         _DRM_HALT_CUR_QUEUES = 0x20  /**< Halt all current queues */
 270 };
 271
 272 /**
 273  * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
 274  *
 275  * \sa drmGetLock() and drmUnlock().
 276  */
 277 struct drm_lock {
 278         int context;
 279         enum drm_lock_flags flags;
 280 };
 281
 282 /**
 283  * DMA flags
 284  *
 285  * \warning
 286  * These values \e must match xf86drm.h.
 287  *
 288  * \sa drm_dma.
 289  */
 290 enum drm_dma_flags {
 291         /* Flags for DMA buffer dispatch */
 292         _DRM_DMA_BLOCK = 0x01,        /**<
 293                                        * Block until buffer dispatched.
 294                                        *
 295                                        * \note The buffer may not yet have
 296                                        * been processed by the hardware --
 297                                        * getting a hardware lock with the
 298                                        * hardware quiescent will ensure
 299                                        * that the buffer has been
 300                                        * processed.
 301                                        */
 302         _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
 303         _DRM_DMA_PRIORITY = 0x04,     /**< High priority dispatch */
 304
 305         /* Flags for DMA buffer request */
 306         _DRM_DMA_WAIT = 0x10,         /**< Wait for free buffers */
 307         _DRM_DMA_SMALLER_OK = 0x20,   /**< Smaller-than-requested buffers OK */
 308         _DRM_DMA_LARGER_OK = 0x40     /**< Larger-than-requested buffers OK */
 309 };
 310
 311 /**
 312  * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
 313  *
 314  * \sa drmAddBufs().
 315  */
 316 struct drm_buf_desc {
 317         int count;               /**< Number of buffers of this size */
 318         int size;                /**< Size in bytes */
 319         int low_mark;            /**< Low water mark */
 320         int high_mark;           /**< High water mark */
 321         enum {
 322                 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
 323                 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
 324                 _DRM_SG_BUFFER = 0x04,  /**< Scatter/gather memory buffer */
 325                 _DRM_FB_BUFFER = 0x08,  /**< Buffer is in frame buffer */
 326                 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
 327         } flags;
 328         unsigned long agp_start; /**<
 329                                   * Start address of where the AGP buffers are
 330                                   * in the AGP aperture
 331                                   */
 332 };
 333
 334 /**
 335  * DRM_IOCTL_INFO_BUFS ioctl argument type.
 336  */
 337 struct drm_buf_info {
 338         int count;              /**< Entries in list */
 339         struct drm_buf_desc __user *list;
 340 };
 341
 342 /**
 343  * DRM_IOCTL_FREE_BUFS ioctl argument type.
 344  */
 345 struct drm_buf_free {
 346         int count;
 347         int __user *list;
 348 };
 349
 350 /**
 351  * Buffer information
 352  *
 353  * \sa drm_buf_map.
 354  */
 355 struct drm_buf_pub {
 356         int idx;                       /**< Index into the master buffer list */
 357         int total;                     /**< Buffer size */
 358         int used;                      /**< Amount of buffer in use (for DMA) */
 359         void __user *address;          /**< Address of buffer */
 360 };
 361
 362 /**
 363  * DRM_IOCTL_MAP_BUFS ioctl argument type.
 364  */
 365 struct drm_buf_map {
 366         int count;              /**< Length of the buffer list */
 367         void __user *virtual;           /**< Mmap'd area in user-virtual */
 368         struct drm_buf_pub __user *list;        /**< Buffer information */
 369 };
 370
 371 /**
 372  * DRM_IOCTL_DMA ioctl argument type.
 373  *
 374  * Indices here refer to the offset into the buffer list in drm_buf_get.
 375  *
 376  * \sa drmDMA().
 377  */
 378 struct drm_dma {
 379         int context;                      /**< Context handle */
 380         int send_count;                   /**< Number of buffers to send */
 381         int __user *send_indices;         /**< List of handles to buffers */
 382         int __user *send_sizes;           /**< Lengths of data to send */
 383         enum drm_dma_flags flags;         /**< Flags */
 384         int request_count;                /**< Number of buffers requested */
 385         int request_size;                 /**< Desired size for buffers */
 386         int __user *request_indices;      /**< Buffer information */
 387         int __user *request_sizes;
 388         int granted_count;                /**< Number of buffers granted */
 389 };
 390
 391 enum drm_ctx_flags {
 392         _DRM_CONTEXT_PRESERVED = 0x01,
 393         _DRM_CONTEXT_2DONLY = 0x02
 394 };
 395
 396 /**
 397  * DRM_IOCTL_ADD_CTX ioctl argument type.
 398  *
 399  * \sa drmCreateContext() and drmDestroyContext().
 400  */
 401 struct drm_ctx {
 402         drm_context_t handle;
 403         enum drm_ctx_flags flags;
 404 };
 405
 406 /**
 407  * DRM_IOCTL_RES_CTX ioctl argument type.
 408  */
 409 struct drm_ctx_res {
 410         int count;
 411         struct drm_ctx __user *contexts;
 412 };
 413
 414 /**
 415  * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
 416  */
 417 struct drm_draw {
 418         drm_drawable_t handle;
 419 };
 420
 421 /**
 422  * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
 423  */
 424 typedef enum {
 425         DRM_DRAWABLE_CLIPRECTS,
 426 } drm_drawable_info_type_t;
 427
 428 struct drm_update_draw {
 429         drm_drawable_t handle;
 430         unsigned int type;
 431         unsigned int num;
 432         unsigned long long data;
 433 };
 434
 435 /**
 436  * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
 437  */
 438 struct drm_auth {
 439         drm_magic_t magic;
 440 };
 441
 442 /**
 443  * DRM_IOCTL_IRQ_BUSID ioctl argument type.
 444  *
 445  * \sa drmGetInterruptFromBusID().
 446  */
 447 struct drm_irq_busid {
 448         int irq;        /**< IRQ number */
 449         int busnum;     /**< bus number */
 450         int devnum;     /**< device number */
 451         int funcnum;    /**< function number */
 452 };
 453
 454 enum drm_vblank_seq_type {
 455         _DRM_VBLANK_ABSOLUTE = 0x0,     /**< Wait for specific vblank sequence number */
 456         _DRM_VBLANK_RELATIVE = 0x1,     /**< Wait for given number of vblanks */
 457         _DRM_VBLANK_FLIP = 0x8000000,   /**< Scheduled buffer swap should flip */
 458         _DRM_VBLANK_NEXTONMISS = 0x10000000,    /**< If missed, wait for next vblank */
 459         _DRM_VBLANK_SECONDARY = 0x20000000,     /**< Secondary display controller */
 460         _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
 461 };
 462
 463 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
 464 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
 465                                 _DRM_VBLANK_NEXTONMISS)
 466
 467 struct drm_wait_vblank_request {
 468         enum drm_vblank_seq_type type;
 469         unsigned int sequence;
 470         unsigned long signal;
 471 };
 472
 473 struct drm_wait_vblank_reply {
 474         enum drm_vblank_seq_type type;
 475         unsigned int sequence;
 476         long tval_sec;
 477         long tval_usec;
 478 };
 479
 480 /**
 481  * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
 482  *
 483  * \sa drmWaitVBlank().
 484  */
 485 union drm_wait_vblank {
 486         struct drm_wait_vblank_request request;
 487         struct drm_wait_vblank_reply reply;
 488 };
 489
 490 #define _DRM_PRE_MODESET 1
 491 #define _DRM_POST_MODESET 2
 492
 493 /**
 494  * DRM_IOCTL_MODESET_CTL ioctl argument type
 495  *
 496  * \sa drmModesetCtl().
 497  */
 498 struct drm_modeset_ctl {
 499         uint32_t crtc;
 500         uint32_t cmd;
 501 };
 502
 503 /**
 504  * DRM_IOCTL_AGP_ENABLE ioctl argument type.
 505  *
 506  * \sa drmAgpEnable().
 507  */
 508 struct drm_agp_mode {
 509         unsigned long mode;     /**< AGP mode */
 510 };
 511
 512 /**
 513  * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
 514  *
 515  * \sa drmAgpAlloc() and drmAgpFree().
 516  */
 517 struct drm_agp_buffer {
 518         unsigned long size;     /**< In bytes -- will round to page boundary */
 519         unsigned long handle;   /**< Used for binding / unbinding */
 520         unsigned long type;     /**< Type of memory to allocate */
 521         unsigned long physical; /**< Physical used by i810 */
 522 };
 523
 524 /**
 525  * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
 526  *
 527  * \sa drmAgpBind() and drmAgpUnbind().
 528  */
 529 struct drm_agp_binding {
 530         unsigned long handle;   /**< From drm_agp_buffer */
 531         unsigned long offset;   /**< In bytes -- will round to page boundary */
 532 };
 533
 534 /**
 535  * DRM_IOCTL_AGP_INFO ioctl argument type.
 536  *
 537  * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
 538  * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
 539  * drmAgpVendorId() and drmAgpDeviceId().
 540  */
 541 struct drm_agp_info {
 542         int agp_version_major;
 543         int agp_version_minor;
 544         unsigned long mode;
 545         unsigned long aperture_base;    /* physical address */
 546         unsigned long aperture_size;    /* bytes */
 547         unsigned long memory_allowed;   /* bytes */
 548         unsigned long memory_used;
 549
 550         /* PCI information */
 551         unsigned short id_vendor;
 552         unsigned short id_device;
 553 };
 554
 555 /**
 556  * DRM_IOCTL_SG_ALLOC ioctl argument type.
 557  */
 558 struct drm_scatter_gather {
 559         unsigned long size;     /**< In bytes -- will round to page boundary */
 560         unsigned long handle;   /**< Used for mapping / unmapping */
 561 };
 562
 563 /**
 564  * DRM_IOCTL_SET_VERSION ioctl argument type.
 565  */
 566 struct drm_set_version {
 567         int drm_di_major;
 568         int drm_di_minor;
 569         int drm_dd_major;
 570         int drm_dd_minor;
 571 };
 572
 573 /** DRM_IOCTL_GEM_CLOSE ioctl argument type */
 574 struct drm_gem_close {
 575         /** Handle of the object to be closed. */
 576         uint32_t handle;
 577         uint32_t pad;
 578 };
 579
 580 /** DRM_IOCTL_GEM_FLINK ioctl argument type */
 581 struct drm_gem_flink {
 582         /** Handle for the object being named */
 583         uint32_t handle;
 584
 585         /** Returned global name */
 586         uint32_t name;
 587 };
 588
 589 /** DRM_IOCTL_GEM_OPEN ioctl argument type */
 590 struct drm_gem_open {
 591         /** Name of object being opened */
 592         uint32_t name;
 593
 594         /** Returned handle for the object */
 595         uint32_t handle;
 596
 597         /** Returned size of the object */
 598         uint64_t size;
 599 };
 600
 601 #define DRM_IOCTL_BASE                  'd'
 602 #define DRM_IO(nr)                      _IO(DRM_IOCTL_BASE,nr)
 603 #define DRM_IOR(nr,type)                _IOR(DRM_IOCTL_BASE,nr,type)
 604 #define DRM_IOW(nr,type)                _IOW(DRM_IOCTL_BASE,nr,type)
 605 #define DRM_IOWR(nr,type)               _IOWR(DRM_IOCTL_BASE,nr,type)
 606
 607 #define DRM_IOCTL_VERSION               DRM_IOWR(0x00, struct drm_version)
 608 #define DRM_IOCTL_GET_UNIQUE            DRM_IOWR(0x01, struct drm_unique)
 609 #define DRM_IOCTL_GET_MAGIC             DRM_IOR( 0x02, struct drm_auth)
 610 #define DRM_IOCTL_IRQ_BUSID             DRM_IOWR(0x03, struct drm_irq_busid)
 611 #define DRM_IOCTL_GET_MAP               DRM_IOWR(0x04, struct drm_map)
 612 #define DRM_IOCTL_GET_CLIENT            DRM_IOWR(0x05, struct drm_client)
 613 #define DRM_IOCTL_GET_STATS             DRM_IOR( 0x06, struct drm_stats)
 614 #define DRM_IOCTL_SET_VERSION           DRM_IOWR(0x07, struct drm_set_version)
 615 #define DRM_IOCTL_MODESET_CTL           DRM_IOW(0x08, struct drm_modeset_ctl)
 616 #define DRM_IOCTL_GEM_CLOSE             DRM_IOW (0x09, struct drm_gem_close)
 617 #define DRM_IOCTL_GEM_FLINK             DRM_IOWR(0x0a, struct drm_gem_flink)
 618 #define DRM_IOCTL_GEM_OPEN              DRM_IOWR(0x0b, struct drm_gem_open)
 619
 620 #define DRM_IOCTL_SET_UNIQUE            DRM_IOW( 0x10, struct drm_unique)
 621 #define DRM_IOCTL_AUTH_MAGIC            DRM_IOW( 0x11, struct drm_auth)
 622 #define DRM_IOCTL_BLOCK                 DRM_IOWR(0x12, struct drm_block)
 623 #define DRM_IOCTL_UNBLOCK               DRM_IOWR(0x13, struct drm_block)
 624 #define DRM_IOCTL_CONTROL               DRM_IOW( 0x14, struct drm_control)
 625 #define DRM_IOCTL_ADD_MAP               DRM_IOWR(0x15, struct drm_map)
 626 #define DRM_IOCTL_ADD_BUFS              DRM_IOWR(0x16, struct drm_buf_desc)
 627 #define DRM_IOCTL_MARK_BUFS             DRM_IOW( 0x17, struct drm_buf_desc)
 628 #define DRM_IOCTL_INFO_BUFS             DRM_IOWR(0x18, struct drm_buf_info)
 629 #define DRM_IOCTL_MAP_BUFS              DRM_IOWR(0x19, struct drm_buf_map)
 630 #define DRM_IOCTL_FREE_BUFS             DRM_IOW( 0x1a, struct drm_buf_free)
 631
 632 #define DRM_IOCTL_RM_MAP                DRM_IOW( 0x1b, struct drm_map)
 633
 634 #define DRM_IOCTL_SET_SAREA_CTX         DRM_IOW( 0x1c, struct drm_ctx_priv_map)
 635 #define DRM_IOCTL_GET_SAREA_CTX         DRM_IOWR(0x1d, struct drm_ctx_priv_map)
 636
 637 #define DRM_IOCTL_ADD_CTX               DRM_IOWR(0x20, struct drm_ctx)
 638 #define DRM_IOCTL_RM_CTX                DRM_IOWR(0x21, struct drm_ctx)
 639 #define DRM_IOCTL_MOD_CTX               DRM_IOW( 0x22, struct drm_ctx)
 640 #define DRM_IOCTL_GET_CTX               DRM_IOWR(0x23, struct drm_ctx)
 641 #define DRM_IOCTL_SWITCH_CTX            DRM_IOW( 0x24, struct drm_ctx)
 642 #define DRM_IOCTL_NEW_CTX               DRM_IOW( 0x25, struct drm_ctx)
 643 #define DRM_IOCTL_RES_CTX               DRM_IOWR(0x26, struct drm_ctx_res)
 644 #define DRM_IOCTL_ADD_DRAW              DRM_IOWR(0x27, struct drm_draw)
 645 #define DRM_IOCTL_RM_DRAW               DRM_IOWR(0x28, struct drm_draw)
 646 #define DRM_IOCTL_DMA                   DRM_IOWR(0x29, struct drm_dma)
 647 #define DRM_IOCTL_LOCK                  DRM_IOW( 0x2a, struct drm_lock)
 648 #define DRM_IOCTL_UNLOCK                DRM_IOW( 0x2b, struct drm_lock)
 649 #define DRM_IOCTL_FINISH                DRM_IOW( 0x2c, struct drm_lock)
 650
 651 #define DRM_IOCTL_AGP_ACQUIRE           DRM_IO(  0x30)
 652 #define DRM_IOCTL_AGP_RELEASE           DRM_IO(  0x31)
 653 #define DRM_IOCTL_AGP_ENABLE            DRM_IOW( 0x32, struct drm_agp_mode)
 654 #define DRM_IOCTL_AGP_INFO              DRM_IOR( 0x33, struct drm_agp_info)
 655 #define DRM_IOCTL_AGP_ALLOC             DRM_IOWR(0x34, struct drm_agp_buffer)
 656 #define DRM_IOCTL_AGP_FREE              DRM_IOW( 0x35, struct drm_agp_buffer)
 657 #define DRM_IOCTL_AGP_BIND              DRM_IOW( 0x36, struct drm_agp_binding)
 658 #define DRM_IOCTL_AGP_UNBIND            DRM_IOW( 0x37, struct drm_agp_binding)
 659
 660 #define DRM_IOCTL_SG_ALLOC              DRM_IOWR(0x38, struct drm_scatter_gather)
 661 #define DRM_IOCTL_SG_FREE               DRM_IOW( 0x39, struct drm_scatter_gather)
 662
 663 #define DRM_IOCTL_WAIT_VBLANK           DRM_IOWR(0x3a, union drm_wait_vblank)
 664
 665 #define DRM_IOCTL_UPDATE_DRAW           DRM_IOW(0x3f, struct drm_update_draw)
 666
 667 /**
 668  * Device specific ioctls should only be in their respective headers
 669  * The device specific ioctl range is from 0x40 to 0x99.
 670  * Generic IOCTLS restart at 0xA0.
 671  *
 672  * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
 673  * drmCommandReadWrite().
 674  */
 675 #define DRM_COMMAND_BASE                0x40
 676 #define DRM_COMMAND_END                 0xA0
 677
 678 /* typedef area */
 679 #ifndef __KERNEL__
 680 typedef struct drm_clip_rect drm_clip_rect_t;
 681 typedef struct drm_drawable_info drm_drawable_info_t;
 682 typedef struct drm_tex_region drm_tex_region_t;
 683 typedef struct drm_hw_lock drm_hw_lock_t;
 684 typedef struct drm_version drm_version_t;
 685 typedef struct drm_unique drm_unique_t;
 686 typedef struct drm_list drm_list_t;
 687 typedef struct drm_block drm_block_t;
 688 typedef struct drm_control drm_control_t;
 689 typedef enum drm_map_type drm_map_type_t;
 690 typedef enum drm_map_flags drm_map_flags_t;
 691 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
 692 typedef struct drm_map drm_map_t;
 693 typedef struct drm_client drm_client_t;
 694 typedef enum drm_stat_type drm_stat_type_t;
 695 typedef struct drm_stats drm_stats_t;
 696 typedef enum drm_lock_flags drm_lock_flags_t;
 697 typedef struct drm_lock drm_lock_t;
 698 typedef enum drm_dma_flags drm_dma_flags_t;
 699 typedef struct drm_buf_desc drm_buf_desc_t;
 700 typedef struct drm_buf_info drm_buf_info_t;
 701 typedef struct drm_buf_free drm_buf_free_t;
 702 typedef struct drm_buf_pub drm_buf_pub_t;
 703 typedef struct drm_buf_map drm_buf_map_t;
 704 typedef struct drm_dma drm_dma_t;
 705 typedef union drm_wait_vblank drm_wait_vblank_t;
 706 typedef struct drm_agp_mode drm_agp_mode_t;
 707 typedef enum drm_ctx_flags drm_ctx_flags_t;
 708 typedef struct drm_ctx drm_ctx_t;
 709 typedef struct drm_ctx_res drm_ctx_res_t;
 710 typedef struct drm_draw drm_draw_t;
 711 typedef struct drm_update_draw drm_update_draw_t;
 712 typedef struct drm_auth drm_auth_t;
 713 typedef struct drm_irq_busid drm_irq_busid_t;
 714 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
 715
 716 typedef struct drm_agp_buffer drm_agp_buffer_t;
 717 typedef struct drm_agp_binding drm_agp_binding_t;
 718 typedef struct drm_agp_info drm_agp_info_t;
 719 typedef struct drm_scatter_gather drm_scatter_gather_t;
 720 typedef struct drm_set_version drm_set_version_t;
 721 #endif
 722
 723 #endif