2 * arch/arm/mach-pxa/include/mach/pxa-regs.h
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
21 #define PXA_CS0_PHYS 0x00000000
22 #define PXA_CS1_PHYS 0x04000000
23 #define PXA_CS2_PHYS 0x08000000
24 #define PXA_CS3_PHYS 0x0C000000
25 #define PXA_CS4_PHYS 0x10000000
26 #define PXA_CS5_PHYS 0x14000000
30 * Personal Computer Memory Card International Association (PCMCIA) sockets
33 #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
34 #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
35 #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
36 #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
37 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
39 #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
40 #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
41 #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
42 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
44 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
45 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
46 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
47 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
49 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
50 (0x20000000 + (Nb)*PCMCIASp)
51 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
52 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
53 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
54 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
55 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
57 #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
58 #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
59 #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
60 #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
62 #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
63 #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
64 #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
65 #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
73 #define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
74 #define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
75 #define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
76 #define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
77 #define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
78 #define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
79 #define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
80 #define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
81 #define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
82 #define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
83 #define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
84 #define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
85 #define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
86 #define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
87 #define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
88 #define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
90 #define DCSR(x) __REG2(0x40000000, (x) << 2)
92 #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
93 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
94 #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
96 #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
97 #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
98 #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
99 #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
100 #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
101 #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
102 #define DCSR_EORINTR (1 << 9) /* The end of Receive */
104 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
105 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
106 #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
107 #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
108 #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
110 #define DALGN __REG(0x400000a0) /* DMA Alignment Register */
111 #define DINT __REG(0x400000f0) /* DMA Interrupt Register */
113 #define DRCMR(n) (*(((n) < 64) ? \
114 &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
115 &__REG2(0x40001100, ((n) & 0x3f) << 2)))
117 #define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
118 #define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
119 #define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
120 #define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
121 #define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
122 #define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
123 #define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
124 #define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
125 #define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
126 #define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
127 #define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
128 #define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
129 #define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
130 #define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
131 #define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
132 #define DRCMR15 __REG(0x4000013c) /* Request to Channel Map Register for SSP2 receive Request */
133 #define DRCMR16 __REG(0x40000140) /* Request to Channel Map Register for SSP2 transmit Request */
134 #define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
135 #define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
136 #define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
137 #define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
138 #define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
139 #define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
140 #define DRCMR23 __REG(0x4000015c) /* Reserved */
141 #define DRCMR24 __REG(0x40000160) /* Reserved */
142 #define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
143 #define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
144 #define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
145 #define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
146 #define DRCMR29 __REG(0x40000174) /* Reserved */
147 #define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
148 #define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
149 #define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
150 #define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
151 #define DRCMR34 __REG(0x40000188) /* Reserved */
152 #define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
153 #define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
154 #define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
155 #define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
156 #define DRCMR39 __REG(0x4000019C) /* Reserved */
157 #define DRCMR66 __REG(0x40001108) /* Request to Channel Map Register for SSP3 receive Request */
158 #define DRCMR67 __REG(0x4000110C) /* Request to Channel Map Register for SSP3 transmit Request */
159 #define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
160 #define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
161 #define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
163 #define DRCMRRXSADR DRCMR2
164 #define DRCMRTXSADR DRCMR3
165 #define DRCMRRXBTRBR DRCMR4
166 #define DRCMRTXBTTHR DRCMR5
167 #define DRCMRRXFFRBR DRCMR6
168 #define DRCMRTXFFTHR DRCMR7
169 #define DRCMRRXMCDR DRCMR8
170 #define DRCMRRXMODR DRCMR9
171 #define DRCMRTXMODR DRCMR10
172 #define DRCMRRXPCDR DRCMR11
173 #define DRCMRTXPCDR DRCMR12
174 #define DRCMRRXSSDR DRCMR13
175 #define DRCMRTXSSDR DRCMR14
176 #define DRCMRRXSS2DR DRCMR15
177 #define DRCMRTXSS2DR DRCMR16
178 #define DRCMRRXICDR DRCMR17
179 #define DRCMRTXICDR DRCMR18
180 #define DRCMRRXSTRBR DRCMR19
181 #define DRCMRTXSTTHR DRCMR20
182 #define DRCMRRXMMC DRCMR21
183 #define DRCMRTXMMC DRCMR22
184 #define DRCMRRXSS3DR DRCMR66
185 #define DRCMRTXSS3DR DRCMR67
186 #define DRCMRUDC(x) DRCMR((x) + 24)
188 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
189 #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
191 #define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
192 #define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
193 #define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
194 #define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
195 #define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
196 #define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
197 #define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
198 #define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
199 #define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
200 #define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
201 #define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
202 #define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
203 #define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
204 #define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
205 #define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
206 #define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
207 #define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
208 #define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
209 #define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
210 #define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
211 #define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
212 #define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
213 #define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
214 #define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
215 #define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
216 #define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
217 #define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
218 #define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
219 #define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
220 #define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
221 #define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
222 #define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
223 #define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
224 #define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
225 #define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
226 #define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
227 #define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
228 #define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
229 #define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
230 #define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
231 #define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
232 #define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
233 #define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
234 #define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
235 #define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
236 #define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
237 #define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
238 #define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
239 #define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
240 #define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
241 #define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
242 #define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
243 #define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
244 #define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
245 #define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
246 #define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
247 #define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
248 #define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
249 #define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
250 #define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
251 #define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
252 #define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
253 #define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
254 #define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
256 #define DDADR(x) __REG2(0x40000200, (x) << 4)
257 #define DSADR(x) __REG2(0x40000204, (x) << 4)
258 #define DTADR(x) __REG2(0x40000208, (x) << 4)
259 #define DCMD(x) __REG2(0x4000020c, (x) << 4)
261 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
262 #define DDADR_STOP (1 << 0) /* Stop (read / write) */
264 #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
265 #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
266 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
267 #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
268 #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
269 #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
270 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
271 #define DCMD_BURST8 (1 << 16) /* 8 byte burst */
272 #define DCMD_BURST16 (2 << 16) /* 16 byte burst */
273 #define DCMD_BURST32 (3 << 16) /* 32 byte burst */
274 #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
275 #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
276 #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
277 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
284 /* Full Function UART (FFUART) */
286 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
287 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
288 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
289 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
290 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
291 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
292 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
293 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
294 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
295 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
296 #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
297 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
298 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
300 /* Bluetooth UART (BTUART) */
302 #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
303 #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
304 #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
305 #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
306 #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
307 #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
308 #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
309 #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
310 #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
311 #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
312 #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
313 #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
314 #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
316 /* Standard UART (STUART) */
318 #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
319 #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
320 #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
321 #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
322 #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
323 #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
324 #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
325 #define STLSR __REG(0x40700014) /* Line Status Register (read only) */
326 #define STMSR __REG(0x40700018) /* Reserved */
327 #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
328 #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
329 #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
330 #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
332 /* Hardware UART (HWUART) */
334 #define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
335 #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
336 #define HWIER __REG(0x41600004) /* Interrupt Enable Register (read/write) */
337 #define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
338 #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
339 #define HWLCR __REG(0x4160000C) /* Line Control Register (read/write) */
340 #define HWMCR __REG(0x41600010) /* Modem Control Register (read/write) */
341 #define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
342 #define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
343 #define HWSPR __REG(0x4160001C) /* Scratch Pad Register (read/write) */
344 #define HWISR __REG(0x41600020) /* Infrared Selection Register (read/write) */
345 #define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
346 #define HWABR __REG(0x41600028) /* Auto-Baud Control Register (read/write) */
347 #define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
348 #define HWDLL __REG(0x41600000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
349 #define HWDLH __REG(0x41600004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
351 #define IER_DMAE (1 << 7) /* DMA Requests Enable */
352 #define IER_UUE (1 << 6) /* UART Unit Enable */
353 #define IER_NRZE (1 << 5) /* NRZ coding Enable */
354 #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
355 #define IER_MIE (1 << 3) /* Modem Interrupt Enable */
356 #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
357 #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
358 #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
360 #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
361 #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
362 #define IIR_TOD (1 << 3) /* Time Out Detected */
363 #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
364 #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
365 #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
367 #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
368 #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
369 #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
370 #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
371 #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
372 #define FCR_ITL_1 (0)
373 #define FCR_ITL_8 (FCR_ITL1)
374 #define FCR_ITL_16 (FCR_ITL2)
375 #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
377 #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
378 #define LCR_SB (1 << 6) /* Set Break */
379 #define LCR_STKYP (1 << 5) /* Sticky Parity */
380 #define LCR_EPS (1 << 4) /* Even Parity Select */
381 #define LCR_PEN (1 << 3) /* Parity Enable */
382 #define LCR_STB (1 << 2) /* Stop Bit */
383 #define LCR_WLS1 (1 << 1) /* Word Length Select */
384 #define LCR_WLS0 (1 << 0) /* Word Length Select */
386 #define LSR_FIFOE (1 << 7) /* FIFO Error Status */
387 #define LSR_TEMT (1 << 6) /* Transmitter Empty */
388 #define LSR_TDRQ (1 << 5) /* Transmit Data Request */
389 #define LSR_BI (1 << 4) /* Break Interrupt */
390 #define LSR_FE (1 << 3) /* Framing Error */
391 #define LSR_PE (1 << 2) /* Parity Error */
392 #define LSR_OE (1 << 1) /* Overrun Error */
393 #define LSR_DR (1 << 0) /* Data Ready */
395 #define MCR_LOOP (1 << 4)
396 #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
397 #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
398 #define MCR_RTS (1 << 1) /* Request to Send */
399 #define MCR_DTR (1 << 0) /* Data Terminal Ready */
401 #define MSR_DCD (1 << 7) /* Data Carrier Detect */
402 #define MSR_RI (1 << 6) /* Ring Indicator */
403 #define MSR_DSR (1 << 5) /* Data Set Ready */
404 #define MSR_CTS (1 << 4) /* Clear To Send */
405 #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
406 #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
407 #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
408 #define MSR_DCTS (1 << 0) /* Delta Clear To Send */
411 * IrSR (Infrared Selection Register)
413 #define STISR_RXPL (1 << 4) /* Receive Data Polarity */
414 #define STISR_TXPL (1 << 3) /* Transmit Data Polarity */
415 #define STISR_XMODE (1 << 2) /* Transmit Pulse Width Select */
416 #define STISR_RCVEIR (1 << 1) /* Receiver SIR Enable */
417 #define STISR_XMITIR (1 << 0) /* Transmitter SIR Enable */
424 #define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
425 #define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
426 #define ICR __REG(0x40301690) /* I2C Control Register - ICR */
427 #define ISR __REG(0x40301698) /* I2C Status Register - ISR */
428 #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
430 #define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
431 #define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
432 #define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
433 #define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
434 #define PWRISAR __REG(0x40f001A0) /*Power I2C Slave Address Register-ISAR */
436 #define ICR_START (1 << 0) /* start bit */
437 #define ICR_STOP (1 << 1) /* stop bit */
438 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
439 #define ICR_TB (1 << 3) /* transfer byte bit */
440 #define ICR_MA (1 << 4) /* master abort */
441 #define ICR_SCLE (1 << 5) /* master clock enable */
442 #define ICR_IUE (1 << 6) /* unit enable */
443 #define ICR_GCD (1 << 7) /* general call disable */
444 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */
445 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */
446 #define ICR_BEIE (1 << 10) /* enable bus error ints */
447 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
448 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
449 #define ICR_SADIE (1 << 13) /* slave address detected int enable */
450 #define ICR_UR (1 << 14) /* unit reset */
451 #define ICR_FM (1 << 15) /* fast mode */
453 #define ISR_RWM (1 << 0) /* read/write mode */
454 #define ISR_ACKNAK (1 << 1) /* ack/nak status */
455 #define ISR_UB (1 << 2) /* unit busy */
456 #define ISR_IBB (1 << 3) /* bus busy */
457 #define ISR_SSD (1 << 4) /* slave stop detected */
458 #define ISR_ALD (1 << 5) /* arbitration loss detected */
459 #define ISR_ITE (1 << 6) /* tx buffer empty */
460 #define ISR_IRF (1 << 7) /* rx buffer full */
461 #define ISR_GCAD (1 << 8) /* general call address detected */
462 #define ISR_SAD (1 << 9) /* slave address detected */
463 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */
467 * Serial Audio Controller
470 #define SACR0 __REG(0x40400000) /* Global Control Register */
471 #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
472 #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
473 #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
474 #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
475 #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
476 #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
478 #define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
479 #define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
480 #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
481 #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
482 #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
483 #define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
484 #define SACR0_ENB (1 << 0) /* Enable I2S Link */
485 #define SACR1_ENLBF (1 << 5) /* Enable Loopback */
486 #define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
487 #define SACR1_DREC (1 << 3) /* Disable Recording Function */
488 #define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
490 #define SASR0_I2SOFF (1 << 7) /* Controller Status */
491 #define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
492 #define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
493 #define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
494 #define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
495 #define SASR0_BSY (1 << 2) /* I2S Busy */
496 #define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
497 #define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
499 #define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
500 #define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
502 #define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
503 #define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
504 #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
505 #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
508 * AC97 Controller registers
511 #define POCR __REG(0x40500000) /* PCM Out Control Register */
512 #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
513 #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
515 #define PICR __REG(0x40500004) /* PCM In Control Register */
516 #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
517 #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
519 #define MCCR __REG(0x40500008) /* Mic In Control Register */
520 #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
521 #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
523 #define GCR __REG(0x4050000C) /* Global Control Register */
525 #define GCR_CLKBPB (1 << 31) /* Internal clock enable */
527 #define GCR_nDMAEN (1 << 24) /* non DMA Enable */
528 #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
529 #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
530 #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
531 #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
532 #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
533 #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
534 #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
535 #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
536 #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
537 #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
539 #define POSR __REG(0x40500010) /* PCM Out Status Register */
540 #define POSR_FIFOE (1 << 4) /* FIFO error */
541 #define POSR_FSR (1 << 2) /* FIFO Service Request */
543 #define PISR __REG(0x40500014) /* PCM In Status Register */
544 #define PISR_FIFOE (1 << 4) /* FIFO error */
545 #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
546 #define PISR_FSR (1 << 2) /* FIFO Service Request */
548 #define MCSR __REG(0x40500018) /* Mic In Status Register */
549 #define MCSR_FIFOE (1 << 4) /* FIFO error */
550 #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
551 #define MCSR_FSR (1 << 2) /* FIFO Service Request */
553 #define GSR __REG(0x4050001C) /* Global Status Register */
554 #define GSR_CDONE (1 << 19) /* Command Done */
555 #define GSR_SDONE (1 << 18) /* Status Done */
556 #define GSR_RDCS (1 << 15) /* Read Completion Status */
557 #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
558 #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
559 #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
560 #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
561 #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
562 #define GSR_SCR (1 << 9) /* Secondary Codec Ready */
563 #define GSR_PCR (1 << 8) /* Primary Codec Ready */
564 #define GSR_MCINT (1 << 7) /* Mic In Interrupt */
565 #define GSR_POINT (1 << 6) /* PCM Out Interrupt */
566 #define GSR_PIINT (1 << 5) /* PCM In Interrupt */
567 #define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */
568 #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
569 #define GSR_MIINT (1 << 1) /* Modem In Interrupt */
570 #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
572 #define CAR __REG(0x40500020) /* CODEC Access Register */
573 #define CAR_CAIP (1 << 0) /* Codec Access In Progress */
575 #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
576 #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
578 #define MOCR __REG(0x40500100) /* Modem Out Control Register */
579 #define MOCR_FEIE (1 << 3) /* FIFO Error */
580 #define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
582 #define MICR __REG(0x40500108) /* Modem In Control Register */
583 #define MICR_FEIE (1 << 3) /* FIFO Error */
584 #define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */
586 #define MOSR __REG(0x40500110) /* Modem Out Status Register */
587 #define MOSR_FIFOE (1 << 4) /* FIFO error */
588 #define MOSR_FSR (1 << 2) /* FIFO Service Request */
590 #define MISR __REG(0x40500118) /* Modem In Status Register */
591 #define MISR_FIFOE (1 << 4) /* FIFO error */
592 #define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */
593 #define MISR_FSR (1 << 2) /* FIFO Service Request */
595 #define MODR __REG(0x40500140) /* Modem FIFO Data Register */
597 #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
598 #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
599 #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
600 #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
604 * Fast Infrared Communication Port
607 #define FICP __REG(0x40800000) /* Start of FICP area */
608 #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
609 #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
610 #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
611 #define ICDR __REG(0x4080000c) /* ICP Data Register */
612 #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
613 #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
615 #define ICCR0_AME (1 << 7) /* Address match enable */
616 #define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
617 #define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
618 #define ICCR0_RXE (1 << 4) /* Receive enable */
619 #define ICCR0_TXE (1 << 3) /* Transmit enable */
620 #define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
621 #define ICCR0_LBM (1 << 1) /* Loopback mode */
622 #define ICCR0_ITR (1 << 0) /* IrDA transmission */
624 #define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
625 #define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
626 #define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
627 #define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
628 #define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
629 #define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
632 #define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
634 #define ICSR0_FRE (1 << 5) /* Framing error */
635 #define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
636 #define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
637 #define ICSR0_RAB (1 << 2) /* Receiver abort */
638 #define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
639 #define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
641 #define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
642 #define ICSR1_CRE (1 << 5) /* CRC error */
643 #define ICSR1_EOF (1 << 4) /* End of frame */
644 #define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
645 #define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
646 #define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
647 #define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
654 #define RCNR __REG(0x40900000) /* RTC Count Register */
655 #define RTAR __REG(0x40900004) /* RTC Alarm Register */
656 #define RTSR __REG(0x40900008) /* RTC Status Register */
657 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
658 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
660 #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
661 #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
662 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
663 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
664 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
665 #define RTSR_AL (1 << 0) /* RTC alarm detected */
669 * OS Timer & Match Registers
672 #define OSMR0 __REG(0x40A00000) /* */
673 #define OSMR1 __REG(0x40A00004) /* */
674 #define OSMR2 __REG(0x40A00008) /* */
675 #define OSMR3 __REG(0x40A0000C) /* */
676 #define OSMR4 __REG(0x40A00080) /* */
677 #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
678 #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
679 #define OMCR4 __REG(0x40A000C0) /* */
680 #define OSSR __REG(0x40A00014) /* OS Timer Status Register */
681 #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
682 #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
684 #define OSSR_M3 (1 << 3) /* Match status channel 3 */
685 #define OSSR_M2 (1 << 2) /* Match status channel 2 */
686 #define OSSR_M1 (1 << 1) /* Match status channel 1 */
687 #define OSSR_M0 (1 << 0) /* Match status channel 0 */
689 #define OWER_WME (1 << 0) /* Watchdog Match Enable */
691 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
692 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
693 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
694 #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
698 * Pulse Width Modulator
701 #define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */
702 #define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
703 #define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
705 #define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
706 #define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
707 #define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
711 * Interrupt Controller
714 #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
715 #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
716 #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
717 #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
718 #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
719 #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
721 #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
722 #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
723 #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
724 #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
725 #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
728 * General Purpose I/O
731 #define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000))
732 #define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004))
733 #define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008))
734 #define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100))
736 #define GPLR_OFFSET 0x00
737 #define GPDR_OFFSET 0x0C
738 #define GPSR_OFFSET 0x18
739 #define GPCR_OFFSET 0x24
740 #define GRER_OFFSET 0x30
741 #define GFER_OFFSET 0x3C
742 #define GEDR_OFFSET 0x48
744 #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
745 #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
746 #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
748 #define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
749 #define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
750 #define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
752 #define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
753 #define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
754 #define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
756 #define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
757 #define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
758 #define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
760 #define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
761 #define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
762 #define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
764 #define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
765 #define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
766 #define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
768 #define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
769 #define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
770 #define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
772 #define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
773 #define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
774 #define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
775 #define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
776 #define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
777 #define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */
778 #define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
779 #define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
781 #define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
782 #define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
783 #define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
784 #define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
785 #define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
786 #define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
787 #define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
789 /* More handy macros. The argument is a literal GPIO number. */
791 #define GPIO_bit(x) (1 << ((x) & 0x1f))
793 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
795 /* Interrupt Controller */
797 #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
798 #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
799 #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
800 #define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
801 #define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
802 #define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
803 #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
804 #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
806 #define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
807 #define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
808 #define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
809 #define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
810 #define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
811 #define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
812 #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
813 #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
814 ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
817 #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
818 #define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
819 #define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
820 #define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
821 #define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
822 #define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
823 #define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
824 #define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
829 * Power Manager - see pxa2xx-regs.h
833 * SSP Serial Port Registers - see arch/arm/mach-pxa/include/mach/regs-ssp.h
837 * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
841 * Core Clock - see arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
846 /* Camera Interface */
847 #define CICR0 __REG(0x50000000)
848 #define CICR1 __REG(0x50000004)
849 #define CICR2 __REG(0x50000008)
850 #define CICR3 __REG(0x5000000C)
851 #define CICR4 __REG(0x50000010)
852 #define CISR __REG(0x50000014)
853 #define CIFR __REG(0x50000018)
854 #define CITOR __REG(0x5000001C)
855 #define CIBR0 __REG(0x50000028)
856 #define CIBR1 __REG(0x50000030)
857 #define CIBR2 __REG(0x50000038)
859 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
860 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
861 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
862 #define CICR0_ENB (1 << 28) /* Camera interface enable */
863 #define CICR0_DIS (1 << 27) /* Camera interface disable */
864 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
865 #define CICR0_TOM (1 << 9) /* Time-out mask */
866 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
867 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
868 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
869 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
870 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
871 #define CICR0_CDM (1 << 3) /* Disable-done mask */
872 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
873 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
874 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
876 #define CICR1_TBIT (1 << 31) /* Transparency bit */
877 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
878 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
879 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
880 #define CICR1_RGB_F (1 << 11) /* RGB format */
881 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
882 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
883 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
884 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
885 #define CICR1_DW (0x7 << 0) /* Data width mask */
887 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
889 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
891 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
892 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
894 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
897 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
899 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
901 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
902 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
904 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
906 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
907 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
908 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
909 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
910 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
911 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
912 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
913 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
915 #define CISR_FTO (1 << 15) /* FIFO time-out */
916 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
917 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
918 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
919 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
920 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
921 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
922 #define CISR_EOL (1 << 8) /* End of line */
923 #define CISR_PAR_ERR (1 << 7) /* Parity error */
924 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
925 #define CISR_CDD (1 << 5) /* Camera interface disable done */
926 #define CISR_SOF (1 << 4) /* Start of frame */
927 #define CISR_EOF (1 << 3) /* End of frame */
928 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
929 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
930 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
932 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
933 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
934 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
935 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
936 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
937 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
938 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
939 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
941 #define SRAM_SIZE 0x40000 /* 4x64K */
943 #define SRAM_MEM_PHYS 0x5C000000
945 #define IMPMCR __REG(0x58000000) /* IM Power Management Control Reg */
946 #define IMPMSR __REG(0x58000008) /* IM Power Management Status Reg */
948 #define IMPMCR_PC3 (0x3 << 22) /* Bank 3 Power Control */
949 #define IMPMCR_PC3_RUN_MODE (0x0 << 22) /* Run mode */
950 #define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /* Standby mode */
951 #define IMPMCR_PC3_AUTO_MODE (0x3 << 22) /* Automatically controlled */
953 #define IMPMCR_PC2 (0x3 << 20) /* Bank 2 Power Control */
954 #define IMPMCR_PC2_RUN_MODE (0x0 << 20) /* Run mode */
955 #define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /* Standby mode */
956 #define IMPMCR_PC2_AUTO_MODE (0x3 << 20) /* Automatically controlled */
958 #define IMPMCR_PC1 (0x3 << 18) /* Bank 1 Power Control */
959 #define IMPMCR_PC1_RUN_MODE (0x0 << 18) /* Run mode */
960 #define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /* Standby mode */
961 #define IMPMCR_PC1_AUTO_MODE (0x3 << 18) /* Automatically controlled */
963 #define IMPMCR_PC0 (0x3 << 16) /* Bank 0 Power Control */
964 #define IMPMCR_PC0_RUN_MODE (0x0 << 16) /* Run mode */
965 #define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /* Standby mode */
966 #define IMPMCR_PC0_AUTO_MODE (0x3 << 16) /* Automatically controlled */
968 #define IMPMCR_AW3 (1 << 11) /* Bank 3 Automatic Wake-up enable */
969 #define IMPMCR_AW2 (1 << 10) /* Bank 2 Automatic Wake-up enable */
970 #define IMPMCR_AW1 (1 << 9) /* Bank 1 Automatic Wake-up enable */
971 #define IMPMCR_AW0 (1 << 8) /* Bank 0 Automatic Wake-up enable */
973 #define IMPMCR_DST (0xFF << 0) /* Delay Standby Time, ms */
975 #define IMPMSR_PS3 (0x3 << 6) /* Bank 3 Power Status: */
976 #define IMPMSR_PS3_RUN_MODE (0x0 << 6) /* Run mode */
977 #define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /* Standby mode */
979 #define IMPMSR_PS2 (0x3 << 4) /* Bank 2 Power Status: */
980 #define IMPMSR_PS2_RUN_MODE (0x0 << 4) /* Run mode */
981 #define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /* Standby mode */
983 #define IMPMSR_PS1 (0x3 << 2) /* Bank 1 Power Status: */
984 #define IMPMSR_PS1_RUN_MODE (0x0 << 2) /* Run mode */
985 #define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /* Standby mode */
987 #define IMPMSR_PS0 (0x3 << 0) /* Bank 0 Power Status: */
988 #define IMPMSR_PS0_RUN_MODE (0x0 << 0) /* Run mode */
989 #define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /* Standby mode */
993 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
995 * UHC: USB Host Controller (OHCI-like) register definitions
997 #define UHC_BASE_PHYS (0x4C000000)
998 #define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
999 #define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
1000 #define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
1001 #define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
1002 #define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
1003 #define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
1004 #define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
1005 #define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
1006 #define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
1007 #define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
1008 #define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
1009 #define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
1010 #define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
1011 #define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
1012 #define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
1013 #define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
1014 #define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
1015 #define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
1017 #define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
1018 #define UHCRHDA_NOCP (1 << 12) /* No over current protection */
1020 #define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
1021 #define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
1022 #define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
1023 #define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
1024 #define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
1026 #define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
1027 #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
1028 #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
1029 #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
1030 #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
1031 #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
1032 #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
1033 #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
1034 #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
1035 #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
1037 #define UHCHR __REG(0x4C000064) /* UHC Reset Register */
1038 #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
1039 #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
1040 #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
1041 #define UHCHR_PCPL (1 << 7) /* Power control polarity low */
1042 #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
1043 #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
1044 #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
1045 #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
1046 #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
1047 #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
1048 #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
1050 #define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
1051 #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
1052 #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
1053 #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
1054 #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
1055 #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
1057 #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
1058 #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
1060 #define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
1062 #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
1064 /* PWRMODE register M field values */
1066 #define PWRMODE_IDLE 0x1
1067 #define PWRMODE_STANDBY 0x2
1068 #define PWRMODE_SLEEP 0x3
1069 #define PWRMODE_DEEPSLEEP 0x7
