drivers/net/ixgbe/ixgbe_common.h

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #ifndef _IXGBE_COMMON_H_
  30 #define _IXGBE_COMMON_H_
  31
  32 #include "ixgbe_type.h"
  33
  34 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
  35 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
  36 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
  37 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
  38 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);
  39 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
  40 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
  41 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
  42
  43 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
  44 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
  45
  46 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
  47 s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
  48 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
  49                                        u16 *data);
  50 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
  51                                            u16 *checksum_val);
  52 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
  53
  54 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
  55                           u32 enable_addr);
  56 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
  57 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
  58 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
  59                                       u32 mc_addr_count,
  60                                       ixgbe_mc_addr_itr func);
  61 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
  62                                       u32 addr_count, ixgbe_mc_addr_itr func);
  63 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
  64 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
  65
  66 s32 ixgbe_validate_mac_addr(u8 *mac_addr);
  67 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
  68 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
  69 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
  70
  71 s32 ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 *val);
  72 s32 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val);
  73
  74 #define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
  75
  76 #define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
  77
  78 #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\
  79     writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
  80
  81 #define IXGBE_READ_REG_ARRAY(a, reg, offset) (\
  82     readl((a)->hw_addr + (reg) + ((offset) << 2)))
  83
  84 #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
  85
  86 #ifdef DEBUG
  87 #define hw_dbg(hw, format, arg...) \
  88 printk(KERN_DEBUG, "%s: " format, ixgbe_get_hw_dev_name(hw), ##arg);
  89 #else
  90 static inline int __attribute__ ((format (printf, 2, 3)))
  91 hw_dbg(struct ixgbe_hw *hw, const char *format, ...)
  92 {
  93         return 0;
  94 }
  95 #endif
  96
  97 #endif /* IXGBE_COMMON */