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sata_mv: async notify for genIIe only
[linux-2.6/mini2440.git] / drivers / ata / sata_mv.c
blob239ea4778c56877fee3f10ef6f7476e568f7e290
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2008: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25 /*
26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
39 *
40 * --> Develop a low-power-consumption strategy, and implement it.
41 *
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
46 *
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
50 *
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
53 */
54
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <linux/interrupt.h>
62 #include <linux/dmapool.h>
63 #include <linux/dma-mapping.h>
64 #include <linux/device.h>
65 #include <linux/platform_device.h>
66 #include <linux/ata_platform.h>
67 #include <linux/mbus.h>
68 #include <linux/bitops.h>
69 #include <scsi/scsi_host.h>
70 #include <scsi/scsi_cmnd.h>
71 #include <scsi/scsi_device.h>
72 #include <linux/libata.h>
73
74 #define DRV_NAME "sata_mv"
75 #define DRV_VERSION "1.20"
76
77 enum {
78 /* BAR's are enumerated in terms of pci_resource_start() terms */
79 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
80 MV_IO_BAR = 2, /* offset 0x18: IO space */
81 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
82
83 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
84 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
85
86 MV_PCI_REG_BASE = 0,
87 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
88 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
89 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
90 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
91 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
92 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
93
94 MV_SATAHC0_REG_BASE = 0x20000,
95 MV_FLASH_CTL_OFS = 0x1046c,
96 MV_GPIO_PORT_CTL_OFS = 0x104f0,
97 MV_RESET_CFG_OFS = 0x180d8,
98
99 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
101 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
102 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
103
104 MV_MAX_Q_DEPTH = 32,
105 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
106
107 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
108 * CRPB needs alignment on a 256B boundary. Size == 256B
109 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
110 */
111 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
112 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
113 MV_MAX_SG_CT = 256,
114 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
115
116 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
117 MV_PORT_HC_SHIFT = 2,
118 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
119 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
120 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
121
122 /* Host Flags */
123 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
124 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
125 /* SoC integrated controllers, no PCI interface */
126 MV_FLAG_SOC = (1 << 28),
127
128 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
129 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
130 ATA_FLAG_PIO_POLLING,
131
132 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
133
134 MV_GENIIE_FLAGS = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
135 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
136 ATA_FLAG_NCQ | ATA_FLAG_AN,
137
138 CRQB_FLAG_READ = (1 << 0),
139 CRQB_TAG_SHIFT = 1,
140 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
141 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
142 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
143 CRQB_CMD_ADDR_SHIFT = 8,
144 CRQB_CMD_CS = (0x2 << 11),
145 CRQB_CMD_LAST = (1 << 15),
146
147 CRPB_FLAG_STATUS_SHIFT = 8,
148 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
149 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
150
151 EPRD_FLAG_END_OF_TBL = (1 << 31),
152
153 /* PCI interface registers */
154
155 PCI_COMMAND_OFS = 0xc00,
156 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
157
158 PCI_MAIN_CMD_STS_OFS = 0xd30,
159 STOP_PCI_MASTER = (1 << 2),
160 PCI_MASTER_EMPTY = (1 << 3),
161 GLOB_SFT_RST = (1 << 4),
162
163 MV_PCI_MODE_OFS = 0xd00,
164 MV_PCI_MODE_MASK = 0x30,
165
166 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
167 MV_PCI_DISC_TIMER = 0xd04,
168 MV_PCI_MSI_TRIGGER = 0xc38,
169 MV_PCI_SERR_MASK = 0xc28,
170 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
171 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
172 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
173 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
174 MV_PCI_ERR_COMMAND = 0x1d50,
175
176 PCI_IRQ_CAUSE_OFS = 0x1d58,
177 PCI_IRQ_MASK_OFS = 0x1d5c,
178 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
179
180 PCIE_IRQ_CAUSE_OFS = 0x1900,
181 PCIE_IRQ_MASK_OFS = 0x1910,
182 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
183
184 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
185 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
186 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
187 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
188 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
189 ERR_IRQ = (1 << 0), /* shift by port # */
190 DONE_IRQ = (1 << 1), /* shift by port # */
191 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
192 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
193 PCI_ERR = (1 << 18),
194 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
195 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
196 PORTS_0_3_COAL_DONE = (1 << 8),
197 PORTS_4_7_COAL_DONE = (1 << 17),
198 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
199 GPIO_INT = (1 << 22),
200 SELF_INT = (1 << 23),
201 TWSI_INT = (1 << 24),
202 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
203 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
204 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
205 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
206 PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
207 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
208 HC_MAIN_RSVD),
209 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
210 HC_MAIN_RSVD_5),
211 HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
212
213 /* SATAHC registers */
214 HC_CFG_OFS = 0,
215
216 HC_IRQ_CAUSE_OFS = 0x14,
217 DMA_IRQ = (1 << 0), /* shift by port # */
218 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
219 DEV_IRQ = (1 << 8), /* shift by port # */
220
221 /* Shadow block registers */
222 SHD_BLK_OFS = 0x100,
223 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
224
225 /* SATA registers */
226 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
227 SATA_ACTIVE_OFS = 0x350,
228 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
229 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
230
231 LTMODE_OFS = 0x30c,
232 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
233
234 PHY_MODE3 = 0x310,
235 PHY_MODE4 = 0x314,
236 PHY_MODE2 = 0x330,
237 SATA_IFCTL_OFS = 0x344,
238 SATA_TESTCTL_OFS = 0x348,
239 SATA_IFSTAT_OFS = 0x34c,
240 VENDOR_UNIQUE_FIS_OFS = 0x35c,
241
242 FISCFG_OFS = 0x360,
243 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
244 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
245
246 MV5_PHY_MODE = 0x74,
247 MV5_LTMODE_OFS = 0x30,
248 MV5_PHY_CTL_OFS = 0x0C,
249 SATA_INTERFACE_CFG_OFS = 0x050,
250
251 MV_M2_PREAMP_MASK = 0x7e0,
252
253 /* Port registers */
254 EDMA_CFG_OFS = 0,
255 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
256 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
257 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
258 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
259 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
260 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
261 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
262
263 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
264 EDMA_ERR_IRQ_MASK_OFS = 0xc,
265 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
266 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
267 EDMA_ERR_DEV = (1 << 2), /* device error */
268 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
269 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
270 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
271 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
272 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
273 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
274 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
275 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
276 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
277 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
278 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
279
280 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
281 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
282 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
283 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
284 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
285
286 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
287
288 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
289 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
290 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
291 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
292 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
293 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
294
295 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
296
297 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
298 EDMA_ERR_OVERRUN_5 = (1 << 5),
299 EDMA_ERR_UNDERRUN_5 = (1 << 6),
300
301 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
302 EDMA_ERR_LNK_CTRL_RX_1 |
303 EDMA_ERR_LNK_CTRL_RX_3 |
304 EDMA_ERR_LNK_CTRL_TX,
305
306 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
307 EDMA_ERR_PRD_PAR |
308 EDMA_ERR_DEV_DCON |
309 EDMA_ERR_DEV_CON |
310 EDMA_ERR_SERR |
311 EDMA_ERR_SELF_DIS |
312 EDMA_ERR_CRQB_PAR |
313 EDMA_ERR_CRPB_PAR |
314 EDMA_ERR_INTRL_PAR |
315 EDMA_ERR_IORDY |
316 EDMA_ERR_LNK_CTRL_RX_2 |
317 EDMA_ERR_LNK_DATA_RX |
318 EDMA_ERR_LNK_DATA_TX |
319 EDMA_ERR_TRANS_PROTO,
320
321 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
322 EDMA_ERR_PRD_PAR |
323 EDMA_ERR_DEV_DCON |
324 EDMA_ERR_DEV_CON |
325 EDMA_ERR_OVERRUN_5 |
326 EDMA_ERR_UNDERRUN_5 |
327 EDMA_ERR_SELF_DIS_5 |
328 EDMA_ERR_CRQB_PAR |
329 EDMA_ERR_CRPB_PAR |
330 EDMA_ERR_INTRL_PAR |
331 EDMA_ERR_IORDY,
332
333 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
334 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
335
336 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
337 EDMA_REQ_Q_PTR_SHIFT = 5,
338
339 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
340 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
341 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
342 EDMA_RSP_Q_PTR_SHIFT = 3,
343
344 EDMA_CMD_OFS = 0x28, /* EDMA command register */
345 EDMA_EN = (1 << 0), /* enable EDMA */
346 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
347 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
348
349 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
350 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
351 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
352
353 EDMA_IORDY_TMOUT_OFS = 0x34,
354 EDMA_ARB_CFG_OFS = 0x38,
355
356 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
357
358 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
359
360 /* Host private flags (hp_flags) */
361 MV_HP_FLAG_MSI = (1 << 0),
362 MV_HP_ERRATA_50XXB0 = (1 << 1),
363 MV_HP_ERRATA_50XXB2 = (1 << 2),
364 MV_HP_ERRATA_60X1B2 = (1 << 3),
365 MV_HP_ERRATA_60X1C0 = (1 << 4),
366 MV_HP_ERRATA_XX42A0 = (1 << 5),
367 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
368 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
369 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
370 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
371 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
372
373 /* Port private flags (pp_flags) */
374 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
375 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
376 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
377 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
378 };
379
380 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
381 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
382 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
383 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
384 #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
385
386 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
387 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
388
389 enum {
390 /* DMA boundary 0xffff is required by the s/g splitting
391 * we need on /length/ in mv_fill-sg().
392 */
393 MV_DMA_BOUNDARY = 0xffffU,
394
395 /* mask of register bits containing lower 32 bits
396 * of EDMA request queue DMA address
397 */
398 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
399
400 /* ditto, for response queue */
401 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
402 };
403
404 enum chip_type {
405 chip_504x,
406 chip_508x,
407 chip_5080,
408 chip_604x,
409 chip_608x,
410 chip_6042,
411 chip_7042,
412 chip_soc,
413 };
414
415 /* Command ReQuest Block: 32B */
416 struct mv_crqb {
417 __le32 sg_addr;
418 __le32 sg_addr_hi;
419 __le16 ctrl_flags;
420 __le16 ata_cmd[11];
421 };
422
423 struct mv_crqb_iie {
424 __le32 addr;
425 __le32 addr_hi;
426 __le32 flags;
427 __le32 len;
428 __le32 ata_cmd[4];
429 };
430
431 /* Command ResPonse Block: 8B */
432 struct mv_crpb {
433 __le16 id;
434 __le16 flags;
435 __le32 tmstmp;
436 };
437
438 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
439 struct mv_sg {
440 __le32 addr;
441 __le32 flags_size;
442 __le32 addr_hi;
443 __le32 reserved;
444 };
445
446 struct mv_port_priv {
447 struct mv_crqb *crqb;
448 dma_addr_t crqb_dma;
449 struct mv_crpb *crpb;
450 dma_addr_t crpb_dma;
451 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
452 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
453
454 unsigned int req_idx;
455 unsigned int resp_idx;
456
457 u32 pp_flags;
458 unsigned int delayed_eh_pmp_map;
459 };
460
461 struct mv_port_signal {
462 u32 amps;
463 u32 pre;
464 };
465
466 struct mv_host_priv {
467 u32 hp_flags;
468 struct mv_port_signal signal[8];
469 const struct mv_hw_ops *ops;
470 int n_ports;
471 void __iomem *base;
472 void __iomem *main_irq_cause_addr;
473 void __iomem *main_irq_mask_addr;
474 u32 irq_cause_ofs;
475 u32 irq_mask_ofs;
476 u32 unmask_all_irqs;
477 /*
478 * These consistent DMA memory pools give us guaranteed
479 * alignment for hardware-accessed data structures,
480 * and less memory waste in accomplishing the alignment.
481 */
482 struct dma_pool *crqb_pool;
483 struct dma_pool *crpb_pool;
484 struct dma_pool *sg_tbl_pool;
485 };
486
487 struct mv_hw_ops {
488 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
489 unsigned int port);
490 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
491 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
492 void __iomem *mmio);
493 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
494 unsigned int n_hc);
495 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
496 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
497 };
498
499 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
500 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
501 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
502 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
503 static int mv_port_start(struct ata_port *ap);
504 static void mv_port_stop(struct ata_port *ap);
505 static int mv_qc_defer(struct ata_queued_cmd *qc);
506 static void mv_qc_prep(struct ata_queued_cmd *qc);
507 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
508 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
509 static int mv_hardreset(struct ata_link *link, unsigned int *class,
510 unsigned long deadline);
511 static void mv_eh_freeze(struct ata_port *ap);
512 static void mv_eh_thaw(struct ata_port *ap);
513 static void mv6_dev_config(struct ata_device *dev);
514
515 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
516 unsigned int port);
517 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
518 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
519 void __iomem *mmio);
520 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
521 unsigned int n_hc);
522 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
523 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
524
525 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
526 unsigned int port);
527 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
528 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
529 void __iomem *mmio);
530 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
531 unsigned int n_hc);
532 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
533 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
534 void __iomem *mmio);
535 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
536 void __iomem *mmio);
537 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
538 void __iomem *mmio, unsigned int n_hc);
539 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
540 void __iomem *mmio);
541 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
542 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
543 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
544 unsigned int port_no);
545 static int mv_stop_edma(struct ata_port *ap);
546 static int mv_stop_edma_engine(void __iomem *port_mmio);
547 static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
548
549 static void mv_pmp_select(struct ata_port *ap, int pmp);
550 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
551 unsigned long deadline);
552 static int mv_softreset(struct ata_link *link, unsigned int *class,
553 unsigned long deadline);
554 static void mv_pmp_error_handler(struct ata_port *ap);
555 static void mv_process_crpb_entries(struct ata_port *ap,
556 struct mv_port_priv *pp);
557
558 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
559 * because we have to allow room for worst case splitting of
560 * PRDs for 64K boundaries in mv_fill_sg().
561 */
562 static struct scsi_host_template mv5_sht = {
563 ATA_BASE_SHT(DRV_NAME),
564 .sg_tablesize = MV_MAX_SG_CT / 2,
565 .dma_boundary = MV_DMA_BOUNDARY,
566 };
567
568 static struct scsi_host_template mv6_sht = {
569 ATA_NCQ_SHT(DRV_NAME),
570 .can_queue = MV_MAX_Q_DEPTH - 1,
571 .sg_tablesize = MV_MAX_SG_CT / 2,
572 .dma_boundary = MV_DMA_BOUNDARY,
573 };
574
575 static struct ata_port_operations mv5_ops = {
576 .inherits = &ata_sff_port_ops,
577
578 .qc_defer = mv_qc_defer,
579 .qc_prep = mv_qc_prep,
580 .qc_issue = mv_qc_issue,
581
582 .freeze = mv_eh_freeze,
583 .thaw = mv_eh_thaw,
584 .hardreset = mv_hardreset,
585 .error_handler = ata_std_error_handler, /* avoid SFF EH */
586 .post_internal_cmd = ATA_OP_NULL,
587
588 .scr_read = mv5_scr_read,
589 .scr_write = mv5_scr_write,
590
591 .port_start = mv_port_start,
592 .port_stop = mv_port_stop,
593 };
594
595 static struct ata_port_operations mv6_ops = {
596 .inherits = &mv5_ops,
597 .dev_config = mv6_dev_config,
598 .scr_read = mv_scr_read,
599 .scr_write = mv_scr_write,
600
601 .pmp_hardreset = mv_pmp_hardreset,
602 .pmp_softreset = mv_softreset,
603 .softreset = mv_softreset,
604 .error_handler = mv_pmp_error_handler,
605 };
606
607 static struct ata_port_operations mv_iie_ops = {
608 .inherits = &mv6_ops,
609 .dev_config = ATA_OP_NULL,
610 .qc_prep = mv_qc_prep_iie,
611 };
612
613 static const struct ata_port_info mv_port_info[] = {
614 { /* chip_504x */
615 .flags = MV_COMMON_FLAGS,
616 .pio_mask = 0x1f, /* pio0-4 */
617 .udma_mask = ATA_UDMA6,
618 .port_ops = &mv5_ops,
619 },
620 { /* chip_508x */
621 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
622 .pio_mask = 0x1f, /* pio0-4 */
623 .udma_mask = ATA_UDMA6,
624 .port_ops = &mv5_ops,
625 },
626 { /* chip_5080 */
627 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
628 .pio_mask = 0x1f, /* pio0-4 */
629 .udma_mask = ATA_UDMA6,
630 .port_ops = &mv5_ops,
631 },
632 { /* chip_604x */
633 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
634 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
635 ATA_FLAG_NCQ,
636 .pio_mask = 0x1f, /* pio0-4 */
637 .udma_mask = ATA_UDMA6,
638 .port_ops = &mv6_ops,
639 },
640 { /* chip_608x */
641 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
642 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
643 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
644 .pio_mask = 0x1f, /* pio0-4 */
645 .udma_mask = ATA_UDMA6,
646 .port_ops = &mv6_ops,
647 },
648 { /* chip_6042 */
649 .flags = MV_GENIIE_FLAGS,
650 .pio_mask = 0x1f, /* pio0-4 */
651 .udma_mask = ATA_UDMA6,
652 .port_ops = &mv_iie_ops,
653 },
654 { /* chip_7042 */
655 .flags = MV_GENIIE_FLAGS,
656 .pio_mask = 0x1f, /* pio0-4 */
657 .udma_mask = ATA_UDMA6,
658 .port_ops = &mv_iie_ops,
659 },
660 { /* chip_soc */
661 .flags = MV_GENIIE_FLAGS | MV_FLAG_SOC,
662 .pio_mask = 0x1f, /* pio0-4 */
663 .udma_mask = ATA_UDMA6,
664 .port_ops = &mv_iie_ops,
665 },
666 };
667
668 static const struct pci_device_id mv_pci_tbl[] = {
669 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
670 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
671 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
672 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
673 /* RocketRAID 1740/174x have different identifiers */
674 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
675 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
676
677 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
678 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
679 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
680 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
681 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
682
683 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
684
685 /* Adaptec 1430SA */
686 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
687
688 /* Marvell 7042 support */
689 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
690
691 /* Highpoint RocketRAID PCIe series */
692 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
693 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
694
695 { } /* terminate list */
696 };
697
698 static const struct mv_hw_ops mv5xxx_ops = {
699 .phy_errata = mv5_phy_errata,
700 .enable_leds = mv5_enable_leds,
701 .read_preamp = mv5_read_preamp,
702 .reset_hc = mv5_reset_hc,
703 .reset_flash = mv5_reset_flash,
704 .reset_bus = mv5_reset_bus,
705 };
706
707 static const struct mv_hw_ops mv6xxx_ops = {
708 .phy_errata = mv6_phy_errata,
709 .enable_leds = mv6_enable_leds,
710 .read_preamp = mv6_read_preamp,
711 .reset_hc = mv6_reset_hc,
712 .reset_flash = mv6_reset_flash,
713 .reset_bus = mv_reset_pci_bus,
714 };
715
716 static const struct mv_hw_ops mv_soc_ops = {
717 .phy_errata = mv6_phy_errata,
718 .enable_leds = mv_soc_enable_leds,
719 .read_preamp = mv_soc_read_preamp,
720 .reset_hc = mv_soc_reset_hc,
721 .reset_flash = mv_soc_reset_flash,
722 .reset_bus = mv_soc_reset_bus,
723 };
724
725 /*
726 * Functions
727 */
728
729 static inline void writelfl(unsigned long data, void __iomem *addr)
730 {
731 writel(data, addr);
732 (void) readl(addr); /* flush to avoid PCI posted write */
733 }
734
735 static inline unsigned int mv_hc_from_port(unsigned int port)
736 {
737 return port >> MV_PORT_HC_SHIFT;
738 }
739
740 static inline unsigned int mv_hardport_from_port(unsigned int port)
741 {
742 return port & MV_PORT_MASK;
743 }
744
745 /*
746 * Consolidate some rather tricky bit shift calculations.
747 * This is hot-path stuff, so not a function.
748 * Simple code, with two return values, so macro rather than inline.
749 *
750 * port is the sole input, in range 0..7.
751 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
752 * hardport is the other output, in range 0..3.
753 *
754 * Note that port and hardport may be the same variable in some cases.
755 */
756 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
757 { \
758 shift = mv_hc_from_port(port) * HC_SHIFT; \
759 hardport = mv_hardport_from_port(port); \
760 shift += hardport * 2; \
761 }
762
763 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
764 {
765 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
766 }
767
768 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
769 unsigned int port)
770 {
771 return mv_hc_base(base, mv_hc_from_port(port));
772 }
773
774 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
775 {
776 return mv_hc_base_from_port(base, port) +
777 MV_SATAHC_ARBTR_REG_SZ +
778 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
779 }
780
781 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
782 {
783 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
784 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
785
786 return hc_mmio + ofs;
787 }
788
789 static inline void __iomem *mv_host_base(struct ata_host *host)
790 {
791 struct mv_host_priv *hpriv = host->private_data;
792 return hpriv->base;
793 }
794
795 static inline void __iomem *mv_ap_base(struct ata_port *ap)
796 {
797 return mv_port_base(mv_host_base(ap->host), ap->port_no);
798 }
799
800 static inline int mv_get_hc_count(unsigned long port_flags)
801 {
802 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
803 }
804
805 static void mv_set_edma_ptrs(void __iomem *port_mmio,
806 struct mv_host_priv *hpriv,
807 struct mv_port_priv *pp)
808 {
809 u32 index;
810
811 /*
812 * initialize request queue
813 */
814 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
815 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
816
817 WARN_ON(pp->crqb_dma & 0x3ff);
818 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
819 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
820 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
821
822 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
823 writelfl((pp->crqb_dma & 0xffffffff) | index,
824 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
825 else
826 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
827
828 /*
829 * initialize response queue
830 */
831 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
832 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
833
834 WARN_ON(pp->crpb_dma & 0xff);
835 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
836
837 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
838 writelfl((pp->crpb_dma & 0xffffffff) | index,
839 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
840 else
841 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
842
843 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
844 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
845 }
846
847 /**
848 * mv_start_dma - Enable eDMA engine
849 * @base: port base address
850 * @pp: port private data
851 *
852 * Verify the local cache of the eDMA state is accurate with a
853 * WARN_ON.
854 *
855 * LOCKING:
856 * Inherited from caller.
857 */
858 static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
859 struct mv_port_priv *pp, u8 protocol)
860 {
861 int want_ncq = (protocol == ATA_PROT_NCQ);
862
863 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
864 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
865 if (want_ncq != using_ncq)
866 mv_stop_edma(ap);
867 }
868 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
869 struct mv_host_priv *hpriv = ap->host->private_data;
870 int hardport = mv_hardport_from_port(ap->port_no);
871 void __iomem *hc_mmio = mv_hc_base_from_port(
872 mv_host_base(ap->host), hardport);
873 u32 hc_irq_cause, ipending;
874
875 /* clear EDMA event indicators, if any */
876 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
877
878 /* clear EDMA interrupt indicator, if any */
879 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
880 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
881 if (hc_irq_cause & ipending) {
882 writelfl(hc_irq_cause & ~ipending,
883 hc_mmio + HC_IRQ_CAUSE_OFS);
884 }
885
886 mv_edma_cfg(ap, want_ncq);
887
888 /* clear FIS IRQ Cause */
889 if (IS_GEN_IIE(hpriv))
890 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
891
892 mv_set_edma_ptrs(port_mmio, hpriv, pp);
893
894 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
895 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
896 }
897 }
898
899 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
900 {
901 void __iomem *port_mmio = mv_ap_base(ap);
902 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
903 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
904 int i;
905
906 /*
907 * Wait for the EDMA engine to finish transactions in progress.
908 * No idea what a good "timeout" value might be, but measurements
909 * indicate that it often requires hundreds of microseconds
910 * with two drives in-use. So we use the 15msec value above
911 * as a rough guess at what even more drives might require.
912 */
913 for (i = 0; i < timeout; ++i) {
914 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
915 if ((edma_stat & empty_idle) == empty_idle)
916 break;
917 udelay(per_loop);
918 }
919 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
920 }
921
922 /**
923 * mv_stop_edma_engine - Disable eDMA engine
924 * @port_mmio: io base address
925 *
926 * LOCKING:
927 * Inherited from caller.
928 */
929 static int mv_stop_edma_engine(void __iomem *port_mmio)
930 {
931 int i;
932
933 /* Disable eDMA. The disable bit auto clears. */
934 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
935
936 /* Wait for the chip to confirm eDMA is off. */
937 for (i = 10000; i > 0; i--) {
938 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
939 if (!(reg & EDMA_EN))
940 return 0;
941 udelay(10);
942 }
943 return -EIO;
944 }
945
946 static int mv_stop_edma(struct ata_port *ap)
947 {
948 void __iomem *port_mmio = mv_ap_base(ap);
949 struct mv_port_priv *pp = ap->private_data;
950
951 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
952 return 0;
953 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
954 mv_wait_for_edma_empty_idle(ap);
955 if (mv_stop_edma_engine(port_mmio)) {
956 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
957 return -EIO;
958 }
959 return 0;
960 }
961
962 #ifdef ATA_DEBUG
963 static void mv_dump_mem(void __iomem *start, unsigned bytes)
964 {
965 int b, w;
966 for (b = 0; b < bytes; ) {
967 DPRINTK("%p: ", start + b);
968 for (w = 0; b < bytes && w < 4; w++) {
969 printk("%08x ", readl(start + b));
970 b += sizeof(u32);
971 }
972 printk("\n");
973 }
974 }
975 #endif
976
977 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
978 {
979 #ifdef ATA_DEBUG
980 int b, w;
981 u32 dw;
982 for (b = 0; b < bytes; ) {
983 DPRINTK("%02x: ", b);
984 for (w = 0; b < bytes && w < 4; w++) {
985 (void) pci_read_config_dword(pdev, b, &dw);
986 printk("%08x ", dw);
987 b += sizeof(u32);
988 }
989 printk("\n");
990 }
991 #endif
992 }
993 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
994 struct pci_dev *pdev)
995 {
996 #ifdef ATA_DEBUG
997 void __iomem *hc_base = mv_hc_base(mmio_base,
998 port >> MV_PORT_HC_SHIFT);
999 void __iomem *port_base;
1000 int start_port, num_ports, p, start_hc, num_hcs, hc;
1001
1002 if (0 > port) {
1003 start_hc = start_port = 0;
1004 num_ports = 8; /* shld be benign for 4 port devs */
1005 num_hcs = 2;
1006 } else {
1007 start_hc = port >> MV_PORT_HC_SHIFT;
1008 start_port = port;
1009 num_ports = num_hcs = 1;
1010 }
1011 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1012 num_ports > 1 ? num_ports - 1 : start_port);
1013
1014 if (NULL != pdev) {
1015 DPRINTK("PCI config space regs:\n");
1016 mv_dump_pci_cfg(pdev, 0x68);
1017 }
1018 DPRINTK("PCI regs:\n");
1019 mv_dump_mem(mmio_base+0xc00, 0x3c);
1020 mv_dump_mem(mmio_base+0xd00, 0x34);
1021 mv_dump_mem(mmio_base+0xf00, 0x4);
1022 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1023 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1024 hc_base = mv_hc_base(mmio_base, hc);
1025 DPRINTK("HC regs (HC %i):\n", hc);
1026 mv_dump_mem(hc_base, 0x1c);
1027 }
1028 for (p = start_port; p < start_port + num_ports; p++) {
1029 port_base = mv_port_base(mmio_base, p);
1030 DPRINTK("EDMA regs (port %i):\n", p);
1031 mv_dump_mem(port_base, 0x54);
1032 DPRINTK("SATA regs (port %i):\n", p);
1033 mv_dump_mem(port_base+0x300, 0x60);
1034 }
1035 #endif
1036 }
1037
1038 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1039 {
1040 unsigned int ofs;
1041
1042 switch (sc_reg_in) {
1043 case SCR_STATUS:
1044 case SCR_CONTROL:
1045 case SCR_ERROR:
1046 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1047 break;
1048 case SCR_ACTIVE:
1049 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1050 break;
1051 default:
1052 ofs = 0xffffffffU;
1053 break;
1054 }
1055 return ofs;
1056 }
1057
1058 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
1059 {
1060 unsigned int ofs = mv_scr_offset(sc_reg_in);
1061
1062 if (ofs != 0xffffffffU) {
1063 *val = readl(mv_ap_base(ap) + ofs);
1064 return 0;
1065 } else
1066 return -EINVAL;
1067 }
1068
1069 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1070 {
1071 unsigned int ofs = mv_scr_offset(sc_reg_in);
1072
1073 if (ofs != 0xffffffffU) {
1074 writelfl(val, mv_ap_base(ap) + ofs);
1075 return 0;
1076 } else
1077 return -EINVAL;
1078 }
1079
1080 static void mv6_dev_config(struct ata_device *adev)
1081 {
1082 /*
1083 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1084 *
1085 * Gen-II does not support NCQ over a port multiplier
1086 * (no FIS-based switching).
1087 *
1088 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1089 * See mv_qc_prep() for more info.
1090 */
1091 if (adev->flags & ATA_DFLAG_NCQ) {
1092 if (sata_pmp_attached(adev->link->ap)) {
1093 adev->flags &= ~ATA_DFLAG_NCQ;
1094 ata_dev_printk(adev, KERN_INFO,
1095 "NCQ disabled for command-based switching\n");
1096 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1097 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1098 ata_dev_printk(adev, KERN_INFO,
1099 "max_sectors limited to %u for NCQ\n",
1100 adev->max_sectors);
1101 }
1102 }
1103 }
1104
1105 static int mv_qc_defer(struct ata_queued_cmd *qc)
1106 {
1107 struct ata_link *link = qc->dev->link;
1108 struct ata_port *ap = link->ap;
1109 struct mv_port_priv *pp = ap->private_data;
1110
1111 /*
1112 * Don't allow new commands if we're in a delayed EH state
1113 * for NCQ and/or FIS-based switching.
1114 */
1115 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1116 return ATA_DEFER_PORT;
1117 /*
1118 * If the port is completely idle, then allow the new qc.
1119 */
1120 if (ap->nr_active_links == 0)
1121 return 0;
1122
1123 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1124 /*
1125 * The port is operating in host queuing mode (EDMA).
1126 * It can accomodate a new qc if the qc protocol
1127 * is compatible with the current host queue mode.
1128 */
1129 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1130 /*
1131 * The host queue (EDMA) is in NCQ mode.
1132 * If the new qc is also an NCQ command,
1133 * then allow the new qc.
1134 */
1135 if (qc->tf.protocol == ATA_PROT_NCQ)
1136 return 0;
1137 } else {
1138 /*
1139 * The host queue (EDMA) is in non-NCQ, DMA mode.
1140 * If the new qc is also a non-NCQ, DMA command,
1141 * then allow the new qc.
1142 */
1143 if (qc->tf.protocol == ATA_PROT_DMA)
1144 return 0;
1145 }
1146 }
1147 return ATA_DEFER_PORT;
1148 }
1149
1150 static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
1151 {
1152 u32 new_fiscfg, old_fiscfg;
1153 u32 new_ltmode, old_ltmode;
1154 u32 new_haltcond, old_haltcond;
1155
1156 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1157 old_ltmode = readl(port_mmio + LTMODE_OFS);
1158 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1159
1160 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1161 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1162 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1163
1164 if (want_fbs) {
1165 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1166 new_ltmode = old_ltmode | LTMODE_BIT8;
1167 if (want_ncq)
1168 new_haltcond &= ~EDMA_ERR_DEV;
1169 else
1170 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
1171 }
1172
1173 if (new_fiscfg != old_fiscfg)
1174 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
1175 if (new_ltmode != old_ltmode)
1176 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
1177 if (new_haltcond != old_haltcond)
1178 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
1179 }
1180
1181 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1182 {
1183 struct mv_host_priv *hpriv = ap->host->private_data;
1184 u32 old, new;
1185
1186 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1187 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1188 if (want_ncq)
1189 new = old | (1 << 22);
1190 else
1191 new = old & ~(1 << 22);
1192 if (new != old)
1193 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1194 }
1195
1196 static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
1197 {
1198 u32 cfg;
1199 struct mv_port_priv *pp = ap->private_data;
1200 struct mv_host_priv *hpriv = ap->host->private_data;
1201 void __iomem *port_mmio = mv_ap_base(ap);
1202
1203 /* set up non-NCQ EDMA configuration */
1204 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1205 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
1206
1207 if (IS_GEN_I(hpriv))
1208 cfg |= (1 << 8); /* enab config burst size mask */
1209
1210 else if (IS_GEN_II(hpriv)) {
1211 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1212 mv_60x1_errata_sata25(ap, want_ncq);
1213
1214 } else if (IS_GEN_IIE(hpriv)) {
1215 int want_fbs = sata_pmp_attached(ap);
1216 /*
1217 * Possible future enhancement:
1218 *
1219 * The chip can use FBS with non-NCQ, if we allow it,
1220 * But first we need to have the error handling in place
1221 * for this mode (datasheet section 7.3.15.4.2.3).
1222 * So disallow non-NCQ FBS for now.
1223 */
1224 want_fbs &= want_ncq;
1225
1226 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1227
1228 if (want_fbs) {
1229 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1230 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1231 }
1232
1233 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1234 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1235 if (HAS_PCI(ap->host))
1236 cfg |= (1 << 18); /* enab early completion */
1237 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1238 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1239 }
1240
1241 if (want_ncq) {
1242 cfg |= EDMA_CFG_NCQ;
1243 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1244 } else
1245 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1246
1247 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1248 }
1249
1250 static void mv_port_free_dma_mem(struct ata_port *ap)
1251 {
1252 struct mv_host_priv *hpriv = ap->host->private_data;
1253 struct mv_port_priv *pp = ap->private_data;
1254 int tag;
1255
1256 if (pp->crqb) {
1257 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1258 pp->crqb = NULL;
1259 }
1260 if (pp->crpb) {
1261 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1262 pp->crpb = NULL;
1263 }
1264 /*
1265 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1266 * For later hardware, we have one unique sg_tbl per NCQ tag.
1267 */
1268 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1269 if (pp->sg_tbl[tag]) {
1270 if (tag == 0 || !IS_GEN_I(hpriv))
1271 dma_pool_free(hpriv->sg_tbl_pool,
1272 pp->sg_tbl[tag],
1273 pp->sg_tbl_dma[tag]);
1274 pp->sg_tbl[tag] = NULL;
1275 }
1276 }
1277 }
1278
1279 /**
1280 * mv_port_start - Port specific init/start routine.
1281 * @ap: ATA channel to manipulate
1282 *
1283 * Allocate and point to DMA memory, init port private memory,
1284 * zero indices.
1285 *
1286 * LOCKING:
1287 * Inherited from caller.
1288 */
1289 static int mv_port_start(struct ata_port *ap)
1290 {
1291 struct device *dev = ap->host->dev;
1292 struct mv_host_priv *hpriv = ap->host->private_data;
1293 struct mv_port_priv *pp;
1294 int tag;
1295
1296 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1297 if (!pp)
1298 return -ENOMEM;
1299 ap->private_data = pp;
1300
1301 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1302 if (!pp->crqb)
1303 return -ENOMEM;
1304 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1305
1306 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1307 if (!pp->crpb)
1308 goto out_port_free_dma_mem;
1309 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1310
1311 /*
1312 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1313 * For later hardware, we need one unique sg_tbl per NCQ tag.
1314 */
1315 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1316 if (tag == 0 || !IS_GEN_I(hpriv)) {
1317 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1318 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1319 if (!pp->sg_tbl[tag])
1320 goto out_port_free_dma_mem;
1321 } else {
1322 pp->sg_tbl[tag] = pp->sg_tbl[0];
1323 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1324 }
1325 }
1326 return 0;
1327
1328 out_port_free_dma_mem:
1329 mv_port_free_dma_mem(ap);
1330 return -ENOMEM;
1331 }
1332
1333 /**
1334 * mv_port_stop - Port specific cleanup/stop routine.
1335 * @ap: ATA channel to manipulate
1336 *
1337 * Stop DMA, cleanup port memory.
1338 *
1339 * LOCKING:
1340 * This routine uses the host lock to protect the DMA stop.
1341 */
1342 static void mv_port_stop(struct ata_port *ap)
1343 {
1344 mv_stop_edma(ap);
1345 mv_port_free_dma_mem(ap);
1346 }
1347
1348 /**
1349 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1350 * @qc: queued command whose SG list to source from
1351 *
1352 * Populate the SG list and mark the last entry.
1353 *
1354 * LOCKING:
1355 * Inherited from caller.
1356 */
1357 static void mv_fill_sg(struct ata_queued_cmd *qc)
1358 {
1359 struct mv_port_priv *pp = qc->ap->private_data;
1360 struct scatterlist *sg;
1361 struct mv_sg *mv_sg, *last_sg = NULL;
1362 unsigned int si;
1363
1364 mv_sg = pp->sg_tbl[qc->tag];
1365 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1366 dma_addr_t addr = sg_dma_address(sg);
1367 u32 sg_len = sg_dma_len(sg);
1368
1369 while (sg_len) {
1370 u32 offset = addr & 0xffff;
1371 u32 len = sg_len;
1372
1373 if ((offset + sg_len > 0x10000))
1374 len = 0x10000 - offset;
1375
1376 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1377 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1378 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1379
1380 sg_len -= len;
1381 addr += len;
1382
1383 last_sg = mv_sg;
1384 mv_sg++;
1385 }
1386 }
1387
1388 if (likely(last_sg))
1389 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1390 }
1391
1392 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1393 {
1394 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1395 (last ? CRQB_CMD_LAST : 0);
1396 *cmdw = cpu_to_le16(tmp);
1397 }
1398
1399 /**
1400 * mv_qc_prep - Host specific command preparation.
1401 * @qc: queued command to prepare
1402 *
1403 * This routine simply redirects to the general purpose routine
1404 * if command is not DMA. Else, it handles prep of the CRQB
1405 * (command request block), does some sanity checking, and calls
1406 * the SG load routine.
1407 *
1408 * LOCKING:
1409 * Inherited from caller.
1410 */
1411 static void mv_qc_prep(struct ata_queued_cmd *qc)
1412 {
1413 struct ata_port *ap = qc->ap;
1414 struct mv_port_priv *pp = ap->private_data;
1415 __le16 *cw;
1416 struct ata_taskfile *tf;
1417 u16 flags = 0;
1418 unsigned in_index;
1419
1420 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1421 (qc->tf.protocol != ATA_PROT_NCQ))
1422 return;
1423
1424 /* Fill in command request block
1425 */
1426 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1427 flags |= CRQB_FLAG_READ;
1428 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1429 flags |= qc->tag << CRQB_TAG_SHIFT;
1430 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1431
1432 /* get current queue index from software */
1433 in_index = pp->req_idx;
1434
1435 pp->crqb[in_index].sg_addr =
1436 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1437 pp->crqb[in_index].sg_addr_hi =
1438 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1439 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1440
1441 cw = &pp->crqb[in_index].ata_cmd[0];
1442 tf = &qc->tf;
1443
1444 /* Sadly, the CRQB cannot accomodate all registers--there are
1445 * only 11 bytes...so we must pick and choose required
1446 * registers based on the command. So, we drop feature and
1447 * hob_feature for [RW] DMA commands, but they are needed for
1448 * NCQ. NCQ will drop hob_nsect.
1449 */
1450 switch (tf->command) {
1451 case ATA_CMD_READ:
1452 case ATA_CMD_READ_EXT:
1453 case ATA_CMD_WRITE:
1454 case ATA_CMD_WRITE_EXT:
1455 case ATA_CMD_WRITE_FUA_EXT:
1456 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1457 break;
1458 case ATA_CMD_FPDMA_READ:
1459 case ATA_CMD_FPDMA_WRITE:
1460 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1461 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1462 break;
1463 default:
1464 /* The only other commands EDMA supports in non-queued and
1465 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1466 * of which are defined/used by Linux. If we get here, this
1467 * driver needs work.
1468 *
1469 * FIXME: modify libata to give qc_prep a return value and
1470 * return error here.
1471 */
1472 BUG_ON(tf->command);
1473 break;
1474 }
1475 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1476 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1477 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1478 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1479 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1480 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1481 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1482 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1483 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1484
1485 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1486 return;
1487 mv_fill_sg(qc);
1488 }
1489
1490 /**
1491 * mv_qc_prep_iie - Host specific command preparation.
1492 * @qc: queued command to prepare
1493 *
1494 * This routine simply redirects to the general purpose routine
1495 * if command is not DMA. Else, it handles prep of the CRQB
1496 * (command request block), does some sanity checking, and calls
1497 * the SG load routine.
1498 *
1499 * LOCKING:
1500 * Inherited from caller.
1501 */
1502 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1503 {
1504 struct ata_port *ap = qc->ap;
1505 struct mv_port_priv *pp = ap->private_data;
1506 struct mv_crqb_iie *crqb;
1507 struct ata_taskfile *tf;
1508 unsigned in_index;
1509 u32 flags = 0;
1510
1511 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1512 (qc->tf.protocol != ATA_PROT_NCQ))
1513 return;
1514
1515 /* Fill in Gen IIE command request block */
1516 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1517 flags |= CRQB_FLAG_READ;
1518
1519 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1520 flags |= qc->tag << CRQB_TAG_SHIFT;
1521 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
1522 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1523
1524 /* get current queue index from software */
1525 in_index = pp->req_idx;
1526
1527 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1528 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1529 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1530 crqb->flags = cpu_to_le32(flags);
1531
1532 tf = &qc->tf;
1533 crqb->ata_cmd[0] = cpu_to_le32(
1534 (tf->command << 16) |
1535 (tf->feature << 24)
1536 );
1537 crqb->ata_cmd[1] = cpu_to_le32(
1538 (tf->lbal << 0) |
1539 (tf->lbam << 8) |
1540 (tf->lbah << 16) |
1541 (tf->device << 24)
1542 );
1543 crqb->ata_cmd[2] = cpu_to_le32(
1544 (tf->hob_lbal << 0) |
1545 (tf->hob_lbam << 8) |
1546 (tf->hob_lbah << 16) |
1547 (tf->hob_feature << 24)
1548 );
1549 crqb->ata_cmd[3] = cpu_to_le32(
1550 (tf->nsect << 0) |
1551 (tf->hob_nsect << 8)
1552 );
1553
1554 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1555 return;
1556 mv_fill_sg(qc);
1557 }
1558
1559 /**
1560 * mv_qc_issue - Initiate a command to the host
1561 * @qc: queued command to start
1562 *
1563 * This routine simply redirects to the general purpose routine
1564 * if command is not DMA. Else, it sanity checks our local
1565 * caches of the request producer/consumer indices then enables
1566 * DMA and bumps the request producer index.
1567 *
1568 * LOCKING:
1569 * Inherited from caller.
1570 */
1571 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1572 {
1573 struct ata_port *ap = qc->ap;
1574 void __iomem *port_mmio = mv_ap_base(ap);
1575 struct mv_port_priv *pp = ap->private_data;
1576 u32 in_index;
1577
1578 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1579 (qc->tf.protocol != ATA_PROT_NCQ)) {
1580 /*
1581 * We're about to send a non-EDMA capable command to the
1582 * port. Turn off EDMA so there won't be problems accessing
1583 * shadow block, etc registers.
1584 */
1585 mv_stop_edma(ap);
1586 mv_pmp_select(ap, qc->dev->link->pmp);
1587 return ata_sff_qc_issue(qc);
1588 }
1589
1590 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
1591
1592 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1593 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1594
1595 /* and write the request in pointer to kick the EDMA to life */
1596 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1597 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1598
1599 return 0;
1600 }
1601
1602 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1603 {
1604 struct mv_port_priv *pp = ap->private_data;
1605 struct ata_queued_cmd *qc;
1606
1607 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1608 return NULL;
1609 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1610 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1611 qc = NULL;
1612 return qc;
1613 }
1614
1615 static void mv_pmp_error_handler(struct ata_port *ap)
1616 {
1617 unsigned int pmp, pmp_map;
1618 struct mv_port_priv *pp = ap->private_data;
1619
1620 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1621 /*
1622 * Perform NCQ error analysis on failed PMPs
1623 * before we freeze the port entirely.
1624 *
1625 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1626 */
1627 pmp_map = pp->delayed_eh_pmp_map;
1628 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1629 for (pmp = 0; pmp_map != 0; pmp++) {
1630 unsigned int this_pmp = (1 << pmp);
1631 if (pmp_map & this_pmp) {
1632 struct ata_link *link = &ap->pmp_link[pmp];
1633 pmp_map &= ~this_pmp;
1634 ata_eh_analyze_ncq_error(link);
1635 }
1636 }
1637 ata_port_freeze(ap);
1638 }
1639 sata_pmp_error_handler(ap);
1640 }
1641
1642 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1643 {
1644 void __iomem *port_mmio = mv_ap_base(ap);
1645
1646 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1647 }
1648
1649 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1650 {
1651 struct ata_eh_info *ehi;
1652 unsigned int pmp;
1653
1654 /*
1655 * Initialize EH info for PMPs which saw device errors
1656 */
1657 ehi = &ap->link.eh_info;
1658 for (pmp = 0; pmp_map != 0; pmp++) {
1659 unsigned int this_pmp = (1 << pmp);
1660 if (pmp_map & this_pmp) {
1661 struct ata_link *link = &ap->pmp_link[pmp];
1662
1663 pmp_map &= ~this_pmp;
1664 ehi = &link->eh_info;
1665 ata_ehi_clear_desc(ehi);
1666 ata_ehi_push_desc(ehi, "dev err");
1667 ehi->err_mask |= AC_ERR_DEV;
1668 ehi->action |= ATA_EH_RESET;
1669 ata_link_abort(link);
1670 }
1671 }
1672 }
1673
1674 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1675 {
1676 struct mv_port_priv *pp = ap->private_data;
1677 int failed_links;
1678 unsigned int old_map, new_map;
1679
1680 /*
1681 * Device error during FBS+NCQ operation:
1682 *
1683 * Set a port flag to prevent further I/O being enqueued.
1684 * Leave the EDMA running to drain outstanding commands from this port.
1685 * Perform the post-mortem/EH only when all responses are complete.
1686 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1687 */
1688 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1689 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1690 pp->delayed_eh_pmp_map = 0;
1691 }
1692 old_map = pp->delayed_eh_pmp_map;
1693 new_map = old_map | mv_get_err_pmp_map(ap);
1694
1695 if (old_map != new_map) {
1696 pp->delayed_eh_pmp_map = new_map;
1697 mv_pmp_eh_prep(ap, new_map & ~old_map);
1698 }
1699 failed_links = hweight16(new_map);
1700
1701 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1702 "failed_links=%d nr_active_links=%d\n",
1703 __func__, pp->delayed_eh_pmp_map,
1704 ap->qc_active, failed_links,
1705 ap->nr_active_links);
1706
1707 if (ap->nr_active_links <= failed_links) {
1708 mv_process_crpb_entries(ap, pp);
1709 mv_stop_edma(ap);
1710 mv_eh_freeze(ap);
1711 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1712 return 1; /* handled */
1713 }
1714 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1715 return 1; /* handled */
1716 }
1717
1718 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1719 {
1720 /*
1721 * Possible future enhancement:
1722 *
1723 * FBS+non-NCQ operation is not yet implemented.
1724 * See related notes in mv_edma_cfg().
1725 *
1726 * Device error during FBS+non-NCQ operation:
1727 *
1728 * We need to snapshot the shadow registers for each failed command.
1729 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1730 */
1731 return 0; /* not handled */
1732 }
1733
1734 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1735 {
1736 struct mv_port_priv *pp = ap->private_data;
1737
1738 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1739 return 0; /* EDMA was not active: not handled */
1740 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1741 return 0; /* FBS was not active: not handled */
1742
1743 if (!(edma_err_cause & EDMA_ERR_DEV))
1744 return 0; /* non DEV error: not handled */
1745 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1746 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1747 return 0; /* other problems: not handled */
1748
1749 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1750 /*
1751 * EDMA should NOT have self-disabled for this case.
1752 * If it did, then something is wrong elsewhere,
1753 * and we cannot handle it here.
1754 */
1755 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1756 ata_port_printk(ap, KERN_WARNING,
1757 "%s: err_cause=0x%x pp_flags=0x%x\n",
1758 __func__, edma_err_cause, pp->pp_flags);
1759 return 0; /* not handled */
1760 }
1761 return mv_handle_fbs_ncq_dev_err(ap);
1762 } else {
1763 /*
1764 * EDMA should have self-disabled for this case.
1765 * If it did not, then something is wrong elsewhere,
1766 * and we cannot handle it here.
1767 */
1768 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1769 ata_port_printk(ap, KERN_WARNING,
1770 "%s: err_cause=0x%x pp_flags=0x%x\n",
1771 __func__, edma_err_cause, pp->pp_flags);
1772 return 0; /* not handled */
1773 }
1774 return mv_handle_fbs_non_ncq_dev_err(ap);
1775 }
1776 return 0; /* not handled */
1777 }
1778
1779 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
1780 {
1781 struct ata_eh_info *ehi = &ap->link.eh_info;
1782 char *when = "idle";
1783
1784 ata_ehi_clear_desc(ehi);
1785 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1786 when = "disabled";
1787 } else if (edma_was_enabled) {
1788 when = "EDMA enabled";
1789 } else {
1790 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1791 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1792 when = "polling";
1793 }
1794 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
1795 ehi->err_mask |= AC_ERR_OTHER;
1796 ehi->action |= ATA_EH_RESET;
1797 ata_port_freeze(ap);
1798 }
1799
1800 /**
1801 * mv_err_intr - Handle error interrupts on the port
1802 * @ap: ATA channel to manipulate
1803 * @qc: affected command (non-NCQ), or NULL
1804 *
1805 * Most cases require a full reset of the chip's state machine,
1806 * which also performs a COMRESET.
1807 * Also, if the port disabled DMA, update our cached copy to match.
1808 *
1809 * LOCKING:
1810 * Inherited from caller.
1811 */
1812 static void mv_err_intr(struct ata_port *ap)
1813 {
1814 void __iomem *port_mmio = mv_ap_base(ap);
1815 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1816 u32 fis_cause = 0;
1817 struct mv_port_priv *pp = ap->private_data;
1818 struct mv_host_priv *hpriv = ap->host->private_data;
1819 unsigned int action = 0, err_mask = 0;
1820 struct ata_eh_info *ehi = &ap->link.eh_info;
1821 struct ata_queued_cmd *qc;
1822 int abort = 0;
1823
1824 /*
1825 * Read and clear the SError and err_cause bits.
1826 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
1827 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
1828 */
1829 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1830 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1831
1832 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1833 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1834 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1835 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1836 }
1837 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1838
1839 if (edma_err_cause & EDMA_ERR_DEV) {
1840 /*
1841 * Device errors during FIS-based switching operation
1842 * require special handling.
1843 */
1844 if (mv_handle_dev_err(ap, edma_err_cause))
1845 return;
1846 }
1847
1848 qc = mv_get_active_qc(ap);
1849 ata_ehi_clear_desc(ehi);
1850 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1851 edma_err_cause, pp->pp_flags);
1852
1853 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1854 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
1855 if (fis_cause & SATA_FIS_IRQ_AN) {
1856 u32 ec = edma_err_cause &
1857 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
1858 sata_async_notification(ap);
1859 if (!ec)
1860 return; /* Just an AN; no need for the nukes */
1861 ata_ehi_push_desc(ehi, "SDB notify");
1862 }
1863 }
1864 /*
1865 * All generations share these EDMA error cause bits:
1866 */
1867 if (edma_err_cause & EDMA_ERR_DEV) {
1868 err_mask |= AC_ERR_DEV;
1869 action |= ATA_EH_RESET;
1870 ata_ehi_push_desc(ehi, "dev error");
1871 }
1872 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
1873 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
1874 EDMA_ERR_INTRL_PAR)) {
1875 err_mask |= AC_ERR_ATA_BUS;
1876 action |= ATA_EH_RESET;
1877 ata_ehi_push_desc(ehi, "parity error");
1878 }
1879 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1880 ata_ehi_hotplugged(ehi);
1881 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
1882 "dev disconnect" : "dev connect");
1883 action |= ATA_EH_RESET;
1884 }
1885
1886 /*
1887 * Gen-I has a different SELF_DIS bit,
1888 * different FREEZE bits, and no SERR bit:
1889 */
1890 if (IS_GEN_I(hpriv)) {
1891 eh_freeze_mask = EDMA_EH_FREEZE_5;
1892 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
1893 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1894 ata_ehi_push_desc(ehi, "EDMA self-disable");
1895 }
1896 } else {
1897 eh_freeze_mask = EDMA_EH_FREEZE;
1898 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1899 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1900 ata_ehi_push_desc(ehi, "EDMA self-disable");
1901 }
1902 if (edma_err_cause & EDMA_ERR_SERR) {
1903 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1904 err_mask |= AC_ERR_ATA_BUS;
1905 action |= ATA_EH_RESET;
1906 }
1907 }
1908
1909 if (!err_mask) {
1910 err_mask = AC_ERR_OTHER;
1911 action |= ATA_EH_RESET;
1912 }
1913
1914 ehi->serror |= serr;
1915 ehi->action |= action;
1916
1917 if (qc)
1918 qc->err_mask |= err_mask;
1919 else
1920 ehi->err_mask |= err_mask;
1921
1922 if (err_mask == AC_ERR_DEV) {
1923 /*
1924 * Cannot do ata_port_freeze() here,
1925 * because it would kill PIO access,
1926 * which is needed for further diagnosis.
1927 */
1928 mv_eh_freeze(ap);
1929 abort = 1;
1930 } else if (edma_err_cause & eh_freeze_mask) {
1931 /*
1932 * Note to self: ata_port_freeze() calls ata_port_abort()
1933 */
1934 ata_port_freeze(ap);
1935 } else {
1936 abort = 1;
1937 }
1938
1939 if (abort) {
1940 if (qc)
1941 ata_link_abort(qc->dev->link);
1942 else
1943 ata_port_abort(ap);
1944 }
1945 }
1946
1947 static void mv_process_crpb_response(struct ata_port *ap,
1948 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1949 {
1950 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1951
1952 if (qc) {
1953 u8 ata_status;
1954 u16 edma_status = le16_to_cpu(response->flags);
1955 /*
1956 * edma_status from a response queue entry:
1957 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1958 * MSB is saved ATA status from command completion.
1959 */
1960 if (!ncq_enabled) {
1961 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1962 if (err_cause) {
1963 /*
1964 * Error will be seen/handled by mv_err_intr().
1965 * So do nothing at all here.
1966 */
1967 return;
1968 }
1969 }
1970 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
1971 if (!ac_err_mask(ata_status))
1972 ata_qc_complete(qc);
1973 /* else: leave it for mv_err_intr() */
1974 } else {
1975 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1976 __func__, tag);
1977 }
1978 }
1979
1980 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
1981 {
1982 void __iomem *port_mmio = mv_ap_base(ap);
1983 struct mv_host_priv *hpriv = ap->host->private_data;
1984 u32 in_index;
1985 bool work_done = false;
1986 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
1987
1988 /* Get the hardware queue position index */
1989 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1990 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1991
1992 /* Process new responses from since the last time we looked */
1993 while (in_index != pp->resp_idx) {
1994 unsigned int tag;
1995 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
1996
1997 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1998
1999 if (IS_GEN_I(hpriv)) {
2000 /* 50xx: no NCQ, only one command active at a time */
2001 tag = ap->link.active_tag;
2002 } else {
2003 /* Gen II/IIE: get command tag from CRPB entry */
2004 tag = le16_to_cpu(response->id) & 0x1f;
2005 }
2006 mv_process_crpb_response(ap, response, tag, ncq_enabled);
2007 work_done = true;
2008 }
2009
2010 /* Update the software queue position index in hardware */
2011 if (work_done)
2012 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2013 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2014 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
2015 }
2016
2017 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2018 {
2019 struct mv_port_priv *pp;
2020 int edma_was_enabled;
2021
2022 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2023 mv_unexpected_intr(ap, 0);
2024 return;
2025 }
2026 /*
2027 * Grab a snapshot of the EDMA_EN flag setting,
2028 * so that we have a consistent view for this port,
2029 * even if something we call of our routines changes it.
2030 */
2031 pp = ap->private_data;
2032 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2033 /*
2034 * Process completed CRPB response(s) before other events.
2035 */
2036 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2037 mv_process_crpb_entries(ap, pp);
2038 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2039 mv_handle_fbs_ncq_dev_err(ap);
2040 }
2041 /*
2042 * Handle chip-reported errors, or continue on to handle PIO.
2043 */
2044 if (unlikely(port_cause & ERR_IRQ)) {
2045 mv_err_intr(ap);
2046 } else if (!edma_was_enabled) {
2047 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2048 if (qc)
2049 ata_sff_host_intr(ap, qc);
2050 else
2051 mv_unexpected_intr(ap, edma_was_enabled);
2052 }
2053 }
2054
2055 /**
2056 * mv_host_intr - Handle all interrupts on the given host controller
2057 * @host: host specific structure
2058 * @main_irq_cause: Main interrupt cause register for the chip.
2059 *
2060 * LOCKING:
2061 * Inherited from caller.
2062 */
2063 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2064 {
2065 struct mv_host_priv *hpriv = host->private_data;
2066 void __iomem *mmio = hpriv->base, *hc_mmio;
2067 unsigned int handled = 0, port;
2068
2069 for (port = 0; port < hpriv->n_ports; port++) {
2070 struct ata_port *ap = host->ports[port];
2071 unsigned int p, shift, hardport, port_cause;
2072
2073 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2074 /*
2075 * Each hc within the host has its own hc_irq_cause register,
2076 * where the interrupting ports bits get ack'd.
2077 */
2078 if (hardport == 0) { /* first port on this hc ? */
2079 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2080 u32 port_mask, ack_irqs;
2081 /*
2082 * Skip this entire hc if nothing pending for any ports
2083 */
2084 if (!hc_cause) {
2085 port += MV_PORTS_PER_HC - 1;
2086 continue;
2087 }
2088 /*
2089 * We don't need/want to read the hc_irq_cause register,
2090 * because doing so hurts performance, and
2091 * main_irq_cause already gives us everything we need.
2092 *
2093 * But we do have to *write* to the hc_irq_cause to ack
2094 * the ports that we are handling this time through.
2095 *
2096 * This requires that we create a bitmap for those
2097 * ports which interrupted us, and use that bitmap
2098 * to ack (only) those ports via hc_irq_cause.
2099 */
2100 ack_irqs = 0;
2101 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2102 if ((port + p) >= hpriv->n_ports)
2103 break;
2104 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2105 if (hc_cause & port_mask)
2106 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2107 }
2108 hc_mmio = mv_hc_base_from_port(mmio, port);
2109 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
2110 handled = 1;
2111 }
2112 /*
2113 * Handle interrupts signalled for this port:
2114 */
2115 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2116 if (port_cause)
2117 mv_port_intr(ap, port_cause);
2118 }
2119 return handled;
2120 }
2121
2122 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2123 {
2124 struct mv_host_priv *hpriv = host->private_data;
2125 struct ata_port *ap;
2126 struct ata_queued_cmd *qc;
2127 struct ata_eh_info *ehi;
2128 unsigned int i, err_mask, printed = 0;
2129 u32 err_cause;
2130
2131 err_cause = readl(mmio + hpriv->irq_cause_ofs);
2132
2133 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2134 err_cause);
2135
2136 DPRINTK("All regs @ PCI error\n");
2137 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2138
2139 writelfl(0, mmio + hpriv->irq_cause_ofs);
2140
2141 for (i = 0; i < host->n_ports; i++) {
2142 ap = host->ports[i];
2143 if (!ata_link_offline(&ap->link)) {
2144 ehi = &ap->link.eh_info;
2145 ata_ehi_clear_desc(ehi);
2146 if (!printed++)
2147 ata_ehi_push_desc(ehi,
2148 "PCI err cause 0x%08x", err_cause);
2149 err_mask = AC_ERR_HOST_BUS;
2150 ehi->action = ATA_EH_RESET;
2151 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2152 if (qc)
2153 qc->err_mask |= err_mask;
2154 else
2155 ehi->err_mask |= err_mask;
2156
2157 ata_port_freeze(ap);
2158 }
2159 }
2160 return 1; /* handled */
2161 }
2162
2163 /**
2164 * mv_interrupt - Main interrupt event handler
2165 * @irq: unused
2166 * @dev_instance: private data; in this case the host structure
2167 *
2168 * Read the read only register to determine if any host
2169 * controllers have pending interrupts. If so, call lower level
2170 * routine to handle. Also check for PCI errors which are only
2171 * reported here.
2172 *
2173 * LOCKING:
2174 * This routine holds the host lock while processing pending
2175 * interrupts.
2176 */
2177 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2178 {
2179 struct ata_host *host = dev_instance;
2180 struct mv_host_priv *hpriv = host->private_data;
2181 unsigned int handled = 0;
2182 u32 main_irq_cause, main_irq_mask;
2183
2184 spin_lock(&host->lock);
2185 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2186 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2187 /*
2188 * Deal with cases where we either have nothing pending, or have read
2189 * a bogus register value which can indicate HW removal or PCI fault.
2190 */
2191 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) {
2192 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host)))
2193 handled = mv_pci_error(host, hpriv->base);
2194 else
2195 handled = mv_host_intr(host, main_irq_cause);
2196 }
2197 spin_unlock(&host->lock);
2198 return IRQ_RETVAL(handled);
2199 }
2200
2201 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2202 {
2203 unsigned int ofs;
2204
2205 switch (sc_reg_in) {
2206 case SCR_STATUS:
2207 case SCR_ERROR:
2208 case SCR_CONTROL:
2209 ofs = sc_reg_in * sizeof(u32);
2210 break;
2211 default:
2212 ofs = 0xffffffffU;
2213 break;
2214 }
2215 return ofs;
2216 }
2217
2218 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
2219 {
2220 struct mv_host_priv *hpriv = ap->host->private_data;
2221 void __iomem *mmio = hpriv->base;
2222 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
2223 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2224
2225 if (ofs != 0xffffffffU) {
2226 *val = readl(addr + ofs);
2227 return 0;
2228 } else
2229 return -EINVAL;
2230 }
2231
2232 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
2233 {
2234 struct mv_host_priv *hpriv = ap->host->private_data;
2235 void __iomem *mmio = hpriv->base;
2236 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
2237 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2238
2239 if (ofs != 0xffffffffU) {
2240 writelfl(val, addr + ofs);
2241 return 0;
2242 } else
2243 return -EINVAL;
2244 }
2245
2246 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
2247 {
2248 struct pci_dev *pdev = to_pci_dev(host->dev);
2249 int early_5080;
2250
2251 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
2252
2253 if (!early_5080) {
2254 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2255 tmp |= (1 << 0);
2256 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2257 }
2258
2259 mv_reset_pci_bus(host, mmio);
2260 }
2261
2262 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2263 {
2264 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
2265 }
2266
2267 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
2268 void __iomem *mmio)
2269 {
2270 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2271 u32 tmp;
2272
2273 tmp = readl(phy_mmio + MV5_PHY_MODE);
2274
2275 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2276 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
2277 }
2278
2279 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2280 {
2281 u32 tmp;
2282
2283 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
2284
2285 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2286
2287 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2288 tmp |= ~(1 << 0);
2289 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2290 }
2291
2292 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2293 unsigned int port)
2294 {
2295 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2296 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2297 u32 tmp;
2298 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2299
2300 if (fix_apm_sq) {
2301 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
2302 tmp |= (1 << 19);
2303 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
2304
2305 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
2306 tmp &= ~0x3;
2307 tmp |= 0x1;
2308 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
2309 }
2310
2311 tmp = readl(phy_mmio + MV5_PHY_MODE);
2312 tmp &= ~mask;
2313 tmp |= hpriv->signal[port].pre;
2314 tmp |= hpriv->signal[port].amps;
2315 writel(tmp, phy_mmio + MV5_PHY_MODE);
2316 }
2317
2318
2319 #undef ZERO
2320 #define ZERO(reg) writel(0, port_mmio + (reg))
2321 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2322 unsigned int port)
2323 {
2324 void __iomem *port_mmio = mv_port_base(mmio, port);
2325
2326 mv_reset_channel(hpriv, mmio, port);
2327
2328 ZERO(0x028); /* command */
2329 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2330 ZERO(0x004); /* timer */
2331 ZERO(0x008); /* irq err cause */
2332 ZERO(0x00c); /* irq err mask */
2333 ZERO(0x010); /* rq bah */
2334 ZERO(0x014); /* rq inp */
2335 ZERO(0x018); /* rq outp */
2336 ZERO(0x01c); /* respq bah */
2337 ZERO(0x024); /* respq outp */
2338 ZERO(0x020); /* respq inp */
2339 ZERO(0x02c); /* test control */
2340 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2341 }
2342 #undef ZERO
2343
2344 #define ZERO(reg) writel(0, hc_mmio + (reg))
2345 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2346 unsigned int hc)
2347 {
2348 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2349 u32 tmp;
2350
2351 ZERO(0x00c);
2352 ZERO(0x010);
2353 ZERO(0x014);
2354 ZERO(0x018);
2355
2356 tmp = readl(hc_mmio + 0x20);
2357 tmp &= 0x1c1c1c1c;
2358 tmp |= 0x03030303;
2359 writel(tmp, hc_mmio + 0x20);
2360 }
2361 #undef ZERO
2362
2363 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2364 unsigned int n_hc)
2365 {
2366 unsigned int hc, port;
2367
2368 for (hc = 0; hc < n_hc; hc++) {
2369 for (port = 0; port < MV_PORTS_PER_HC; port++)
2370 mv5_reset_hc_port(hpriv, mmio,
2371 (hc * MV_PORTS_PER_HC) + port);
2372
2373 mv5_reset_one_hc(hpriv, mmio, hc);
2374 }
2375
2376 return 0;
2377 }
2378
2379 #undef ZERO
2380 #define ZERO(reg) writel(0, mmio + (reg))
2381 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
2382 {
2383 struct mv_host_priv *hpriv = host->private_data;
2384 u32 tmp;
2385
2386 tmp = readl(mmio + MV_PCI_MODE_OFS);
2387 tmp &= 0xff00ffff;
2388 writel(tmp, mmio + MV_PCI_MODE_OFS);
2389
2390 ZERO(MV_PCI_DISC_TIMER);
2391 ZERO(MV_PCI_MSI_TRIGGER);
2392 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
2393 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
2394 ZERO(MV_PCI_SERR_MASK);
2395 ZERO(hpriv->irq_cause_ofs);
2396 ZERO(hpriv->irq_mask_ofs);
2397 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2398 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2399 ZERO(MV_PCI_ERR_ATTRIBUTE);
2400 ZERO(MV_PCI_ERR_COMMAND);
2401 }
2402 #undef ZERO
2403
2404 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2405 {
2406 u32 tmp;
2407
2408 mv5_reset_flash(hpriv, mmio);
2409
2410 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
2411 tmp &= 0x3;
2412 tmp |= (1 << 5) | (1 << 6);
2413 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
2414 }
2415
2416 /**
2417 * mv6_reset_hc - Perform the 6xxx global soft reset
2418 * @mmio: base address of the HBA
2419 *
2420 * This routine only applies to 6xxx parts.
2421 *
2422 * LOCKING:
2423 * Inherited from caller.
2424 */
2425 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2426 unsigned int n_hc)
2427 {
2428 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2429 int i, rc = 0;
2430 u32 t;
2431
2432 /* Following procedure defined in PCI "main command and status
2433 * register" table.
2434 */
2435 t = readl(reg);
2436 writel(t | STOP_PCI_MASTER, reg);
2437
2438 for (i = 0; i < 1000; i++) {
2439 udelay(1);
2440 t = readl(reg);
2441 if (PCI_MASTER_EMPTY & t)
2442 break;
2443 }
2444 if (!(PCI_MASTER_EMPTY & t)) {
2445 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2446 rc = 1;
2447 goto done;
2448 }
2449
2450 /* set reset */
2451 i = 5;
2452 do {
2453 writel(t | GLOB_SFT_RST, reg);
2454 t = readl(reg);
2455 udelay(1);
2456 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2457
2458 if (!(GLOB_SFT_RST & t)) {
2459 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2460 rc = 1;
2461 goto done;
2462 }
2463
2464 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2465 i = 5;
2466 do {
2467 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2468 t = readl(reg);
2469 udelay(1);
2470 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2471
2472 if (GLOB_SFT_RST & t) {
2473 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2474 rc = 1;
2475 }
2476 done:
2477 return rc;
2478 }
2479
2480 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
2481 void __iomem *mmio)
2482 {
2483 void __iomem *port_mmio;
2484 u32 tmp;
2485
2486 tmp = readl(mmio + MV_RESET_CFG_OFS);
2487 if ((tmp & (1 << 0)) == 0) {
2488 hpriv->signal[idx].amps = 0x7 << 8;
2489 hpriv->signal[idx].pre = 0x1 << 5;
2490 return;
2491 }
2492
2493 port_mmio = mv_port_base(mmio, idx);
2494 tmp = readl(port_mmio + PHY_MODE2);
2495
2496 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2497 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2498 }
2499
2500 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2501 {
2502 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
2503 }
2504
2505 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2506 unsigned int port)
2507 {
2508 void __iomem *port_mmio = mv_port_base(mmio, port);
2509
2510 u32 hp_flags = hpriv->hp_flags;
2511 int fix_phy_mode2 =
2512 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2513 int fix_phy_mode4 =
2514 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2515 u32 m2, tmp;
2516
2517 if (fix_phy_mode2) {
2518 m2 = readl(port_mmio + PHY_MODE2);
2519 m2 &= ~(1 << 16);
2520 m2 |= (1 << 31);
2521 writel(m2, port_mmio + PHY_MODE2);
2522
2523 udelay(200);
2524
2525 m2 = readl(port_mmio + PHY_MODE2);
2526 m2 &= ~((1 << 16) | (1 << 31));
2527 writel(m2, port_mmio + PHY_MODE2);
2528
2529 udelay(200);
2530 }
2531
2532 /* who knows what this magic does */
2533 tmp = readl(port_mmio + PHY_MODE3);
2534 tmp &= ~0x7F800000;
2535 tmp |= 0x2A800000;
2536 writel(tmp, port_mmio + PHY_MODE3);
2537
2538 if (fix_phy_mode4) {
2539 u32 m4;
2540
2541 m4 = readl(port_mmio + PHY_MODE4);
2542
2543 if (hp_flags & MV_HP_ERRATA_60X1B2)
2544 tmp = readl(port_mmio + PHY_MODE3);
2545
2546 /* workaround for errata FEr SATA#10 (part 1) */
2547 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2548
2549 writel(m4, port_mmio + PHY_MODE4);
2550
2551 if (hp_flags & MV_HP_ERRATA_60X1B2)
2552 writel(tmp, port_mmio + PHY_MODE3);
2553 }
2554
2555 /* Revert values of pre-emphasis and signal amps to the saved ones */
2556 m2 = readl(port_mmio + PHY_MODE2);
2557
2558 m2 &= ~MV_M2_PREAMP_MASK;
2559 m2 |= hpriv->signal[port].amps;
2560 m2 |= hpriv->signal[port].pre;
2561 m2 &= ~(1 << 16);
2562
2563 /* according to mvSata 3.6.1, some IIE values are fixed */
2564 if (IS_GEN_IIE(hpriv)) {
2565 m2 &= ~0xC30FF01F;
2566 m2 |= 0x0000900F;
2567 }
2568
2569 writel(m2, port_mmio + PHY_MODE2);
2570 }
2571
2572 /* TODO: use the generic LED interface to configure the SATA Presence */
2573 /* & Acitivy LEDs on the board */
2574 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2575 void __iomem *mmio)
2576 {
2577 return;
2578 }
2579
2580 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2581 void __iomem *mmio)
2582 {
2583 void __iomem *port_mmio;
2584 u32 tmp;
2585
2586 port_mmio = mv_port_base(mmio, idx);
2587 tmp = readl(port_mmio + PHY_MODE2);
2588
2589 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2590 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2591 }
2592
2593 #undef ZERO
2594 #define ZERO(reg) writel(0, port_mmio + (reg))
2595 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2596 void __iomem *mmio, unsigned int port)
2597 {
2598 void __iomem *port_mmio = mv_port_base(mmio, port);
2599
2600 mv_reset_channel(hpriv, mmio, port);
2601
2602 ZERO(0x028); /* command */
2603 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2604 ZERO(0x004); /* timer */
2605 ZERO(0x008); /* irq err cause */
2606 ZERO(0x00c); /* irq err mask */
2607 ZERO(0x010); /* rq bah */
2608 ZERO(0x014); /* rq inp */
2609 ZERO(0x018); /* rq outp */
2610 ZERO(0x01c); /* respq bah */
2611 ZERO(0x024); /* respq outp */
2612 ZERO(0x020); /* respq inp */
2613 ZERO(0x02c); /* test control */
2614 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2615 }
2616
2617 #undef ZERO
2618
2619 #define ZERO(reg) writel(0, hc_mmio + (reg))
2620 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2621 void __iomem *mmio)
2622 {
2623 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2624
2625 ZERO(0x00c);
2626 ZERO(0x010);
2627 ZERO(0x014);
2628
2629 }
2630
2631 #undef ZERO
2632
2633 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2634 void __iomem *mmio, unsigned int n_hc)
2635 {
2636 unsigned int port;
2637
2638 for (port = 0; port < hpriv->n_ports; port++)
2639 mv_soc_reset_hc_port(hpriv, mmio, port);
2640
2641 mv_soc_reset_one_hc(hpriv, mmio);
2642
2643 return 0;
2644 }
2645
2646 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2647 void __iomem *mmio)
2648 {
2649 return;
2650 }
2651
2652 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2653 {
2654 return;
2655 }
2656
2657 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
2658 {
2659 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
2660
2661 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
2662 if (want_gen2i)
2663 ifcfg |= (1 << 7); /* enable gen2i speed */
2664 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
2665 }
2666
2667 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
2668 unsigned int port_no)
2669 {
2670 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2671
2672 /*
2673 * The datasheet warns against setting EDMA_RESET when EDMA is active
2674 * (but doesn't say what the problem might be). So we first try
2675 * to disable the EDMA engine before doing the EDMA_RESET operation.
2676 */
2677 mv_stop_edma_engine(port_mmio);
2678 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2679
2680 if (!IS_GEN_I(hpriv)) {
2681 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2682 mv_setup_ifcfg(port_mmio, 1);
2683 }
2684 /*
2685 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
2686 * link, and physical layers. It resets all SATA interface registers
2687 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
2688 */
2689 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2690 udelay(25); /* allow reset propagation */
2691 writelfl(0, port_mmio + EDMA_CMD_OFS);
2692
2693 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2694
2695 if (IS_GEN_I(hpriv))
2696 mdelay(1);
2697 }
2698
2699 static void mv_pmp_select(struct ata_port *ap, int pmp)
2700 {
2701 if (sata_pmp_supported(ap)) {
2702 void __iomem *port_mmio = mv_ap_base(ap);
2703 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2704 int old = reg & 0xf;
2705
2706 if (old != pmp) {
2707 reg = (reg & ~0xf) | pmp;
2708 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2709 }
2710 }
2711 }
2712
2713 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2714 unsigned long deadline)
2715 {
2716 mv_pmp_select(link->ap, sata_srst_pmp(link));
2717 return sata_std_hardreset(link, class, deadline);
2718 }
2719
2720 static int mv_softreset(struct ata_link *link, unsigned int *class,
2721 unsigned long deadline)
2722 {
2723 mv_pmp_select(link->ap, sata_srst_pmp(link));
2724 return ata_sff_softreset(link, class, deadline);
2725 }
2726
2727 static int mv_hardreset(struct ata_link *link, unsigned int *class,
2728 unsigned long deadline)
2729 {
2730 struct ata_port *ap = link->ap;
2731 struct mv_host_priv *hpriv = ap->host->private_data;
2732 struct mv_port_priv *pp = ap->private_data;
2733 void __iomem *mmio = hpriv->base;
2734 int rc, attempts = 0, extra = 0;
2735 u32 sstatus;
2736 bool online;
2737
2738 mv_reset_channel(hpriv, mmio, ap->port_no);
2739 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2740
2741 /* Workaround for errata FEr SATA#10 (part 2) */
2742 do {
2743 const unsigned long *timing =
2744 sata_ehc_deb_timing(&link->eh_context);
2745
2746 rc = sata_link_hardreset(link, timing, deadline + extra,
2747 &online, NULL);
2748 rc = online ? -EAGAIN : rc;
2749 if (rc)
2750 return rc;
2751 sata_scr_read(link, SCR_STATUS, &sstatus);
2752 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2753 /* Force 1.5gb/s link speed and try again */
2754 mv_setup_ifcfg(mv_ap_base(ap), 0);
2755 if (time_after(jiffies + HZ, deadline))
2756 extra = HZ; /* only extend it once, max */
2757 }
2758 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
2759
2760 return rc;
2761 }
2762
2763 static void mv_eh_freeze(struct ata_port *ap)
2764 {
2765 struct mv_host_priv *hpriv = ap->host->private_data;
2766 unsigned int shift, hardport, port = ap->port_no;
2767 u32 main_irq_mask;
2768
2769 /* FIXME: handle coalescing completion events properly */
2770
2771 mv_stop_edma(ap);
2772 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2773
2774 /* disable assertion of portN err, done events */
2775 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2776 main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift);
2777 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
2778 }
2779
2780 static void mv_eh_thaw(struct ata_port *ap)
2781 {
2782 struct mv_host_priv *hpriv = ap->host->private_data;
2783 unsigned int shift, hardport, port = ap->port_no;
2784 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
2785 void __iomem *port_mmio = mv_ap_base(ap);
2786 u32 main_irq_mask, hc_irq_cause;
2787
2788 /* FIXME: handle coalescing completion events properly */
2789
2790 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2791
2792 /* clear EDMA errors on this port */
2793 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2794
2795 /* clear pending irq events */
2796 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
2797 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2798 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
2799
2800 /* enable assertion of portN err, done events */
2801 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2802 main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift);
2803 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
2804 }
2805
2806 /**
2807 * mv_port_init - Perform some early initialization on a single port.
2808 * @port: libata data structure storing shadow register addresses
2809 * @port_mmio: base address of the port
2810 *
2811 * Initialize shadow register mmio addresses, clear outstanding
2812 * interrupts on the port, and unmask interrupts for the future
2813 * start of the port.
2814 *
2815 * LOCKING:
2816 * Inherited from caller.
2817 */
2818 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2819 {
2820 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
2821 unsigned serr_ofs;
2822
2823 /* PIO related setup
2824 */
2825 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2826 port->error_addr =
2827 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2828 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2829 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2830 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2831 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2832 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2833 port->status_addr =
2834 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2835 /* special case: control/altstatus doesn't have ATA_REG_ address */
2836 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2837
2838 /* unused: */
2839 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
2840
2841 /* Clear any currently outstanding port interrupt conditions */
2842 serr_ofs = mv_scr_offset(SCR_ERROR);
2843 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2844 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2845
2846 /* unmask all non-transient EDMA error interrupts */
2847 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2848
2849 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2850 readl(port_mmio + EDMA_CFG_OFS),
2851 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2852 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2853 }
2854
2855 static unsigned int mv_in_pcix_mode(struct ata_host *host)
2856 {
2857 struct mv_host_priv *hpriv = host->private_data;
2858 void __iomem *mmio = hpriv->base;
2859 u32 reg;
2860
2861 if (!HAS_PCI(host) || !IS_PCIE(hpriv))
2862 return 0; /* not PCI-X capable */
2863 reg = readl(mmio + MV_PCI_MODE_OFS);
2864 if ((reg & MV_PCI_MODE_MASK) == 0)
2865 return 0; /* conventional PCI mode */
2866 return 1; /* chip is in PCI-X mode */
2867 }
2868
2869 static int mv_pci_cut_through_okay(struct ata_host *host)
2870 {
2871 struct mv_host_priv *hpriv = host->private_data;
2872 void __iomem *mmio = hpriv->base;
2873 u32 reg;
2874
2875 if (!mv_in_pcix_mode(host)) {
2876 reg = readl(mmio + PCI_COMMAND_OFS);
2877 if (reg & PCI_COMMAND_MRDTRIG)
2878 return 0; /* not okay */
2879 }
2880 return 1; /* okay */
2881 }
2882
2883 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2884 {
2885 struct pci_dev *pdev = to_pci_dev(host->dev);
2886 struct mv_host_priv *hpriv = host->private_data;
2887 u32 hp_flags = hpriv->hp_flags;
2888
2889 switch (board_idx) {
2890 case chip_5080:
2891 hpriv->ops = &mv5xxx_ops;
2892 hp_flags |= MV_HP_GEN_I;
2893
2894 switch (pdev->revision) {
2895 case 0x1:
2896 hp_flags |= MV_HP_ERRATA_50XXB0;
2897 break;
2898 case 0x3:
2899 hp_flags |= MV_HP_ERRATA_50XXB2;
2900 break;
2901 default:
2902 dev_printk(KERN_WARNING, &pdev->dev,
2903 "Applying 50XXB2 workarounds to unknown rev\n");
2904 hp_flags |= MV_HP_ERRATA_50XXB2;
2905 break;
2906 }
2907 break;
2908
2909 case chip_504x:
2910 case chip_508x:
2911 hpriv->ops = &mv5xxx_ops;
2912 hp_flags |= MV_HP_GEN_I;
2913
2914 switch (pdev->revision) {
2915 case 0x0:
2916 hp_flags |= MV_HP_ERRATA_50XXB0;
2917 break;
2918 case 0x3:
2919 hp_flags |= MV_HP_ERRATA_50XXB2;
2920 break;
2921 default:
2922 dev_printk(KERN_WARNING, &pdev->dev,
2923 "Applying B2 workarounds to unknown rev\n");
2924 hp_flags |= MV_HP_ERRATA_50XXB2;
2925 break;
2926 }
2927 break;
2928
2929 case chip_604x:
2930 case chip_608x:
2931 hpriv->ops = &mv6xxx_ops;
2932 hp_flags |= MV_HP_GEN_II;
2933
2934 switch (pdev->revision) {
2935 case 0x7:
2936 hp_flags |= MV_HP_ERRATA_60X1B2;
2937 break;
2938 case 0x9:
2939 hp_flags |= MV_HP_ERRATA_60X1C0;
2940 break;
2941 default:
2942 dev_printk(KERN_WARNING, &pdev->dev,
2943 "Applying B2 workarounds to unknown rev\n");
2944 hp_flags |= MV_HP_ERRATA_60X1B2;
2945 break;
2946 }
2947 break;
2948
2949 case chip_7042:
2950 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
2951 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2952 (pdev->device == 0x2300 || pdev->device == 0x2310))
2953 {
2954 /*
2955 * Highpoint RocketRAID PCIe 23xx series cards:
2956 *
2957 * Unconfigured drives are treated as "Legacy"
2958 * by the BIOS, and it overwrites sector 8 with
2959 * a "Lgcy" metadata block prior to Linux boot.
2960 *
2961 * Configured drives (RAID or JBOD) leave sector 8
2962 * alone, but instead overwrite a high numbered
2963 * sector for the RAID metadata. This sector can
2964 * be determined exactly, by truncating the physical
2965 * drive capacity to a nice even GB value.
2966 *
2967 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2968 *
2969 * Warn the user, lest they think we're just buggy.
2970 */
2971 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2972 " BIOS CORRUPTS DATA on all attached drives,"
2973 " regardless of if/how they are configured."
2974 " BEWARE!\n");
2975 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2976 " use sectors 8-9 on \"Legacy\" drives,"
2977 " and avoid the final two gigabytes on"
2978 " all RocketRAID BIOS initialized drives.\n");
2979 }
2980 /* drop through */
2981 case chip_6042:
2982 hpriv->ops = &mv6xxx_ops;
2983 hp_flags |= MV_HP_GEN_IIE;
2984 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2985 hp_flags |= MV_HP_CUT_THROUGH;
2986
2987 switch (pdev->revision) {
2988 case 0x0:
2989 hp_flags |= MV_HP_ERRATA_XX42A0;
2990 break;
2991 case 0x1:
2992 hp_flags |= MV_HP_ERRATA_60X1C0;
2993 break;
2994 default:
2995 dev_printk(KERN_WARNING, &pdev->dev,
2996 "Applying 60X1C0 workarounds to unknown rev\n");
2997 hp_flags |= MV_HP_ERRATA_60X1C0;
2998 break;
2999 }
3000 break;
3001 case chip_soc:
3002 hpriv->ops = &mv_soc_ops;
3003 hp_flags |= MV_HP_ERRATA_60X1C0;
3004 break;
3005
3006 default:
3007 dev_printk(KERN_ERR, host->dev,
3008 "BUG: invalid board index %u\n", board_idx);
3009 return 1;
3010 }
3011
3012 hpriv->hp_flags = hp_flags;
3013 if (hp_flags & MV_HP_PCIE) {
3014 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3015 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3016 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3017 } else {
3018 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3019 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3020 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3021 }
3022
3023 return 0;
3024 }
3025
3026 /**
3027 * mv_init_host - Perform some early initialization of the host.
3028 * @host: ATA host to initialize
3029 * @board_idx: controller index
3030 *
3031 * If possible, do an early global reset of the host. Then do
3032 * our port init and clear/unmask all/relevant host interrupts.
3033 *
3034 * LOCKING:
3035 * Inherited from caller.
3036 */
3037 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3038 {
3039 int rc = 0, n_hc, port, hc;
3040 struct mv_host_priv *hpriv = host->private_data;
3041 void __iomem *mmio = hpriv->base;
3042
3043 rc = mv_chip_id(host, board_idx);
3044 if (rc)
3045 goto done;
3046
3047 if (HAS_PCI(host)) {
3048 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3049 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3050 } else {
3051 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3052 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
3053 }
3054
3055 /* global interrupt mask: 0 == mask everything */
3056 writel(0, hpriv->main_irq_mask_addr);
3057
3058 n_hc = mv_get_hc_count(host->ports[0]->flags);
3059
3060 for (port = 0; port < host->n_ports; port++)
3061 hpriv->ops->read_preamp(hpriv, port, mmio);
3062
3063 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3064 if (rc)
3065 goto done;
3066
3067 hpriv->ops->reset_flash(hpriv, mmio);
3068 hpriv->ops->reset_bus(host, mmio);
3069 hpriv->ops->enable_leds(hpriv, mmio);
3070
3071 for (port = 0; port < host->n_ports; port++) {
3072 struct ata_port *ap = host->ports[port];
3073 void __iomem *port_mmio = mv_port_base(mmio, port);
3074
3075 mv_port_init(&ap->ioaddr, port_mmio);
3076
3077 #ifdef CONFIG_PCI
3078 if (HAS_PCI(host)) {
3079 unsigned int offset = port_mmio - mmio;
3080 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3081 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3082 }
3083 #endif
3084 }
3085
3086 for (hc = 0; hc < n_hc; hc++) {
3087 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3088
3089 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3090 "(before clear)=0x%08x\n", hc,
3091 readl(hc_mmio + HC_CFG_OFS),
3092 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3093
3094 /* Clear any currently outstanding hc interrupt conditions */
3095 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
3096 }
3097
3098 if (HAS_PCI(host)) {
3099 /* Clear any currently outstanding host interrupt conditions */
3100 writelfl(0, mmio + hpriv->irq_cause_ofs);
3101
3102 /* and unmask interrupt generation for host regs */
3103 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3104 if (IS_GEN_I(hpriv))
3105 writelfl(~HC_MAIN_MASKED_IRQS_5,
3106 hpriv->main_irq_mask_addr);
3107 else
3108 writelfl(~HC_MAIN_MASKED_IRQS,
3109 hpriv->main_irq_mask_addr);
3110
3111 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
3112 "PCI int cause/mask=0x%08x/0x%08x\n",
3113 readl(hpriv->main_irq_cause_addr),
3114 readl(hpriv->main_irq_mask_addr),
3115 readl(mmio + hpriv->irq_cause_ofs),
3116 readl(mmio + hpriv->irq_mask_ofs));
3117 } else {
3118 writelfl(~HC_MAIN_MASKED_IRQS_SOC,
3119 hpriv->main_irq_mask_addr);
3120 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
3121 readl(hpriv->main_irq_cause_addr),
3122 readl(hpriv->main_irq_mask_addr));
3123 }
3124 done:
3125 return rc;
3126 }
3127
3128 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3129 {
3130 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3131 MV_CRQB_Q_SZ, 0);
3132 if (!hpriv->crqb_pool)
3133 return -ENOMEM;
3134
3135 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3136 MV_CRPB_Q_SZ, 0);
3137 if (!hpriv->crpb_pool)
3138 return -ENOMEM;
3139
3140 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3141 MV_SG_TBL_SZ, 0);
3142 if (!hpriv->sg_tbl_pool)
3143 return -ENOMEM;
3144
3145 return 0;
3146 }
3147
3148 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3149 struct mbus_dram_target_info *dram)
3150 {
3151 int i;
3152
3153 for (i = 0; i < 4; i++) {
3154 writel(0, hpriv->base + WINDOW_CTRL(i));
3155 writel(0, hpriv->base + WINDOW_BASE(i));
3156 }
3157
3158 for (i = 0; i < dram->num_cs; i++) {
3159 struct mbus_dram_window *cs = dram->cs + i;
3160
3161 writel(((cs->size - 1) & 0xffff0000) |
3162 (cs->mbus_attr << 8) |
3163 (dram->mbus_dram_target_id << 4) | 1,
3164 hpriv->base + WINDOW_CTRL(i));
3165 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3166 }
3167 }
3168
3169 /**
3170 * mv_platform_probe - handle a positive probe of an soc Marvell
3171 * host
3172 * @pdev: platform device found
3173 *
3174 * LOCKING:
3175 * Inherited from caller.
3176 */
3177 static int mv_platform_probe(struct platform_device *pdev)
3178 {
3179 static int printed_version;
3180 const struct mv_sata_platform_data *mv_platform_data;
3181 const struct ata_port_info *ppi[] =
3182 { &mv_port_info[chip_soc], NULL };
3183 struct ata_host *host;
3184 struct mv_host_priv *hpriv;
3185 struct resource *res;
3186 int n_ports, rc;
3187
3188 if (!printed_version++)
3189 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3190
3191 /*
3192 * Simple resource validation ..
3193 */
3194 if (unlikely(pdev->num_resources != 2)) {
3195 dev_err(&pdev->dev, "invalid number of resources\n");
3196 return -EINVAL;
3197 }
3198
3199 /*
3200 * Get the register base first
3201 */
3202 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3203 if (res == NULL)
3204 return -EINVAL;
3205
3206 /* allocate host */
3207 mv_platform_data = pdev->dev.platform_data;
3208 n_ports = mv_platform_data->n_ports;
3209
3210 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3211 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3212
3213 if (!host || !hpriv)
3214 return -ENOMEM;
3215 host->private_data = hpriv;
3216 hpriv->n_ports = n_ports;
3217
3218 host->iomap = NULL;
3219 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3220 res->end - res->start + 1);
3221 hpriv->base -= MV_SATAHC0_REG_BASE;
3222
3223 /*
3224 * (Re-)program MBUS remapping windows if we are asked to.
3225 */
3226 if (mv_platform_data->dram != NULL)
3227 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3228
3229 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3230 if (rc)
3231 return rc;
3232
3233 /* initialize adapter */
3234 rc = mv_init_host(host, chip_soc);
3235 if (rc)
3236 return rc;
3237
3238 dev_printk(KERN_INFO, &pdev->dev,
3239 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3240 host->n_ports);
3241
3242 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3243 IRQF_SHARED, &mv6_sht);
3244 }
3245
3246 /*
3247 *
3248 * mv_platform_remove - unplug a platform interface
3249 * @pdev: platform device
3250 *
3251 * A platform bus SATA device has been unplugged. Perform the needed
3252 * cleanup. Also called on module unload for any active devices.
3253 */
3254 static int __devexit mv_platform_remove(struct platform_device *pdev)
3255 {
3256 struct device *dev = &pdev->dev;
3257 struct ata_host *host = dev_get_drvdata(dev);
3258
3259 ata_host_detach(host);
3260 return 0;
3261 }
3262
3263 static struct platform_driver mv_platform_driver = {
3264 .probe = mv_platform_probe,
3265 .remove = __devexit_p(mv_platform_remove),
3266 .driver = {
3267 .name = DRV_NAME,
3268 .owner = THIS_MODULE,
3269 },
3270 };
3271
3272
3273 #ifdef CONFIG_PCI
3274 static int mv_pci_init_one(struct pci_dev *pdev,
3275 const struct pci_device_id *ent);
3276
3277
3278 static struct pci_driver mv_pci_driver = {
3279 .name = DRV_NAME,
3280 .id_table = mv_pci_tbl,
3281 .probe = mv_pci_init_one,
3282 .remove = ata_pci_remove_one,
3283 };
3284
3285 /*
3286 * module options
3287 */
3288 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3289
3290
3291 /* move to PCI layer or libata core? */
3292 static int pci_go_64(struct pci_dev *pdev)
3293 {
3294 int rc;
3295
3296 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3297 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3298 if (rc) {
3299 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3300 if (rc) {
3301 dev_printk(KERN_ERR, &pdev->dev,
3302 "64-bit DMA enable failed\n");
3303 return rc;
3304 }
3305 }
3306 } else {
3307 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3308 if (rc) {
3309 dev_printk(KERN_ERR, &pdev->dev,
3310 "32-bit DMA enable failed\n");
3311 return rc;
3312 }
3313 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3314 if (rc) {
3315 dev_printk(KERN_ERR, &pdev->dev,
3316 "32-bit consistent DMA enable failed\n");
3317 return rc;
3318 }
3319 }
3320
3321 return rc;
3322 }
3323
3324 /**
3325 * mv_print_info - Dump key info to kernel log for perusal.
3326 * @host: ATA host to print info about
3327 *
3328 * FIXME: complete this.
3329 *
3330 * LOCKING:
3331 * Inherited from caller.
3332 */
3333 static void mv_print_info(struct ata_host *host)
3334 {
3335 struct pci_dev *pdev = to_pci_dev(host->dev);
3336 struct mv_host_priv *hpriv = host->private_data;
3337 u8 scc;
3338 const char *scc_s, *gen;
3339
3340 /* Use this to determine the HW stepping of the chip so we know
3341 * what errata to workaround
3342 */
3343 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3344 if (scc == 0)
3345 scc_s = "SCSI";
3346 else if (scc == 0x01)
3347 scc_s = "RAID";
3348 else
3349 scc_s = "?";
3350
3351 if (IS_GEN_I(hpriv))
3352 gen = "I";
3353 else if (IS_GEN_II(hpriv))
3354 gen = "II";
3355 else if (IS_GEN_IIE(hpriv))
3356 gen = "IIE";
3357 else
3358 gen = "?";
3359
3360 dev_printk(KERN_INFO, &pdev->dev,
3361 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3362 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
3363 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3364 }
3365
3366 /**
3367 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
3368 * @pdev: PCI device found
3369 * @ent: PCI device ID entry for the matched host
3370 *
3371 * LOCKING:
3372 * Inherited from caller.
3373 */
3374 static int mv_pci_init_one(struct pci_dev *pdev,
3375 const struct pci_device_id *ent)
3376 {
3377 static int printed_version;
3378 unsigned int board_idx = (unsigned int)ent->driver_data;
3379 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3380 struct ata_host *host;
3381 struct mv_host_priv *hpriv;
3382 int n_ports, rc;
3383
3384 if (!printed_version++)
3385 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3386
3387 /* allocate host */
3388 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3389
3390 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3391 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3392 if (!host || !hpriv)
3393 return -ENOMEM;
3394 host->private_data = hpriv;
3395 hpriv->n_ports = n_ports;
3396
3397 /* acquire resources */
3398 rc = pcim_enable_device(pdev);
3399 if (rc)
3400 return rc;
3401
3402 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3403 if (rc == -EBUSY)
3404 pcim_pin_device(pdev);
3405 if (rc)
3406 return rc;
3407 host->iomap = pcim_iomap_table(pdev);
3408 hpriv->base = host->iomap[MV_PRIMARY_BAR];
3409
3410 rc = pci_go_64(pdev);
3411 if (rc)
3412 return rc;
3413
3414 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3415 if (rc)
3416 return rc;
3417
3418 /* initialize adapter */
3419 rc = mv_init_host(host, board_idx);
3420 if (rc)
3421 return rc;
3422
3423 /* Enable interrupts */
3424 if (msi && pci_enable_msi(pdev))
3425 pci_intx(pdev, 1);
3426
3427 mv_dump_pci_cfg(pdev, 0x68);
3428 mv_print_info(host);
3429
3430 pci_set_master(pdev);
3431 pci_try_set_mwi(pdev);
3432 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
3433 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
3434 }
3435 #endif
3436
3437 static int mv_platform_probe(struct platform_device *pdev);
3438 static int __devexit mv_platform_remove(struct platform_device *pdev);
3439
3440 static int __init mv_init(void)
3441 {
3442 int rc = -ENODEV;
3443 #ifdef CONFIG_PCI
3444 rc = pci_register_driver(&mv_pci_driver);
3445 if (rc < 0)
3446 return rc;
3447 #endif
3448 rc = platform_driver_register(&mv_platform_driver);
3449
3450 #ifdef CONFIG_PCI
3451 if (rc < 0)
3452 pci_unregister_driver(&mv_pci_driver);
3453 #endif
3454 return rc;
3455 }
3456
3457 static void __exit mv_exit(void)
3458 {
3459 #ifdef CONFIG_PCI
3460 pci_unregister_driver(&mv_pci_driver);
3461 #endif
3462 platform_driver_unregister(&mv_platform_driver);
3463 }
3464
3465 MODULE_AUTHOR("Brett Russ");
3466 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3467 MODULE_LICENSE("GPL");
3468 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3469 MODULE_VERSION(DRV_VERSION);
3470 MODULE_ALIAS("platform:" DRV_NAME);
3471
3472 #ifdef CONFIG_PCI
3473 module_param(msi, int, 0444);
3474 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
3475 #endif
3476
3477 module_init(mv_init);
3478 module_exit(mv_exit);
Support for the Chinese Samsung S3C2440 based development boards