include/asm-i386/spinlock.h

   1 #ifndef __ASM_SPINLOCK_H
   2 #define __ASM_SPINLOCK_H
   3
   4 #include <asm/atomic.h>
   5 #include <asm/rwlock.h>
   6 #include <asm/page.h>
   7 #include <linux/config.h>
   8 #include <linux/compiler.h>
   9
  10 /*
  11  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  12  *
  13  * Simple spin lock operations.  There are two variants, one clears IRQ's
  14  * on the local processor, one does not.
  15  *
  16  * We make no fairness assumptions. They have a cost.
  17  *
  18  * (the type definitions are in asm/spinlock_types.h)
  19  */
  20
  21 #define __raw_spin_is_locked(x) \
  22                 (*(volatile signed char *)(&(x)->slock) <= 0)
  23
  24 #define __raw_spin_lock_string \
  25         "\n1:\t" \
  26         "lock ; decb %0\n\t" \
  27         "jns 3f\n" \
  28         "2:\t" \
  29         "rep;nop\n\t" \
  30         "cmpb $0,%0\n\t" \
  31         "jle 2b\n\t" \
  32         "jmp 1b\n" \
  33         "3:\n\t"
  34
  35 #define __raw_spin_lock_string_flags \
  36         "\n1:\t" \
  37         "lock ; decb %0\n\t" \
  38         "jns 5f\n" \
  39         "2:\t" \
  40         "testl $0x200, %1\n\t" \
  41         "jz 4f\n\t" \
  42         "sti\n" \
  43         "3:\t" \
  44         "rep;nop\n\t" \
  45         "cmpb $0, %0\n\t" \
  46         "jle 3b\n\t" \
  47         "cli\n\t" \
  48         "jmp 1b\n" \
  49         "4:\t" \
  50         "rep;nop\n\t" \
  51         "cmpb $0, %0\n\t" \
  52         "jg 1b\n\t" \
  53         "jmp 4b\n" \
  54         "5:\n\t"
  55
  56 #define __raw_spin_lock_string_up \
  57         "\n\tdecb %0"
  58
  59 static inline void __raw_spin_lock(raw_spinlock_t *lock)
  60 {
  61         alternative_smp(
  62                 __raw_spin_lock_string,
  63                 __raw_spin_lock_string_up,
  64                 "=m" (lock->slock) : : "memory");
  65 }
  66
  67 static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
  68 {
  69         alternative_smp(
  70                 __raw_spin_lock_string_flags,
  71                 __raw_spin_lock_string_up,
  72                 "=m" (lock->slock) : "r" (flags) : "memory");
  73 }
  74
  75 static inline int __raw_spin_trylock(raw_spinlock_t *lock)
  76 {
  77         char oldval;
  78         __asm__ __volatile__(
  79                 "xchgb %b0,%1"
  80                 :"=q" (oldval), "=m" (lock->slock)
  81                 :"0" (0) : "memory");
  82         return oldval > 0;
  83 }
  84
  85 /*
  86  * __raw_spin_unlock based on writing $1 to the low byte.
  87  * This method works. Despite all the confusion.
  88  * (except on PPro SMP or if we are using OOSTORE, so we use xchgb there)
  89  * (PPro errata 66, 92)
  90  */
  91
  92 #if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
  93
  94 #define __raw_spin_unlock_string \
  95         "movb $1,%0" \
  96                 :"=m" (lock->slock) : : "memory"
  97
  98
  99 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 100 {
 101         __asm__ __volatile__(
 102                 __raw_spin_unlock_string
 103         );
 104 }
 105
 106 #else
 107
 108 #define __raw_spin_unlock_string \
 109         "xchgb %b0, %1" \
 110                 :"=q" (oldval), "=m" (lock->slock) \
 111                 :"0" (oldval) : "memory"
 112
 113 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 114 {
 115         char oldval = 1;
 116
 117         __asm__ __volatile__(
 118                 __raw_spin_unlock_string
 119         );
 120 }
 121
 122 #endif
 123
 124 #define __raw_spin_unlock_wait(lock) \
 125         do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
 126
 127 /*
 128  * Read-write spinlocks, allowing multiple readers
 129  * but only one writer.
 130  *
 131  * NOTE! it is quite common to have readers in interrupts
 132  * but no interrupt writers. For those circumstances we
 133  * can "mix" irq-safe locks - any writer needs to get a
 134  * irq-safe write-lock, but readers can get non-irqsafe
 135  * read-locks.
 136  *
 137  * On x86, we implement read-write locks as a 32-bit counter
 138  * with the high bit (sign) being the "contended" bit.
 139  *
 140  * The inline assembly is non-obvious. Think about it.
 141  *
 142  * Changed to use the same technique as rw semaphores.  See
 143  * semaphore.h for details.  -ben
 144  *
 145  * the helpers are in arch/i386/kernel/semaphore.c
 146  */
 147
 148 /**
 149  * read_can_lock - would read_trylock() succeed?
 150  * @lock: the rwlock in question.
 151  */
 152 #define __raw_read_can_lock(x)          ((int)(x)->lock > 0)
 153
 154 /**
 155  * write_can_lock - would write_trylock() succeed?
 156  * @lock: the rwlock in question.
 157  */
 158 #define __raw_write_can_lock(x)         ((x)->lock == RW_LOCK_BIAS)
 159
 160 static inline void __raw_read_lock(raw_rwlock_t *rw)
 161 {
 162         __build_read_lock(rw, "__read_lock_failed");
 163 }
 164
 165 static inline void __raw_write_lock(raw_rwlock_t *rw)
 166 {
 167         __build_write_lock(rw, "__write_lock_failed");
 168 }
 169
 170 static inline int __raw_read_trylock(raw_rwlock_t *lock)
 171 {
 172         atomic_t *count = (atomic_t *)lock;
 173         atomic_dec(count);
 174         if (atomic_read(count) >= 0)
 175                 return 1;
 176         atomic_inc(count);
 177         return 0;
 178 }
 179
 180 static inline int __raw_write_trylock(raw_rwlock_t *lock)
 181 {
 182         atomic_t *count = (atomic_t *)lock;
 183         if (atomic_sub_and_test(RW_LOCK_BIAS, count))
 184                 return 1;
 185         atomic_add(RW_LOCK_BIAS, count);
 186         return 0;
 187 }
 188
 189 static inline void __raw_read_unlock(raw_rwlock_t *rw)
 190 {
 191         asm volatile(LOCK_PREFIX "incl %0" :"=m" (rw->lock) : : "memory");
 192 }
 193
 194 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 195 {
 196         asm volatile(LOCK_PREFIX "addl $" RW_LOCK_BIAS_STR ", %0"
 197                                  : "=m" (rw->lock) : : "memory");
 198 }
 199
 200 #endif /* __ASM_SPINLOCK_H */