?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ath9k: Remove unnecessary count for addba attempt
[linux-2.6/mini2440.git] / drivers / net / wireless / ath / ath9k / xmit.c
blobe08c8174d656e4230178a691b1ba37f262f3f295
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
23 #define L_STF 8
24 #define L_LTF 8
25 #define L_SIG 4
26 #define HT_SIG 8
27 #define HT_STF 4
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
33
34 #define OFDM_SIFS_TIME 16
35
36 static u32 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
54 };
55
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
57
58 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
59 struct ath_atx_tid *tid,
60 struct list_head *bf_head);
61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
62 struct list_head *bf_q,
63 int txok, int sendbar);
64 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
65 struct list_head *head);
66 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
67 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
68 int txok);
69 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
70 int nbad, int txok, bool update_rc);
71
72 /*********************/
73 /* Aggregation logic */
74 /*********************/
75
76 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
77 {
78 struct ath_atx_ac *ac = tid->ac;
79
80 if (tid->paused)
81 return;
82
83 if (tid->sched)
84 return;
85
86 tid->sched = true;
87 list_add_tail(&tid->list, &ac->tid_q);
88
89 if (ac->sched)
90 return;
91
92 ac->sched = true;
93 list_add_tail(&ac->list, &txq->axq_acq);
94 }
95
96 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
97 {
98 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
99
100 spin_lock_bh(&txq->axq_lock);
101 tid->paused++;
102 spin_unlock_bh(&txq->axq_lock);
103 }
104
105 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
106 {
107 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
108
109 ASSERT(tid->paused > 0);
110 spin_lock_bh(&txq->axq_lock);
111
112 tid->paused--;
113
114 if (tid->paused > 0)
115 goto unlock;
116
117 if (list_empty(&tid->buf_q))
118 goto unlock;
119
120 ath_tx_queue_tid(txq, tid);
121 ath_txq_schedule(sc, txq);
122 unlock:
123 spin_unlock_bh(&txq->axq_lock);
124 }
125
126 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
127 {
128 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
129 struct ath_buf *bf;
130 struct list_head bf_head;
131 INIT_LIST_HEAD(&bf_head);
132
133 ASSERT(tid->paused > 0);
134 spin_lock_bh(&txq->axq_lock);
135
136 tid->paused--;
137
138 if (tid->paused > 0) {
139 spin_unlock_bh(&txq->axq_lock);
140 return;
141 }
142
143 while (!list_empty(&tid->buf_q)) {
144 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
145 ASSERT(!bf_isretried(bf));
146 list_move_tail(&bf->list, &bf_head);
147 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
148 }
149
150 spin_unlock_bh(&txq->axq_lock);
151 }
152
153 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
154 int seqno)
155 {
156 int index, cindex;
157
158 index = ATH_BA_INDEX(tid->seq_start, seqno);
159 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
160
161 tid->tx_buf[cindex] = NULL;
162
163 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
164 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
165 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
166 }
167 }
168
169 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
170 struct ath_buf *bf)
171 {
172 int index, cindex;
173
174 if (bf_isretried(bf))
175 return;
176
177 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
178 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
179
180 ASSERT(tid->tx_buf[cindex] == NULL);
181 tid->tx_buf[cindex] = bf;
182
183 if (index >= ((tid->baw_tail - tid->baw_head) &
184 (ATH_TID_MAX_BUFS - 1))) {
185 tid->baw_tail = cindex;
186 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
187 }
188 }
189
190 /*
191 * TODO: For frame(s) that are in the retry state, we will reuse the
192 * sequence number(s) without setting the retry bit. The
193 * alternative is to give up on these and BAR the receiver's window
194 * forward.
195 */
196 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
197 struct ath_atx_tid *tid)
198
199 {
200 struct ath_buf *bf;
201 struct list_head bf_head;
202 INIT_LIST_HEAD(&bf_head);
203
204 for (;;) {
205 if (list_empty(&tid->buf_q))
206 break;
207
208 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
209 list_move_tail(&bf->list, &bf_head);
210
211 if (bf_isretried(bf))
212 ath_tx_update_baw(sc, tid, bf->bf_seqno);
213
214 spin_unlock(&txq->axq_lock);
215 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
216 spin_lock(&txq->axq_lock);
217 }
218
219 tid->seq_next = tid->seq_start;
220 tid->baw_tail = tid->baw_head;
221 }
222
223 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
224 {
225 struct sk_buff *skb;
226 struct ieee80211_hdr *hdr;
227
228 bf->bf_state.bf_type |= BUF_RETRY;
229 bf->bf_retries++;
230
231 skb = bf->bf_mpdu;
232 hdr = (struct ieee80211_hdr *)skb->data;
233 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
234 }
235
236 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
237 {
238 struct ath_buf *tbf;
239
240 spin_lock_bh(&sc->tx.txbuflock);
241 ASSERT(!list_empty((&sc->tx.txbuf)));
242 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
243 list_del(&tbf->list);
244 spin_unlock_bh(&sc->tx.txbuflock);
245
246 ATH_TXBUF_RESET(tbf);
247
248 tbf->bf_mpdu = bf->bf_mpdu;
249 tbf->bf_buf_addr = bf->bf_buf_addr;
250 *(tbf->bf_desc) = *(bf->bf_desc);
251 tbf->bf_state = bf->bf_state;
252 tbf->bf_dmacontext = bf->bf_dmacontext;
253
254 return tbf;
255 }
256
257 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
258 struct ath_buf *bf, struct list_head *bf_q,
259 int txok)
260 {
261 struct ath_node *an = NULL;
262 struct sk_buff *skb;
263 struct ieee80211_sta *sta;
264 struct ieee80211_hdr *hdr;
265 struct ath_atx_tid *tid = NULL;
266 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
267 struct ath_desc *ds = bf_last->bf_desc;
268 struct list_head bf_head, bf_pending;
269 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
270 u32 ba[WME_BA_BMP_SIZE >> 5];
271 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
272 bool rc_update = true;
273
274 skb = bf->bf_mpdu;
275 hdr = (struct ieee80211_hdr *)skb->data;
276
277 rcu_read_lock();
278
279 sta = ieee80211_find_sta(sc->hw, hdr->addr1);
280 if (!sta) {
281 rcu_read_unlock();
282 return;
283 }
284
285 an = (struct ath_node *)sta->drv_priv;
286 tid = ATH_AN_2_TID(an, bf->bf_tidno);
287
288 isaggr = bf_isaggr(bf);
289 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
290
291 if (isaggr && txok) {
292 if (ATH_DS_TX_BA(ds)) {
293 seq_st = ATH_DS_BA_SEQ(ds);
294 memcpy(ba, ATH_DS_BA_BITMAP(ds),
295 WME_BA_BMP_SIZE >> 3);
296 } else {
297 /*
298 * AR5416 can become deaf/mute when BA
299 * issue happens. Chip needs to be reset.
300 * But AP code may have sychronization issues
301 * when perform internal reset in this routine.
302 * Only enable reset in STA mode for now.
303 */
304 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
305 needreset = 1;
306 }
307 }
308
309 INIT_LIST_HEAD(&bf_pending);
310 INIT_LIST_HEAD(&bf_head);
311
312 nbad = ath_tx_num_badfrms(sc, bf, txok);
313 while (bf) {
314 txfail = txpending = 0;
315 bf_next = bf->bf_next;
316
317 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
318 /* transmit completion, subframe is
319 * acked by block ack */
320 acked_cnt++;
321 } else if (!isaggr && txok) {
322 /* transmit completion */
323 acked_cnt++;
324 } else {
325 if (!(tid->state & AGGR_CLEANUP) &&
326 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
327 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
328 ath_tx_set_retry(sc, bf);
329 txpending = 1;
330 } else {
331 bf->bf_state.bf_type |= BUF_XRETRY;
332 txfail = 1;
333 sendbar = 1;
334 txfail_cnt++;
335 }
336 } else {
337 /*
338 * cleanup in progress, just fail
339 * the un-acked sub-frames
340 */
341 txfail = 1;
342 }
343 }
344
345 if (bf_next == NULL) {
346 /*
347 * Make sure the last desc is reclaimed if it
348 * not a holding desc.
349 */
350 if (!bf_last->bf_stale)
351 list_move_tail(&bf->list, &bf_head);
352 else
353 INIT_LIST_HEAD(&bf_head);
354 } else {
355 ASSERT(!list_empty(bf_q));
356 list_move_tail(&bf->list, &bf_head);
357 }
358
359 if (!txpending) {
360 /*
361 * complete the acked-ones/xretried ones; update
362 * block-ack window
363 */
364 spin_lock_bh(&txq->axq_lock);
365 ath_tx_update_baw(sc, tid, bf->bf_seqno);
366 spin_unlock_bh(&txq->axq_lock);
367
368 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
369 ath_tx_rc_status(bf, ds, nbad, txok, true);
370 rc_update = false;
371 } else {
372 ath_tx_rc_status(bf, ds, nbad, txok, false);
373 }
374
375 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
376 } else {
377 /* retry the un-acked ones */
378 if (bf->bf_next == NULL && bf_last->bf_stale) {
379 struct ath_buf *tbf;
380
381 tbf = ath_clone_txbuf(sc, bf_last);
382 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
383 list_add_tail(&tbf->list, &bf_head);
384 } else {
385 /*
386 * Clear descriptor status words for
387 * software retry
388 */
389 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
390 }
391
392 /*
393 * Put this buffer to the temporary pending
394 * queue to retain ordering
395 */
396 list_splice_tail_init(&bf_head, &bf_pending);
397 }
398
399 bf = bf_next;
400 }
401
402 if (tid->state & AGGR_CLEANUP) {
403 if (tid->baw_head == tid->baw_tail) {
404 tid->state &= ~AGGR_ADDBA_COMPLETE;
405 tid->state &= ~AGGR_CLEANUP;
406
407 /* send buffered frames as singles */
408 ath_tx_flush_tid(sc, tid);
409 }
410 rcu_read_unlock();
411 return;
412 }
413
414 /* prepend un-acked frames to the beginning of the pending frame queue */
415 if (!list_empty(&bf_pending)) {
416 spin_lock_bh(&txq->axq_lock);
417 list_splice(&bf_pending, &tid->buf_q);
418 ath_tx_queue_tid(txq, tid);
419 spin_unlock_bh(&txq->axq_lock);
420 }
421
422 rcu_read_unlock();
423
424 if (needreset)
425 ath_reset(sc, false);
426 }
427
428 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
429 struct ath_atx_tid *tid)
430 {
431 const struct ath_rate_table *rate_table = sc->cur_rate_table;
432 struct sk_buff *skb;
433 struct ieee80211_tx_info *tx_info;
434 struct ieee80211_tx_rate *rates;
435 struct ath_tx_info_priv *tx_info_priv;
436 u32 max_4ms_framelen, frmlen;
437 u16 aggr_limit, legacy = 0, maxampdu;
438 int i;
439
440 skb = bf->bf_mpdu;
441 tx_info = IEEE80211_SKB_CB(skb);
442 rates = tx_info->control.rates;
443 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
444
445 /*
446 * Find the lowest frame length among the rate series that will have a
447 * 4ms transmit duration.
448 * TODO - TXOP limit needs to be considered.
449 */
450 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
451
452 for (i = 0; i < 4; i++) {
453 if (rates[i].count) {
454 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) {
455 legacy = 1;
456 break;
457 }
458
459 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen;
460 max_4ms_framelen = min(max_4ms_framelen, frmlen);
461 }
462 }
463
464 /*
465 * limit aggregate size by the minimum rate if rate selected is
466 * not a probe rate, if rate selected is a probe rate then
467 * avoid aggregation of this packet.
468 */
469 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
470 return 0;
471
472 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT);
473
474 /*
475 * h/w can accept aggregates upto 16 bit lengths (65535).
476 * The IE, however can hold upto 65536, which shows up here
477 * as zero. Ignore 65536 since we are constrained by hw.
478 */
479 maxampdu = tid->an->maxampdu;
480 if (maxampdu)
481 aggr_limit = min(aggr_limit, maxampdu);
482
483 return aggr_limit;
484 }
485
486 /*
487 * Returns the number of delimiters to be added to
488 * meet the minimum required mpdudensity.
489 * caller should make sure that the rate is HT rate .
490 */
491 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
492 struct ath_buf *bf, u16 frmlen)
493 {
494 const struct ath_rate_table *rt = sc->cur_rate_table;
495 struct sk_buff *skb = bf->bf_mpdu;
496 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
497 u32 nsymbits, nsymbols, mpdudensity;
498 u16 minlen;
499 u8 rc, flags, rix;
500 int width, half_gi, ndelim, mindelim;
501
502 /* Select standard number of delimiters based on frame length alone */
503 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
504
505 /*
506 * If encryption enabled, hardware requires some more padding between
507 * subframes.
508 * TODO - this could be improved to be dependent on the rate.
509 * The hardware can keep up at lower rates, but not higher rates
510 */
511 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
512 ndelim += ATH_AGGR_ENCRYPTDELIM;
513
514 /*
515 * Convert desired mpdu density from microeconds to bytes based
516 * on highest rate in rate series (i.e. first rate) to determine
517 * required minimum length for subframe. Take into account
518 * whether high rate is 20 or 40Mhz and half or full GI.
519 */
520 mpdudensity = tid->an->mpdudensity;
521
522 /*
523 * If there is no mpdu density restriction, no further calculation
524 * is needed.
525 */
526 if (mpdudensity == 0)
527 return ndelim;
528
529 rix = tx_info->control.rates[0].idx;
530 flags = tx_info->control.rates[0].flags;
531 rc = rt->info[rix].ratecode;
532 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
533 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
534
535 if (half_gi)
536 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
537 else
538 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
539
540 if (nsymbols == 0)
541 nsymbols = 1;
542
543 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
544 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
545
546 if (frmlen < minlen) {
547 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
548 ndelim = max(mindelim, ndelim);
549 }
550
551 return ndelim;
552 }
553
554 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
555 struct ath_atx_tid *tid,
556 struct list_head *bf_q)
557 {
558 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
559 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
560 int rl = 0, nframes = 0, ndelim, prev_al = 0;
561 u16 aggr_limit = 0, al = 0, bpad = 0,
562 al_delta, h_baw = tid->baw_size / 2;
563 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
564
565 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
566
567 do {
568 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
569
570 /* do not step over block-ack window */
571 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
572 status = ATH_AGGR_BAW_CLOSED;
573 break;
574 }
575
576 if (!rl) {
577 aggr_limit = ath_lookup_rate(sc, bf, tid);
578 rl = 1;
579 }
580
581 /* do not exceed aggregation limit */
582 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
583
584 if (nframes &&
585 (aggr_limit < (al + bpad + al_delta + prev_al))) {
586 status = ATH_AGGR_LIMITED;
587 break;
588 }
589
590 /* do not exceed subframe limit */
591 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
592 status = ATH_AGGR_LIMITED;
593 break;
594 }
595 nframes++;
596
597 /* add padding for previous frame to aggregation length */
598 al += bpad + al_delta;
599
600 /*
601 * Get the delimiters needed to meet the MPDU
602 * density for this node.
603 */
604 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
605 bpad = PADBYTES(al_delta) + (ndelim << 2);
606
607 bf->bf_next = NULL;
608 bf->bf_desc->ds_link = 0;
609
610 /* link buffers of this frame to the aggregate */
611 ath_tx_addto_baw(sc, tid, bf);
612 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
613 list_move_tail(&bf->list, bf_q);
614 if (bf_prev) {
615 bf_prev->bf_next = bf;
616 bf_prev->bf_desc->ds_link = bf->bf_daddr;
617 }
618 bf_prev = bf;
619 } while (!list_empty(&tid->buf_q));
620
621 bf_first->bf_al = al;
622 bf_first->bf_nframes = nframes;
623
624 return status;
625 #undef PADBYTES
626 }
627
628 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
629 struct ath_atx_tid *tid)
630 {
631 struct ath_buf *bf;
632 enum ATH_AGGR_STATUS status;
633 struct list_head bf_q;
634
635 do {
636 if (list_empty(&tid->buf_q))
637 return;
638
639 INIT_LIST_HEAD(&bf_q);
640
641 status = ath_tx_form_aggr(sc, tid, &bf_q);
642
643 /*
644 * no frames picked up to be aggregated;
645 * block-ack window is not open.
646 */
647 if (list_empty(&bf_q))
648 break;
649
650 bf = list_first_entry(&bf_q, struct ath_buf, list);
651 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
652
653 /* if only one frame, send as non-aggregate */
654 if (bf->bf_nframes == 1) {
655 bf->bf_state.bf_type &= ~BUF_AGGR;
656 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
657 ath_buf_set_rate(sc, bf);
658 ath_tx_txqaddbuf(sc, txq, &bf_q);
659 continue;
660 }
661
662 /* setup first desc of aggregate */
663 bf->bf_state.bf_type |= BUF_AGGR;
664 ath_buf_set_rate(sc, bf);
665 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
666
667 /* anchor last desc of aggregate */
668 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
669
670 txq->axq_aggr_depth++;
671 ath_tx_txqaddbuf(sc, txq, &bf_q);
672
673 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
674 status != ATH_AGGR_BAW_CLOSED);
675 }
676
677 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
678 u16 tid, u16 *ssn)
679 {
680 struct ath_atx_tid *txtid;
681 struct ath_node *an;
682
683 an = (struct ath_node *)sta->drv_priv;
684
685 if (sc->sc_flags & SC_OP_TXAGGR) {
686 txtid = ATH_AN_2_TID(an, tid);
687 txtid->state |= AGGR_ADDBA_PROGRESS;
688 ath_tx_pause_tid(sc, txtid);
689 *ssn = txtid->seq_start;
690 }
691
692 return 0;
693 }
694
695 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
696 {
697 struct ath_node *an = (struct ath_node *)sta->drv_priv;
698 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
699 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
700 struct ath_buf *bf;
701 struct list_head bf_head;
702 INIT_LIST_HEAD(&bf_head);
703
704 if (txtid->state & AGGR_CLEANUP)
705 return 0;
706
707 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
708 txtid->state &= ~AGGR_ADDBA_PROGRESS;
709 return 0;
710 }
711
712 ath_tx_pause_tid(sc, txtid);
713
714 /* drop all software retried frames and mark this TID */
715 spin_lock_bh(&txq->axq_lock);
716 while (!list_empty(&txtid->buf_q)) {
717 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
718 if (!bf_isretried(bf)) {
719 /*
720 * NB: it's based on the assumption that
721 * software retried frame will always stay
722 * at the head of software queue.
723 */
724 break;
725 }
726 list_move_tail(&bf->list, &bf_head);
727 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
728 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
729 }
730 spin_unlock_bh(&txq->axq_lock);
731
732 if (txtid->baw_head != txtid->baw_tail) {
733 txtid->state |= AGGR_CLEANUP;
734 } else {
735 txtid->state &= ~AGGR_ADDBA_COMPLETE;
736 ath_tx_flush_tid(sc, txtid);
737 }
738
739 return 0;
740 }
741
742 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
743 {
744 struct ath_atx_tid *txtid;
745 struct ath_node *an;
746
747 an = (struct ath_node *)sta->drv_priv;
748
749 if (sc->sc_flags & SC_OP_TXAGGR) {
750 txtid = ATH_AN_2_TID(an, tid);
751 txtid->baw_size =
752 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
753 txtid->state |= AGGR_ADDBA_COMPLETE;
754 txtid->state &= ~AGGR_ADDBA_PROGRESS;
755 ath_tx_resume_tid(sc, txtid);
756 }
757 }
758
759 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
760 {
761 struct ath_atx_tid *txtid;
762
763 if (!(sc->sc_flags & SC_OP_TXAGGR))
764 return false;
765
766 txtid = ATH_AN_2_TID(an, tidno);
767
768 if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
769 return true;
770 return false;
771 }
772
773 /********************/
774 /* Queue Management */
775 /********************/
776
777 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
778 struct ath_txq *txq)
779 {
780 struct ath_atx_ac *ac, *ac_tmp;
781 struct ath_atx_tid *tid, *tid_tmp;
782
783 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
784 list_del(&ac->list);
785 ac->sched = false;
786 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
787 list_del(&tid->list);
788 tid->sched = false;
789 ath_tid_drain(sc, txq, tid);
790 }
791 }
792 }
793
794 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
795 {
796 struct ath_hw *ah = sc->sc_ah;
797 struct ath9k_tx_queue_info qi;
798 int qnum;
799
800 memset(&qi, 0, sizeof(qi));
801 qi.tqi_subtype = subtype;
802 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
803 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
804 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
805 qi.tqi_physCompBuf = 0;
806
807 /*
808 * Enable interrupts only for EOL and DESC conditions.
809 * We mark tx descriptors to receive a DESC interrupt
810 * when a tx queue gets deep; otherwise waiting for the
811 * EOL to reap descriptors. Note that this is done to
812 * reduce interrupt load and this only defers reaping
813 * descriptors, never transmitting frames. Aside from
814 * reducing interrupts this also permits more concurrency.
815 * The only potential downside is if the tx queue backs
816 * up in which case the top half of the kernel may backup
817 * due to a lack of tx descriptors.
818 *
819 * The UAPSD queue is an exception, since we take a desc-
820 * based intr on the EOSP frames.
821 */
822 if (qtype == ATH9K_TX_QUEUE_UAPSD)
823 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
824 else
825 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
826 TXQ_FLAG_TXDESCINT_ENABLE;
827 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
828 if (qnum == -1) {
829 /*
830 * NB: don't print a message, this happens
831 * normally on parts with too few tx queues
832 */
833 return NULL;
834 }
835 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
836 DPRINTF(sc, ATH_DBG_FATAL,
837 "qnum %u out of range, max %u!\n",
838 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
839 ath9k_hw_releasetxqueue(ah, qnum);
840 return NULL;
841 }
842 if (!ATH_TXQ_SETUP(sc, qnum)) {
843 struct ath_txq *txq = &sc->tx.txq[qnum];
844
845 txq->axq_qnum = qnum;
846 txq->axq_link = NULL;
847 INIT_LIST_HEAD(&txq->axq_q);
848 INIT_LIST_HEAD(&txq->axq_acq);
849 spin_lock_init(&txq->axq_lock);
850 txq->axq_depth = 0;
851 txq->axq_aggr_depth = 0;
852 txq->axq_totalqueued = 0;
853 txq->axq_linkbuf = NULL;
854 sc->tx.txqsetup |= 1<<qnum;
855 }
856 return &sc->tx.txq[qnum];
857 }
858
859 static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
860 {
861 int qnum;
862
863 switch (qtype) {
864 case ATH9K_TX_QUEUE_DATA:
865 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
866 DPRINTF(sc, ATH_DBG_FATAL,
867 "HAL AC %u out of range, max %zu!\n",
868 haltype, ARRAY_SIZE(sc->tx.hwq_map));
869 return -1;
870 }
871 qnum = sc->tx.hwq_map[haltype];
872 break;
873 case ATH9K_TX_QUEUE_BEACON:
874 qnum = sc->beacon.beaconq;
875 break;
876 case ATH9K_TX_QUEUE_CAB:
877 qnum = sc->beacon.cabq->axq_qnum;
878 break;
879 default:
880 qnum = -1;
881 }
882 return qnum;
883 }
884
885 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
886 {
887 struct ath_txq *txq = NULL;
888 int qnum;
889
890 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
891 txq = &sc->tx.txq[qnum];
892
893 spin_lock_bh(&txq->axq_lock);
894
895 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
896 DPRINTF(sc, ATH_DBG_XMIT,
897 "TX queue: %d is full, depth: %d\n",
898 qnum, txq->axq_depth);
899 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
900 txq->stopped = 1;
901 spin_unlock_bh(&txq->axq_lock);
902 return NULL;
903 }
904
905 spin_unlock_bh(&txq->axq_lock);
906
907 return txq;
908 }
909
910 int ath_txq_update(struct ath_softc *sc, int qnum,
911 struct ath9k_tx_queue_info *qinfo)
912 {
913 struct ath_hw *ah = sc->sc_ah;
914 int error = 0;
915 struct ath9k_tx_queue_info qi;
916
917 if (qnum == sc->beacon.beaconq) {
918 /*
919 * XXX: for beacon queue, we just save the parameter.
920 * It will be picked up by ath_beaconq_config when
921 * it's necessary.
922 */
923 sc->beacon.beacon_qi = *qinfo;
924 return 0;
925 }
926
927 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum);
928
929 ath9k_hw_get_txq_props(ah, qnum, &qi);
930 qi.tqi_aifs = qinfo->tqi_aifs;
931 qi.tqi_cwmin = qinfo->tqi_cwmin;
932 qi.tqi_cwmax = qinfo->tqi_cwmax;
933 qi.tqi_burstTime = qinfo->tqi_burstTime;
934 qi.tqi_readyTime = qinfo->tqi_readyTime;
935
936 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
937 DPRINTF(sc, ATH_DBG_FATAL,
938 "Unable to update hardware queue %u!\n", qnum);
939 error = -EIO;
940 } else {
941 ath9k_hw_resettxqueue(ah, qnum);
942 }
943
944 return error;
945 }
946
947 int ath_cabq_update(struct ath_softc *sc)
948 {
949 struct ath9k_tx_queue_info qi;
950 int qnum = sc->beacon.cabq->axq_qnum;
951
952 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
953 /*
954 * Ensure the readytime % is within the bounds.
955 */
956 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
957 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
958 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
959 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
960
961 qi.tqi_readyTime = (sc->beacon_interval *
962 sc->config.cabqReadytime) / 100;
963 ath_txq_update(sc, qnum, &qi);
964
965 return 0;
966 }
967
968 /*
969 * Drain a given TX queue (could be Beacon or Data)
970 *
971 * This assumes output has been stopped and
972 * we do not need to block ath_tx_tasklet.
973 */
974 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
975 {
976 struct ath_buf *bf, *lastbf;
977 struct list_head bf_head;
978
979 INIT_LIST_HEAD(&bf_head);
980
981 for (;;) {
982 spin_lock_bh(&txq->axq_lock);
983
984 if (list_empty(&txq->axq_q)) {
985 txq->axq_link = NULL;
986 txq->axq_linkbuf = NULL;
987 spin_unlock_bh(&txq->axq_lock);
988 break;
989 }
990
991 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
992
993 if (bf->bf_stale) {
994 list_del(&bf->list);
995 spin_unlock_bh(&txq->axq_lock);
996
997 spin_lock_bh(&sc->tx.txbuflock);
998 list_add_tail(&bf->list, &sc->tx.txbuf);
999 spin_unlock_bh(&sc->tx.txbuflock);
1000 continue;
1001 }
1002
1003 lastbf = bf->bf_lastbf;
1004 if (!retry_tx)
1005 lastbf->bf_desc->ds_txstat.ts_flags =
1006 ATH9K_TX_SW_ABORTED;
1007
1008 /* remove ath_buf's of the same mpdu from txq */
1009 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1010 txq->axq_depth--;
1011
1012 spin_unlock_bh(&txq->axq_lock);
1013
1014 if (bf_isampdu(bf))
1015 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0);
1016 else
1017 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1018 }
1019
1020 /* flush any pending frames if aggregation is enabled */
1021 if (sc->sc_flags & SC_OP_TXAGGR) {
1022 if (!retry_tx) {
1023 spin_lock_bh(&txq->axq_lock);
1024 ath_txq_drain_pending_buffers(sc, txq);
1025 spin_unlock_bh(&txq->axq_lock);
1026 }
1027 }
1028 }
1029
1030 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1031 {
1032 struct ath_hw *ah = sc->sc_ah;
1033 struct ath_txq *txq;
1034 int i, npend = 0;
1035
1036 if (sc->sc_flags & SC_OP_INVALID)
1037 return;
1038
1039 /* Stop beacon queue */
1040 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1041
1042 /* Stop data queues */
1043 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1044 if (ATH_TXQ_SETUP(sc, i)) {
1045 txq = &sc->tx.txq[i];
1046 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1047 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1048 }
1049 }
1050
1051 if (npend) {
1052 int r;
1053
1054 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
1055
1056 spin_lock_bh(&sc->sc_resetlock);
1057 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
1058 if (r)
1059 DPRINTF(sc, ATH_DBG_FATAL,
1060 "Unable to reset hardware; reset status %d\n",
1061 r);
1062 spin_unlock_bh(&sc->sc_resetlock);
1063 }
1064
1065 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1066 if (ATH_TXQ_SETUP(sc, i))
1067 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1068 }
1069 }
1070
1071 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1072 {
1073 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1074 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1075 }
1076
1077 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1078 {
1079 struct ath_atx_ac *ac;
1080 struct ath_atx_tid *tid;
1081
1082 if (list_empty(&txq->axq_acq))
1083 return;
1084
1085 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1086 list_del(&ac->list);
1087 ac->sched = false;
1088
1089 do {
1090 if (list_empty(&ac->tid_q))
1091 return;
1092
1093 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1094 list_del(&tid->list);
1095 tid->sched = false;
1096
1097 if (tid->paused)
1098 continue;
1099
1100 if ((txq->axq_depth % 2) == 0)
1101 ath_tx_sched_aggr(sc, txq, tid);
1102
1103 /*
1104 * add tid to round-robin queue if more frames
1105 * are pending for the tid
1106 */
1107 if (!list_empty(&tid->buf_q))
1108 ath_tx_queue_tid(txq, tid);
1109
1110 break;
1111 } while (!list_empty(&ac->tid_q));
1112
1113 if (!list_empty(&ac->tid_q)) {
1114 if (!ac->sched) {
1115 ac->sched = true;
1116 list_add_tail(&ac->list, &txq->axq_acq);
1117 }
1118 }
1119 }
1120
1121 int ath_tx_setup(struct ath_softc *sc, int haltype)
1122 {
1123 struct ath_txq *txq;
1124
1125 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1126 DPRINTF(sc, ATH_DBG_FATAL,
1127 "HAL AC %u out of range, max %zu!\n",
1128 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1129 return 0;
1130 }
1131 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1132 if (txq != NULL) {
1133 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1134 return 1;
1135 } else
1136 return 0;
1137 }
1138
1139 /***********/
1140 /* TX, DMA */
1141 /***********/
1142
1143 /*
1144 * Insert a chain of ath_buf (descriptors) on a txq and
1145 * assume the descriptors are already chained together by caller.
1146 */
1147 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1148 struct list_head *head)
1149 {
1150 struct ath_hw *ah = sc->sc_ah;
1151 struct ath_buf *bf;
1152
1153 /*
1154 * Insert the frame on the outbound list and
1155 * pass it on to the hardware.
1156 */
1157
1158 if (list_empty(head))
1159 return;
1160
1161 bf = list_first_entry(head, struct ath_buf, list);
1162
1163 list_splice_tail_init(head, &txq->axq_q);
1164 txq->axq_depth++;
1165 txq->axq_totalqueued++;
1166 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1167
1168 DPRINTF(sc, ATH_DBG_QUEUE,
1169 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1170
1171 if (txq->axq_link == NULL) {
1172 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1173 DPRINTF(sc, ATH_DBG_XMIT,
1174 "TXDP[%u] = %llx (%p)\n",
1175 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1176 } else {
1177 *txq->axq_link = bf->bf_daddr;
1178 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1179 txq->axq_qnum, txq->axq_link,
1180 ito64(bf->bf_daddr), bf->bf_desc);
1181 }
1182 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1183 ath9k_hw_txstart(ah, txq->axq_qnum);
1184 }
1185
1186 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1187 {
1188 struct ath_buf *bf = NULL;
1189
1190 spin_lock_bh(&sc->tx.txbuflock);
1191
1192 if (unlikely(list_empty(&sc->tx.txbuf))) {
1193 spin_unlock_bh(&sc->tx.txbuflock);
1194 return NULL;
1195 }
1196
1197 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
1198 list_del(&bf->list);
1199
1200 spin_unlock_bh(&sc->tx.txbuflock);
1201
1202 return bf;
1203 }
1204
1205 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1206 struct list_head *bf_head,
1207 struct ath_tx_control *txctl)
1208 {
1209 struct ath_buf *bf;
1210
1211 bf = list_first_entry(bf_head, struct ath_buf, list);
1212 bf->bf_state.bf_type |= BUF_AMPDU;
1213
1214 /*
1215 * Do not queue to h/w when any of the following conditions is true:
1216 * - there are pending frames in software queue
1217 * - the TID is currently paused for ADDBA/BAR request
1218 * - seqno is not within block-ack window
1219 * - h/w queue depth exceeds low water mark
1220 */
1221 if (!list_empty(&tid->buf_q) || tid->paused ||
1222 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1223 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1224 /*
1225 * Add this frame to software queue for scheduling later
1226 * for aggregation.
1227 */
1228 list_move_tail(&bf->list, &tid->buf_q);
1229 ath_tx_queue_tid(txctl->txq, tid);
1230 return;
1231 }
1232
1233 /* Add sub-frame to BAW */
1234 ath_tx_addto_baw(sc, tid, bf);
1235
1236 /* Queue to h/w without aggregation */
1237 bf->bf_nframes = 1;
1238 bf->bf_lastbf = bf;
1239 ath_buf_set_rate(sc, bf);
1240 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1241 }
1242
1243 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
1244 struct ath_atx_tid *tid,
1245 struct list_head *bf_head)
1246 {
1247 struct ath_buf *bf;
1248
1249 bf = list_first_entry(bf_head, struct ath_buf, list);
1250 bf->bf_state.bf_type &= ~BUF_AMPDU;
1251
1252 /* update starting sequence number for subsequent ADDBA request */
1253 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1254
1255 bf->bf_nframes = 1;
1256 bf->bf_lastbf = bf;
1257 ath_buf_set_rate(sc, bf);
1258 ath_tx_txqaddbuf(sc, txq, bf_head);
1259 }
1260
1261 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1262 struct list_head *bf_head)
1263 {
1264 struct ath_buf *bf;
1265
1266 bf = list_first_entry(bf_head, struct ath_buf, list);
1267
1268 bf->bf_lastbf = bf;
1269 bf->bf_nframes = 1;
1270 ath_buf_set_rate(sc, bf);
1271 ath_tx_txqaddbuf(sc, txq, bf_head);
1272 }
1273
1274 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1275 {
1276 struct ieee80211_hdr *hdr;
1277 enum ath9k_pkt_type htype;
1278 __le16 fc;
1279
1280 hdr = (struct ieee80211_hdr *)skb->data;
1281 fc = hdr->frame_control;
1282
1283 if (ieee80211_is_beacon(fc))
1284 htype = ATH9K_PKT_TYPE_BEACON;
1285 else if (ieee80211_is_probe_resp(fc))
1286 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1287 else if (ieee80211_is_atim(fc))
1288 htype = ATH9K_PKT_TYPE_ATIM;
1289 else if (ieee80211_is_pspoll(fc))
1290 htype = ATH9K_PKT_TYPE_PSPOLL;
1291 else
1292 htype = ATH9K_PKT_TYPE_NORMAL;
1293
1294 return htype;
1295 }
1296
1297 static bool is_pae(struct sk_buff *skb)
1298 {
1299 struct ieee80211_hdr *hdr;
1300 __le16 fc;
1301
1302 hdr = (struct ieee80211_hdr *)skb->data;
1303 fc = hdr->frame_control;
1304
1305 if (ieee80211_is_data(fc)) {
1306 if (ieee80211_is_nullfunc(fc) ||
1307 /* Port Access Entity (IEEE 802.1X) */
1308 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1309 return true;
1310 }
1311 }
1312
1313 return false;
1314 }
1315
1316 static int get_hw_crypto_keytype(struct sk_buff *skb)
1317 {
1318 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1319
1320 if (tx_info->control.hw_key) {
1321 if (tx_info->control.hw_key->alg == ALG_WEP)
1322 return ATH9K_KEY_TYPE_WEP;
1323 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1324 return ATH9K_KEY_TYPE_TKIP;
1325 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1326 return ATH9K_KEY_TYPE_AES;
1327 }
1328
1329 return ATH9K_KEY_TYPE_CLEAR;
1330 }
1331
1332 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1333 struct ath_buf *bf)
1334 {
1335 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1336 struct ieee80211_hdr *hdr;
1337 struct ath_node *an;
1338 struct ath_atx_tid *tid;
1339 __le16 fc;
1340 u8 *qc;
1341
1342 if (!tx_info->control.sta)
1343 return;
1344
1345 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1346 hdr = (struct ieee80211_hdr *)skb->data;
1347 fc = hdr->frame_control;
1348
1349 if (ieee80211_is_data_qos(fc)) {
1350 qc = ieee80211_get_qos_ctl(hdr);
1351 bf->bf_tidno = qc[0] & 0xf;
1352 }
1353
1354 /*
1355 * For HT capable stations, we save tidno for later use.
1356 * We also override seqno set by upper layer with the one
1357 * in tx aggregation state.
1358 *
1359 * If fragmentation is on, the sequence number is
1360 * not overridden, since it has been
1361 * incremented by the fragmentation routine.
1362 *
1363 * FIXME: check if the fragmentation threshold exceeds
1364 * IEEE80211 max.
1365 */
1366 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1367 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
1368 IEEE80211_SEQ_SEQ_SHIFT);
1369 bf->bf_seqno = tid->seq_next;
1370 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1371 }
1372
1373 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1374 struct ath_txq *txq)
1375 {
1376 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1377 int flags = 0;
1378
1379 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1380 flags |= ATH9K_TXDESC_INTREQ;
1381
1382 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1383 flags |= ATH9K_TXDESC_NOACK;
1384
1385 return flags;
1386 }
1387
1388 /*
1389 * rix - rate index
1390 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1391 * width - 0 for 20 MHz, 1 for 40 MHz
1392 * half_gi - to use 4us v/s 3.6 us for symbol time
1393 */
1394 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1395 int width, int half_gi, bool shortPreamble)
1396 {
1397 const struct ath_rate_table *rate_table = sc->cur_rate_table;
1398 u32 nbits, nsymbits, duration, nsymbols;
1399 u8 rc;
1400 int streams, pktlen;
1401
1402 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1403 rc = rate_table->info[rix].ratecode;
1404
1405 /* for legacy rates, use old function to compute packet duration */
1406 if (!IS_HT_RATE(rc))
1407 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
1408 rix, shortPreamble);
1409
1410 /* find number of symbols: PLCP + data */
1411 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1412 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1413 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1414
1415 if (!half_gi)
1416 duration = SYMBOL_TIME(nsymbols);
1417 else
1418 duration = SYMBOL_TIME_HALFGI(nsymbols);
1419
1420 /* addup duration for legacy/ht training and signal fields */
1421 streams = HT_RC_2_STREAMS(rc);
1422 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1423
1424 return duration;
1425 }
1426
1427 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1428 {
1429 const struct ath_rate_table *rt = sc->cur_rate_table;
1430 struct ath9k_11n_rate_series series[4];
1431 struct sk_buff *skb;
1432 struct ieee80211_tx_info *tx_info;
1433 struct ieee80211_tx_rate *rates;
1434 struct ieee80211_hdr *hdr;
1435 int i, flags = 0;
1436 u8 rix = 0, ctsrate = 0;
1437 bool is_pspoll;
1438
1439 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1440
1441 skb = bf->bf_mpdu;
1442 tx_info = IEEE80211_SKB_CB(skb);
1443 rates = tx_info->control.rates;
1444 hdr = (struct ieee80211_hdr *)skb->data;
1445 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1446
1447 /*
1448 * We check if Short Preamble is needed for the CTS rate by
1449 * checking the BSS's global flag.
1450 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1451 */
1452 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1453 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode |
1454 rt->info[tx_info->control.rts_cts_rate_idx].short_preamble;
1455 else
1456 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode;
1457
1458 /*
1459 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
1460 * Check the first rate in the series to decide whether RTS/CTS
1461 * or CTS-to-self has to be used.
1462 */
1463 if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1464 flags = ATH9K_TXDESC_CTSENA;
1465 else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1466 flags = ATH9K_TXDESC_RTSENA;
1467
1468 /* FIXME: Handle aggregation protection */
1469 if (sc->config.ath_aggr_prot &&
1470 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
1471 flags = ATH9K_TXDESC_RTSENA;
1472 }
1473
1474 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1475 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1476 flags &= ~(ATH9K_TXDESC_RTSENA);
1477
1478 for (i = 0; i < 4; i++) {
1479 if (!rates[i].count || (rates[i].idx < 0))
1480 continue;
1481
1482 rix = rates[i].idx;
1483 series[i].Tries = rates[i].count;
1484 series[i].ChSel = sc->tx_chainmask;
1485
1486 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1487 series[i].Rate = rt->info[rix].ratecode |
1488 rt->info[rix].short_preamble;
1489 else
1490 series[i].Rate = rt->info[rix].ratecode;
1491
1492 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1493 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1494 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1495 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1496 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1497 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1498
1499 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1500 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0,
1501 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI),
1502 (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE));
1503 }
1504
1505 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1506 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1507 bf->bf_lastbf->bf_desc,
1508 !is_pspoll, ctsrate,
1509 0, series, 4, flags);
1510
1511 if (sc->config.ath_aggr_prot && flags)
1512 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1513 }
1514
1515 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1516 struct sk_buff *skb,
1517 struct ath_tx_control *txctl)
1518 {
1519 struct ath_wiphy *aphy = hw->priv;
1520 struct ath_softc *sc = aphy->sc;
1521 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1522 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1523 struct ath_tx_info_priv *tx_info_priv;
1524 int hdrlen;
1525 __le16 fc;
1526
1527 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);
1528 if (unlikely(!tx_info_priv))
1529 return -ENOMEM;
1530 tx_info->rate_driver_data[0] = tx_info_priv;
1531 tx_info_priv->aphy = aphy;
1532 tx_info_priv->frame_type = txctl->frame_type;
1533 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1534 fc = hdr->frame_control;
1535
1536 ATH_TXBUF_RESET(bf);
1537
1538 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1539
1540 if (conf_is_ht(&sc->hw->conf) && !is_pae(skb))
1541 bf->bf_state.bf_type |= BUF_HT;
1542
1543 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1544
1545 bf->bf_keytype = get_hw_crypto_keytype(skb);
1546 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1547 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1548 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1549 } else {
1550 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1551 }
1552
1553 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR))
1554 assign_aggr_tid_seqno(skb, bf);
1555
1556 bf->bf_mpdu = skb;
1557
1558 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1559 skb->len, DMA_TO_DEVICE);
1560 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1561 bf->bf_mpdu = NULL;
1562 kfree(tx_info_priv);
1563 tx_info->rate_driver_data[0] = NULL;
1564 DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error() on TX\n");
1565 return -ENOMEM;
1566 }
1567
1568 bf->bf_buf_addr = bf->bf_dmacontext;
1569 return 0;
1570 }
1571
1572 /* FIXME: tx power */
1573 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1574 struct ath_tx_control *txctl)
1575 {
1576 struct sk_buff *skb = bf->bf_mpdu;
1577 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1578 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1579 struct ath_node *an = NULL;
1580 struct list_head bf_head;
1581 struct ath_desc *ds;
1582 struct ath_atx_tid *tid;
1583 struct ath_hw *ah = sc->sc_ah;
1584 int frm_type;
1585 __le16 fc;
1586
1587 frm_type = get_hw_packet_type(skb);
1588 fc = hdr->frame_control;
1589
1590 INIT_LIST_HEAD(&bf_head);
1591 list_add_tail(&bf->list, &bf_head);
1592
1593 ds = bf->bf_desc;
1594 ds->ds_link = 0;
1595 ds->ds_data = bf->bf_buf_addr;
1596
1597 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1598 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1599
1600 ath9k_hw_filltxdesc(ah, ds,
1601 skb->len, /* segment length */
1602 true, /* first segment */
1603 true, /* last segment */
1604 ds); /* first descriptor */
1605
1606 spin_lock_bh(&txctl->txq->axq_lock);
1607
1608 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1609 tx_info->control.sta) {
1610 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1611 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1612
1613 if (!ieee80211_is_data_qos(fc)) {
1614 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1615 goto tx_done;
1616 }
1617
1618 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1619 /*
1620 * Try aggregation if it's a unicast data frame
1621 * and the destination is HT capable.
1622 */
1623 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1624 } else {
1625 /*
1626 * Send this frame as regular when ADDBA
1627 * exchange is neither complete nor pending.
1628 */
1629 ath_tx_send_ht_normal(sc, txctl->txq,
1630 tid, &bf_head);
1631 }
1632 } else {
1633 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1634 }
1635
1636 tx_done:
1637 spin_unlock_bh(&txctl->txq->axq_lock);
1638 }
1639
1640 /* Upon failure caller should free skb */
1641 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1642 struct ath_tx_control *txctl)
1643 {
1644 struct ath_wiphy *aphy = hw->priv;
1645 struct ath_softc *sc = aphy->sc;
1646 struct ath_buf *bf;
1647 int r;
1648
1649 bf = ath_tx_get_buffer(sc);
1650 if (!bf) {
1651 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n");
1652 return -1;
1653 }
1654
1655 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1656 if (unlikely(r)) {
1657 struct ath_txq *txq = txctl->txq;
1658
1659 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n");
1660
1661 /* upon ath_tx_processq() this TX queue will be resumed, we
1662 * guarantee this will happen by knowing beforehand that
1663 * we will at least have to run TX completionon one buffer
1664 * on the queue */
1665 spin_lock_bh(&txq->axq_lock);
1666 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1667 ieee80211_stop_queue(sc->hw,
1668 skb_get_queue_mapping(skb));
1669 txq->stopped = 1;
1670 }
1671 spin_unlock_bh(&txq->axq_lock);
1672
1673 spin_lock_bh(&sc->tx.txbuflock);
1674 list_add_tail(&bf->list, &sc->tx.txbuf);
1675 spin_unlock_bh(&sc->tx.txbuflock);
1676
1677 return r;
1678 }
1679
1680 ath_tx_start_dma(sc, bf, txctl);
1681
1682 return 0;
1683 }
1684
1685 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1686 {
1687 struct ath_wiphy *aphy = hw->priv;
1688 struct ath_softc *sc = aphy->sc;
1689 int hdrlen, padsize;
1690 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1691 struct ath_tx_control txctl;
1692
1693 memset(&txctl, 0, sizeof(struct ath_tx_control));
1694
1695 /*
1696 * As a temporary workaround, assign seq# here; this will likely need
1697 * to be cleaned up to work better with Beacon transmission and virtual
1698 * BSSes.
1699 */
1700 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1701 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1702 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1703 sc->tx.seq_no += 0x10;
1704 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1705 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1706 }
1707
1708 /* Add the padding after the header if this is not already done */
1709 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1710 if (hdrlen & 3) {
1711 padsize = hdrlen % 4;
1712 if (skb_headroom(skb) < padsize) {
1713 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n");
1714 dev_kfree_skb_any(skb);
1715 return;
1716 }
1717 skb_push(skb, padsize);
1718 memmove(skb->data, skb->data + padsize, hdrlen);
1719 }
1720
1721 txctl.txq = sc->beacon.cabq;
1722
1723 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
1724
1725 if (ath_tx_start(hw, skb, &txctl) != 0) {
1726 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n");
1727 goto exit;
1728 }
1729
1730 return;
1731 exit:
1732 dev_kfree_skb_any(skb);
1733 }
1734
1735 /*****************/
1736 /* TX Completion */
1737 /*****************/
1738
1739 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1740 int tx_flags)
1741 {
1742 struct ieee80211_hw *hw = sc->hw;
1743 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1744 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1745 int hdrlen, padsize;
1746 int frame_type = ATH9K_NOT_INTERNAL;
1747
1748 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1749
1750 if (tx_info_priv) {
1751 hw = tx_info_priv->aphy->hw;
1752 frame_type = tx_info_priv->frame_type;
1753 }
1754
1755 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
1756 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
1757 kfree(tx_info_priv);
1758 tx_info->rate_driver_data[0] = NULL;
1759 }
1760
1761 if (tx_flags & ATH_TX_BAR)
1762 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1763
1764 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1765 /* Frame was ACKed */
1766 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1767 }
1768
1769 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1770 padsize = hdrlen & 3;
1771 if (padsize && hdrlen >= 24) {
1772 /*
1773 * Remove MAC header padding before giving the frame back to
1774 * mac80211.
1775 */
1776 memmove(skb->data + padsize, skb->data, hdrlen);
1777 skb_pull(skb, padsize);
1778 }
1779
1780 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) {
1781 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK;
1782 DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having "
1783 "received TX status (0x%x)\n",
1784 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
1785 SC_OP_WAIT_FOR_CAB |
1786 SC_OP_WAIT_FOR_PSPOLL_DATA |
1787 SC_OP_WAIT_FOR_TX_ACK));
1788 }
1789
1790 if (frame_type == ATH9K_NOT_INTERNAL)
1791 ieee80211_tx_status(hw, skb);
1792 else
1793 ath9k_tx_status(hw, skb);
1794 }
1795
1796 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1797 struct list_head *bf_q,
1798 int txok, int sendbar)
1799 {
1800 struct sk_buff *skb = bf->bf_mpdu;
1801 unsigned long flags;
1802 int tx_flags = 0;
1803
1804
1805 if (sendbar)
1806 tx_flags = ATH_TX_BAR;
1807
1808 if (!txok) {
1809 tx_flags |= ATH_TX_ERROR;
1810
1811 if (bf_isxretried(bf))
1812 tx_flags |= ATH_TX_XRETRY;
1813 }
1814
1815 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1816 ath_tx_complete(sc, skb, tx_flags);
1817
1818 /*
1819 * Return the list of ath_buf of this mpdu to free queue
1820 */
1821 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1822 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1823 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1824 }
1825
1826 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1827 int txok)
1828 {
1829 struct ath_buf *bf_last = bf->bf_lastbf;
1830 struct ath_desc *ds = bf_last->bf_desc;
1831 u16 seq_st = 0;
1832 u32 ba[WME_BA_BMP_SIZE >> 5];
1833 int ba_index;
1834 int nbad = 0;
1835 int isaggr = 0;
1836
1837 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
1838 return 0;
1839
1840 isaggr = bf_isaggr(bf);
1841 if (isaggr) {
1842 seq_st = ATH_DS_BA_SEQ(ds);
1843 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
1844 }
1845
1846 while (bf) {
1847 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1848 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1849 nbad++;
1850
1851 bf = bf->bf_next;
1852 }
1853
1854 return nbad;
1855 }
1856
1857 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1858 int nbad, int txok, bool update_rc)
1859 {
1860 struct sk_buff *skb = bf->bf_mpdu;
1861 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1862 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1863 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1864 struct ieee80211_hw *hw = tx_info_priv->aphy->hw;
1865 u8 i, tx_rateindex;
1866
1867 if (txok)
1868 tx_info->status.ack_signal = ds->ds_txstat.ts_rssi;
1869
1870 tx_rateindex = ds->ds_txstat.ts_rateindex;
1871 WARN_ON(tx_rateindex >= hw->max_rates);
1872
1873 tx_info_priv->update_rc = update_rc;
1874 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1875 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1876
1877 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1878 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1879 if (ieee80211_is_data(hdr->frame_control)) {
1880 memcpy(&tx_info_priv->tx, &ds->ds_txstat,
1881 sizeof(tx_info_priv->tx));
1882 tx_info_priv->n_frames = bf->bf_nframes;
1883 tx_info_priv->n_bad_frames = nbad;
1884 }
1885 }
1886
1887 for (i = tx_rateindex + 1; i < hw->max_rates; i++)
1888 tx_info->status.rates[i].count = 0;
1889
1890 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
1891 }
1892
1893 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1894 {
1895 int qnum;
1896
1897 spin_lock_bh(&txq->axq_lock);
1898 if (txq->stopped &&
1899 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1900 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1901 if (qnum != -1) {
1902 ieee80211_wake_queue(sc->hw, qnum);
1903 txq->stopped = 0;
1904 }
1905 }
1906 spin_unlock_bh(&txq->axq_lock);
1907 }
1908
1909 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1910 {
1911 struct ath_hw *ah = sc->sc_ah;
1912 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1913 struct list_head bf_head;
1914 struct ath_desc *ds;
1915 int txok;
1916 int status;
1917
1918 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1919 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1920 txq->axq_link);
1921
1922 for (;;) {
1923 spin_lock_bh(&txq->axq_lock);
1924 if (list_empty(&txq->axq_q)) {
1925 txq->axq_link = NULL;
1926 txq->axq_linkbuf = NULL;
1927 spin_unlock_bh(&txq->axq_lock);
1928 break;
1929 }
1930 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1931
1932 /*
1933 * There is a race condition that a BH gets scheduled
1934 * after sw writes TxE and before hw re-load the last
1935 * descriptor to get the newly chained one.
1936 * Software must keep the last DONE descriptor as a
1937 * holding descriptor - software does so by marking
1938 * it with the STALE flag.
1939 */
1940 bf_held = NULL;
1941 if (bf->bf_stale) {
1942 bf_held = bf;
1943 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1944 txq->axq_link = NULL;
1945 txq->axq_linkbuf = NULL;
1946 spin_unlock_bh(&txq->axq_lock);
1947
1948 /*
1949 * The holding descriptor is the last
1950 * descriptor in queue. It's safe to remove
1951 * the last holding descriptor in BH context.
1952 */
1953 spin_lock_bh(&sc->tx.txbuflock);
1954 list_move_tail(&bf_held->list, &sc->tx.txbuf);
1955 spin_unlock_bh(&sc->tx.txbuflock);
1956
1957 break;
1958 } else {
1959 bf = list_entry(bf_held->list.next,
1960 struct ath_buf, list);
1961 }
1962 }
1963
1964 lastbf = bf->bf_lastbf;
1965 ds = lastbf->bf_desc;
1966
1967 status = ath9k_hw_txprocdesc(ah, ds);
1968 if (status == -EINPROGRESS) {
1969 spin_unlock_bh(&txq->axq_lock);
1970 break;
1971 }
1972 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1973 txq->axq_lastdsWithCTS = NULL;
1974 if (ds == txq->axq_gatingds)
1975 txq->axq_gatingds = NULL;
1976
1977 /*
1978 * Remove ath_buf's of the same transmit unit from txq,
1979 * however leave the last descriptor back as the holding
1980 * descriptor for hw.
1981 */
1982 lastbf->bf_stale = true;
1983 INIT_LIST_HEAD(&bf_head);
1984 if (!list_is_singular(&lastbf->list))
1985 list_cut_position(&bf_head,
1986 &txq->axq_q, lastbf->list.prev);
1987
1988 txq->axq_depth--;
1989 if (bf_isaggr(bf))
1990 txq->axq_aggr_depth--;
1991
1992 txok = (ds->ds_txstat.ts_status == 0);
1993 spin_unlock_bh(&txq->axq_lock);
1994
1995 if (bf_held) {
1996 spin_lock_bh(&sc->tx.txbuflock);
1997 list_move_tail(&bf_held->list, &sc->tx.txbuf);
1998 spin_unlock_bh(&sc->tx.txbuflock);
1999 }
2000
2001 if (!bf_isampdu(bf)) {
2002 /*
2003 * This frame is sent out as a single frame.
2004 * Use hardware retry status for this frame.
2005 */
2006 bf->bf_retries = ds->ds_txstat.ts_longretry;
2007 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
2008 bf->bf_state.bf_type |= BUF_XRETRY;
2009 ath_tx_rc_status(bf, ds, 0, txok, true);
2010 }
2011
2012 if (bf_isampdu(bf))
2013 ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok);
2014 else
2015 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
2016
2017 ath_wake_mac80211_queue(sc, txq);
2018
2019 spin_lock_bh(&txq->axq_lock);
2020 if (sc->sc_flags & SC_OP_TXAGGR)
2021 ath_txq_schedule(sc, txq);
2022 spin_unlock_bh(&txq->axq_lock);
2023 }
2024 }
2025
2026
2027 void ath_tx_tasklet(struct ath_softc *sc)
2028 {
2029 int i;
2030 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2031
2032 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2033
2034 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2035 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2036 ath_tx_processq(sc, &sc->tx.txq[i]);
2037 }
2038 }
2039
2040 /*****************/
2041 /* Init, Cleanup */
2042 /*****************/
2043
2044 int ath_tx_init(struct ath_softc *sc, int nbufs)
2045 {
2046 int error = 0;
2047
2048 spin_lock_init(&sc->tx.txbuflock);
2049
2050 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2051 "tx", nbufs, 1);
2052 if (error != 0) {
2053 DPRINTF(sc, ATH_DBG_FATAL,
2054 "Failed to allocate tx descriptors: %d\n", error);
2055 goto err;
2056 }
2057
2058 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2059 "beacon", ATH_BCBUF, 1);
2060 if (error != 0) {
2061 DPRINTF(sc, ATH_DBG_FATAL,
2062 "Failed to allocate beacon descriptors: %d\n", error);
2063 goto err;
2064 }
2065
2066 err:
2067 if (error != 0)
2068 ath_tx_cleanup(sc);
2069
2070 return error;
2071 }
2072
2073 void ath_tx_cleanup(struct ath_softc *sc)
2074 {
2075 if (sc->beacon.bdma.dd_desc_len != 0)
2076 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2077
2078 if (sc->tx.txdma.dd_desc_len != 0)
2079 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2080 }
2081
2082 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2083 {
2084 struct ath_atx_tid *tid;
2085 struct ath_atx_ac *ac;
2086 int tidno, acno;
2087
2088 for (tidno = 0, tid = &an->tid[tidno];
2089 tidno < WME_NUM_TID;
2090 tidno++, tid++) {
2091 tid->an = an;
2092 tid->tidno = tidno;
2093 tid->seq_start = tid->seq_next = 0;
2094 tid->baw_size = WME_MAX_BA;
2095 tid->baw_head = tid->baw_tail = 0;
2096 tid->sched = false;
2097 tid->paused = false;
2098 tid->state &= ~AGGR_CLEANUP;
2099 INIT_LIST_HEAD(&tid->buf_q);
2100 acno = TID_TO_WME_AC(tidno);
2101 tid->ac = &an->ac[acno];
2102 tid->state &= ~AGGR_ADDBA_COMPLETE;
2103 tid->state &= ~AGGR_ADDBA_PROGRESS;
2104 }
2105
2106 for (acno = 0, ac = &an->ac[acno];
2107 acno < WME_NUM_AC; acno++, ac++) {
2108 ac->sched = false;
2109 INIT_LIST_HEAD(&ac->tid_q);
2110
2111 switch (acno) {
2112 case WME_AC_BE:
2113 ac->qnum = ath_tx_get_qnum(sc,
2114 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2115 break;
2116 case WME_AC_BK:
2117 ac->qnum = ath_tx_get_qnum(sc,
2118 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2119 break;
2120 case WME_AC_VI:
2121 ac->qnum = ath_tx_get_qnum(sc,
2122 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2123 break;
2124 case WME_AC_VO:
2125 ac->qnum = ath_tx_get_qnum(sc,
2126 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2127 break;
2128 }
2129 }
2130 }
2131
2132 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2133 {
2134 int i;
2135 struct ath_atx_ac *ac, *ac_tmp;
2136 struct ath_atx_tid *tid, *tid_tmp;
2137 struct ath_txq *txq;
2138
2139 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2140 if (ATH_TXQ_SETUP(sc, i)) {
2141 txq = &sc->tx.txq[i];
2142
2143 spin_lock(&txq->axq_lock);
2144
2145 list_for_each_entry_safe(ac,
2146 ac_tmp, &txq->axq_acq, list) {
2147 tid = list_first_entry(&ac->tid_q,
2148 struct ath_atx_tid, list);
2149 if (tid && tid->an != an)
2150 continue;
2151 list_del(&ac->list);
2152 ac->sched = false;
2153
2154 list_for_each_entry_safe(tid,
2155 tid_tmp, &ac->tid_q, list) {
2156 list_del(&tid->list);
2157 tid->sched = false;
2158 ath_tid_drain(sc, txq, tid);
2159 tid->state &= ~AGGR_ADDBA_COMPLETE;
2160 tid->state &= ~AGGR_CLEANUP;
2161 }
2162 }
2163
2164 spin_unlock(&txq->axq_lock);
2165 }
2166 }
2167 }
Support for the Chinese Samsung S3C2440 based development boards