include/asm-powerpc/mmu-hash64.h

   1 #ifndef _ASM_POWERPC_MMU_HASH64_H_
   2 #define _ASM_POWERPC_MMU_HASH64_H_
   3 /*
   4  * PowerPC64 memory management structures
   5  *
   6  * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
   7  *   PPC64 rework.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14
  15 #include <asm/asm-compat.h>
  16 #include <asm/page.h>
  17
  18 /*
  19  * Segment table
  20  */
  21
  22 #define STE_ESID_V      0x80
  23 #define STE_ESID_KS     0x20
  24 #define STE_ESID_KP     0x10
  25 #define STE_ESID_N      0x08
  26
  27 #define STE_VSID_SHIFT  12
  28
  29 /* Location of cpu0's segment table */
  30 #define STAB0_PAGE      0x6
  31 #define STAB0_OFFSET    (STAB0_PAGE << 12)
  32 #define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
  33
  34 #ifndef __ASSEMBLY__
  35 extern char initial_stab[];
  36 #endif /* ! __ASSEMBLY */
  37
  38 /*
  39  * SLB
  40  */
  41
  42 #define SLB_NUM_BOLTED          3
  43 #define SLB_CACHE_ENTRIES       8
  44
  45 /* Bits in the SLB ESID word */
  46 #define SLB_ESID_V              ASM_CONST(0x0000000008000000) /* valid */
  47
  48 /* Bits in the SLB VSID word */
  49 #define SLB_VSID_SHIFT          12
  50 #define SLB_VSID_B              ASM_CONST(0xc000000000000000)
  51 #define SLB_VSID_B_256M         ASM_CONST(0x0000000000000000)
  52 #define SLB_VSID_B_1T           ASM_CONST(0x4000000000000000)
  53 #define SLB_VSID_KS             ASM_CONST(0x0000000000000800)
  54 #define SLB_VSID_KP             ASM_CONST(0x0000000000000400)
  55 #define SLB_VSID_N              ASM_CONST(0x0000000000000200) /* no-execute */
  56 #define SLB_VSID_L              ASM_CONST(0x0000000000000100)
  57 #define SLB_VSID_C              ASM_CONST(0x0000000000000080) /* class */
  58 #define SLB_VSID_LP             ASM_CONST(0x0000000000000030)
  59 #define SLB_VSID_LP_00          ASM_CONST(0x0000000000000000)
  60 #define SLB_VSID_LP_01          ASM_CONST(0x0000000000000010)
  61 #define SLB_VSID_LP_10          ASM_CONST(0x0000000000000020)
  62 #define SLB_VSID_LP_11          ASM_CONST(0x0000000000000030)
  63 #define SLB_VSID_LLP            (SLB_VSID_L|SLB_VSID_LP)
  64
  65 #define SLB_VSID_KERNEL         (SLB_VSID_KP)
  66 #define SLB_VSID_USER           (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
  67
  68 #define SLBIE_C                 (0x08000000)
  69
  70 /*
  71  * Hash table
  72  */
  73
  74 #define HPTES_PER_GROUP 8
  75
  76 #define HPTE_V_SSIZE_SHIFT      62
  77 #define HPTE_V_AVPN_SHIFT       7
  78 #define HPTE_V_AVPN             ASM_CONST(0x3fffffffffffff80)
  79 #define HPTE_V_AVPN_VAL(x)      (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
  80 #define HPTE_V_COMPARE(x,y)     (!(((x) ^ (y)) & HPTE_V_AVPN))
  81 #define HPTE_V_BOLTED           ASM_CONST(0x0000000000000010)
  82 #define HPTE_V_LOCK             ASM_CONST(0x0000000000000008)
  83 #define HPTE_V_LARGE            ASM_CONST(0x0000000000000004)
  84 #define HPTE_V_SECONDARY        ASM_CONST(0x0000000000000002)
  85 #define HPTE_V_VALID            ASM_CONST(0x0000000000000001)
  86
  87 #define HPTE_R_PP0              ASM_CONST(0x8000000000000000)
  88 #define HPTE_R_TS               ASM_CONST(0x4000000000000000)
  89 #define HPTE_R_RPN_SHIFT        12
  90 #define HPTE_R_RPN              ASM_CONST(0x3ffffffffffff000)
  91 #define HPTE_R_FLAGS            ASM_CONST(0x00000000000003ff)
  92 #define HPTE_R_PP               ASM_CONST(0x0000000000000003)
  93 #define HPTE_R_N                ASM_CONST(0x0000000000000004)
  94 #define HPTE_R_C                ASM_CONST(0x0000000000000080)
  95 #define HPTE_R_R                ASM_CONST(0x0000000000000100)
  96
  97 /* Values for PP (assumes Ks=0, Kp=1) */
  98 /* pp0 will always be 0 for linux     */
  99 #define PP_RWXX 0       /* Supervisor read/write, User none */
 100 #define PP_RWRX 1       /* Supervisor read/write, User read */
 101 #define PP_RWRW 2       /* Supervisor read/write, User read/write */
 102 #define PP_RXRX 3       /* Supervisor read,       User read */
 103
 104 #ifndef __ASSEMBLY__
 105
 106 typedef struct {
 107         unsigned long v;
 108         unsigned long r;
 109 } hpte_t;
 110
 111 extern hpte_t *htab_address;
 112 extern unsigned long htab_size_bytes;
 113 extern unsigned long htab_hash_mask;
 114
 115 /*
 116  * Page size definition
 117  *
 118  *    shift : is the "PAGE_SHIFT" value for that page size
 119  *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
 120  *            directly to a slbmte "vsid" value
 121  *    penc  : is the HPTE encoding mask for the "LP" field:
 122  *
 123  */
 124 struct mmu_psize_def
 125 {
 126         unsigned int    shift;  /* number of bits */
 127         unsigned int    penc;   /* HPTE encoding */
 128         unsigned int    tlbiel; /* tlbiel supported for that page size */
 129         unsigned long   avpnm;  /* bits to mask out in AVPN in the HPTE */
 130         unsigned long   sllp;   /* SLB L||LP (exact mask to use in slbmte) */
 131 };
 132
 133 #endif /* __ASSEMBLY__ */
 134
 135 /*
 136  * The kernel use the constants below to index in the page sizes array.
 137  * The use of fixed constants for this purpose is better for performances
 138  * of the low level hash refill handlers.
 139  *
 140  * A non supported page size has a "shift" field set to 0
 141  *
 142  * Any new page size being implemented can get a new entry in here. Whether
 143  * the kernel will use it or not is a different matter though. The actual page
 144  * size used by hugetlbfs is not defined here and may be made variable
 145  */
 146
 147 #define MMU_PAGE_4K             0       /* 4K */
 148 #define MMU_PAGE_64K            1       /* 64K */
 149 #define MMU_PAGE_64K_AP         2       /* 64K Admixed (in a 4K segment) */
 150 #define MMU_PAGE_1M             3       /* 1M */
 151 #define MMU_PAGE_16M            4       /* 16M */
 152 #define MMU_PAGE_16G            5       /* 16G */
 153 #define MMU_PAGE_COUNT          6
 154
 155 /*
 156  * Segment sizes.
 157  * These are the values used by hardware in the B field of
 158  * SLB entries and the first dword of MMU hashtable entries.
 159  * The B field is 2 bits; the values 2 and 3 are unused and reserved.
 160  */
 161 #define MMU_SEGSIZE_256M        0
 162 #define MMU_SEGSIZE_1T          1
 163
 164 #ifndef __ASSEMBLY__
 165
 166 /*
 167  * The current system page sizes
 168  */
 169 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 170 extern int mmu_linear_psize;
 171 extern int mmu_virtual_psize;
 172 extern int mmu_vmalloc_psize;
 173 extern int mmu_io_psize;
 174
 175 /*
 176  * If the processor supports 64k normal pages but not 64k cache
 177  * inhibited pages, we have to be prepared to switch processes
 178  * to use 4k pages when they create cache-inhibited mappings.
 179  * If this is the case, mmu_ci_restrictions will be set to 1.
 180  */
 181 extern int mmu_ci_restrictions;
 182
 183 #ifdef CONFIG_HUGETLB_PAGE
 184 /*
 185  * The page size index of the huge pages for use by hugetlbfs
 186  */
 187 extern int mmu_huge_psize;
 188
 189 #endif /* CONFIG_HUGETLB_PAGE */
 190
 191 /*
 192  * This function sets the AVPN and L fields of the HPTE  appropriately
 193  * for the page size
 194  */
 195 static inline unsigned long hpte_encode_v(unsigned long va, int psize)
 196 {
 197         unsigned long v =
 198         v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
 199         v <<= HPTE_V_AVPN_SHIFT;
 200         if (psize != MMU_PAGE_4K)
 201                 v |= HPTE_V_LARGE;
 202         return v;
 203 }
 204
 205 /*
 206  * This function sets the ARPN, and LP fields of the HPTE appropriately
 207  * for the page size. We assume the pa is already "clean" that is properly
 208  * aligned for the requested page size
 209  */
 210 static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
 211 {
 212         unsigned long r;
 213
 214         /* A 4K page needs no special encoding */
 215         if (psize == MMU_PAGE_4K)
 216                 return pa & HPTE_R_RPN;
 217         else {
 218                 unsigned int penc = mmu_psize_defs[psize].penc;
 219                 unsigned int shift = mmu_psize_defs[psize].shift;
 220                 return (pa & ~((1ul << shift) - 1)) | (penc << 12);
 221         }
 222         return r;
 223 }
 224
 225 /*
 226  * This hashes a virtual address for a 256Mb segment only for now
 227  */
 228
 229 static inline unsigned long hpt_hash(unsigned long va, unsigned int shift)
 230 {
 231         return ((va >> 28) & 0x7fffffffffUL) ^ ((va & 0x0fffffffUL) >> shift);
 232 }
 233
 234 extern int __hash_page_4K(unsigned long ea, unsigned long access,
 235                           unsigned long vsid, pte_t *ptep, unsigned long trap,
 236                           unsigned int local);
 237 extern int __hash_page_64K(unsigned long ea, unsigned long access,
 238                            unsigned long vsid, pte_t *ptep, unsigned long trap,
 239                            unsigned int local);
 240 struct mm_struct;
 241 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap);
 242 extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
 243                           unsigned long ea, unsigned long vsid, int local,
 244                           unsigned long trap);
 245
 246 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
 247                              unsigned long pstart, unsigned long mode,
 248                              int psize);
 249
 250 extern void htab_initialize(void);
 251 extern void htab_initialize_secondary(void);
 252 extern void hpte_init_native(void);
 253 extern void hpte_init_lpar(void);
 254 extern void hpte_init_iSeries(void);
 255 extern void hpte_init_beat(void);
 256
 257 extern void stabs_alloc(void);
 258 extern void slb_initialize(void);
 259 extern void slb_flush_and_rebolt(void);
 260 extern void stab_initialize(unsigned long stab);
 261
 262 #endif /* __ASSEMBLY__ */
 263
 264 /*
 265  * VSID allocation
 266  *
 267  * We first generate a 36-bit "proto-VSID".  For kernel addresses this
 268  * is equal to the ESID, for user addresses it is:
 269  *      (context << 15) | (esid & 0x7fff)
 270  *
 271  * The two forms are distinguishable because the top bit is 0 for user
 272  * addresses, whereas the top two bits are 1 for kernel addresses.
 273  * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
 274  * now.
 275  *
 276  * The proto-VSIDs are then scrambled into real VSIDs with the
 277  * multiplicative hash:
 278  *
 279  *      VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
 280  *      where   VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
 281  *              VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
 282  *
 283  * This scramble is only well defined for proto-VSIDs below
 284  * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
 285  * reserved.  VSID_MULTIPLIER is prime, so in particular it is
 286  * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
 287  * Because the modulus is 2^n-1 we can compute it efficiently without
 288  * a divide or extra multiply (see below).
 289  *
 290  * This scheme has several advantages over older methods:
 291  *
 292  *      - We have VSIDs allocated for every kernel address
 293  * (i.e. everything above 0xC000000000000000), except the very top
 294  * segment, which simplifies several things.
 295  *
 296  *      - We allow for 15 significant bits of ESID and 20 bits of
 297  * context for user addresses.  i.e. 8T (43 bits) of address space for
 298  * up to 1M contexts (although the page table structure and context
 299  * allocation will need changes to take advantage of this).
 300  *
 301  *      - The scramble function gives robust scattering in the hash
 302  * table (at least based on some initial results).  The previous
 303  * method was more susceptible to pathological cases giving excessive
 304  * hash collisions.
 305  */
 306 /*
 307  * WARNING - If you change these you must make sure the asm
 308  * implementations in slb_allocate (slb_low.S), do_stab_bolted
 309  * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
 310  *
 311  * You'll also need to change the precomputed VSID values in head.S
 312  * which are used by the iSeries firmware.
 313  */
 314
 315 #define VSID_MULTIPLIER ASM_CONST(200730139)    /* 28-bit prime */
 316 #define VSID_BITS       36
 317 #define VSID_MODULUS    ((1UL<<VSID_BITS)-1)
 318
 319 #define CONTEXT_BITS    19
 320 #define USER_ESID_BITS  16
 321
 322 #define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
 323
 324 /*
 325  * This macro generates asm code to compute the VSID scramble
 326  * function.  Used in slb_allocate() and do_stab_bolted.  The function
 327  * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
 328  *
 329  *      rt = register continaing the proto-VSID and into which the
 330  *              VSID will be stored
 331  *      rx = scratch register (clobbered)
 332  *
 333  *      - rt and rx must be different registers
 334  *      - The answer will end up in the low 36 bits of rt.  The higher
 335  *        bits may contain other garbage, so you may need to mask the
 336  *        result.
 337  */
 338 #define ASM_VSID_SCRAMBLE(rt, rx)       \
 339         lis     rx,VSID_MULTIPLIER@h;                                   \
 340         ori     rx,rx,VSID_MULTIPLIER@l;                                \
 341         mulld   rt,rt,rx;               /* rt = rt * MULTIPLIER */      \
 342                                                                         \
 343         srdi    rx,rt,VSID_BITS;                                        \
 344         clrldi  rt,rt,(64-VSID_BITS);                                   \
 345         add     rt,rt,rx;               /* add high and low bits */     \
 346         /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and         \
 347          * 2^36-1+2^28-1.  That in particular means that if r3 >=       \
 348          * 2^36-1, then r3+1 has the 2^36 bit set.  So, if r3+1 has     \
 349          * the bit clear, r3 already has the answer we want, if it      \
 350          * doesn't, the answer is the low 36 bits of r3+1.  So in all   \
 351          * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
 352         addi    rx,rt,1;                                                \
 353         srdi    rx,rx,VSID_BITS;        /* extract 2^36 bit */          \
 354         add     rt,rt,rx
 355
 356
 357 #ifndef __ASSEMBLY__
 358
 359 typedef unsigned long mm_context_id_t;
 360
 361 typedef struct {
 362         mm_context_id_t id;
 363         u16 user_psize;         /* page size index */
 364
 365 #ifdef CONFIG_PPC_MM_SLICES
 366         u64 low_slices_psize;   /* SLB page size encodings */
 367         u64 high_slices_psize;  /* 4 bits per slice for now */
 368 #else
 369         u16 sllp;               /* SLB page size encoding */
 370 #endif
 371         unsigned long vdso_base;
 372 } mm_context_t;
 373
 374
 375 static inline unsigned long vsid_scramble(unsigned long protovsid)
 376 {
 377 #if 0
 378         /* The code below is equivalent to this function for arguments
 379          * < 2^VSID_BITS, which is all this should ever be called
 380          * with.  However gcc is not clever enough to compute the
 381          * modulus (2^n-1) without a second multiply. */
 382         return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS);
 383 #else /* 1 */
 384         unsigned long x;
 385
 386         x = protovsid * VSID_MULTIPLIER;
 387         x = (x >> VSID_BITS) + (x & VSID_MODULUS);
 388         return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS;
 389 #endif /* 1 */
 390 }
 391
 392 /* This is only valid for addresses >= KERNELBASE */
 393 static inline unsigned long get_kernel_vsid(unsigned long ea)
 394 {
 395         return vsid_scramble(ea >> SID_SHIFT);
 396 }
 397
 398 /* This is only valid for user addresses (which are below 2^41) */
 399 static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
 400 {
 401         return vsid_scramble((context << USER_ESID_BITS)
 402                              | (ea >> SID_SHIFT));
 403 }
 404
 405 #define VSID_SCRAMBLE(pvsid)    (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS)
 406 #define KERNEL_VSID(ea)         VSID_SCRAMBLE(GET_ESID(ea))
 407
 408 /* Physical address used by some IO functions */
 409 typedef unsigned long phys_addr_t;
 410
 411 #endif /* __ASSEMBLY__ */
 412
 413 #endif /* _ASM_POWERPC_MMU_HASH64_H_ */