2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
34 #include <asm/atomic.h>
37 #include <asm/mpspec.h>
39 #include <asm/arch_hooks.h>
41 #include <asm/pgalloc.h>
42 #include <asm/i8253.h>
45 #include <asm/proto.h>
46 #include <asm/timex.h>
48 #include <asm/i8259.h>
50 #include <mach_apic.h>
51 #include <mach_apicdef.h>
57 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
58 # error SPURIOUS_APIC_VECTOR definition error
63 * Knob to control our willingness to enable the local APIC.
67 static int force_enable_local_apic
;
69 * APIC command line parameters
71 static int __init
parse_lapic(char *arg
)
73 force_enable_local_apic
= 1;
76 early_param("lapic", parse_lapic
);
77 /* Local APIC was disabled by the BIOS and enabled by the kernel */
78 static int enabled_via_apicbase
;
83 static int apic_calibrate_pmtmr __initdata
;
84 static __init
int setup_apicpmtimer(char *s
)
86 apic_calibrate_pmtmr
= 1;
90 __setup("apicpmtimer", setup_apicpmtimer
);
99 /* x2apic enabled before OS handover */
100 int x2apic_preenabled
;
102 static __init
int setup_nox2apic(char *str
)
105 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
108 early_param("nox2apic", setup_nox2apic
);
111 unsigned long mp_lapic_addr
;
113 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
114 static int disable_apic_timer __cpuinitdata
;
115 /* Local APIC timer works in C2 */
116 int local_apic_timer_c2_ok
;
117 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
119 int first_system_vector
= 0xfe;
121 char system_vectors
[NR_VECTORS
] = { [0 ... NR_VECTORS
-1] = SYS_VECTOR_FREE
};
124 * Debug level, exported for io_apic.c
126 unsigned int apic_verbosity
;
130 /* Have we found an MP table */
131 int smp_found_config
;
133 static struct resource lapic_resource
= {
134 .name
= "Local APIC",
135 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
138 static unsigned int calibration_result
;
140 static int lapic_next_event(unsigned long delta
,
141 struct clock_event_device
*evt
);
142 static void lapic_timer_setup(enum clock_event_mode mode
,
143 struct clock_event_device
*evt
);
144 static void lapic_timer_broadcast(cpumask_t mask
);
145 static void apic_pm_activate(void);
148 * The local apic timer can be used for any function which is CPU local.
150 static struct clock_event_device lapic_clockevent
= {
152 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
153 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
155 .set_mode
= lapic_timer_setup
,
156 .set_next_event
= lapic_next_event
,
157 .broadcast
= lapic_timer_broadcast
,
161 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
163 static unsigned long apic_phys
;
166 * Get the LAPIC version
168 static inline int lapic_get_version(void)
170 return GET_APIC_VERSION(apic_read(APIC_LVR
));
174 * Check, if the APIC is integrated or a separate chip
176 static inline int lapic_is_integrated(void)
181 return APIC_INTEGRATED(lapic_get_version());
186 * Check, whether this is a modern or a first generation APIC
188 static int modern_apic(void)
190 /* AMD systems use old APIC versions, so check the CPU */
191 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
192 boot_cpu_data
.x86
>= 0xf)
194 return lapic_get_version() >= 0x14;
198 * Paravirt kernels also might be using these below ops. So we still
199 * use generic apic_read()/apic_write(), which might be pointing to different
200 * ops in PARAVIRT case.
202 void xapic_wait_icr_idle(void)
204 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
208 u32
safe_xapic_wait_icr_idle(void)
215 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
219 } while (timeout
++ < 1000);
224 void xapic_icr_write(u32 low
, u32 id
)
226 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
227 apic_write(APIC_ICR
, low
);
230 u64
xapic_icr_read(void)
234 icr2
= apic_read(APIC_ICR2
);
235 icr1
= apic_read(APIC_ICR
);
237 return icr1
| ((u64
)icr2
<< 32);
240 static struct apic_ops xapic_ops
= {
241 .read
= native_apic_mem_read
,
242 .write
= native_apic_mem_write
,
243 .icr_read
= xapic_icr_read
,
244 .icr_write
= xapic_icr_write
,
245 .wait_icr_idle
= xapic_wait_icr_idle
,
246 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
249 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
250 EXPORT_SYMBOL_GPL(apic_ops
);
253 static void x2apic_wait_icr_idle(void)
255 /* no need to wait for icr idle in x2apic */
259 static u32
safe_x2apic_wait_icr_idle(void)
261 /* no need to wait for icr idle in x2apic */
265 void x2apic_icr_write(u32 low
, u32 id
)
267 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
270 u64
x2apic_icr_read(void)
274 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
278 static struct apic_ops x2apic_ops
= {
279 .read
= native_apic_msr_read
,
280 .write
= native_apic_msr_write
,
281 .icr_read
= x2apic_icr_read
,
282 .icr_write
= x2apic_icr_write
,
283 .wait_icr_idle
= x2apic_wait_icr_idle
,
284 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
289 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
291 void __cpuinit
enable_NMI_through_LVT0(void)
295 /* unmask and set to NMI */
298 /* Level triggered for 82489DX (32bit mode) */
299 if (!lapic_is_integrated())
300 v
|= APIC_LVT_LEVEL_TRIGGER
;
302 apic_write(APIC_LVT0
, v
);
307 * get_physical_broadcast - Get number of physical broadcast IDs
309 int get_physical_broadcast(void)
311 return modern_apic() ? 0xff : 0xf;
316 * lapic_get_maxlvt - get the maximum number of local vector table entries
318 int lapic_get_maxlvt(void)
322 v
= apic_read(APIC_LVR
);
324 * - we always have APIC integrated on 64bit mode
325 * - 82489DXs do not report # of LVT entries
327 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
335 #define APIC_DIVISOR 16
338 * This function sets up the local APIC timer, with a timeout of
339 * 'clocks' APIC bus clock. During calibration we actually call
340 * this function twice on the boot CPU, once with a bogus timeout
341 * value, second time for real. The other (noncalibrating) CPUs
342 * call this function only once, with the real, calibrated value.
344 * We do reads before writes even if unnecessary, to get around the
345 * P5 APIC double write bug.
347 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
349 unsigned int lvtt_value
, tmp_value
;
351 lvtt_value
= LOCAL_TIMER_VECTOR
;
353 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
354 if (!lapic_is_integrated())
355 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
358 lvtt_value
|= APIC_LVT_MASKED
;
360 apic_write(APIC_LVTT
, lvtt_value
);
365 tmp_value
= apic_read(APIC_TDCR
);
366 apic_write(APIC_TDCR
,
367 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
371 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
375 * Setup extended LVT, AMD specific (K8, family 10h)
377 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
378 * MCE interrupts are supported. Thus MCE offset must be set to 0.
380 * If mask=1, the LVT entry does not generate interrupts while mask=0
381 * enables the vector. See also the BKDGs.
384 #define APIC_EILVT_LVTOFF_MCE 0
385 #define APIC_EILVT_LVTOFF_IBS 1
387 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
389 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
390 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
395 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
397 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
398 return APIC_EILVT_LVTOFF_MCE
;
401 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
403 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
404 return APIC_EILVT_LVTOFF_IBS
;
406 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
409 * Program the next event, relative to now
411 static int lapic_next_event(unsigned long delta
,
412 struct clock_event_device
*evt
)
414 apic_write(APIC_TMICT
, delta
);
419 * Setup the lapic timer in periodic or oneshot mode
421 static void lapic_timer_setup(enum clock_event_mode mode
,
422 struct clock_event_device
*evt
)
427 /* Lapic used as dummy for broadcast ? */
428 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
431 local_irq_save(flags
);
434 case CLOCK_EVT_MODE_PERIODIC
:
435 case CLOCK_EVT_MODE_ONESHOT
:
436 __setup_APIC_LVTT(calibration_result
,
437 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
439 case CLOCK_EVT_MODE_UNUSED
:
440 case CLOCK_EVT_MODE_SHUTDOWN
:
441 v
= apic_read(APIC_LVTT
);
442 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
443 apic_write(APIC_LVTT
, v
);
444 apic_write(APIC_TMICT
, 0xffffffff);
446 case CLOCK_EVT_MODE_RESUME
:
447 /* Nothing to do here */
451 local_irq_restore(flags
);
455 * Local APIC timer broadcast function
457 static void lapic_timer_broadcast(cpumask_t mask
)
460 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
465 * Setup the local APIC timer for this CPU. Copy the initilized values
466 * of the boot CPU and register the clock event in the framework.
468 static void __cpuinit
setup_APIC_timer(void)
470 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
472 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
473 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
475 clockevents_register_device(levt
);
479 * In this functions we calibrate APIC bus clocks to the external timer.
481 * We want to do the calibration only once since we want to have local timer
482 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
485 * This was previously done by reading the PIT/HPET and waiting for a wrap
486 * around to find out, that a tick has elapsed. I have a box, where the PIT
487 * readout is broken, so it never gets out of the wait loop again. This was
488 * also reported by others.
490 * Monitoring the jiffies value is inaccurate and the clockevents
491 * infrastructure allows us to do a simple substitution of the interrupt
494 * The calibration routine also uses the pm_timer when possible, as the PIT
495 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
496 * back to normal later in the boot process).
499 #define LAPIC_CAL_LOOPS (HZ/10)
501 static __initdata
int lapic_cal_loops
= -1;
502 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
503 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
504 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
505 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
508 * Temporary interrupt handler.
510 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
512 unsigned long long tsc
= 0;
513 long tapic
= apic_read(APIC_TMCCT
);
514 unsigned long pm
= acpi_pm_read_early();
519 switch (lapic_cal_loops
++) {
521 lapic_cal_t1
= tapic
;
522 lapic_cal_tsc1
= tsc
;
524 lapic_cal_j1
= jiffies
;
527 case LAPIC_CAL_LOOPS
:
528 lapic_cal_t2
= tapic
;
529 lapic_cal_tsc2
= tsc
;
530 if (pm
< lapic_cal_pm1
)
531 pm
+= ACPI_PM_OVRRUN
;
533 lapic_cal_j2
= jiffies
;
538 static int __init
calibrate_by_pmtimer(long deltapm
, long *delta
)
540 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
541 const long pm_thresh
= pm_100ms
/ 100;
545 #ifndef CONFIG_X86_PM_TIMER
549 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
551 /* Check, if the PM timer is available */
555 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
557 if (deltapm
> (pm_100ms
- pm_thresh
) &&
558 deltapm
< (pm_100ms
+ pm_thresh
)) {
559 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
561 res
= (((u64
)deltapm
) * mult
) >> 22;
562 do_div(res
, 1000000);
563 pr_warning("APIC calibration not consistent "
564 "with PM Timer: %ldms instead of 100ms\n",
566 /* Correct the lapic counter value */
567 res
= (((u64
)(*delta
)) * pm_100ms
);
568 do_div(res
, deltapm
);
569 pr_info("APIC delta adjusted to PM-Timer: "
570 "%lu (%ld)\n", (unsigned long)res
, *delta
);
577 static int __init
calibrate_APIC_clock(void)
579 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
580 void (*real_handler
)(struct clock_event_device
*dev
);
581 unsigned long deltaj
;
583 int pm_referenced
= 0;
587 /* Replace the global interrupt handler */
588 real_handler
= global_clock_event
->event_handler
;
589 global_clock_event
->event_handler
= lapic_cal_handler
;
592 * Setup the APIC counter to maximum. There is no way the lapic
593 * can underflow in the 100ms detection time frame
595 __setup_APIC_LVTT(0xffffffff, 0, 0);
597 /* Let the interrupts run */
600 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
605 /* Restore the real event handler */
606 global_clock_event
->event_handler
= real_handler
;
608 /* Build delta t1-t2 as apic timer counts down */
609 delta
= lapic_cal_t1
- lapic_cal_t2
;
610 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
612 /* we trust the PM based calibration if possible */
613 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
616 /* Calculate the scaled math multiplication factor */
617 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
618 lapic_clockevent
.shift
);
619 lapic_clockevent
.max_delta_ns
=
620 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
621 lapic_clockevent
.min_delta_ns
=
622 clockevent_delta2ns(0xF, &lapic_clockevent
);
624 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
626 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
627 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
628 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
632 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
633 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
635 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
636 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
639 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
641 calibration_result
/ (1000000 / HZ
),
642 calibration_result
% (1000000 / HZ
));
645 * Do a sanity check on the APIC calibration result
647 if (calibration_result
< (1000000 / HZ
)) {
649 pr_warning("APIC frequency too slow, disabling apic timer\n");
653 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
656 * PM timer calibration failed or not turned on
657 * so lets try APIC timer based calibration
659 if (!pm_referenced
) {
660 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
663 * Setup the apic timer manually
665 levt
->event_handler
= lapic_cal_handler
;
666 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
667 lapic_cal_loops
= -1;
669 /* Let the interrupts run */
672 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
675 /* Stop the lapic timer */
676 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
679 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
680 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
682 /* Check, if the jiffies result is consistent */
683 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
684 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
686 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
690 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
691 pr_warning("APIC timer disabled due to verification failure.\n");
699 * Setup the boot APIC
701 * Calibrate and verify the result.
703 void __init
setup_boot_APIC_clock(void)
706 * The local apic timer can be disabled via the kernel
707 * commandline or from the CPU detection code. Register the lapic
708 * timer as a dummy clock event source on SMP systems, so the
709 * broadcast mechanism is used. On UP systems simply ignore it.
711 if (disable_apic_timer
) {
712 pr_info("Disabling APIC timer\n");
713 /* No broadcast on UP ! */
714 if (num_possible_cpus() > 1) {
715 lapic_clockevent
.mult
= 1;
721 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
722 "calibrating APIC timer ...\n");
724 if (calibrate_APIC_clock()) {
725 /* No broadcast on UP ! */
726 if (num_possible_cpus() > 1)
732 * If nmi_watchdog is set to IO_APIC, we need the
733 * PIT/HPET going. Otherwise register lapic as a dummy
736 if (nmi_watchdog
!= NMI_IO_APIC
)
737 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
739 pr_warning("APIC timer registered as dummy,"
740 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
742 /* Setup the lapic or request the broadcast */
746 void __cpuinit
setup_secondary_APIC_clock(void)
752 * The guts of the apic timer interrupt
754 static void local_apic_timer_interrupt(void)
756 int cpu
= smp_processor_id();
757 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
760 * Normally we should not be here till LAPIC has been initialized but
761 * in some cases like kdump, its possible that there is a pending LAPIC
762 * timer interrupt from previous kernel's context and is delivered in
763 * new kernel the moment interrupts are enabled.
765 * Interrupts are enabled early and LAPIC is setup much later, hence
766 * its possible that when we get here evt->event_handler is NULL.
767 * Check for event_handler being NULL and discard the interrupt as
770 if (!evt
->event_handler
) {
771 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
773 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
778 * the NMI deadlock-detector uses this.
780 inc_irq_stat(apic_timer_irqs
);
782 evt
->event_handler(evt
);
786 * Local APIC timer interrupt. This is the most natural way for doing
787 * local interrupts, but local timer interrupts can be emulated by
788 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
790 * [ if a single-CPU system runs an SMP kernel then we call the local
791 * interrupt as well. Thus we cannot inline the local irq ... ]
793 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
795 struct pt_regs
*old_regs
= set_irq_regs(regs
);
798 * NOTE! We'd better ACK the irq immediately,
799 * because timer handling can be slow.
803 * update_process_times() expects us to have done irq_enter().
804 * Besides, if we don't timer interrupts ignore the global
805 * interrupt lock, which is the WrongThing (tm) to do.
811 local_apic_timer_interrupt();
814 set_irq_regs(old_regs
);
817 int setup_profiling_timer(unsigned int multiplier
)
823 * Local APIC start and shutdown
827 * clear_local_APIC - shutdown the local APIC
829 * This is called, when a CPU is disabled and before rebooting, so the state of
830 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
831 * leftovers during boot.
833 void clear_local_APIC(void)
838 /* APIC hasn't been mapped yet */
842 maxlvt
= lapic_get_maxlvt();
844 * Masking an LVT entry can trigger a local APIC error
845 * if the vector is zero. Mask LVTERR first to prevent this.
848 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
849 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
852 * Careful: we have to set masks only first to deassert
853 * any level-triggered sources.
855 v
= apic_read(APIC_LVTT
);
856 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
857 v
= apic_read(APIC_LVT0
);
858 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
859 v
= apic_read(APIC_LVT1
);
860 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
862 v
= apic_read(APIC_LVTPC
);
863 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
866 /* lets not touch this if we didn't frob it */
867 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
869 v
= apic_read(APIC_LVTTHMR
);
870 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
874 * Clean APIC state for other OSs:
876 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
877 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
878 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
880 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
882 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
884 /* Integrated APIC (!82489DX) ? */
885 if (lapic_is_integrated()) {
887 /* Clear ESR due to Pentium errata 3AP and 11AP */
888 apic_write(APIC_ESR
, 0);
894 * disable_local_APIC - clear and disable the local APIC
896 void disable_local_APIC(void)
903 * Disable APIC (implies clearing of registers
906 value
= apic_read(APIC_SPIV
);
907 value
&= ~APIC_SPIV_APIC_ENABLED
;
908 apic_write(APIC_SPIV
, value
);
912 * When LAPIC was disabled by the BIOS and enabled by the kernel,
913 * restore the disabled state.
915 if (enabled_via_apicbase
) {
918 rdmsr(MSR_IA32_APICBASE
, l
, h
);
919 l
&= ~MSR_IA32_APICBASE_ENABLE
;
920 wrmsr(MSR_IA32_APICBASE
, l
, h
);
926 * If Linux enabled the LAPIC against the BIOS default disable it down before
927 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
928 * not power-off. Additionally clear all LVT entries before disable_local_APIC
929 * for the case where Linux didn't enable the LAPIC.
931 void lapic_shutdown(void)
938 local_irq_save(flags
);
941 if (!enabled_via_apicbase
)
945 disable_local_APIC();
948 local_irq_restore(flags
);
952 * This is to verify that we're looking at a real local APIC.
953 * Check these against your board if the CPUs aren't getting
954 * started for no apparent reason.
956 int __init
verify_local_APIC(void)
958 unsigned int reg0
, reg1
;
961 * The version register is read-only in a real APIC.
963 reg0
= apic_read(APIC_LVR
);
964 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
965 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
966 reg1
= apic_read(APIC_LVR
);
967 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
970 * The two version reads above should print the same
971 * numbers. If the second one is different, then we
972 * poke at a non-APIC.
978 * Check if the version looks reasonably.
980 reg1
= GET_APIC_VERSION(reg0
);
981 if (reg1
== 0x00 || reg1
== 0xff)
983 reg1
= lapic_get_maxlvt();
984 if (reg1
< 0x02 || reg1
== 0xff)
988 * The ID register is read/write in a real APIC.
990 reg0
= apic_read(APIC_ID
);
991 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
992 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
993 reg1
= apic_read(APIC_ID
);
994 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
995 apic_write(APIC_ID
, reg0
);
996 if (reg1
!= (reg0
^ APIC_ID_MASK
))
1000 * The next two are just to see if we have sane values.
1001 * They're only really relevant if we're in Virtual Wire
1002 * compatibility mode, but most boxes are anymore.
1004 reg0
= apic_read(APIC_LVT0
);
1005 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1006 reg1
= apic_read(APIC_LVT1
);
1007 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1013 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1015 void __init
sync_Arb_IDs(void)
1018 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1021 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1027 apic_wait_icr_idle();
1029 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1030 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1031 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1035 * An initial setup of the virtual wire mode.
1037 void __init
init_bsp_APIC(void)
1042 * Don't do the setup now if we have a SMP BIOS as the
1043 * through-I/O-APIC virtual wire mode might be active.
1045 if (smp_found_config
|| !cpu_has_apic
)
1049 * Do not trust the local APIC being empty at bootup.
1056 value
= apic_read(APIC_SPIV
);
1057 value
&= ~APIC_VECTOR_MASK
;
1058 value
|= APIC_SPIV_APIC_ENABLED
;
1060 #ifdef CONFIG_X86_32
1061 /* This bit is reserved on P4/Xeon and should be cleared */
1062 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1063 (boot_cpu_data
.x86
== 15))
1064 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1067 value
|= APIC_SPIV_FOCUS_DISABLED
;
1068 value
|= SPURIOUS_APIC_VECTOR
;
1069 apic_write(APIC_SPIV
, value
);
1072 * Set up the virtual wire mode.
1074 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1075 value
= APIC_DM_NMI
;
1076 if (!lapic_is_integrated()) /* 82489DX */
1077 value
|= APIC_LVT_LEVEL_TRIGGER
;
1078 apic_write(APIC_LVT1
, value
);
1081 static void __cpuinit
lapic_setup_esr(void)
1083 unsigned int oldvalue
, value
, maxlvt
;
1085 if (!lapic_is_integrated()) {
1086 pr_info("No ESR for 82489DX.\n");
1092 * Something untraceable is creating bad interrupts on
1093 * secondary quads ... for the moment, just leave the
1094 * ESR disabled - we can't do anything useful with the
1095 * errors anyway - mbligh
1097 pr_info("Leaving ESR disabled.\n");
1101 maxlvt
= lapic_get_maxlvt();
1102 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1103 apic_write(APIC_ESR
, 0);
1104 oldvalue
= apic_read(APIC_ESR
);
1106 /* enables sending errors */
1107 value
= ERROR_APIC_VECTOR
;
1108 apic_write(APIC_LVTERR
, value
);
1111 * spec says clear errors after enabling vector.
1114 apic_write(APIC_ESR
, 0);
1115 value
= apic_read(APIC_ESR
);
1116 if (value
!= oldvalue
)
1117 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1118 "vector: 0x%08x after: 0x%08x\n",
1124 * setup_local_APIC - setup the local APIC
1126 void __cpuinit
setup_local_APIC(void)
1131 #ifdef CONFIG_X86_32
1132 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1133 if (lapic_is_integrated() && esr_disable
) {
1134 apic_write(APIC_ESR
, 0);
1135 apic_write(APIC_ESR
, 0);
1136 apic_write(APIC_ESR
, 0);
1137 apic_write(APIC_ESR
, 0);
1144 * Double-check whether this APIC is really registered.
1145 * This is meaningless in clustered apic mode, so we skip it.
1147 if (!apic_id_registered())
1151 * Intel recommends to set DFR, LDR and TPR before enabling
1152 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1153 * document number 292116). So here it goes...
1158 * Set Task Priority to 'accept all'. We never change this
1161 value
= apic_read(APIC_TASKPRI
);
1162 value
&= ~APIC_TPRI_MASK
;
1163 apic_write(APIC_TASKPRI
, value
);
1166 * After a crash, we no longer service the interrupts and a pending
1167 * interrupt from previous kernel might still have ISR bit set.
1169 * Most probably by now CPU has serviced that pending interrupt and
1170 * it might not have done the ack_APIC_irq() because it thought,
1171 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1172 * does not clear the ISR bit and cpu thinks it has already serivced
1173 * the interrupt. Hence a vector might get locked. It was noticed
1174 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1176 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1177 value
= apic_read(APIC_ISR
+ i
*0x10);
1178 for (j
= 31; j
>= 0; j
--) {
1185 * Now that we are all set up, enable the APIC
1187 value
= apic_read(APIC_SPIV
);
1188 value
&= ~APIC_VECTOR_MASK
;
1192 value
|= APIC_SPIV_APIC_ENABLED
;
1194 #ifdef CONFIG_X86_32
1196 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1197 * certain networking cards. If high frequency interrupts are
1198 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1199 * entry is masked/unmasked at a high rate as well then sooner or
1200 * later IOAPIC line gets 'stuck', no more interrupts are received
1201 * from the device. If focus CPU is disabled then the hang goes
1204 * [ This bug can be reproduced easily with a level-triggered
1205 * PCI Ne2000 networking cards and PII/PIII processors, dual
1209 * Actually disabling the focus CPU check just makes the hang less
1210 * frequent as it makes the interrupt distributon model be more
1211 * like LRU than MRU (the short-term load is more even across CPUs).
1212 * See also the comment in end_level_ioapic_irq(). --macro
1216 * - enable focus processor (bit==0)
1217 * - 64bit mode always use processor focus
1218 * so no need to set it
1220 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1224 * Set spurious IRQ vector
1226 value
|= SPURIOUS_APIC_VECTOR
;
1227 apic_write(APIC_SPIV
, value
);
1230 * Set up LVT0, LVT1:
1232 * set up through-local-APIC on the BP's LINT0. This is not
1233 * strictly necessary in pure symmetric-IO mode, but sometimes
1234 * we delegate interrupts to the 8259A.
1237 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1239 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1240 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1241 value
= APIC_DM_EXTINT
;
1242 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1243 smp_processor_id());
1245 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1246 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1247 smp_processor_id());
1249 apic_write(APIC_LVT0
, value
);
1252 * only the BP should see the LINT1 NMI signal, obviously.
1254 if (!smp_processor_id())
1255 value
= APIC_DM_NMI
;
1257 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1258 if (!lapic_is_integrated()) /* 82489DX */
1259 value
|= APIC_LVT_LEVEL_TRIGGER
;
1260 apic_write(APIC_LVT1
, value
);
1265 void __cpuinit
end_local_APIC_setup(void)
1269 #ifdef CONFIG_X86_32
1272 /* Disable the local apic timer */
1273 value
= apic_read(APIC_LVTT
);
1274 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1275 apic_write(APIC_LVTT
, value
);
1279 setup_apic_nmi_watchdog(NULL
);
1284 void check_x2apic(void)
1288 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1290 if (msr
& X2APIC_ENABLE
) {
1291 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1292 x2apic_preenabled
= x2apic
= 1;
1293 apic_ops
= &x2apic_ops
;
1297 void enable_x2apic(void)
1301 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1302 if (!(msr
& X2APIC_ENABLE
)) {
1303 pr_info("Enabling x2apic\n");
1304 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1308 void __init
enable_IR_x2apic(void)
1310 #ifdef CONFIG_INTR_REMAP
1312 unsigned long flags
;
1314 if (!cpu_has_x2apic
)
1317 if (!x2apic_preenabled
&& disable_x2apic
) {
1318 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1319 "because of nox2apic\n");
1323 if (x2apic_preenabled
&& disable_x2apic
)
1324 panic("Bios already enabled x2apic, can't enforce nox2apic");
1326 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1327 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1328 "because of skipping io-apic setup\n");
1332 ret
= dmar_table_init();
1334 pr_info("dmar_table_init() failed with %d:\n", ret
);
1336 if (x2apic_preenabled
)
1337 panic("x2apic enabled by bios. But IR enabling failed");
1339 pr_info("Not enabling x2apic,Intr-remapping\n");
1343 local_irq_save(flags
);
1346 ret
= save_mask_IO_APIC_setup();
1348 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1352 ret
= enable_intr_remapping(1);
1354 if (ret
&& x2apic_preenabled
) {
1355 local_irq_restore(flags
);
1356 panic("x2apic enabled by bios. But IR enabling failed");
1364 apic_ops
= &x2apic_ops
;
1371 * IR enabling failed
1373 restore_IO_APIC_setup();
1375 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1379 local_irq_restore(flags
);
1382 if (!x2apic_preenabled
)
1383 pr_info("Enabled x2apic and interrupt-remapping\n");
1385 pr_info("Enabled Interrupt-remapping\n");
1387 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1389 if (!cpu_has_x2apic
)
1392 if (x2apic_preenabled
)
1393 panic("x2apic enabled prior OS handover,"
1394 " enable CONFIG_INTR_REMAP");
1396 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1402 #endif /* HAVE_X2APIC */
1404 #ifdef CONFIG_X86_64
1406 * Detect and enable local APICs on non-SMP boards.
1407 * Original code written by Keir Fraser.
1408 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1409 * not correctly set up (usually the APIC timer won't work etc.)
1411 static int __init
detect_init_APIC(void)
1413 if (!cpu_has_apic
) {
1414 pr_info("No local APIC present\n");
1418 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1419 boot_cpu_physical_apicid
= 0;
1424 * Detect and initialize APIC
1426 static int __init
detect_init_APIC(void)
1430 /* Disabled by kernel option? */
1434 switch (boot_cpu_data
.x86_vendor
) {
1435 case X86_VENDOR_AMD
:
1436 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1437 (boot_cpu_data
.x86
== 15))
1440 case X86_VENDOR_INTEL
:
1441 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1442 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1449 if (!cpu_has_apic
) {
1451 * Over-ride BIOS and try to enable the local APIC only if
1452 * "lapic" specified.
1454 if (!force_enable_local_apic
) {
1455 pr_info("Local APIC disabled by BIOS -- "
1456 "you can enable it with \"lapic\"\n");
1460 * Some BIOSes disable the local APIC in the APIC_BASE
1461 * MSR. This can only be done in software for Intel P6 or later
1462 * and AMD K7 (Model > 1) or later.
1464 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1465 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1466 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1467 l
&= ~MSR_IA32_APICBASE_BASE
;
1468 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1469 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1470 enabled_via_apicbase
= 1;
1474 * The APIC feature bit should now be enabled
1477 features
= cpuid_edx(1);
1478 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1479 pr_warning("Could not enable APIC!\n");
1482 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1483 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1485 /* The BIOS may have set up the APIC at some other address */
1486 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1487 if (l
& MSR_IA32_APICBASE_ENABLE
)
1488 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1490 pr_info("Found and enabled local APIC!\n");
1497 pr_info("No local APIC present or hardware disabled\n");
1502 #ifdef CONFIG_X86_64
1503 void __init
early_init_lapic_mapping(void)
1505 unsigned long phys_addr
;
1508 * If no local APIC can be found then go out
1509 * : it means there is no mpatable and MADT
1511 if (!smp_found_config
)
1514 phys_addr
= mp_lapic_addr
;
1516 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1517 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1518 APIC_BASE
, phys_addr
);
1521 * Fetch the APIC ID of the BSP in case we have a
1522 * default configuration (or the MP table is broken).
1524 boot_cpu_physical_apicid
= read_apic_id();
1529 * init_apic_mappings - initialize APIC mappings
1531 void __init
init_apic_mappings(void)
1535 boot_cpu_physical_apicid
= read_apic_id();
1541 * If no local APIC can be found then set up a fake all
1542 * zeroes page to simulate the local APIC and another
1543 * one for the IO-APIC.
1545 if (!smp_found_config
&& detect_init_APIC()) {
1546 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1547 apic_phys
= __pa(apic_phys
);
1549 apic_phys
= mp_lapic_addr
;
1551 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1552 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1553 APIC_BASE
, apic_phys
);
1556 * Fetch the APIC ID of the BSP in case we have a
1557 * default configuration (or the MP table is broken).
1559 if (boot_cpu_physical_apicid
== -1U)
1560 boot_cpu_physical_apicid
= read_apic_id();
1564 * This initializes the IO-APIC and APIC hardware if this is
1567 int apic_version
[MAX_APICS
];
1569 int __init
APIC_init_uniprocessor(void)
1571 #ifdef CONFIG_X86_64
1573 pr_info("Apic disabled\n");
1576 if (!cpu_has_apic
) {
1578 pr_info("Apic disabled by BIOS\n");
1582 if (!smp_found_config
&& !cpu_has_apic
)
1586 * Complain if the BIOS pretends there is one.
1588 if (!cpu_has_apic
&&
1589 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1590 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1591 boot_cpu_physical_apicid
);
1592 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1600 #ifdef CONFIG_X86_64
1601 setup_apic_routing();
1604 verify_local_APIC();
1607 #ifdef CONFIG_X86_64
1608 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1611 * Hack: In case of kdump, after a crash, kernel might be booting
1612 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1613 * might be zero if read from MP tables. Get it from LAPIC.
1615 # ifdef CONFIG_CRASH_DUMP
1616 boot_cpu_physical_apicid
= read_apic_id();
1619 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1622 #ifdef CONFIG_X86_64
1624 * Now enable IO-APICs, actually call clear_IO_APIC
1625 * We need clear_IO_APIC before enabling vector on BP
1627 if (!skip_ioapic_setup
&& nr_ioapics
)
1631 #ifdef CONFIG_X86_IO_APIC
1632 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1634 localise_nmi_watchdog();
1635 end_local_APIC_setup();
1637 #ifdef CONFIG_X86_IO_APIC
1638 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1640 # ifdef CONFIG_X86_64
1646 #ifdef CONFIG_X86_64
1647 setup_boot_APIC_clock();
1648 check_nmi_watchdog();
1657 * Local APIC interrupts
1661 * This interrupt should _never_ happen with our APIC/SMP architecture
1663 void smp_spurious_interrupt(struct pt_regs
*regs
)
1667 #ifdef CONFIG_X86_64
1672 * Check if this really is a spurious interrupt and ACK it
1673 * if it is a vectored one. Just in case...
1674 * Spurious interrupts should not be ACKed.
1676 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1677 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1680 inc_irq_stat(irq_spurious_count
);
1682 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1683 pr_info("spurious APIC interrupt on CPU#%d, "
1684 "should never happen.\n", smp_processor_id());
1689 * This interrupt should never happen with our APIC/SMP architecture
1691 void smp_error_interrupt(struct pt_regs
*regs
)
1695 #ifdef CONFIG_X86_64
1699 /* First tickle the hardware, only then report what went on. -- REW */
1700 v
= apic_read(APIC_ESR
);
1701 apic_write(APIC_ESR
, 0);
1702 v1
= apic_read(APIC_ESR
);
1704 atomic_inc(&irq_err_count
);
1707 * Here is what the APIC error bits mean:
1709 * 1: Receive CS error
1710 * 2: Send accept error
1711 * 3: Receive accept error
1713 * 5: Send illegal vector
1714 * 6: Received illegal vector
1715 * 7: Illegal register address
1717 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1718 smp_processor_id(), v
, v1
);
1723 * connect_bsp_APIC - attach the APIC to the interrupt system
1725 void __init
connect_bsp_APIC(void)
1727 #ifdef CONFIG_X86_32
1730 * Do not trust the local APIC being empty at bootup.
1734 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1735 * local APIC to INT and NMI lines.
1737 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1738 "enabling APIC mode.\n");
1747 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1748 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1750 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1753 void disconnect_bsp_APIC(int virt_wire_setup
)
1757 #ifdef CONFIG_X86_32
1760 * Put the board back into PIC mode (has an effect only on
1761 * certain older boards). Note that APIC interrupts, including
1762 * IPIs, won't work beyond this point! The only exception are
1765 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1766 "entering PIC mode.\n");
1773 /* Go back to Virtual Wire compatibility mode */
1775 /* For the spurious interrupt use vector F, and enable it */
1776 value
= apic_read(APIC_SPIV
);
1777 value
&= ~APIC_VECTOR_MASK
;
1778 value
|= APIC_SPIV_APIC_ENABLED
;
1780 apic_write(APIC_SPIV
, value
);
1782 if (!virt_wire_setup
) {
1784 * For LVT0 make it edge triggered, active high,
1785 * external and enabled
1787 value
= apic_read(APIC_LVT0
);
1788 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1789 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1790 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1791 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1792 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1793 apic_write(APIC_LVT0
, value
);
1796 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1800 * For LVT1 make it edge triggered, active high,
1803 value
= apic_read(APIC_LVT1
);
1804 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1805 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1806 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1807 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1808 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1809 apic_write(APIC_LVT1
, value
);
1812 void __cpuinit
generic_processor_info(int apicid
, int version
)
1820 if (version
== 0x0) {
1821 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1822 "fixing up to 0x10. (tell your hw vendor)\n",
1826 apic_version
[apicid
] = version
;
1828 if (num_processors
>= NR_CPUS
) {
1829 pr_warning("WARNING: NR_CPUS limit of %i reached."
1830 " Processor ignored.\n", NR_CPUS
);
1835 cpus_complement(tmp_map
, cpu_present_map
);
1836 cpu
= first_cpu(tmp_map
);
1838 physid_set(apicid
, phys_cpu_present_map
);
1839 if (apicid
== boot_cpu_physical_apicid
) {
1841 * x86_bios_cpu_apicid is required to have processors listed
1842 * in same order as logical cpu numbers. Hence the first
1843 * entry is BSP, and so on.
1847 if (apicid
> max_physical_apicid
)
1848 max_physical_apicid
= apicid
;
1850 #ifdef CONFIG_X86_32
1852 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1853 * but we need to work other dependencies like SMP_SUSPEND etc
1854 * before this can be done without some confusion.
1855 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1856 * - Ashok Raj <ashok.raj@intel.com>
1858 if (max_physical_apicid
>= 8) {
1859 switch (boot_cpu_data
.x86_vendor
) {
1860 case X86_VENDOR_INTEL
:
1861 if (!APIC_XAPIC(version
)) {
1865 /* If P4 and above fall through */
1866 case X86_VENDOR_AMD
:
1872 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1873 /* are we being called early in kernel startup? */
1874 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1875 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1876 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1878 cpu_to_apicid
[cpu
] = apicid
;
1879 bios_cpu_apicid
[cpu
] = apicid
;
1881 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1882 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1886 cpu_set(cpu
, cpu_possible_map
);
1887 cpu_set(cpu
, cpu_present_map
);
1890 #ifdef CONFIG_X86_64
1891 int hard_smp_processor_id(void)
1893 return read_apic_id();
1904 * 'active' is true if the local APIC was enabled by us and
1905 * not the BIOS; this signifies that we are also responsible
1906 * for disabling it before entering apm/acpi suspend
1909 /* r/w apic fields */
1910 unsigned int apic_id
;
1911 unsigned int apic_taskpri
;
1912 unsigned int apic_ldr
;
1913 unsigned int apic_dfr
;
1914 unsigned int apic_spiv
;
1915 unsigned int apic_lvtt
;
1916 unsigned int apic_lvtpc
;
1917 unsigned int apic_lvt0
;
1918 unsigned int apic_lvt1
;
1919 unsigned int apic_lvterr
;
1920 unsigned int apic_tmict
;
1921 unsigned int apic_tdcr
;
1922 unsigned int apic_thmr
;
1925 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1927 unsigned long flags
;
1930 if (!apic_pm_state
.active
)
1933 maxlvt
= lapic_get_maxlvt();
1935 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1936 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1937 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1938 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1939 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1940 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1942 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1943 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1944 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1945 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1946 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1947 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1948 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1950 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1953 local_irq_save(flags
);
1954 disable_local_APIC();
1955 local_irq_restore(flags
);
1959 static int lapic_resume(struct sys_device
*dev
)
1962 unsigned long flags
;
1965 if (!apic_pm_state
.active
)
1968 maxlvt
= lapic_get_maxlvt();
1970 local_irq_save(flags
);
1979 * Make sure the APICBASE points to the right address
1981 * FIXME! This will be wrong if we ever support suspend on
1982 * SMP! We'll need to do this as part of the CPU restore!
1984 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1985 l
&= ~MSR_IA32_APICBASE_BASE
;
1986 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1987 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1990 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1991 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1992 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1993 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1994 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1995 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1996 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1997 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1998 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2000 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2003 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2004 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2005 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2006 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2007 apic_write(APIC_ESR
, 0);
2008 apic_read(APIC_ESR
);
2009 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2010 apic_write(APIC_ESR
, 0);
2011 apic_read(APIC_ESR
);
2013 local_irq_restore(flags
);
2019 * This device has no shutdown method - fully functioning local APICs
2020 * are needed on every CPU up until machine_halt/restart/poweroff.
2023 static struct sysdev_class lapic_sysclass
= {
2025 .resume
= lapic_resume
,
2026 .suspend
= lapic_suspend
,
2029 static struct sys_device device_lapic
= {
2031 .cls
= &lapic_sysclass
,
2034 static void __cpuinit
apic_pm_activate(void)
2036 apic_pm_state
.active
= 1;
2039 static int __init
init_lapic_sysfs(void)
2045 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2047 error
= sysdev_class_register(&lapic_sysclass
);
2049 error
= sysdev_register(&device_lapic
);
2052 device_initcall(init_lapic_sysfs
);
2054 #else /* CONFIG_PM */
2056 static void apic_pm_activate(void) { }
2058 #endif /* CONFIG_PM */
2060 #ifdef CONFIG_X86_64
2062 * apic_is_clustered_box() -- Check if we can expect good TSC
2064 * Thus far, the major user of this is IBM's Summit2 series:
2066 * Clustered boxes may have unsynced TSC problems if they are
2067 * multi-chassis. Use available data to take a good guess.
2068 * If in doubt, go HPET.
2070 __cpuinit
int apic_is_clustered_box(void)
2072 int i
, clusters
, zeros
;
2074 u16
*bios_cpu_apicid
;
2075 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2078 * there is not this kind of box with AMD CPU yet.
2079 * Some AMD box with quadcore cpu and 8 sockets apicid
2080 * will be [4, 0x23] or [8, 0x27] could be thought to
2081 * vsmp box still need checking...
2083 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2086 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2087 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2089 for (i
= 0; i
< NR_CPUS
; i
++) {
2090 /* are we being called early in kernel startup? */
2091 if (bios_cpu_apicid
) {
2092 id
= bios_cpu_apicid
[i
];
2094 else if (i
< nr_cpu_ids
) {
2096 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2103 if (id
!= BAD_APICID
)
2104 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2107 /* Problem: Partially populated chassis may not have CPUs in some of
2108 * the APIC clusters they have been allocated. Only present CPUs have
2109 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2110 * Since clusters are allocated sequentially, count zeros only if
2111 * they are bounded by ones.
2115 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2116 if (test_bit(i
, clustermap
)) {
2117 clusters
+= 1 + zeros
;
2123 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2124 * not guaranteed to be synced between boards
2126 if (is_vsmp_box() && clusters
> 1)
2130 * If clusters > 2, then should be multi-chassis.
2131 * May have to revisit this when multi-core + hyperthreaded CPUs come
2132 * out, but AFAIK this will work even for them.
2134 return (clusters
> 2);
2139 * APIC command line parameters
2141 static int __init
setup_disableapic(char *arg
)
2144 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2147 early_param("disableapic", setup_disableapic
);
2149 /* same as disableapic, for compatibility */
2150 static int __init
setup_nolapic(char *arg
)
2152 return setup_disableapic(arg
);
2154 early_param("nolapic", setup_nolapic
);
2156 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2158 local_apic_timer_c2_ok
= 1;
2161 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2163 static int __init
parse_disable_apic_timer(char *arg
)
2165 disable_apic_timer
= 1;
2168 early_param("noapictimer", parse_disable_apic_timer
);
2170 static int __init
parse_nolapic_timer(char *arg
)
2172 disable_apic_timer
= 1;
2175 early_param("nolapic_timer", parse_nolapic_timer
);
2177 static int __init
apic_set_verbosity(char *arg
)
2180 #ifdef CONFIG_X86_64
2181 skip_ioapic_setup
= 0;
2187 if (strcmp("debug", arg
) == 0)
2188 apic_verbosity
= APIC_DEBUG
;
2189 else if (strcmp("verbose", arg
) == 0)
2190 apic_verbosity
= APIC_VERBOSE
;
2192 pr_warning("APIC Verbosity level %s not recognised"
2193 " use apic=verbose or apic=debug\n", arg
);
2199 early_param("apic", apic_set_verbosity
);
2201 static int __init
lapic_insert_resource(void)
2206 /* Put local APIC into the resource map. */
2207 lapic_resource
.start
= apic_phys
;
2208 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2209 insert_resource(&iomem_resource
, &lapic_resource
);
2215 * need call insert after e820_reserve_resources()
2216 * that is using request_resource
2218 late_initcall(lapic_insert_resource
);