arch/arm/mach-pxa/include/mach/pxa-regs.h

   1 /*
   2  *  arch/arm/mach-pxa/include/mach/pxa-regs.h
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    Jun 15, 2001
   6  *  Copyright:  MontaVista Software Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __PXA_REGS_H
  14 #define __PXA_REGS_H
  15
  16
  17 /*
  18  * PXA Chip selects
  19  */
  20
  21 #define PXA_CS0_PHYS    0x00000000
  22 #define PXA_CS1_PHYS    0x04000000
  23 #define PXA_CS2_PHYS    0x08000000
  24 #define PXA_CS3_PHYS    0x0C000000
  25 #define PXA_CS4_PHYS    0x10000000
  26 #define PXA_CS5_PHYS    0x14000000
  27
  28
  29 /*
  30  * Personal Computer Memory Card International Association (PCMCIA) sockets
  31  */
  32
  33 #define PCMCIAPrtSp     0x04000000      /* PCMCIA Partition Space [byte]   */
  34 #define PCMCIASp        (4*PCMCIAPrtSp) /* PCMCIA Space [byte]             */
  35 #define PCMCIAIOSp      PCMCIAPrtSp     /* PCMCIA I/O Space [byte]         */
  36 #define PCMCIAAttrSp    PCMCIAPrtSp     /* PCMCIA Attribute Space [byte]   */
  37 #define PCMCIAMemSp     PCMCIAPrtSp     /* PCMCIA Memory Space [byte]      */
  38
  39 #define PCMCIA0Sp       PCMCIASp        /* PCMCIA 0 Space [byte]           */
  40 #define PCMCIA0IOSp     PCMCIAIOSp      /* PCMCIA 0 I/O Space [byte]       */
  41 #define PCMCIA0AttrSp   PCMCIAAttrSp    /* PCMCIA 0 Attribute Space [byte] */
  42 #define PCMCIA0MemSp    PCMCIAMemSp     /* PCMCIA 0 Memory Space [byte]    */
  43
  44 #define PCMCIA1Sp       PCMCIASp        /* PCMCIA 1 Space [byte]           */
  45 #define PCMCIA1IOSp     PCMCIAIOSp      /* PCMCIA 1 I/O Space [byte]       */
  46 #define PCMCIA1AttrSp   PCMCIAAttrSp    /* PCMCIA 1 Attribute Space [byte] */
  47 #define PCMCIA1MemSp    PCMCIAMemSp     /* PCMCIA 1 Memory Space [byte]    */
  48
  49 #define _PCMCIA(Nb)                     /* PCMCIA [0..1]                   */ \
  50                         (0x20000000 + (Nb)*PCMCIASp)
  51 #define _PCMCIAIO(Nb)   _PCMCIA (Nb)    /* PCMCIA I/O [0..1]               */
  52 #define _PCMCIAAttr(Nb)                 /* PCMCIA Attribute [0..1]         */ \
  53                         (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
  54 #define _PCMCIAMem(Nb)                  /* PCMCIA Memory [0..1]            */ \
  55                         (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
  56
  57 #define _PCMCIA0        _PCMCIA (0)     /* PCMCIA 0                        */
  58 #define _PCMCIA0IO      _PCMCIAIO (0)   /* PCMCIA 0 I/O                    */
  59 #define _PCMCIA0Attr    _PCMCIAAttr (0) /* PCMCIA 0 Attribute              */
  60 #define _PCMCIA0Mem     _PCMCIAMem (0)  /* PCMCIA 0 Memory                 */
  61
  62 #define _PCMCIA1        _PCMCIA (1)     /* PCMCIA 1                        */
  63 #define _PCMCIA1IO      _PCMCIAIO (1)   /* PCMCIA 1 I/O                    */
  64 #define _PCMCIA1Attr    _PCMCIAAttr (1) /* PCMCIA 1 Attribute              */
  65 #define _PCMCIA1Mem     _PCMCIAMem (1)  /* PCMCIA 1 Memory                 */
  66
  67
  68
  69 /*
  70  * DMA Controller
  71  */
  72 #define DCSR(x)         __REG2(0x40000000, (x) << 2)
  73
  74 #define DCSR_RUN        (1 << 31)       /* Run Bit (read / write) */
  75 #define DCSR_NODESC     (1 << 30)       /* No-Descriptor Fetch (read / write) */
  76 #define DCSR_STOPIRQEN  (1 << 29)       /* Stop Interrupt Enable (read / write) */
  77 #define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
  78 #define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
  79 #define DCSR_ENDINTR    (1 << 2)        /* End Interrupt (read / write) */
  80 #define DCSR_STARTINTR  (1 << 1)        /* Start Interrupt (read / write) */
  81 #define DCSR_BUSERR     (1 << 0)        /* Bus Error Interrupt (read / write) */
  82
  83 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  84 #define DCSR_EORIRQEN   (1 << 28)       /* End of Receive Interrupt Enable (R/W) */
  85 #define DCSR_EORJMPEN   (1 << 27)       /* Jump to next descriptor on EOR */
  86 #define DCSR_EORSTOPEN  (1 << 26)       /* STOP on an EOR */
  87 #define DCSR_SETCMPST   (1 << 25)       /* Set Descriptor Compare Status */
  88 #define DCSR_CLRCMPST   (1 << 24)       /* Clear Descriptor Compare Status */
  89 #define DCSR_CMPST      (1 << 10)       /* The Descriptor Compare Status */
  90 #define DCSR_EORINTR    (1 << 9)        /* The end of Receive */
  91 #endif
  92
  93 #define DALGN           __REG(0x400000a0)  /* DMA Alignment Register */
  94 #define DINT            __REG(0x400000f0)  /* DMA Interrupt Register */
  95
  96 #define DRCMR(n)        (*(((n) < 64) ? \
  97                         &__REG2(0x40000100, ((n) & 0x3f) << 2) : \
  98                         &__REG2(0x40001100, ((n) & 0x3f) << 2)))
  99
 100 #define DRCMR_MAPVLD    (1 << 7)        /* Map Valid (read / write) */
 101 #define DRCMR_CHLNUM    0x1f            /* mask for Channel Number (read / write) */
 102
 103 #define DDADR(x)        __REG2(0x40000200, (x) << 4)
 104 #define DSADR(x)        __REG2(0x40000204, (x) << 4)
 105 #define DTADR(x)        __REG2(0x40000208, (x) << 4)
 106 #define DCMD(x)         __REG2(0x4000020c, (x) << 4)
 107
 108 #define DDADR_DESCADDR  0xfffffff0      /* Address of next descriptor (mask) */
 109 #define DDADR_STOP      (1 << 0)        /* Stop (read / write) */
 110
 111 #define DCMD_INCSRCADDR (1 << 31)       /* Source Address Increment Setting. */
 112 #define DCMD_INCTRGADDR (1 << 30)       /* Target Address Increment Setting. */
 113 #define DCMD_FLOWSRC    (1 << 29)       /* Flow Control by the source. */
 114 #define DCMD_FLOWTRG    (1 << 28)       /* Flow Control by the target. */
 115 #define DCMD_STARTIRQEN (1 << 22)       /* Start Interrupt Enable */
 116 #define DCMD_ENDIRQEN   (1 << 21)       /* End Interrupt Enable */
 117 #define DCMD_ENDIAN     (1 << 18)       /* Device Endian-ness. */
 118 #define DCMD_BURST8     (1 << 16)       /* 8 byte burst */
 119 #define DCMD_BURST16    (2 << 16)       /* 16 byte burst */
 120 #define DCMD_BURST32    (3 << 16)       /* 32 byte burst */
 121 #define DCMD_WIDTH1     (1 << 14)       /* 1 byte width */
 122 #define DCMD_WIDTH2     (2 << 14)       /* 2 byte width (HalfWord) */
 123 #define DCMD_WIDTH4     (3 << 14)       /* 4 byte width (Word) */
 124 #define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
 125
 126 /*
 127  * Real Time Clock
 128  */
 129
 130 #define RCNR            __REG(0x40900000)  /* RTC Count Register */
 131 #define RTAR            __REG(0x40900004)  /* RTC Alarm Register */
 132 #define RTSR            __REG(0x40900008)  /* RTC Status Register */
 133 #define RTTR            __REG(0x4090000C)  /* RTC Timer Trim Register */
 134 #define PIAR            __REG(0x40900038)  /* Periodic Interrupt Alarm Register */
 135
 136 #define RTSR_PICE       (1 << 15)       /* Periodic interrupt count enable */
 137 #define RTSR_PIALE      (1 << 14)       /* Periodic interrupt Alarm enable */
 138 #define RTSR_HZE        (1 << 3)        /* HZ interrupt enable */
 139 #define RTSR_ALE        (1 << 2)        /* RTC alarm interrupt enable */
 140 #define RTSR_HZ         (1 << 1)        /* HZ rising-edge detected */
 141 #define RTSR_AL         (1 << 0)        /* RTC alarm detected */
 142
 143
 144 /*
 145  * OS Timer & Match Registers
 146  */
 147
 148 #define OSMR0           __REG(0x40A00000)  /* */
 149 #define OSMR1           __REG(0x40A00004)  /* */
 150 #define OSMR2           __REG(0x40A00008)  /* */
 151 #define OSMR3           __REG(0x40A0000C)  /* */
 152 #define OSMR4           __REG(0x40A00080)  /* */
 153 #define OSCR            __REG(0x40A00010)  /* OS Timer Counter Register */
 154 #define OSCR4           __REG(0x40A00040)  /* OS Timer Counter Register */
 155 #define OMCR4           __REG(0x40A000C0)  /* */
 156 #define OSSR            __REG(0x40A00014)  /* OS Timer Status Register */
 157 #define OWER            __REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
 158 #define OIER            __REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */
 159
 160 #define OSSR_M3         (1 << 3)        /* Match status channel 3 */
 161 #define OSSR_M2         (1 << 2)        /* Match status channel 2 */
 162 #define OSSR_M1         (1 << 1)        /* Match status channel 1 */
 163 #define OSSR_M0         (1 << 0)        /* Match status channel 0 */
 164
 165 #define OWER_WME        (1 << 0)        /* Watchdog Match Enable */
 166
 167 #define OIER_E3         (1 << 3)        /* Interrupt enable channel 3 */
 168 #define OIER_E2         (1 << 2)        /* Interrupt enable channel 2 */
 169 #define OIER_E1         (1 << 1)        /* Interrupt enable channel 1 */
 170 #define OIER_E0         (1 << 0)        /* Interrupt enable channel 0 */
 171
 172
 173 /*
 174  * Interrupt Controller
 175  */
 176
 177 #define ICIP            __REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
 178 #define ICMR            __REG(0x40D00004)  /* Interrupt Controller Mask Register */
 179 #define ICLR            __REG(0x40D00008)  /* Interrupt Controller Level Register */
 180 #define ICFP            __REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
 181 #define ICPR            __REG(0x40D00010)  /* Interrupt Controller Pending Register */
 182 #define ICCR            __REG(0x40D00014)  /* Interrupt Controller Control Register */
 183
 184 #define ICIP2           __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
 185 #define ICMR2           __REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
 186 #define ICLR2           __REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
 187 #define ICFP2           __REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
 188 #define ICPR2           __REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
 189
 190 /*
 191  * General Purpose I/O
 192  */
 193
 194 #define GPLR0           __REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
 195 #define GPLR1           __REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
 196 #define GPLR2           __REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */
 197
 198 #define GPDR0           __REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
 199 #define GPDR1           __REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
 200 #define GPDR2           __REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<80:64> */
 201
 202 #define GPSR0           __REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
 203 #define GPSR1           __REG(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
 204 #define GPSR2           __REG(0x40E00020)  /* GPIO Pin Output Set Register GPIO<80:64> */
 205
 206 #define GPCR0           __REG(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
 207 #define GPCR1           __REG(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
 208 #define GPCR2           __REG(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <80:64> */
 209
 210 #define GRER0           __REG(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
 211 #define GRER1           __REG(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
 212 #define GRER2           __REG(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<80:64> */
 213
 214 #define GFER0           __REG(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
 215 #define GFER1           __REG(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
 216 #define GFER2           __REG(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<80:64> */
 217
 218 #define GEDR0           __REG(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
 219 #define GEDR1           __REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
 220 #define GEDR2           __REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<80:64> */
 221
 222 #define GAFR0_L         __REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
 223 #define GAFR0_U         __REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
 224 #define GAFR1_L         __REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
 225 #define GAFR1_U         __REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
 226 #define GAFR2_L         __REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
 227 #define GAFR2_U         __REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO<95-80> */
 228 #define GAFR3_L         __REG(0x40E0006C)  /* GPIO Alternate Function Select Register GPIO<111:96> */
 229 #define GAFR3_U         __REG(0x40E00070)  /* GPIO Alternate Function Select Register GPIO<127:112> */
 230
 231 #define GPLR3           __REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<127:96> */
 232 #define GPDR3           __REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<127:96> */
 233 #define GPSR3           __REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<127:96> */
 234 #define GPCR3           __REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO<127:96> */
 235 #define GRER3           __REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
 236 #define GFER3           __REG(0x40E0013C)  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
 237 #define GEDR3           __REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<127:96> */
 238
 239 /* More handy macros.  The argument is a literal GPIO number. */
 240
 241 #define GPIO_bit(x)     (1 << ((x) & 0x1f))
 242
 243 #define _GPLR(x)        __REG2(0x40E00000, ((x) & 0x60) >> 3)
 244 #define _GPDR(x)        __REG2(0x40E0000C, ((x) & 0x60) >> 3)
 245 #define _GPSR(x)        __REG2(0x40E00018, ((x) & 0x60) >> 3)
 246 #define _GPCR(x)        __REG2(0x40E00024, ((x) & 0x60) >> 3)
 247 #define _GRER(x)        __REG2(0x40E00030, ((x) & 0x60) >> 3)
 248 #define _GFER(x)        __REG2(0x40E0003C, ((x) & 0x60) >> 3)
 249 #define _GEDR(x)        __REG2(0x40E00048, ((x) & 0x60) >> 3)
 250 #define _GAFR(x)        __REG2(0x40E00054, ((x) & 0x70) >> 2)
 251
 252 #define GPLR(x)         (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
 253 #define GPDR(x)         (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
 254 #define GPSR(x)         (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
 255 #define GPCR(x)         (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
 256 #define GRER(x)         (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
 257 #define GFER(x)         (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
 258 #define GEDR(x)         (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
 259 #define GAFR(x)         (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
 260                          ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
 261
 262 #endif