drivers/ide/pci/siimage.c

   1 /*
   2  * linux/drivers/ide/pci/siimage.c              Version 1.07    Nov 30, 2003
   3  *
   4  * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2003           Red Hat <alan@redhat.com>
   6  *
   7  *  May be copied or modified under the terms of the GNU General Public License
   8  *
   9  *  Documentation for CMD680:
  10  *  http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
  11  *
  12  *  Documentation for SiI 3112:
  13  *  http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
  14  *
  15  *  Errata and other documentation only available under NDA.
  16  *
  17  *
  18  *  FAQ Items:
  19  *      If you are using Marvell SATA-IDE adapters with Maxtor drives
  20  *      ensure the system is set up for ATA100/UDMA5 not UDMA6.
  21  *
  22  *      If you are using WD drives with SATA bridges you must set the
  23  *      drive to "Single". "Master" will hang
  24  *
  25  *      If you have strange problems with nVidia chipset systems please
  26  *      see the SI support documentation and update your system BIOS
  27  *      if neccessary
  28  */
  29
  30 #include <linux/config.h>
  31 #include <linux/types.h>
  32 #include <linux/module.h>
  33 #include <linux/pci.h>
  34 #include <linux/delay.h>
  35 #include <linux/hdreg.h>
  36 #include <linux/ide.h>
  37 #include <linux/init.h>
  38
  39 #include <asm/io.h>
  40
  41 #undef SIIMAGE_VIRTUAL_DMAPIO
  42 #undef SIIMAGE_LARGE_DMA
  43
  44 /**
  45  *      pdev_is_sata            -       check if device is SATA
  46  *      @pdev:  PCI device to check
  47  *
  48  *      Returns true if this is a SATA controller
  49  */
  50
  51 static int pdev_is_sata(struct pci_dev *pdev)
  52 {
  53         switch(pdev->device)
  54         {
  55                 case PCI_DEVICE_ID_SII_3112:
  56                 case PCI_DEVICE_ID_SII_1210SA:
  57                         return 1;
  58                 case PCI_DEVICE_ID_SII_680:
  59                         return 0;
  60         }
  61         BUG();
  62         return 0;
  63 }
  64
  65 /**
  66  *      is_sata                 -       check if hwif is SATA
  67  *      @hwif:  interface to check
  68  *
  69  *      Returns true if this is a SATA controller
  70  */
  71
  72 static inline int is_sata(ide_hwif_t *hwif)
  73 {
  74         return pdev_is_sata(hwif->pci_dev);
  75 }
  76
  77 /**
  78  *      siimage_selreg          -       return register base
  79  *      @hwif: interface
  80  *      @r: config offset
  81  *
  82  *      Turn a config register offset into the right address in either
  83  *      PCI space or MMIO space to access the control register in question
  84  *      Thankfully this is a configuration operation so isnt performance
  85  *      criticial.
  86  */
  87
  88 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
  89 {
  90         unsigned long base = (unsigned long)hwif->hwif_data;
  91         base += 0xA0 + r;
  92         if(hwif->mmio)
  93                 base += (hwif->channel << 6);
  94         else
  95                 base += (hwif->channel << 4);
  96         return base;
  97 }
  98
  99 /**
 100  *      siimage_seldev          -       return register base
 101  *      @hwif: interface
 102  *      @r: config offset
 103  *
 104  *      Turn a config register offset into the right address in either
 105  *      PCI space or MMIO space to access the control register in question
 106  *      including accounting for the unit shift.
 107  */
 108
 109 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
 110 {
 111         ide_hwif_t *hwif        = HWIF(drive);
 112         unsigned long base = (unsigned long)hwif->hwif_data;
 113         base += 0xA0 + r;
 114         if(hwif->mmio)
 115                 base += (hwif->channel << 6);
 116         else
 117                 base += (hwif->channel << 4);
 118         base |= drive->select.b.unit << drive->select.b.unit;
 119         return base;
 120 }
 121
 122 /**
 123  *      siimage_ratemask        -       Compute available modes
 124  *      @drive: IDE drive
 125  *
 126  *      Compute the available speeds for the devices on the interface.
 127  *      For the CMD680 this depends on the clocking mode (scsc), for the
 128  *      SI3312 SATA controller life is a bit simpler. Enforce UDMA33
 129  *      as a limit if there is no 80pin cable present.
 130  */
 131
 132 static byte siimage_ratemask (ide_drive_t *drive)
 133 {
 134         ide_hwif_t *hwif        = HWIF(drive);
 135         u8 mode = 0, scsc = 0;
 136         unsigned long base = (unsigned long) hwif->hwif_data;
 137
 138         if (hwif->mmio)
 139                 scsc = hwif->INB(base + 0x4A);
 140         else
 141                 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
 142
 143         if(is_sata(hwif))
 144         {
 145                 if(strstr(drive->id->model, "Maxtor"))
 146                         return 3;
 147                 return 4;
 148         }
 149
 150         if ((scsc & 0x30) == 0x10)      /* 133 */
 151                 mode = 4;
 152         else if ((scsc & 0x30) == 0x20) /* 2xPCI */
 153                 mode = 4;
 154         else if ((scsc & 0x30) == 0x00) /* 100 */
 155                 mode = 3;
 156         else    /* Disabled ? */
 157                 BUG();
 158
 159         if (!eighty_ninty_three(drive))
 160                 mode = min(mode, (u8)1);
 161         return mode;
 162 }
 163
 164 /**
 165  *      siimage_taskfile_timing -       turn timing data to a mode
 166  *      @hwif: interface to query
 167  *
 168  *      Read the timing data for the interface and return the
 169  *      mode that is being used.
 170  */
 171
 172 static byte siimage_taskfile_timing (ide_hwif_t *hwif)
 173 {
 174         u16 timing      = 0x328a;
 175         unsigned long addr = siimage_selreg(hwif, 2);
 176
 177         if (hwif->mmio)
 178                 timing = hwif->INW(addr);
 179         else
 180                 pci_read_config_word(hwif->pci_dev, addr, &timing);
 181
 182         switch (timing) {
 183                 case 0x10c1:    return 4;
 184                 case 0x10c3:    return 3;
 185                 case 0x1104:
 186                 case 0x1281:    return 2;
 187                 case 0x2283:    return 1;
 188                 case 0x328a:
 189                 default:        return 0;
 190         }
 191 }
 192
 193 /**
 194  *      simmage_tuneproc        -       tune a drive
 195  *      @drive: drive to tune
 196  *      @mode_wanted: the target operating mode
 197  *
 198  *      Load the timing settings for this device mode into the
 199  *      controller. If we are in PIO mode 3 or 4 turn on IORDY
 200  *      monitoring (bit 9). The TF timing is bits 31:16
 201  */
 202
 203 static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted)
 204 {
 205         ide_hwif_t *hwif        = HWIF(drive);
 206         u32 speedt              = 0;
 207         u16 speedp              = 0;
 208         unsigned long addr      = siimage_seldev(drive, 0x04);
 209         unsigned long tfaddr    = siimage_selreg(hwif, 0x02);
 210
 211         /* cheat for now and use the docs */
 212         switch(mode_wanted) {
 213                 case 4:
 214                         speedp = 0x10c1;
 215                         speedt = 0x10c1;
 216                         break;
 217                 case 3:
 218                         speedp = 0x10C3;
 219                         speedt = 0x10C3;
 220                         break;
 221                 case 2:
 222                         speedp = 0x1104;
 223                         speedt = 0x1281;
 224                         break;
 225                 case 1:
 226                         speedp = 0x2283;
 227                         speedt = 0x1281;
 228                         break;
 229                 case 0:
 230                 default:
 231                         speedp = 0x328A;
 232                         speedt = 0x328A;
 233                         break;
 234         }
 235         if (hwif->mmio)
 236         {
 237                 hwif->OUTW(speedt, addr);
 238                 hwif->OUTW(speedp, tfaddr);
 239                 /* Now set up IORDY */
 240                 if(mode_wanted == 3 || mode_wanted == 4)
 241                         hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
 242                 else
 243                         hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
 244         }
 245         else
 246         {
 247                 pci_write_config_word(hwif->pci_dev, addr, speedp);
 248                 pci_write_config_word(hwif->pci_dev, tfaddr, speedt);
 249                 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp);
 250                 speedp &= ~0x200;
 251                 /* Set IORDY for mode 3 or 4 */
 252                 if(mode_wanted == 3 || mode_wanted == 4)
 253                         speedp |= 0x200;
 254                 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp);
 255         }
 256 }
 257
 258 /**
 259  *      config_siimage_chipset_for_pio  -       set drive timings
 260  *      @drive: drive to tune
 261  *      @speed we want
 262  *
 263  *      Compute the best pio mode we can for a given device. Also honour
 264  *      the timings for the driver when dealing with mixed devices. Some
 265  *      of this is ugly but its all wrapped up here
 266  *
 267  *      The SI680 can also do VDMA - we need to start using that
 268  *
 269  *      FIXME: we use the BIOS channel timings to avoid driving the task
 270  *      files too fast at the disk. We need to compute the master/slave
 271  *      drive PIO mode properly so that we can up the speed on a hotplug
 272  *      system.
 273  */
 274
 275 static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed)
 276 {
 277         u8 channel_timings      = siimage_taskfile_timing(HWIF(drive));
 278         u8 speed = 0, set_pio   = ide_get_best_pio_mode(drive, 4, 5, NULL);
 279
 280         /* WARNING PIO timing mess is going to happen b/w devices, argh */
 281         if ((channel_timings != set_pio) && (set_pio > channel_timings))
 282                 set_pio = channel_timings;
 283
 284         siimage_tuneproc(drive, set_pio);
 285         speed = XFER_PIO_0 + set_pio;
 286         if (set_speed)
 287                 (void) ide_config_drive_speed(drive, speed);
 288 }
 289
 290 static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
 291 {
 292         config_siimage_chipset_for_pio(drive, set_speed);
 293 }
 294
 295 /**
 296  *      siimage_tune_chipset    -       set controller timings
 297  *      @drive: Drive to set up
 298  *      @xferspeed: speed we want to achieve
 299  *
 300  *      Tune the SII chipset for the desired mode. If we can't achieve
 301  *      the desired mode then tune for a lower one, but ultimately
 302  *      make the thing work.
 303  */
 304
 305 static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed)
 306 {
 307         u8 ultra6[]             = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
 308         u8 ultra5[]             = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
 309         u16 dma[]               = { 0x2208, 0x10C2, 0x10C1 };
 310
 311         ide_hwif_t *hwif        = HWIF(drive);
 312         u16 ultra = 0, multi    = 0;
 313         u8 mode = 0, unit       = drive->select.b.unit;
 314         u8 speed                = ide_rate_filter(siimage_ratemask(drive), xferspeed);
 315         unsigned long base      = (unsigned long)hwif->hwif_data;
 316         u8 scsc = 0, addr_mask  = ((hwif->channel) ?
 317                                     ((hwif->mmio) ? 0xF4 : 0x84) :
 318                                     ((hwif->mmio) ? 0xB4 : 0x80));
 319
 320         unsigned long ma        = siimage_seldev(drive, 0x08);
 321         unsigned long ua        = siimage_seldev(drive, 0x0C);
 322
 323         if (hwif->mmio) {
 324                 scsc = hwif->INB(base + 0x4A);
 325                 mode = hwif->INB(base + addr_mask);
 326                 multi = hwif->INW(ma);
 327                 ultra = hwif->INW(ua);
 328         } else {
 329                 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
 330                 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
 331                 pci_read_config_word(hwif->pci_dev, ma, &multi);
 332                 pci_read_config_word(hwif->pci_dev, ua, &ultra);
 333         }
 334
 335         mode &= ~((unit) ? 0x30 : 0x03);
 336         ultra &= ~0x3F;
 337         scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
 338
 339         scsc = is_sata(hwif) ? 1 : scsc;
 340
 341         switch(speed) {
 342                 case XFER_PIO_4:
 343                 case XFER_PIO_3:
 344                 case XFER_PIO_2:
 345                 case XFER_PIO_1:
 346                 case XFER_PIO_0:
 347                         siimage_tuneproc(drive, (speed - XFER_PIO_0));
 348                         mode |= ((unit) ? 0x10 : 0x01);
 349                         break;
 350                 case XFER_MW_DMA_2:
 351                 case XFER_MW_DMA_1:
 352                 case XFER_MW_DMA_0:
 353                         multi = dma[speed - XFER_MW_DMA_0];
 354                         mode |= ((unit) ? 0x20 : 0x02);
 355                         config_siimage_chipset_for_pio(drive, 0);
 356                         break;
 357                 case XFER_UDMA_6:
 358                 case XFER_UDMA_5:
 359                 case XFER_UDMA_4:
 360                 case XFER_UDMA_3:
 361                 case XFER_UDMA_2:
 362                 case XFER_UDMA_1:
 363                 case XFER_UDMA_0:
 364                         multi = dma[2];
 365                         ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
 366                                            (ultra5[speed - XFER_UDMA_0]));
 367                         mode |= ((unit) ? 0x30 : 0x03);
 368                         config_siimage_chipset_for_pio(drive, 0);
 369                         break;
 370                 default:
 371                         return 1;
 372         }
 373
 374         if (hwif->mmio) {
 375                 hwif->OUTB(mode, base + addr_mask);
 376                 hwif->OUTW(multi, ma);
 377                 hwif->OUTW(ultra, ua);
 378         } else {
 379                 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
 380                 pci_write_config_word(hwif->pci_dev, ma, multi);
 381                 pci_write_config_word(hwif->pci_dev, ua, ultra);
 382         }
 383         return (ide_config_drive_speed(drive, speed));
 384 }
 385
 386 /**
 387  *      config_chipset_for_dma  -       configure for DMA
 388  *      @drive: drive to configure
 389  *
 390  *      Called by the IDE layer when it wants the timings set up.
 391  *      For the CMD680 we also need to set up the PIO timings and
 392  *      enable DMA.
 393  */
 394
 395 static int config_chipset_for_dma (ide_drive_t *drive)
 396 {
 397         u8 speed        = ide_dma_speed(drive, siimage_ratemask(drive));
 398
 399         config_chipset_for_pio(drive, !speed);
 400
 401         if (!speed)
 402                 return 0;
 403
 404         if (ide_set_xfer_rate(drive, speed))
 405                 return 0;
 406
 407         if (!drive->init_speed)
 408                 drive->init_speed = speed;
 409
 410         return ide_dma_enable(drive);
 411 }
 412
 413 /**
 414  *      siimage_configure_drive_for_dma -       set up for DMA transfers
 415  *      @drive: drive we are going to set up
 416  *
 417  *      Set up the drive for DMA, tune the controller and drive as
 418  *      required. If the drive isn't suitable for DMA or we hit
 419  *      other problems then we will drop down to PIO and set up
 420  *      PIO appropriately
 421  */
 422
 423 static int siimage_config_drive_for_dma (ide_drive_t *drive)
 424 {
 425         ide_hwif_t *hwif        = HWIF(drive);
 426         struct hd_driveid *id   = drive->id;
 427
 428         if ((id->capability & 1) != 0 && drive->autodma) {
 429
 430                 if (ide_use_dma(drive)) {
 431                         if (config_chipset_for_dma(drive))
 432                                 return hwif->ide_dma_on(drive);
 433                 }
 434
 435                 goto fast_ata_pio;
 436
 437         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 438 fast_ata_pio:
 439                 config_chipset_for_pio(drive, 1);
 440                 return hwif->ide_dma_off_quietly(drive);
 441         }
 442         /* IORDY not supported */
 443         return 0;
 444 }
 445
 446 /* returns 1 if dma irq issued, 0 otherwise */
 447 static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
 448 {
 449         ide_hwif_t *hwif        = HWIF(drive);
 450         u8 dma_altstat          = 0;
 451         unsigned long addr      = siimage_selreg(hwif, 1);
 452
 453         /* return 1 if INTR asserted */
 454         if ((hwif->INB(hwif->dma_status) & 4) == 4)
 455                 return 1;
 456
 457         /* return 1 if Device INTR asserted */
 458         pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat);
 459         if (dma_altstat & 8)
 460                 return 0;       //return 1;
 461         return 0;
 462 }
 463
 464 #if 0
 465 /**
 466  *      siimage_mmio_ide_dma_count      -       DMA bytes done
 467  *      @drive
 468  *
 469  *      If we are doing VDMA the CMD680 requires a little bit
 470  *      of more careful handling and we have to read the counts
 471  *      off ourselves. For non VDMA life is normal.
 472  */
 473
 474 static int siimage_mmio_ide_dma_count (ide_drive_t *drive)
 475 {
 476 #ifdef SIIMAGE_VIRTUAL_DMAPIO
 477         struct request *rq      = HWGROUP(drive)->rq;
 478         ide_hwif_t *hwif        = HWIF(drive);
 479         u32 count               = (rq->nr_sectors * SECTOR_SIZE);
 480         u32 rcount              = 0;
 481         unsigned long addr      = siimage_selreg(hwif, 0x1C);
 482
 483         hwif->OUTL(count, addr);
 484         rcount = hwif->INL(addr);
 485
 486         printk("\n%s: count = %d, rcount = %d, nr_sectors = %lu\n",
 487                 drive->name, count, rcount, rq->nr_sectors);
 488
 489 #endif /* SIIMAGE_VIRTUAL_DMAPIO */
 490         return __ide_dma_count(drive);
 491 }
 492 #endif
 493
 494 /**
 495  *      siimage_mmio_ide_dma_test_irq   -       check we caused an IRQ
 496  *      @drive: drive we are testing
 497  *
 498  *      Check if we caused an IDE DMA interrupt. We may also have caused
 499  *      SATA status interrupts, if so we clean them up and continue.
 500  */
 501
 502 static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
 503 {
 504         ide_hwif_t *hwif        = HWIF(drive);
 505         unsigned long base      = (unsigned long)hwif->hwif_data;
 506         unsigned long addr      = siimage_selreg(hwif, 0x1);
 507
 508         if (SATA_ERROR_REG) {
 509                 u32 ext_stat = hwif->INL(base + 0x10);
 510                 u8 watchdog = 0;
 511                 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
 512                         u32 sata_error = hwif->INL(SATA_ERROR_REG);
 513                         hwif->OUTL(sata_error, SATA_ERROR_REG);
 514                         watchdog = (sata_error & 0x00680000) ? 1 : 0;
 515 #if 1
 516                         printk(KERN_WARNING "%s: sata_error = 0x%08x, "
 517                                 "watchdog = %d, %s\n",
 518                                 drive->name, sata_error, watchdog,
 519                                 __FUNCTION__);
 520 #endif
 521
 522                 } else {
 523                         watchdog = (ext_stat & 0x8000) ? 1 : 0;
 524                 }
 525                 ext_stat >>= 16;
 526
 527                 if (!(ext_stat & 0x0404) && !watchdog)
 528                         return 0;
 529         }
 530
 531         /* return 1 if INTR asserted */
 532         if ((hwif->INB(hwif->dma_status) & 0x04) == 0x04)
 533                 return 1;
 534
 535         /* return 1 if Device INTR asserted */
 536         if ((hwif->INB(addr) & 8) == 8)
 537                 return 0;       //return 1;
 538
 539         return 0;
 540 }
 541
 542 /**
 543  *      siimage_busproc         -       bus isolation ioctl
 544  *      @drive: drive to isolate/restore
 545  *      @state: bus state to set
 546  *
 547  *      Used by the SII3112 to handle bus isolation. As this is a
 548  *      SATA controller the work required is quite limited, we
 549  *      just have to clean up the statistics
 550  */
 551
 552 static int siimage_busproc (ide_drive_t * drive, int state)
 553 {
 554         ide_hwif_t *hwif        = HWIF(drive);
 555         u32 stat_config         = 0;
 556         unsigned long addr      = siimage_selreg(hwif, 0);
 557
 558         if (hwif->mmio) {
 559                 stat_config = hwif->INL(addr);
 560         } else
 561                 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
 562
 563         switch (state) {
 564                 case BUSSTATE_ON:
 565                         hwif->drives[0].failures = 0;
 566                         hwif->drives[1].failures = 0;
 567                         break;
 568                 case BUSSTATE_OFF:
 569                         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 570                         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 571                         break;
 572                 case BUSSTATE_TRISTATE:
 573                         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 574                         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 575                         break;
 576                 default:
 577                         return -EINVAL;
 578         }
 579         hwif->bus_state = state;
 580         return 0;
 581 }
 582
 583 /**
 584  *      siimage_reset_poll      -       wait for sata reset
 585  *      @drive: drive we are resetting
 586  *
 587  *      Poll the SATA phy and see whether it has come back from the dead
 588  *      yet.
 589  */
 590
 591 static int siimage_reset_poll (ide_drive_t *drive)
 592 {
 593         if (SATA_STATUS_REG) {
 594                 ide_hwif_t *hwif        = HWIF(drive);
 595
 596                 if ((hwif->INL(SATA_STATUS_REG) & 0x03) != 0x03) {
 597                         printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
 598                                 hwif->name, hwif->INL(SATA_STATUS_REG));
 599                         HWGROUP(drive)->polling = 0;
 600                         return ide_started;
 601                 }
 602                 return 0;
 603         } else {
 604                 return 0;
 605         }
 606 }
 607
 608 /**
 609  *      siimage_pre_reset       -       reset hook
 610  *      @drive: IDE device being reset
 611  *
 612  *      For the SATA devices we need to handle recalibration/geometry
 613  *      differently
 614  */
 615
 616 static void siimage_pre_reset (ide_drive_t *drive)
 617 {
 618         if (drive->media != ide_disk)
 619                 return;
 620
 621         if (is_sata(HWIF(drive)))
 622         {
 623                 drive->special.b.set_geometry = 0;
 624                 drive->special.b.recalibrate = 0;
 625         }
 626 }
 627
 628 /**
 629  *      siimage_reset   -       reset a device on an siimage controller
 630  *      @drive: drive to reset
 631  *
 632  *      Perform a controller level reset fo the device. For
 633  *      SATA we must also check the PHY.
 634  */
 635
 636 static void siimage_reset (ide_drive_t *drive)
 637 {
 638         ide_hwif_t *hwif        = HWIF(drive);
 639         u8 reset                = 0;
 640         unsigned long addr      = siimage_selreg(hwif, 0);
 641
 642         if (hwif->mmio) {
 643                 reset = hwif->INB(addr);
 644                 hwif->OUTB((reset|0x03), addr);
 645                 /* FIXME:posting */
 646                 udelay(25);
 647                 hwif->OUTB(reset, addr);
 648                 (void) hwif->INB(addr);
 649         } else {
 650                 pci_read_config_byte(hwif->pci_dev, addr, &reset);
 651                 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03);
 652                 udelay(25);
 653                 pci_write_config_byte(hwif->pci_dev, addr, reset);
 654                 pci_read_config_byte(hwif->pci_dev, addr, &reset);
 655         }
 656
 657         if (SATA_STATUS_REG) {
 658                 u32 sata_stat = hwif->INL(SATA_STATUS_REG);
 659                 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
 660                         hwif->name, sata_stat, __FUNCTION__);
 661                 if (!(sata_stat)) {
 662                         printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
 663                                 hwif->name, sata_stat);
 664                         drive->failures++;
 665                 }
 666         }
 667
 668 }
 669
 670 /**
 671  *      proc_reports_siimage            -       add siimage controller to proc
 672  *      @dev: PCI device
 673  *      @clocking: SCSC value
 674  *      @name: controller name
 675  *
 676  *      Report the clocking mode of the controller and add it to
 677  *      the /proc interface layer
 678  */
 679
 680 static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
 681 {
 682         if (!pdev_is_sata(dev)) {
 683                 printk(KERN_INFO "%s: BASE CLOCK ", name);
 684                 clocking &= 0x03;
 685                 switch (clocking) {
 686                         case 0x03: printk("DISABLED!\n"); break;
 687                         case 0x02: printk("== 2X PCI\n"); break;
 688                         case 0x01: printk("== 133\n"); break;
 689                         case 0x00: printk("== 100\n"); break;
 690                 }
 691         }
 692 }
 693
 694 /**
 695  *      setup_mmio_siimage      -       switch an SI controller into MMIO
 696  *      @dev: PCI device we are configuring
 697  *      @name: device name
 698  *
 699  *      Attempt to put the device into mmio mode. There are some slight
 700  *      complications here with certain systems where the mmio bar isnt
 701  *      mapped so we have to be sure we can fall back to I/O.
 702  */
 703
 704 static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
 705 {
 706         unsigned long bar5      = pci_resource_start(dev, 5);
 707         unsigned long barsize   = pci_resource_len(dev, 5);
 708         u8 tmpbyte      = 0;
 709         void __iomem *ioaddr;
 710         u32 tmp, irq_mask;
 711
 712         /*
 713          *      Drop back to PIO if we can't map the mmio. Some
 714          *      systems seem to get terminally confused in the PCI
 715          *      spaces.
 716          */
 717
 718         if(!request_mem_region(bar5, barsize, name))
 719         {
 720                 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
 721                 return 0;
 722         }
 723
 724         ioaddr = ioremap(bar5, barsize);
 725
 726         if (ioaddr == NULL)
 727         {
 728                 release_mem_region(bar5, barsize);
 729                 return 0;
 730         }
 731
 732         pci_set_master(dev);
 733         pci_set_drvdata(dev, (void *) ioaddr);
 734
 735         if (pdev_is_sata(dev)) {
 736                 /* make sure IDE0/1 interrupts are not masked */
 737                 irq_mask = (1 << 22) | (1 << 23);
 738                 tmp = readl(ioaddr + 0x48);
 739                 if (tmp & irq_mask) {
 740                         tmp &= ~irq_mask;
 741                         writel(tmp, ioaddr + 0x48);
 742                         readl(ioaddr + 0x48); /* flush */
 743                 }
 744                 writel(0, ioaddr + 0x148);
 745                 writel(0, ioaddr + 0x1C8);
 746         }
 747
 748         writeb(0, ioaddr + 0xB4);
 749         writeb(0, ioaddr + 0xF4);
 750         tmpbyte = readb(ioaddr + 0x4A);
 751
 752         switch(tmpbyte & 0x30) {
 753                 case 0x00:
 754                         /* In 100 MHz clocking, try and switch to 133 */
 755                         writeb(tmpbyte|0x10, ioaddr + 0x4A);
 756                         break;
 757                 case 0x10:
 758                         /* On 133Mhz clocking */
 759                         break;
 760                 case 0x20:
 761                         /* On PCIx2 clocking */
 762                         break;
 763                 case 0x30:
 764                         /* Clocking is disabled */
 765                         /* 133 clock attempt to force it on */
 766                         writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
 767                         break;
 768         }
 769
 770         writeb(      0x72, ioaddr + 0xA1);
 771         writew(    0x328A, ioaddr + 0xA2);
 772         writel(0x62DD62DD, ioaddr + 0xA4);
 773         writel(0x43924392, ioaddr + 0xA8);
 774         writel(0x40094009, ioaddr + 0xAC);
 775         writeb(      0x72, ioaddr + 0xE1);
 776         writew(    0x328A, ioaddr + 0xE2);
 777         writel(0x62DD62DD, ioaddr + 0xE4);
 778         writel(0x43924392, ioaddr + 0xE8);
 779         writel(0x40094009, ioaddr + 0xEC);
 780
 781         if (pdev_is_sata(dev)) {
 782                 writel(0xFFFF0000, ioaddr + 0x108);
 783                 writel(0xFFFF0000, ioaddr + 0x188);
 784                 writel(0x00680000, ioaddr + 0x148);
 785                 writel(0x00680000, ioaddr + 0x1C8);
 786         }
 787
 788         tmpbyte = readb(ioaddr + 0x4A);
 789
 790         proc_reports_siimage(dev, (tmpbyte>>4), name);
 791         return 1;
 792 }
 793
 794 /**
 795  *      init_chipset_siimage    -       set up an SI device
 796  *      @dev: PCI device
 797  *      @name: device name
 798  *
 799  *      Perform the initial PCI set up for this device. Attempt to switch
 800  *      to 133MHz clocking if the system isn't already set up to do it.
 801  */
 802
 803 static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
 804 {
 805         u32 class_rev   = 0;
 806         u8 tmpbyte      = 0;
 807         u8 BA5_EN       = 0;
 808
 809         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 810         class_rev &= 0xff;
 811         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
 812
 813         pci_read_config_byte(dev, 0x8A, &BA5_EN);
 814         if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
 815                 if (setup_mmio_siimage(dev, name)) {
 816                         return 0;
 817                 }
 818         }
 819
 820         pci_write_config_byte(dev, 0x80, 0x00);
 821         pci_write_config_byte(dev, 0x84, 0x00);
 822         pci_read_config_byte(dev, 0x8A, &tmpbyte);
 823         switch(tmpbyte & 0x30) {
 824                 case 0x00:
 825                         /* 133 clock attempt to force it on */
 826                         pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
 827                 case 0x30:
 828                         /* if clocking is disabled */
 829                         /* 133 clock attempt to force it on */
 830                         pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
 831                 case 0x10:
 832                         /* 133 already */
 833                         break;
 834                 case 0x20:
 835                         /* BIOS set PCI x2 clocking */
 836                         break;
 837         }
 838
 839         pci_read_config_byte(dev,   0x8A, &tmpbyte);
 840
 841         pci_write_config_byte(dev,  0xA1, 0x72);
 842         pci_write_config_word(dev,  0xA2, 0x328A);
 843         pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
 844         pci_write_config_dword(dev, 0xA8, 0x43924392);
 845         pci_write_config_dword(dev, 0xAC, 0x40094009);
 846         pci_write_config_byte(dev,  0xB1, 0x72);
 847         pci_write_config_word(dev,  0xB2, 0x328A);
 848         pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
 849         pci_write_config_dword(dev, 0xB8, 0x43924392);
 850         pci_write_config_dword(dev, 0xBC, 0x40094009);
 851
 852         proc_reports_siimage(dev, (tmpbyte>>4), name);
 853         return 0;
 854 }
 855
 856 /**
 857  *      init_mmio_iops_siimage  -       set up the iops for MMIO
 858  *      @hwif: interface to set up
 859  *
 860  *      The basic setup here is fairly simple, we can use standard MMIO
 861  *      operations. However we do have to set the taskfile register offsets
 862  *      by hand as there isnt a standard defined layout for them this
 863  *      time.
 864  *
 865  *      The hardware supports buffered taskfiles and also some rather nice
 866  *      extended PRD tables. Unfortunately right now we don't.
 867  */
 868
 869 static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
 870 {
 871         struct pci_dev *dev     = hwif->pci_dev;
 872         void *addr              = pci_get_drvdata(dev);
 873         u8 ch                   = hwif->channel;
 874         hw_regs_t               hw;
 875         unsigned long           base;
 876
 877         /*
 878          *      Fill in the basic HWIF bits
 879          */
 880
 881         default_hwif_mmiops(hwif);
 882         hwif->hwif_data                 = addr;
 883
 884         /*
 885          *      Now set up the hw. We have to do this ourselves as
 886          *      the MMIO layout isnt the same as the the standard port
 887          *      based I/O
 888          */
 889
 890         memset(&hw, 0, sizeof(hw_regs_t));
 891
 892         base = (unsigned long)addr;
 893         if (ch)
 894                 base += 0xC0;
 895         else
 896                 base += 0x80;
 897
 898         /*
 899          *      The buffered task file doesn't have status/control
 900          *      so we can't currently use it sanely since we want to
 901          *      use LBA48 mode.
 902          */
 903 //      base += 0x10;
 904 //      hwif->no_lba48 = 1;
 905
 906         hw.io_ports[IDE_DATA_OFFSET]    = base;
 907         hw.io_ports[IDE_ERROR_OFFSET]   = base + 1;
 908         hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
 909         hw.io_ports[IDE_SECTOR_OFFSET]  = base + 3;
 910         hw.io_ports[IDE_LCYL_OFFSET]    = base + 4;
 911         hw.io_ports[IDE_HCYL_OFFSET]    = base + 5;
 912         hw.io_ports[IDE_SELECT_OFFSET]  = base + 6;
 913         hw.io_ports[IDE_STATUS_OFFSET]  = base + 7;
 914         hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
 915
 916         hw.io_ports[IDE_IRQ_OFFSET]     = 0;
 917
 918         if (pdev_is_sata(dev)) {
 919                 base = (unsigned long)addr;
 920                 if (ch)
 921                         base += 0x80;
 922                 hwif->sata_scr[SATA_STATUS_OFFSET]      = base + 0x104;
 923                 hwif->sata_scr[SATA_ERROR_OFFSET]       = base + 0x108;
 924                 hwif->sata_scr[SATA_CONTROL_OFFSET]     = base + 0x100;
 925                 hwif->sata_misc[SATA_MISC_OFFSET]       = base + 0x140;
 926                 hwif->sata_misc[SATA_PHY_OFFSET]        = base + 0x144;
 927                 hwif->sata_misc[SATA_IEN_OFFSET]        = base + 0x148;
 928         }
 929
 930         hw.irq                          = hwif->pci_dev->irq;
 931
 932         memcpy(&hwif->hw, &hw, sizeof(hw));
 933         memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
 934
 935         hwif->irq                       = hw.irq;
 936
 937         base = (unsigned long) addr;
 938
 939 #ifdef SIIMAGE_LARGE_DMA
 940 /* Watch the brackets - even Ken and Dennis get some language design wrong */
 941         hwif->dma_base                  = base + (ch ? 0x18 : 0x10);
 942         hwif->dma_base2                 = base + (ch ? 0x08 : 0x00);
 943         hwif->dma_prdtable              = hwif->dma_base2 + 4;
 944 #else /* ! SIIMAGE_LARGE_DMA */
 945         hwif->dma_base                  = base + (ch ? 0x08 : 0x00);
 946         hwif->dma_base2                 = base + (ch ? 0x18 : 0x10);
 947 #endif /* SIIMAGE_LARGE_DMA */
 948         hwif->mmio                      = 2;
 949 }
 950
 951 static int is_dev_seagate_sata(ide_drive_t *drive)
 952 {
 953         const char *s = &drive->id->model[0];
 954         unsigned len;
 955
 956         if (!drive->present)
 957                 return 0;
 958
 959         len = strnlen(s, sizeof(drive->id->model));
 960
 961         if ((len > 4) && (!memcmp(s, "ST", 2))) {
 962                 if ((!memcmp(s + len - 2, "AS", 2)) ||
 963                     (!memcmp(s + len - 3, "ASL", 3))) {
 964                         printk(KERN_INFO "%s: applying pessimistic Seagate "
 965                                          "errata fix\n", drive->name);
 966                         return 1;
 967                 }
 968         }
 969         return 0;
 970 }
 971
 972 /**
 973  *      siimage_fixup           -       post probe fixups
 974  *      @hwif: interface to fix up
 975  *
 976  *      Called after drive probe we use this to decide whether the
 977  *      Seagate fixup must be applied. This used to be in init_iops but
 978  *      that can occur before we know what drives are present.
 979  */
 980
 981 static void __devinit siimage_fixup(ide_hwif_t *hwif)
 982 {
 983         /* Try and raise the rqsize */
 984         if (!is_sata(hwif) || !is_dev_seagate_sata(&hwif->drives[0]))
 985                 hwif->rqsize = 128;
 986 }
 987
 988 /**
 989  *      init_iops_siimage       -       set up iops
 990  *      @hwif: interface to set up
 991  *
 992  *      Do the basic setup for the SIIMAGE hardware interface
 993  *      and then do the MMIO setup if we can. This is the first
 994  *      look in we get for setting up the hwif so that we
 995  *      can get the iops right before using them.
 996  */
 997
 998 static void __devinit init_iops_siimage(ide_hwif_t *hwif)
 999 {
1000         struct pci_dev *dev     = hwif->pci_dev;
1001         u32 class_rev           = 0;
1002
1003         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1004         class_rev &= 0xff;
1005
1006         hwif->hwif_data = NULL;
1007
1008         /* Pessimal until we finish probing */
1009         hwif->rqsize = 15;
1010
1011         if (pci_get_drvdata(dev) == NULL)
1012                 return;
1013         init_mmio_iops_siimage(hwif);
1014 }
1015
1016 /**
1017  *      ata66_siimage   -       check for 80 pin cable
1018  *      @hwif: interface to check
1019  *
1020  *      Check for the presence of an ATA66 capable cable on the
1021  *      interface.
1022  */
1023
1024 static unsigned int __devinit ata66_siimage(ide_hwif_t *hwif)
1025 {
1026         unsigned long addr = siimage_selreg(hwif, 0);
1027         if (pci_get_drvdata(hwif->pci_dev) == NULL) {
1028                 u8 ata66 = 0;
1029                 pci_read_config_byte(hwif->pci_dev, addr, &ata66);
1030                 return (ata66 & 0x01) ? 1 : 0;
1031         }
1032
1033         return (hwif->INB(addr) & 0x01) ? 1 : 0;
1034 }
1035
1036 /**
1037  *      init_hwif_siimage       -       set up hwif structs
1038  *      @hwif: interface to set up
1039  *
1040  *      We do the basic set up of the interface structure. The SIIMAGE
1041  *      requires several custom handlers so we override the default
1042  *      ide DMA handlers appropriately
1043  */
1044
1045 static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
1046 {
1047         hwif->autodma = 0;
1048
1049         hwif->resetproc = &siimage_reset;
1050         hwif->speedproc = &siimage_tune_chipset;
1051         hwif->tuneproc  = &siimage_tuneproc;
1052         hwif->reset_poll = &siimage_reset_poll;
1053         hwif->pre_reset = &siimage_pre_reset;
1054
1055         if(is_sata(hwif))
1056                 hwif->busproc   = &siimage_busproc;
1057
1058         if (!hwif->dma_base) {
1059                 hwif->drives[0].autotune = 1;
1060                 hwif->drives[1].autotune = 1;
1061                 return;
1062         }
1063
1064         hwif->ultra_mask = 0x7f;
1065         hwif->mwdma_mask = 0x07;
1066         hwif->swdma_mask = 0x07;
1067
1068         if (!is_sata(hwif))
1069                 hwif->atapi_dma = 1;
1070
1071         hwif->ide_dma_check = &siimage_config_drive_for_dma;
1072         if (!(hwif->udma_four))
1073                 hwif->udma_four = ata66_siimage(hwif);
1074
1075         if (hwif->mmio) {
1076                 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
1077         } else {
1078                 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
1079         }
1080
1081         /*
1082          *      The BIOS often doesn't set up DMA on this controller
1083          *      so we always do it.
1084          */
1085
1086         hwif->autodma = 1;
1087         hwif->drives[0].autodma = hwif->autodma;
1088         hwif->drives[1].autodma = hwif->autodma;
1089 }
1090
1091 #define DECLARE_SII_DEV(name_str)                       \
1092         {                                               \
1093                 .name           = name_str,             \
1094                 .init_chipset   = init_chipset_siimage, \
1095                 .init_iops      = init_iops_siimage,    \
1096                 .init_hwif      = init_hwif_siimage,    \
1097                 .fixup          = siimage_fixup,        \
1098                 .channels       = 2,                    \
1099                 .autodma        = AUTODMA,              \
1100                 .bootable       = ON_BOARD,             \
1101         }
1102
1103 static ide_pci_device_t siimage_chipsets[] __devinitdata = {
1104         /* 0 */ DECLARE_SII_DEV("SiI680"),
1105         /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
1106         /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
1107 };
1108
1109 /**
1110  *      siimage_init_one        -       pci layer discovery entry
1111  *      @dev: PCI device
1112  *      @id: ident table entry
1113  *
1114  *      Called by the PCI code when it finds an SI680 or SI3112 controller.
1115  *      We then use the IDE PCI generic helper to do most of the work.
1116  */
1117
1118 static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1119 {
1120         return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]);
1121 }
1122
1123 static struct pci_device_id siimage_pci_tbl[] = {
1124         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1125 #ifdef CONFIG_BLK_DEV_IDE_SATA
1126         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1127         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1128 #endif
1129         { 0, },
1130 };
1131 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
1132
1133 static struct pci_driver driver = {
1134         .name           = "SiI_IDE",
1135         .id_table       = siimage_pci_tbl,
1136         .probe          = siimage_init_one,
1137 };
1138
1139 static int siimage_ide_init(void)
1140 {
1141         return ide_pci_register_driver(&driver);
1142 }
1143
1144 module_init(siimage_ide_init);
1145
1146 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1147 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1148 MODULE_LICENSE("GPL");