?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
drm/radeon: prep for r6xx/r7xx support
[linux-2.6/mini2440.git] / drivers / gpu / drm / radeon / radeon_drv.h
blob9326c73976cf3e63889226d1b995ab0729c7d5f1
1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
33
34 /* General customization:
35 */
36
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20080528"
42
43 /* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading).
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 * 1.17- Add initial support for R300 (3D).
86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
90 * 1.19- Add support for gart table in FB memory and PCIE r300
91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
94 * 1.23- Add new radeon memory map work from benh
95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
100 * 1.28- Add support for VBL on CRTC2
101 * 1.29- R500 3D cmd buffer support
102 */
103 #define DRIVER_MAJOR 1
104 #define DRIVER_MINOR 29
105 #define DRIVER_PATCHLEVEL 0
106
107 /*
108 * Radeon chip families
109 */
110 enum radeon_family {
111 CHIP_R100,
112 CHIP_RV100,
113 CHIP_RS100,
114 CHIP_RV200,
115 CHIP_RS200,
116 CHIP_R200,
117 CHIP_RV250,
118 CHIP_RS300,
119 CHIP_RV280,
120 CHIP_R300,
121 CHIP_R350,
122 CHIP_RV350,
123 CHIP_RV380,
124 CHIP_R420,
125 CHIP_R423,
126 CHIP_RV410,
127 CHIP_RS400,
128 CHIP_RS480,
129 CHIP_RS690,
130 CHIP_RS740,
131 CHIP_RV515,
132 CHIP_R520,
133 CHIP_RV530,
134 CHIP_RV560,
135 CHIP_RV570,
136 CHIP_R580,
137 CHIP_R600,
138 CHIP_RV610,
139 CHIP_RV630,
140 CHIP_RV620,
141 CHIP_RV635,
142 CHIP_RV670,
143 CHIP_RS780,
144 CHIP_RV770,
145 CHIP_RV730,
146 CHIP_RV710,
147 CHIP_LAST,
148 };
149
150 enum radeon_cp_microcode_version {
151 UCODE_R100,
152 UCODE_R200,
153 UCODE_R300,
154 };
155
156 /*
157 * Chip flags
158 */
159 enum radeon_chip_flags {
160 RADEON_FAMILY_MASK = 0x0000ffffUL,
161 RADEON_FLAGS_MASK = 0xffff0000UL,
162 RADEON_IS_MOBILITY = 0x00010000UL,
163 RADEON_IS_IGP = 0x00020000UL,
164 RADEON_SINGLE_CRTC = 0x00040000UL,
165 RADEON_IS_AGP = 0x00080000UL,
166 RADEON_HAS_HIERZ = 0x00100000UL,
167 RADEON_IS_PCIE = 0x00200000UL,
168 RADEON_NEW_MEMMAP = 0x00400000UL,
169 RADEON_IS_PCI = 0x00800000UL,
170 RADEON_IS_IGPGART = 0x01000000UL,
171 };
172
173 typedef struct drm_radeon_freelist {
174 unsigned int age;
175 struct drm_buf *buf;
176 struct drm_radeon_freelist *next;
177 struct drm_radeon_freelist *prev;
178 } drm_radeon_freelist_t;
179
180 typedef struct drm_radeon_ring_buffer {
181 u32 *start;
182 u32 *end;
183 int size;
184 int size_l2qw;
185
186 int rptr_update; /* Double Words */
187 int rptr_update_l2qw; /* log2 Quad Words */
188
189 int fetch_size; /* Double Words */
190 int fetch_size_l2ow; /* log2 Oct Words */
191
192 u32 tail;
193 u32 tail_mask;
194 int space;
195
196 int high_mark;
197 } drm_radeon_ring_buffer_t;
198
199 typedef struct drm_radeon_depth_clear_t {
200 u32 rb3d_cntl;
201 u32 rb3d_zstencilcntl;
202 u32 se_cntl;
203 } drm_radeon_depth_clear_t;
204
205 struct drm_radeon_driver_file_fields {
206 int64_t radeon_fb_delta;
207 };
208
209 struct mem_block {
210 struct mem_block *next;
211 struct mem_block *prev;
212 int start;
213 int size;
214 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
215 };
216
217 struct radeon_surface {
218 int refcount;
219 u32 lower;
220 u32 upper;
221 u32 flags;
222 };
223
224 struct radeon_virt_surface {
225 int surface_index;
226 u32 lower;
227 u32 upper;
228 u32 flags;
229 struct drm_file *file_priv;
230 #define PCIGART_FILE_PRIV ((void *) -1L)
231 };
232
233 #define RADEON_FLUSH_EMITED (1 << 0)
234 #define RADEON_PURGE_EMITED (1 << 1)
235
236 struct drm_radeon_master_private {
237 drm_local_map_t *sarea;
238 drm_radeon_sarea_t *sarea_priv;
239 };
240
241 typedef struct drm_radeon_private {
242 drm_radeon_ring_buffer_t ring;
243
244 u32 fb_location;
245 u32 fb_size;
246 int new_memmap;
247
248 int gart_size;
249 u32 gart_vm_start;
250 unsigned long gart_buffers_offset;
251
252 int cp_mode;
253 int cp_running;
254
255 drm_radeon_freelist_t *head;
256 drm_radeon_freelist_t *tail;
257 int last_buf;
258 int writeback_works;
259
260 int usec_timeout;
261
262 int microcode_version;
263
264 struct {
265 u32 boxes;
266 int freelist_timeouts;
267 int freelist_loops;
268 int requested_bufs;
269 int last_frame_reads;
270 int last_clear_reads;
271 int clears;
272 int texture_uploads;
273 } stats;
274
275 int do_boxes;
276 int page_flipping;
277
278 u32 color_fmt;
279 unsigned int front_offset;
280 unsigned int front_pitch;
281 unsigned int back_offset;
282 unsigned int back_pitch;
283
284 u32 depth_fmt;
285 unsigned int depth_offset;
286 unsigned int depth_pitch;
287
288 u32 front_pitch_offset;
289 u32 back_pitch_offset;
290 u32 depth_pitch_offset;
291
292 drm_radeon_depth_clear_t depth_clear;
293
294 unsigned long ring_offset;
295 unsigned long ring_rptr_offset;
296 unsigned long buffers_offset;
297 unsigned long gart_textures_offset;
298
299 drm_local_map_t *sarea;
300 drm_local_map_t *cp_ring;
301 drm_local_map_t *ring_rptr;
302 drm_local_map_t *gart_textures;
303
304 struct mem_block *gart_heap;
305 struct mem_block *fb_heap;
306
307 /* SW interrupt */
308 wait_queue_head_t swi_queue;
309 atomic_t swi_emitted;
310 int vblank_crtc;
311 uint32_t irq_enable_reg;
312 uint32_t r500_disp_irq_reg;
313
314 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
315 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
316
317 unsigned long pcigart_offset;
318 unsigned int pcigart_offset_set;
319 struct drm_ati_pcigart_info gart_info;
320
321 u32 scratch_ages[5];
322
323 /* starting from here on, data is preserved accross an open */
324 uint32_t flags; /* see radeon_chip_flags */
325 resource_size_t fb_aper_offset;
326
327 int num_gb_pipes;
328 int track_flush;
329 drm_local_map_t *mmio;
330
331 /* r6xx/r7xx pipe/shader config */
332 int r600_max_pipes;
333 int r600_max_tile_pipes;
334 int r600_max_simds;
335 int r600_max_backends;
336 int r600_max_gprs;
337 int r600_max_threads;
338 int r600_max_stack_entries;
339 int r600_max_hw_contexts;
340 int r600_max_gs_threads;
341 int r600_sx_max_export_size;
342 int r600_sx_max_export_pos_size;
343 int r600_sx_max_export_smx_size;
344 int r600_sq_num_cf_insts;
345 int r700_sx_num_of_sets;
346 int r700_sc_prim_fifo_size;
347 int r700_sc_hiz_tile_fifo_size;
348 int r700_sc_earlyz_tile_fifo_fize;
349
350 } drm_radeon_private_t;
351
352 typedef struct drm_radeon_buf_priv {
353 u32 age;
354 } drm_radeon_buf_priv_t;
355
356 typedef struct drm_radeon_kcmd_buffer {
357 int bufsz;
358 char *buf;
359 int nbox;
360 struct drm_clip_rect __user *boxes;
361 } drm_radeon_kcmd_buffer_t;
362
363 extern int radeon_no_wb;
364 extern struct drm_ioctl_desc radeon_ioctls[];
365 extern int radeon_max_ioctl;
366
367 extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv);
368 extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
369
370 #define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv)
371 #define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)
372
373 /* Check whether the given hardware address is inside the framebuffer or the
374 * GART area.
375 */
376 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
377 u64 off)
378 {
379 u32 fb_start = dev_priv->fb_location;
380 u32 fb_end = fb_start + dev_priv->fb_size - 1;
381 u32 gart_start = dev_priv->gart_vm_start;
382 u32 gart_end = gart_start + dev_priv->gart_size - 1;
383
384 return ((off >= fb_start && off <= fb_end) ||
385 (off >= gart_start && off <= gart_end));
386 }
387
388 /* radeon_cp.c */
389 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
390 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
391 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
392 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
393 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
394 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
395 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
396 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
397 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
398 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
399 extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr);
400
401 extern void radeon_freelist_reset(struct drm_device * dev);
402 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
403
404 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
405
406 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
407
408 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
409 extern int radeon_presetup(struct drm_device *dev);
410 extern int radeon_driver_postcleanup(struct drm_device *dev);
411
412 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
413 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
414 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
415 extern void radeon_mem_takedown(struct mem_block **heap);
416 extern void radeon_mem_release(struct drm_file *file_priv,
417 struct mem_block *heap);
418
419 /* radeon_irq.c */
420 extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
421 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
422 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
423
424 extern void radeon_do_release(struct drm_device * dev);
425 extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
426 extern int radeon_enable_vblank(struct drm_device *dev, int crtc);
427 extern void radeon_disable_vblank(struct drm_device *dev, int crtc);
428 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
429 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
430 extern int radeon_driver_irq_postinstall(struct drm_device *dev);
431 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
432 extern void radeon_enable_interrupt(struct drm_device *dev);
433 extern int radeon_vblank_crtc_get(struct drm_device *dev);
434 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
435
436 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
437 extern int radeon_driver_unload(struct drm_device *dev);
438 extern int radeon_driver_firstopen(struct drm_device *dev);
439 extern void radeon_driver_preclose(struct drm_device *dev,
440 struct drm_file *file_priv);
441 extern void radeon_driver_postclose(struct drm_device *dev,
442 struct drm_file *file_priv);
443 extern void radeon_driver_lastclose(struct drm_device * dev);
444 extern int radeon_driver_open(struct drm_device *dev,
445 struct drm_file *file_priv);
446 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
447 unsigned long arg);
448
449 extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
450 extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
451 extern void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master);
452 /* r300_cmdbuf.c */
453 extern void r300_init_reg_flags(struct drm_device *dev);
454
455 extern int r300_do_cp_cmdbuf(struct drm_device *dev,
456 struct drm_file *file_priv,
457 drm_radeon_kcmd_buffer_t *cmdbuf);
458
459 /* Flags for stats.boxes
460 */
461 #define RADEON_BOX_DMA_IDLE 0x1
462 #define RADEON_BOX_RING_FULL 0x2
463 #define RADEON_BOX_FLIP 0x4
464 #define RADEON_BOX_WAIT_IDLE 0x8
465 #define RADEON_BOX_TEXTURE_LOAD 0x10
466
467 /* Register definitions, register access macros and drmAddMap constants
468 * for Radeon kernel driver.
469 */
470 #define RADEON_MM_INDEX 0x0000
471 #define RADEON_MM_DATA 0x0004
472
473 #define RADEON_AGP_COMMAND 0x0f60
474 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
475 # define RADEON_AGP_ENABLE (1<<8)
476 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
477 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
478 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
479 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
480 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
481 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
482 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
483
484 /*
485 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
486 * don't have an explicit bus mastering disable bit. It's handled
487 * by the PCI D-states. PMI_BM_DIS disables D-state bus master
488 * handling, not bus mastering itself.
489 */
490 #define RADEON_BUS_CNTL 0x0030
491 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
492 # define RADEON_BUS_MASTER_DIS (1 << 6)
493 /* rs600/rs690/rs740 */
494 # define RS600_BUS_MASTER_DIS (1 << 14)
495 # define RS600_MSI_REARM (1 << 20)
496 /* see RS400_MSI_REARM in AIC_CNTL for rs480 */
497
498 #define RADEON_BUS_CNTL1 0x0034
499 # define RADEON_PMI_BM_DIS (1 << 2)
500 # define RADEON_PMI_INT_DIS (1 << 3)
501
502 #define RV370_BUS_CNTL 0x004c
503 # define RV370_PMI_BM_DIS (1 << 5)
504 # define RV370_PMI_INT_DIS (1 << 6)
505
506 #define RADEON_MSI_REARM_EN 0x0160
507 /* rv370/rv380, rv410, r423/r430/r480, r5xx */
508 # define RV370_MSI_REARM_EN (1 << 0)
509
510 #define RADEON_CLOCK_CNTL_DATA 0x000c
511 # define RADEON_PLL_WR_EN (1 << 7)
512 #define RADEON_CLOCK_CNTL_INDEX 0x0008
513 #define RADEON_CONFIG_APER_SIZE 0x0108
514 #define RADEON_CONFIG_MEMSIZE 0x00f8
515 #define RADEON_CRTC_OFFSET 0x0224
516 #define RADEON_CRTC_OFFSET_CNTL 0x0228
517 # define RADEON_CRTC_TILE_EN (1 << 15)
518 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
519 #define RADEON_CRTC2_OFFSET 0x0324
520 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
521
522 #define RADEON_PCIE_INDEX 0x0030
523 #define RADEON_PCIE_DATA 0x0034
524 #define RADEON_PCIE_TX_GART_CNTL 0x10
525 # define RADEON_PCIE_TX_GART_EN (1 << 0)
526 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
527 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
528 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
529 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
530 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
531 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
532 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
533 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
534 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
535 #define RADEON_PCIE_TX_GART_BASE 0x13
536 #define RADEON_PCIE_TX_GART_START_LO 0x14
537 #define RADEON_PCIE_TX_GART_START_HI 0x15
538 #define RADEON_PCIE_TX_GART_END_LO 0x16
539 #define RADEON_PCIE_TX_GART_END_HI 0x17
540
541 #define RS480_NB_MC_INDEX 0x168
542 # define RS480_NB_MC_IND_WR_EN (1 << 8)
543 #define RS480_NB_MC_DATA 0x16c
544
545 #define RS690_MC_INDEX 0x78
546 # define RS690_MC_INDEX_MASK 0x1ff
547 # define RS690_MC_INDEX_WR_EN (1 << 9)
548 # define RS690_MC_INDEX_WR_ACK 0x7f
549 #define RS690_MC_DATA 0x7c
550
551 /* MC indirect registers */
552 #define RS480_MC_MISC_CNTL 0x18
553 # define RS480_DISABLE_GTW (1 << 1)
554 /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
555 # define RS480_GART_INDEX_REG_EN (1 << 12)
556 # define RS690_BLOCK_GFX_D3_EN (1 << 14)
557 #define RS480_K8_FB_LOCATION 0x1e
558 #define RS480_GART_FEATURE_ID 0x2b
559 # define RS480_HANG_EN (1 << 11)
560 # define RS480_TLB_ENABLE (1 << 18)
561 # define RS480_P2P_ENABLE (1 << 19)
562 # define RS480_GTW_LAC_EN (1 << 25)
563 # define RS480_2LEVEL_GART (0 << 30)
564 # define RS480_1LEVEL_GART (1 << 30)
565 # define RS480_PDC_EN (1 << 31)
566 #define RS480_GART_BASE 0x2c
567 #define RS480_GART_CACHE_CNTRL 0x2e
568 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
569 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
570 # define RS480_GART_EN (1 << 0)
571 # define RS480_VA_SIZE_32MB (0 << 1)
572 # define RS480_VA_SIZE_64MB (1 << 1)
573 # define RS480_VA_SIZE_128MB (2 << 1)
574 # define RS480_VA_SIZE_256MB (3 << 1)
575 # define RS480_VA_SIZE_512MB (4 << 1)
576 # define RS480_VA_SIZE_1GB (5 << 1)
577 # define RS480_VA_SIZE_2GB (6 << 1)
578 #define RS480_AGP_MODE_CNTL 0x39
579 # define RS480_POST_GART_Q_SIZE (1 << 18)
580 # define RS480_NONGART_SNOOP (1 << 19)
581 # define RS480_AGP_RD_BUF_SIZE (1 << 20)
582 # define RS480_REQ_TYPE_SNOOP_SHIFT 22
583 # define RS480_REQ_TYPE_SNOOP_MASK 0x3
584 # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
585 #define RS480_MC_MISC_UMA_CNTL 0x5f
586 #define RS480_MC_MCLK_CNTL 0x7a
587 #define RS480_MC_UMA_DUALCH_CNTL 0x86
588
589 #define RS690_MC_FB_LOCATION 0x100
590 #define RS690_MC_AGP_LOCATION 0x101
591 #define RS690_MC_AGP_BASE 0x102
592 #define RS690_MC_AGP_BASE_2 0x103
593
594 #define R520_MC_IND_INDEX 0x70
595 #define R520_MC_IND_WR_EN (1 << 24)
596 #define R520_MC_IND_DATA 0x74
597
598 #define RV515_MC_FB_LOCATION 0x01
599 #define RV515_MC_AGP_LOCATION 0x02
600 #define RV515_MC_AGP_BASE 0x03
601 #define RV515_MC_AGP_BASE_2 0x04
602
603 #define R520_MC_FB_LOCATION 0x04
604 #define R520_MC_AGP_LOCATION 0x05
605 #define R520_MC_AGP_BASE 0x06
606 #define R520_MC_AGP_BASE_2 0x07
607
608 #define RADEON_MPP_TB_CONFIG 0x01c0
609 #define RADEON_MEM_CNTL 0x0140
610 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
611 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
612 #define RS480_AGP_BASE_2 0x0164
613 #define RADEON_AGP_BASE 0x0170
614
615 /* pipe config regs */
616 #define R400_GB_PIPE_SELECT 0x402c
617 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
618 #define R500_SU_REG_DEST 0x42c8
619 #define R300_GB_TILE_CONFIG 0x4018
620 # define R300_ENABLE_TILING (1 << 0)
621 # define R300_PIPE_COUNT_RV350 (0 << 1)
622 # define R300_PIPE_COUNT_R300 (3 << 1)
623 # define R300_PIPE_COUNT_R420_3P (6 << 1)
624 # define R300_PIPE_COUNT_R420 (7 << 1)
625 # define R300_TILE_SIZE_8 (0 << 4)
626 # define R300_TILE_SIZE_16 (1 << 4)
627 # define R300_TILE_SIZE_32 (2 << 4)
628 # define R300_SUBPIXEL_1_12 (0 << 16)
629 # define R300_SUBPIXEL_1_16 (1 << 16)
630 #define R300_DST_PIPE_CONFIG 0x170c
631 # define R300_PIPE_AUTO_CONFIG (1 << 31)
632 #define R300_RB2D_DSTCACHE_MODE 0x3428
633 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
634 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
635
636 #define RADEON_RB3D_COLOROFFSET 0x1c40
637 #define RADEON_RB3D_COLORPITCH 0x1c48
638
639 #define RADEON_SRC_X_Y 0x1590
640
641 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
642 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
643 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
644 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
645 # define RADEON_GMC_BRUSH_NONE (15 << 4)
646 # define RADEON_GMC_DST_16BPP (4 << 8)
647 # define RADEON_GMC_DST_24BPP (5 << 8)
648 # define RADEON_GMC_DST_32BPP (6 << 8)
649 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
650 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
651 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
652 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
653 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
654 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
655 # define RADEON_ROP3_S 0x00cc0000
656 # define RADEON_ROP3_P 0x00f00000
657 #define RADEON_DP_WRITE_MASK 0x16cc
658 #define RADEON_SRC_PITCH_OFFSET 0x1428
659 #define RADEON_DST_PITCH_OFFSET 0x142c
660 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
661 # define RADEON_DST_TILE_LINEAR (0 << 30)
662 # define RADEON_DST_TILE_MACRO (1 << 30)
663 # define RADEON_DST_TILE_MICRO (2 << 30)
664 # define RADEON_DST_TILE_BOTH (3 << 30)
665
666 #define RADEON_SCRATCH_REG0 0x15e0
667 #define RADEON_SCRATCH_REG1 0x15e4
668 #define RADEON_SCRATCH_REG2 0x15e8
669 #define RADEON_SCRATCH_REG3 0x15ec
670 #define RADEON_SCRATCH_REG4 0x15f0
671 #define RADEON_SCRATCH_REG5 0x15f4
672 #define RADEON_SCRATCH_UMSK 0x0770
673 #define RADEON_SCRATCH_ADDR 0x0774
674
675 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
676
677 extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
678
679 #define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)
680
681 #define R600_SCRATCH_REG0 0x8500
682 #define R600_SCRATCH_REG1 0x8504
683 #define R600_SCRATCH_REG2 0x8508
684 #define R600_SCRATCH_REG3 0x850c
685 #define R600_SCRATCH_REG4 0x8510
686 #define R600_SCRATCH_REG5 0x8514
687 #define R600_SCRATCH_REG6 0x8518
688 #define R600_SCRATCH_REG7 0x851c
689 #define R600_SCRATCH_UMSK 0x8540
690 #define R600_SCRATCH_ADDR 0x8544
691
692 #define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x))
693
694 #define RADEON_GEN_INT_CNTL 0x0040
695 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
696 # define RADEON_CRTC2_VBLANK_MASK (1 << 9)
697 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
698 # define RADEON_SW_INT_ENABLE (1 << 25)
699
700 #define RADEON_GEN_INT_STATUS 0x0044
701 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
702 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
703 # define RADEON_CRTC2_VBLANK_STAT (1 << 9)
704 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
705 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
706 # define RADEON_SW_INT_TEST (1 << 25)
707 # define RADEON_SW_INT_TEST_ACK (1 << 25)
708 # define RADEON_SW_INT_FIRE (1 << 26)
709 # define R500_DISPLAY_INT_STATUS (1 << 0)
710
711 #define RADEON_HOST_PATH_CNTL 0x0130
712 # define RADEON_HDP_SOFT_RESET (1 << 26)
713 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
714 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
715
716 #define RADEON_ISYNC_CNTL 0x1724
717 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
718 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
719 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
720 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
721 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
722 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
723
724 #define RADEON_RBBM_GUICNTL 0x172c
725 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
726 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
727 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
728 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
729
730 #define RADEON_MC_AGP_LOCATION 0x014c
731 #define RADEON_MC_FB_LOCATION 0x0148
732 #define RADEON_MCLK_CNTL 0x0012
733 # define RADEON_FORCEON_MCLKA (1 << 16)
734 # define RADEON_FORCEON_MCLKB (1 << 17)
735 # define RADEON_FORCEON_YCLKA (1 << 18)
736 # define RADEON_FORCEON_YCLKB (1 << 19)
737 # define RADEON_FORCEON_MC (1 << 20)
738 # define RADEON_FORCEON_AIC (1 << 21)
739
740 #define RADEON_PP_BORDER_COLOR_0 0x1d40
741 #define RADEON_PP_BORDER_COLOR_1 0x1d44
742 #define RADEON_PP_BORDER_COLOR_2 0x1d48
743 #define RADEON_PP_CNTL 0x1c38
744 # define RADEON_SCISSOR_ENABLE (1 << 1)
745 #define RADEON_PP_LUM_MATRIX 0x1d00
746 #define RADEON_PP_MISC 0x1c14
747 #define RADEON_PP_ROT_MATRIX_0 0x1d58
748 #define RADEON_PP_TXFILTER_0 0x1c54
749 #define RADEON_PP_TXOFFSET_0 0x1c5c
750 #define RADEON_PP_TXFILTER_1 0x1c6c
751 #define RADEON_PP_TXFILTER_2 0x1c84
752
753 #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
754 #define R300_DSTCACHE_CTLSTAT 0x1714
755 # define R300_RB2D_DC_FLUSH (3 << 0)
756 # define R300_RB2D_DC_FREE (3 << 2)
757 # define R300_RB2D_DC_FLUSH_ALL 0xf
758 # define R300_RB2D_DC_BUSY (1 << 31)
759 #define RADEON_RB3D_CNTL 0x1c3c
760 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
761 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
762 # define RADEON_DITHER_ENABLE (1 << 2)
763 # define RADEON_ROUND_ENABLE (1 << 3)
764 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
765 # define RADEON_DITHER_INIT (1 << 5)
766 # define RADEON_ROP_ENABLE (1 << 6)
767 # define RADEON_STENCIL_ENABLE (1 << 7)
768 # define RADEON_Z_ENABLE (1 << 8)
769 # define RADEON_ZBLOCK16 (1 << 15)
770 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
771 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
772 #define RADEON_RB3D_DEPTHPITCH 0x1c28
773 #define RADEON_RB3D_PLANEMASK 0x1d84
774 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
775 #define RADEON_RB3D_ZCACHE_MODE 0x3250
776 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
777 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
778 # define RADEON_RB3D_ZC_FREE (1 << 2)
779 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
780 # define RADEON_RB3D_ZC_BUSY (1 << 31)
781 #define R300_ZB_ZCACHE_CTLSTAT 0x4f18
782 # define R300_ZC_FLUSH (1 << 0)
783 # define R300_ZC_FREE (1 << 1)
784 # define R300_ZC_BUSY (1 << 31)
785 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
786 # define RADEON_RB3D_DC_FLUSH (3 << 0)
787 # define RADEON_RB3D_DC_FREE (3 << 2)
788 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
789 # define RADEON_RB3D_DC_BUSY (1 << 31)
790 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
791 # define R300_RB3D_DC_FLUSH (2 << 0)
792 # define R300_RB3D_DC_FREE (2 << 2)
793 # define R300_RB3D_DC_FINISH (1 << 4)
794 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
795 # define RADEON_Z_TEST_MASK (7 << 4)
796 # define RADEON_Z_TEST_ALWAYS (7 << 4)
797 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
798 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
799 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
800 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
801 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
802 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
803 # define RADEON_FORCE_Z_DIRTY (1 << 29)
804 # define RADEON_Z_WRITE_ENABLE (1 << 30)
805 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
806 #define RADEON_RBBM_SOFT_RESET 0x00f0
807 # define RADEON_SOFT_RESET_CP (1 << 0)
808 # define RADEON_SOFT_RESET_HI (1 << 1)
809 # define RADEON_SOFT_RESET_SE (1 << 2)
810 # define RADEON_SOFT_RESET_RE (1 << 3)
811 # define RADEON_SOFT_RESET_PP (1 << 4)
812 # define RADEON_SOFT_RESET_E2 (1 << 5)
813 # define RADEON_SOFT_RESET_RB (1 << 6)
814 # define RADEON_SOFT_RESET_HDP (1 << 7)
815 /*
816 * 6:0 Available slots in the FIFO
817 * 8 Host Interface active
818 * 9 CP request active
819 * 10 FIFO request active
820 * 11 Host Interface retry active
821 * 12 CP retry active
822 * 13 FIFO retry active
823 * 14 FIFO pipeline busy
824 * 15 Event engine busy
825 * 16 CP command stream busy
826 * 17 2D engine busy
827 * 18 2D portion of render backend busy
828 * 20 3D setup engine busy
829 * 26 GA engine busy
830 * 27 CBA 2D engine busy
831 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
832 * command stream queue not empty or Ring Buffer not empty
833 */
834 #define RADEON_RBBM_STATUS 0x0e40
835 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
836 /* #define RADEON_RBBM_STATUS 0x1740 */
837 /* bits 6:0 are dword slots available in the cmd fifo */
838 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
839 # define RADEON_HIRQ_ON_RBB (1 << 8)
840 # define RADEON_CPRQ_ON_RBB (1 << 9)
841 # define RADEON_CFRQ_ON_RBB (1 << 10)
842 # define RADEON_HIRQ_IN_RTBUF (1 << 11)
843 # define RADEON_CPRQ_IN_RTBUF (1 << 12)
844 # define RADEON_CFRQ_IN_RTBUF (1 << 13)
845 # define RADEON_PIPE_BUSY (1 << 14)
846 # define RADEON_ENG_EV_BUSY (1 << 15)
847 # define RADEON_CP_CMDSTRM_BUSY (1 << 16)
848 # define RADEON_E2_BUSY (1 << 17)
849 # define RADEON_RB2D_BUSY (1 << 18)
850 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
851 # define RADEON_VAP_BUSY (1 << 20)
852 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
853 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
854 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
855 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
856 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
857 # define RADEON_GA_BUSY (1 << 26)
858 # define RADEON_CBA2D_BUSY (1 << 27)
859 # define RADEON_RBBM_ACTIVE (1 << 31)
860 #define RADEON_RE_LINE_PATTERN 0x1cd0
861 #define RADEON_RE_MISC 0x26c4
862 #define RADEON_RE_TOP_LEFT 0x26c0
863 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
864 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
865 #define RADEON_RE_STIPPLE_DATA 0x1ccc
866
867 #define RADEON_SCISSOR_TL_0 0x1cd8
868 #define RADEON_SCISSOR_BR_0 0x1cdc
869 #define RADEON_SCISSOR_TL_1 0x1ce0
870 #define RADEON_SCISSOR_BR_1 0x1ce4
871 #define RADEON_SCISSOR_TL_2 0x1ce8
872 #define RADEON_SCISSOR_BR_2 0x1cec
873 #define RADEON_SE_COORD_FMT 0x1c50
874 #define RADEON_SE_CNTL 0x1c4c
875 # define RADEON_FFACE_CULL_CW (0 << 0)
876 # define RADEON_BFACE_SOLID (3 << 1)
877 # define RADEON_FFACE_SOLID (3 << 3)
878 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
879 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
880 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
881 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
882 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
883 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
884 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
885 # define RADEON_FOG_SHADE_FLAT (1 << 14)
886 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
887 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
888 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
889 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
890 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
891 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
892 #define RADEON_SE_CNTL_STATUS 0x2140
893 #define RADEON_SE_LINE_WIDTH 0x1db8
894 #define RADEON_SE_VPORT_XSCALE 0x1d98
895 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
896 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
897 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
898 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
899 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
900 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
901 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
902 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
903 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
904 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
905 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
906 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
907 #define RADEON_SURFACE_CNTL 0x0b00
908 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
909 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
910 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
911 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
912 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
913 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
914 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
915 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
916 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
917 #define RADEON_SURFACE0_INFO 0x0b0c
918 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
919 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
920 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
921 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
922 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
923 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
924 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
925 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
926 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
927 #define RADEON_SURFACE1_INFO 0x0b1c
928 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
929 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
930 #define RADEON_SURFACE2_INFO 0x0b2c
931 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
932 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
933 #define RADEON_SURFACE3_INFO 0x0b3c
934 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
935 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
936 #define RADEON_SURFACE4_INFO 0x0b4c
937 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
938 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
939 #define RADEON_SURFACE5_INFO 0x0b5c
940 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
941 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
942 #define RADEON_SURFACE6_INFO 0x0b6c
943 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
944 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
945 #define RADEON_SURFACE7_INFO 0x0b7c
946 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
947 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
948 #define RADEON_SW_SEMAPHORE 0x013c
949
950 #define RADEON_WAIT_UNTIL 0x1720
951 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
952 # define RADEON_WAIT_2D_IDLE (1 << 14)
953 # define RADEON_WAIT_3D_IDLE (1 << 15)
954 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
955 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
956 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
957
958 #define RADEON_RB3D_ZMASKOFFSET 0x3234
959 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
960 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
961 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
962
963 /* CP registers */
964 #define RADEON_CP_ME_RAM_ADDR 0x07d4
965 #define RADEON_CP_ME_RAM_RADDR 0x07d8
966 #define RADEON_CP_ME_RAM_DATAH 0x07dc
967 #define RADEON_CP_ME_RAM_DATAL 0x07e0
968
969 #define RADEON_CP_RB_BASE 0x0700
970 #define RADEON_CP_RB_CNTL 0x0704
971 # define RADEON_BUF_SWAP_32BIT (2 << 16)
972 # define RADEON_RB_NO_UPDATE (1 << 27)
973 # define RADEON_RB_RPTR_WR_ENA (1 << 31)
974 #define RADEON_CP_RB_RPTR_ADDR 0x070c
975 #define RADEON_CP_RB_RPTR 0x0710
976 #define RADEON_CP_RB_WPTR 0x0714
977
978 #define RADEON_CP_RB_WPTR_DELAY 0x0718
979 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
980 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
981
982 #define RADEON_CP_IB_BASE 0x0738
983
984 #define RADEON_CP_CSQ_CNTL 0x0740
985 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
986 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
987 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
988 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
989 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
990 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
991 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
992
993 #define RADEON_AIC_CNTL 0x01d0
994 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
995 # define RS400_MSI_REARM (1 << 3)
996 #define RADEON_AIC_STAT 0x01d4
997 #define RADEON_AIC_PT_BASE 0x01d8
998 #define RADEON_AIC_LO_ADDR 0x01dc
999 #define RADEON_AIC_HI_ADDR 0x01e0
1000 #define RADEON_AIC_TLB_ADDR 0x01e4
1001 #define RADEON_AIC_TLB_DATA 0x01e8
1002
1003 /* CP command packets */
1004 #define RADEON_CP_PACKET0 0x00000000
1005 # define RADEON_ONE_REG_WR (1 << 15)
1006 #define RADEON_CP_PACKET1 0x40000000
1007 #define RADEON_CP_PACKET2 0x80000000
1008 #define RADEON_CP_PACKET3 0xC0000000
1009 # define RADEON_CP_NOP 0x00001000
1010 # define RADEON_CP_NEXT_CHAR 0x00001900
1011 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
1012 # define RADEON_CP_SET_SCISSORS 0x00001E00
1013 /* GEN_INDX_PRIM is unsupported starting with R300 */
1014 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
1015 # define RADEON_WAIT_FOR_IDLE 0x00002600
1016 # define RADEON_3D_DRAW_VBUF 0x00002800
1017 # define RADEON_3D_DRAW_IMMD 0x00002900
1018 # define RADEON_3D_DRAW_INDX 0x00002A00
1019 # define RADEON_CP_LOAD_PALETTE 0x00002C00
1020 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
1021 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
1022 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
1023 # define RADEON_3D_CLEAR_ZMASK 0x00003200
1024 # define RADEON_CP_INDX_BUFFER 0x00003300
1025 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
1026 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
1027 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1028 # define RADEON_3D_CLEAR_HIZ 0x00003700
1029 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
1030 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
1031 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
1032 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
1033 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
1034
1035 # define R600_IT_INDIRECT_BUFFER 0x00003200
1036 # define R600_IT_ME_INITIALIZE 0x00004400
1037 # define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1038 # define R600_IT_EVENT_WRITE 0x00004600
1039 # define R600_IT_SET_CONFIG_REG 0x00006800
1040 # define R600_SET_CONFIG_REG_OFFSET 0x00008000
1041 # define R600_SET_CONFIG_REG_END 0x0000ac00
1042
1043 #define RADEON_CP_PACKET_MASK 0xC0000000
1044 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
1045 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
1046 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
1047 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
1048
1049 #define RADEON_VTX_Z_PRESENT (1 << 31)
1050 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
1051
1052 #define RADEON_PRIM_TYPE_NONE (0 << 0)
1053 #define RADEON_PRIM_TYPE_POINT (1 << 0)
1054 #define RADEON_PRIM_TYPE_LINE (2 << 0)
1055 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
1056 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
1057 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
1058 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
1059 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1060 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
1061 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1062 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1063 #define RADEON_PRIM_TYPE_MASK 0xf
1064 #define RADEON_PRIM_WALK_IND (1 << 4)
1065 #define RADEON_PRIM_WALK_LIST (2 << 4)
1066 #define RADEON_PRIM_WALK_RING (3 << 4)
1067 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
1068 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
1069 #define RADEON_MAOS_ENABLE (1 << 7)
1070 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
1071 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
1072 #define RADEON_NUM_VERTICES_SHIFT 16
1073
1074 #define RADEON_COLOR_FORMAT_CI8 2
1075 #define RADEON_COLOR_FORMAT_ARGB1555 3
1076 #define RADEON_COLOR_FORMAT_RGB565 4
1077 #define RADEON_COLOR_FORMAT_ARGB8888 6
1078 #define RADEON_COLOR_FORMAT_RGB332 7
1079 #define RADEON_COLOR_FORMAT_RGB8 9
1080 #define RADEON_COLOR_FORMAT_ARGB4444 15
1081
1082 #define RADEON_TXFORMAT_I8 0
1083 #define RADEON_TXFORMAT_AI88 1
1084 #define RADEON_TXFORMAT_RGB332 2
1085 #define RADEON_TXFORMAT_ARGB1555 3
1086 #define RADEON_TXFORMAT_RGB565 4
1087 #define RADEON_TXFORMAT_ARGB4444 5
1088 #define RADEON_TXFORMAT_ARGB8888 6
1089 #define RADEON_TXFORMAT_RGBA8888 7
1090 #define RADEON_TXFORMAT_Y8 8
1091 #define RADEON_TXFORMAT_VYUY422 10
1092 #define RADEON_TXFORMAT_YVYU422 11
1093 #define RADEON_TXFORMAT_DXT1 12
1094 #define RADEON_TXFORMAT_DXT23 14
1095 #define RADEON_TXFORMAT_DXT45 15
1096
1097 #define R200_PP_TXCBLEND_0 0x2f00
1098 #define R200_PP_TXCBLEND_1 0x2f10
1099 #define R200_PP_TXCBLEND_2 0x2f20
1100 #define R200_PP_TXCBLEND_3 0x2f30
1101 #define R200_PP_TXCBLEND_4 0x2f40
1102 #define R200_PP_TXCBLEND_5 0x2f50
1103 #define R200_PP_TXCBLEND_6 0x2f60
1104 #define R200_PP_TXCBLEND_7 0x2f70
1105 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1106 #define R200_PP_TFACTOR_0 0x2ee0
1107 #define R200_SE_VTX_FMT_0 0x2088
1108 #define R200_SE_VAP_CNTL 0x2080
1109 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
1110 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1111 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1112 #define R200_PP_TXFILTER_5 0x2ca0
1113 #define R200_PP_TXFILTER_4 0x2c80
1114 #define R200_PP_TXFILTER_3 0x2c60
1115 #define R200_PP_TXFILTER_2 0x2c40
1116 #define R200_PP_TXFILTER_1 0x2c20
1117 #define R200_PP_TXFILTER_0 0x2c00
1118 #define R200_PP_TXOFFSET_5 0x2d78
1119 #define R200_PP_TXOFFSET_4 0x2d60
1120 #define R200_PP_TXOFFSET_3 0x2d48
1121 #define R200_PP_TXOFFSET_2 0x2d30
1122 #define R200_PP_TXOFFSET_1 0x2d18
1123 #define R200_PP_TXOFFSET_0 0x2d00
1124
1125 #define R200_PP_CUBIC_FACES_0 0x2c18
1126 #define R200_PP_CUBIC_FACES_1 0x2c38
1127 #define R200_PP_CUBIC_FACES_2 0x2c58
1128 #define R200_PP_CUBIC_FACES_3 0x2c78
1129 #define R200_PP_CUBIC_FACES_4 0x2c98
1130 #define R200_PP_CUBIC_FACES_5 0x2cb8
1131 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1132 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1133 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1134 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1135 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1136 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1137 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1138 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1139 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1140 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1141 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1142 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1143 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1144 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1145 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1146 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1147 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1148 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1149 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1150 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1151 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1152 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1153 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1154 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1155 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1156 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1157 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1158 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1159 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1160 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1161
1162 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1163 #define R200_SE_VTE_CNTL 0x20b0
1164 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1165 #define R200_PP_TAM_DEBUG3 0x2d9c
1166 #define R200_PP_CNTL_X 0x2cc4
1167 #define R200_SE_VAP_CNTL_STATUS 0x2140
1168 #define R200_RE_SCISSOR_TL_0 0x1cd8
1169 #define R200_RE_SCISSOR_TL_1 0x1ce0
1170 #define R200_RE_SCISSOR_TL_2 0x1ce8
1171 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1172 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1173 #define R200_SE_VTX_STATE_CNTL 0x2180
1174 #define R200_RE_POINTSIZE 0x2648
1175 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1176
1177 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1178 #define RADEON_PP_TEX_SIZE_1 0x1d0c
1179 #define RADEON_PP_TEX_SIZE_2 0x1d14
1180
1181 #define RADEON_PP_CUBIC_FACES_0 0x1d24
1182 #define RADEON_PP_CUBIC_FACES_1 0x1d28
1183 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
1184 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1185 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1186 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1187
1188 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
1189
1190 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1191 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1192 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1193 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1194 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1195 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1196 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1197 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1198 #define R200_3D_DRAW_IMMD_2 0xC0003500
1199 #define R200_SE_VTX_FMT_1 0x208c
1200 #define R200_RE_CNTL 0x1c50
1201
1202 #define R200_RB3D_BLENDCOLOR 0x3218
1203
1204 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1205
1206 #define R200_PP_TRI_PERF 0x2cf8
1207
1208 #define R200_PP_AFS_0 0x2f80
1209 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
1210
1211 #define R200_VAP_PVS_CNTL_1 0x22D0
1212
1213 #define RADEON_CRTC_CRNT_FRAME 0x0214
1214 #define RADEON_CRTC2_CRNT_FRAME 0x0314
1215
1216 #define R500_D1CRTC_STATUS 0x609c
1217 #define R500_D2CRTC_STATUS 0x689c
1218 #define R500_CRTC_V_BLANK (1<<0)
1219
1220 #define R500_D1CRTC_FRAME_COUNT 0x60a4
1221 #define R500_D2CRTC_FRAME_COUNT 0x68a4
1222
1223 #define R500_D1MODE_V_COUNTER 0x6530
1224 #define R500_D2MODE_V_COUNTER 0x6d30
1225
1226 #define R500_D1MODE_VBLANK_STATUS 0x6534
1227 #define R500_D2MODE_VBLANK_STATUS 0x6d34
1228 #define R500_VBLANK_OCCURED (1<<0)
1229 #define R500_VBLANK_ACK (1<<4)
1230 #define R500_VBLANK_STAT (1<<12)
1231 #define R500_VBLANK_INT (1<<16)
1232
1233 #define R500_DxMODE_INT_MASK 0x6540
1234 #define R500_D1MODE_INT_MASK (1<<0)
1235 #define R500_D2MODE_INT_MASK (1<<8)
1236
1237 #define R500_DISP_INTERRUPT_STATUS 0x7edc
1238 #define R500_D1_VBLANK_INTERRUPT (1 << 4)
1239 #define R500_D2_VBLANK_INTERRUPT (1 << 5)
1240
1241 /* R6xx/R7xx registers */
1242 #define R600_MC_VM_FB_LOCATION 0x2180
1243 #define R600_MC_VM_AGP_TOP 0x2184
1244 #define R600_MC_VM_AGP_BOT 0x2188
1245 #define R600_MC_VM_AGP_BASE 0x218c
1246 #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
1247 #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
1248 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
1249
1250 #define R700_MC_VM_FB_LOCATION 0x2024
1251 #define R700_MC_VM_AGP_TOP 0x2028
1252 #define R700_MC_VM_AGP_BOT 0x202c
1253 #define R700_MC_VM_AGP_BASE 0x2030
1254 #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
1255 #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
1256 #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c
1257
1258 #define R600_MCD_RD_A_CNTL 0x219c
1259 #define R600_MCD_RD_B_CNTL 0x21a0
1260
1261 #define R600_MCD_WR_A_CNTL 0x21a4
1262 #define R600_MCD_WR_B_CNTL 0x21a8
1263
1264 #define R600_MCD_RD_SYS_CNTL 0x2200
1265 #define R600_MCD_WR_SYS_CNTL 0x2214
1266
1267 #define R600_MCD_RD_GFX_CNTL 0x21fc
1268 #define R600_MCD_RD_HDP_CNTL 0x2204
1269 #define R600_MCD_RD_PDMA_CNTL 0x2208
1270 #define R600_MCD_RD_SEM_CNTL 0x220c
1271 #define R600_MCD_WR_GFX_CNTL 0x2210
1272 #define R600_MCD_WR_HDP_CNTL 0x2218
1273 #define R600_MCD_WR_PDMA_CNTL 0x221c
1274 #define R600_MCD_WR_SEM_CNTL 0x2220
1275
1276 # define R600_MCD_L1_TLB (1 << 0)
1277 # define R600_MCD_L1_FRAG_PROC (1 << 1)
1278 # define R600_MCD_L1_STRICT_ORDERING (1 << 2)
1279
1280 # define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6)
1281 # define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
1282 # define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
1283 # define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
1284 # define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
1285
1286 # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
1287 # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
1288
1289 # define R600_MCD_SEMAPHORE_MODE (1 << 10)
1290 # define R600_MCD_WAIT_L2_QUERY (1 << 11)
1291 # define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12)
1292 # define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
1293
1294 #define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654
1295 #define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658
1296 #define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c
1297
1298 #define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234
1299 #define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238
1300 #define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c
1301 #define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240
1302
1303 # define R700_ENABLE_L1_TLB (1 << 0)
1304 # define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
1305 # define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
1306 # define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
1307 # define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15)
1308 # define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18)
1309
1310 #define R700_MC_ARB_RAMCFG 0x2760
1311 # define R700_NOOFBANK_SHIFT 0
1312 # define R700_NOOFBANK_MASK 0x3
1313 # define R700_NOOFRANK_SHIFT 2
1314 # define R700_NOOFRANK_MASK 0x1
1315 # define R700_NOOFROWS_SHIFT 3
1316 # define R700_NOOFROWS_MASK 0x7
1317 # define R700_NOOFCOLS_SHIFT 6
1318 # define R700_NOOFCOLS_MASK 0x3
1319 # define R700_CHANSIZE_SHIFT 8
1320 # define R700_CHANSIZE_MASK 0x1
1321 # define R700_BURSTLENGTH_SHIFT 9
1322 # define R700_BURSTLENGTH_MASK 0x1
1323 #define R600_RAMCFG 0x2408
1324 # define R600_NOOFBANK_SHIFT 0
1325 # define R600_NOOFBANK_MASK 0x1
1326 # define R600_NOOFRANK_SHIFT 1
1327 # define R600_NOOFRANK_MASK 0x1
1328 # define R600_NOOFROWS_SHIFT 2
1329 # define R600_NOOFROWS_MASK 0x7
1330 # define R600_NOOFCOLS_SHIFT 5
1331 # define R600_NOOFCOLS_MASK 0x3
1332 # define R600_CHANSIZE_SHIFT 7
1333 # define R600_CHANSIZE_MASK 0x1
1334 # define R600_BURSTLENGTH_SHIFT 8
1335 # define R600_BURSTLENGTH_MASK 0x1
1336
1337 #define R600_VM_L2_CNTL 0x1400
1338 # define R600_VM_L2_CACHE_EN (1 << 0)
1339 # define R600_VM_L2_FRAG_PROC (1 << 1)
1340 # define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9)
1341 # define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13)
1342 # define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14)
1343
1344 #define R600_VM_L2_CNTL2 0x1404
1345 # define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0)
1346 # define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1)
1347 #define R600_VM_L2_CNTL3 0x1408
1348 # define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0)
1349 # define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5)
1350 # define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10)
1351 # define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0)
1352 # define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6)
1353
1354 #define R600_VM_L2_STATUS 0x140c
1355
1356 #define R600_VM_CONTEXT0_CNTL 0x1410
1357 # define R600_VM_ENABLE_CONTEXT (1 << 0)
1358 # define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1)
1359
1360 #define R600_VM_CONTEXT0_CNTL2 0x1430
1361 #define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470
1362 #define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
1363 #define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0
1364 #define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
1365 #define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
1366 #define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4
1367
1368 #define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
1369 #define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
1370 #define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c
1371
1372 #define R600_HDP_HOST_PATH_CNTL 0x2c00
1373
1374 #define R600_GRBM_CNTL 0x8000
1375 # define R600_GRBM_READ_TIMEOUT(x) ((x) << 0)
1376
1377 #define R600_GRBM_STATUS 0x8010
1378 # define R600_CMDFIFO_AVAIL_MASK 0x1f
1379 # define R700_CMDFIFO_AVAIL_MASK 0xf
1380 # define R600_GUI_ACTIVE (1 << 31)
1381 #define R600_GRBM_STATUS2 0x8014
1382 #define R600_GRBM_SOFT_RESET 0x8020
1383 # define R600_SOFT_RESET_CP (1 << 0)
1384 #define R600_WAIT_UNTIL 0x8040
1385
1386 #define R600_CP_SEM_WAIT_TIMER 0x85bc
1387 #define R600_CP_ME_CNTL 0x86d8
1388 # define R600_CP_ME_HALT (1 << 28)
1389 #define R600_CP_QUEUE_THRESHOLDS 0x8760
1390 # define R600_ROQ_IB1_START(x) ((x) << 0)
1391 # define R600_ROQ_IB2_START(x) ((x) << 8)
1392 #define R600_CP_MEQ_THRESHOLDS 0x8764
1393 # define R700_STQ_SPLIT(x) ((x) << 0)
1394 # define R600_MEQ_END(x) ((x) << 16)
1395 # define R600_ROQ_END(x) ((x) << 24)
1396 #define R600_CP_PERFMON_CNTL 0x87fc
1397 #define R600_CP_RB_BASE 0xc100
1398 #define R600_CP_RB_CNTL 0xc104
1399 # define R600_RB_BUFSZ(x) ((x) << 0)
1400 # define R600_RB_BLKSZ(x) ((x) << 8)
1401 # define R600_RB_NO_UPDATE (1 << 27)
1402 # define R600_RB_RPTR_WR_ENA (1 << 31)
1403 #define R600_CP_RB_RPTR_WR 0xc108
1404 #define R600_CP_RB_RPTR_ADDR 0xc10c
1405 #define R600_CP_RB_RPTR_ADDR_HI 0xc110
1406 #define R600_CP_RB_WPTR 0xc114
1407 #define R600_CP_RB_WPTR_ADDR 0xc118
1408 #define R600_CP_RB_WPTR_ADDR_HI 0xc11c
1409 #define R600_CP_RB_RPTR 0x8700
1410 #define R600_CP_RB_WPTR_DELAY 0x8704
1411 #define R600_CP_PFP_UCODE_ADDR 0xc150
1412 #define R600_CP_PFP_UCODE_DATA 0xc154
1413 #define R600_CP_ME_RAM_RADDR 0xc158
1414 #define R600_CP_ME_RAM_WADDR 0xc15c
1415 #define R600_CP_ME_RAM_DATA 0xc160
1416 #define R600_CP_DEBUG 0xc1fc
1417
1418 #define R600_PA_CL_ENHANCE 0x8a14
1419 # define R600_CLIP_VTX_REORDER_ENA (1 << 0)
1420 # define R600_NUM_CLIP_SEQ(x) ((x) << 1)
1421 #define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10
1422 #define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20
1423 #define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24
1424 # define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1425 # define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1426 #define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40
1427 #define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44
1428 #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48
1429 #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c
1430 # define R600_S0_X(x) ((x) << 0)
1431 # define R600_S0_Y(x) ((x) << 4)
1432 # define R600_S1_X(x) ((x) << 8)
1433 # define R600_S1_Y(x) ((x) << 12)
1434 # define R600_S2_X(x) ((x) << 16)
1435 # define R600_S2_Y(x) ((x) << 20)
1436 # define R600_S3_X(x) ((x) << 24)
1437 # define R600_S3_Y(x) ((x) << 28)
1438 # define R600_S4_X(x) ((x) << 0)
1439 # define R600_S4_Y(x) ((x) << 4)
1440 # define R600_S5_X(x) ((x) << 8)
1441 # define R600_S5_Y(x) ((x) << 12)
1442 # define R600_S6_X(x) ((x) << 16)
1443 # define R600_S6_Y(x) ((x) << 20)
1444 # define R600_S7_X(x) ((x) << 24)
1445 # define R600_S7_Y(x) ((x) << 28)
1446 #define R600_PA_SC_FIFO_SIZE 0x8bd0
1447 # define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1448 # define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8)
1449 # define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16)
1450 #define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc
1451 # define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1452 # define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
1453 # define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
1454 #define R600_PA_SC_ENHANCE 0x8bf0
1455 # define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1456 # define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
1457 #define R600_PA_SC_CLIPRECT_RULE 0x2820c
1458 #define R700_PA_SC_EDGERULE 0x28230
1459 #define R600_PA_SC_LINE_STIPPLE 0x28a0c
1460 #define R600_PA_SC_MODE_CNTL 0x28a4c
1461 #define R600_PA_SC_AA_CONFIG 0x28c04
1462
1463 #define R600_SX_EXPORT_BUFFER_SIZES 0x900c
1464 # define R600_COLOR_BUFFER_SIZE(x) ((x) << 0)
1465 # define R600_POSITION_BUFFER_SIZE(x) ((x) << 8)
1466 # define R600_SMX_BUFFER_SIZE(x) ((x) << 16)
1467 #define R600_SX_DEBUG_1 0x9054
1468 # define R600_SMX_EVENT_RELEASE (1 << 0)
1469 # define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1470 #define R700_SX_DEBUG_1 0x9058
1471 # define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1472 #define R600_SX_MISC 0x28350
1473
1474 #define R600_DB_DEBUG 0x9830
1475 # define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
1476 #define R600_DB_WATERMARKS 0x9838
1477 # define R600_DEPTH_FREE(x) ((x) << 0)
1478 # define R600_DEPTH_FLUSH(x) ((x) << 5)
1479 # define R600_DEPTH_PENDING_FREE(x) ((x) << 15)
1480 # define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20)
1481 #define R700_DB_DEBUG3 0x98b0
1482 # define R700_DB_CLK_OFF_DELAY(x) ((x) << 11)
1483 #define RV700_DB_DEBUG4 0x9b8c
1484 # define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
1485
1486 #define R600_VGT_CACHE_INVALIDATION 0x88c4
1487 # define R600_CACHE_INVALIDATION(x) ((x) << 0)
1488 # define R600_VC_ONLY 0
1489 # define R600_TC_ONLY 1
1490 # define R600_VC_AND_TC 2
1491 # define R700_AUTO_INVLD_EN(x) ((x) << 6)
1492 # define R700_NO_AUTO 0
1493 # define R700_ES_AUTO 1
1494 # define R700_GS_AUTO 2
1495 # define R700_ES_AND_GS_AUTO 3
1496 #define R600_VGT_GS_PER_ES 0x88c8
1497 #define R600_VGT_ES_PER_GS 0x88cc
1498 #define R600_VGT_GS_PER_VS 0x88e8
1499 #define R600_VGT_GS_VERTEX_REUSE 0x88d4
1500 #define R600_VGT_NUM_INSTANCES 0x8974
1501 #define R600_VGT_STRMOUT_EN 0x28ab0
1502 #define R600_VGT_EVENT_INITIATOR 0x28a90
1503 # define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
1504 #define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58
1505 # define R600_VTX_REUSE_DEPTH_MASK 0xff
1506 #define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c
1507 # define R600_DEALLOC_DIST_MASK 0x7f
1508
1509 #define R600_CB_COLOR0_BASE 0x28040
1510 #define R600_CB_COLOR1_BASE 0x28044
1511 #define R600_CB_COLOR2_BASE 0x28048
1512 #define R600_CB_COLOR3_BASE 0x2804c
1513 #define R600_CB_COLOR4_BASE 0x28050
1514 #define R600_CB_COLOR5_BASE 0x28054
1515 #define R600_CB_COLOR6_BASE 0x28058
1516 #define R600_CB_COLOR7_BASE 0x2805c
1517 #define R600_CB_COLOR7_FRAG 0x280fc
1518
1519 #define R600_TC_CNTL 0x9608
1520 # define R600_TC_L2_SIZE(x) ((x) << 5)
1521 # define R600_L2_DISABLE_LATE_HIT (1 << 9)
1522
1523 #define R600_ARB_POP 0x2418
1524 # define R600_ENABLE_TC128 (1 << 30)
1525 #define R600_ARB_GDEC_RD_CNTL 0x246c
1526
1527 #define R600_TA_CNTL_AUX 0x9508
1528 # define R600_DISABLE_CUBE_WRAP (1 << 0)
1529 # define R600_DISABLE_CUBE_ANISO (1 << 1)
1530 # define R700_GETLOD_SELECT(x) ((x) << 2)
1531 # define R600_SYNC_GRADIENT (1 << 24)
1532 # define R600_SYNC_WALKER (1 << 25)
1533 # define R600_SYNC_ALIGNER (1 << 26)
1534 # define R600_BILINEAR_PRECISION_6_BIT (0 << 31)
1535 # define R600_BILINEAR_PRECISION_8_BIT (1 << 31)
1536
1537 #define R700_TCP_CNTL 0x9610
1538
1539 #define R600_SMX_DC_CTL0 0xa020
1540 # define R700_USE_HASH_FUNCTION (1 << 0)
1541 # define R700_CACHE_DEPTH(x) ((x) << 1)
1542 # define R700_FLUSH_ALL_ON_EVENT (1 << 10)
1543 # define R700_STALL_ON_EVENT (1 << 11)
1544 #define R700_SMX_EVENT_CTL 0xa02c
1545 # define R700_ES_FLUSH_CTL(x) ((x) << 0)
1546 # define R700_GS_FLUSH_CTL(x) ((x) << 3)
1547 # define R700_ACK_FLUSH_CTL(x) ((x) << 6)
1548 # define R700_SYNC_FLUSH_CTL (1 << 8)
1549
1550 #define R600_SQ_CONFIG 0x8c00
1551 # define R600_VC_ENABLE (1 << 0)
1552 # define R600_EXPORT_SRC_C (1 << 1)
1553 # define R600_DX9_CONSTS (1 << 2)
1554 # define R600_ALU_INST_PREFER_VECTOR (1 << 3)
1555 # define R600_DX10_CLAMP (1 << 4)
1556 # define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8)
1557 # define R600_PS_PRIO(x) ((x) << 24)
1558 # define R600_VS_PRIO(x) ((x) << 26)
1559 # define R600_GS_PRIO(x) ((x) << 28)
1560 # define R600_ES_PRIO(x) ((x) << 30)
1561 #define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04
1562 # define R600_NUM_PS_GPRS(x) ((x) << 0)
1563 # define R600_NUM_VS_GPRS(x) ((x) << 16)
1564 # define R700_DYN_GPR_ENABLE (1 << 27)
1565 # define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
1566 #define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08
1567 # define R600_NUM_GS_GPRS(x) ((x) << 0)
1568 # define R600_NUM_ES_GPRS(x) ((x) << 16)
1569 #define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c
1570 # define R600_NUM_PS_THREADS(x) ((x) << 0)
1571 # define R600_NUM_VS_THREADS(x) ((x) << 8)
1572 # define R600_NUM_GS_THREADS(x) ((x) << 16)
1573 # define R600_NUM_ES_THREADS(x) ((x) << 24)
1574 #define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10
1575 # define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0)
1576 # define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16)
1577 #define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14
1578 # define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0)
1579 # define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16)
1580 #define R600_SQ_MS_FIFO_SIZES 0x8cf0
1581 # define R600_CACHE_FIFO_SIZE(x) ((x) << 0)
1582 # define R600_FETCH_FIFO_HIWATER(x) ((x) << 8)
1583 # define R600_DONE_FIFO_HIWATER(x) ((x) << 16)
1584 # define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
1585 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0
1586 # define R700_SIMDA_RING0(x) ((x) << 0)
1587 # define R700_SIMDA_RING1(x) ((x) << 8)
1588 # define R700_SIMDB_RING0(x) ((x) << 16)
1589 # define R700_SIMDB_RING1(x) ((x) << 24)
1590 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4
1591 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8
1592 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc
1593 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0
1594 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4
1595 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8
1596 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc
1597
1598 #define R600_SPI_PS_IN_CONTROL_0 0x286cc
1599 # define R600_NUM_INTERP(x) ((x) << 0)
1600 # define R600_POSITION_ENA (1 << 8)
1601 # define R600_POSITION_CENTROID (1 << 9)
1602 # define R600_POSITION_ADDR(x) ((x) << 10)
1603 # define R600_PARAM_GEN(x) ((x) << 15)
1604 # define R600_PARAM_GEN_ADDR(x) ((x) << 19)
1605 # define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26)
1606 # define R600_PERSP_GRADIENT_ENA (1 << 28)
1607 # define R600_LINEAR_GRADIENT_ENA (1 << 29)
1608 # define R600_POSITION_SAMPLE (1 << 30)
1609 # define R600_BARYC_AT_SAMPLE_ENA (1 << 31)
1610 #define R600_SPI_PS_IN_CONTROL_1 0x286d0
1611 # define R600_GEN_INDEX_PIX (1 << 0)
1612 # define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)
1613 # define R600_FRONT_FACE_ENA (1 << 8)
1614 # define R600_FRONT_FACE_CHAN(x) ((x) << 9)
1615 # define R600_FRONT_FACE_ALL_BITS (1 << 11)
1616 # define R600_FRONT_FACE_ADDR(x) ((x) << 12)
1617 # define R600_FOG_ADDR(x) ((x) << 17)
1618 # define R600_FIXED_PT_POSITION_ENA (1 << 24)
1619 # define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25)
1620 # define R700_POSITION_ULC (1 << 30)
1621 #define R600_SPI_INPUT_Z 0x286d8
1622
1623 #define R600_SPI_CONFIG_CNTL 0x9100
1624 # define R600_GPR_WRITE_PRIORITY(x) ((x) << 0)
1625 # define R600_DISABLE_INTERP_1 (1 << 5)
1626 #define R600_SPI_CONFIG_CNTL_1 0x913c
1627 # define R600_VTX_DONE_DELAY(x) ((x) << 0)
1628 # define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4)
1629
1630 #define R600_GB_TILING_CONFIG 0x98f0
1631 # define R600_PIPE_TILING(x) ((x) << 1)
1632 # define R600_BANK_TILING(x) ((x) << 4)
1633 # define R600_GROUP_SIZE(x) ((x) << 6)
1634 # define R600_ROW_TILING(x) ((x) << 8)
1635 # define R600_BANK_SWAPS(x) ((x) << 11)
1636 # define R600_SAMPLE_SPLIT(x) ((x) << 14)
1637 # define R600_BACKEND_MAP(x) ((x) << 16)
1638 #define R600_DCP_TILING_CONFIG 0x6ca0
1639 #define R600_HDP_TILING_CONFIG 0x2f3c
1640
1641 #define R600_CC_RB_BACKEND_DISABLE 0x98f4
1642 #define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88
1643 # define R600_BACKEND_DISABLE(x) ((x) << 16)
1644
1645 #define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950
1646 #define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954
1647 # define R600_INACTIVE_QD_PIPES(x) ((x) << 8)
1648 # define R600_INACTIVE_QD_PIPES_MASK (0xff << 8)
1649 # define R600_INACTIVE_SIMDS(x) ((x) << 16)
1650 # define R600_INACTIVE_SIMDS_MASK (0xff << 16)
1651
1652 #define R700_CGTS_SYS_TCC_DISABLE 0x3f90
1653 #define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94
1654 #define R700_CGTS_TCC_DISABLE 0x9148
1655 #define R700_CGTS_USER_TCC_DISABLE 0x914c
1656
1657 /* Constants */
1658 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1659
1660 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1661 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1662 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1663 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1664 #define RADEON_LAST_DISPATCH 1
1665
1666 #define R600_LAST_FRAME_REG R600_SCRATCH_REG0
1667 #define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1
1668 #define R600_LAST_CLEAR_REG R600_SCRATCH_REG2
1669 #define R600_LAST_SWI_REG R600_SCRATCH_REG3
1670
1671 #define RADEON_MAX_VB_AGE 0x7fffffff
1672 #define RADEON_MAX_VB_VERTS (0xffff)
1673
1674 #define RADEON_RING_HIGH_MARK 128
1675
1676 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
1677
1678 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1679 #define RADEON_WRITE(reg, val) \
1680 do { \
1681 if (reg < 0x10000) { \
1682 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
1683 } else { \
1684 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
1685 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
1686 } \
1687 } while (0)
1688 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1689 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1690
1691 #define RADEON_WRITE_PLL(addr, val) \
1692 do { \
1693 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1694 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1695 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1696 } while (0)
1697
1698 #define RADEON_WRITE_PCIE(addr, val) \
1699 do { \
1700 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1701 ((addr) & 0xff)); \
1702 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1703 } while (0)
1704
1705 #define R500_WRITE_MCIND(addr, val) \
1706 do { \
1707 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1708 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1709 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1710 } while (0)
1711
1712 #define RS480_WRITE_MCIND(addr, val) \
1713 do { \
1714 RADEON_WRITE(RS480_NB_MC_INDEX, \
1715 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1716 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1717 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1718 } while (0)
1719
1720 #define RS690_WRITE_MCIND(addr, val) \
1721 do { \
1722 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1723 RADEON_WRITE(RS690_MC_DATA, val); \
1724 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1725 } while (0)
1726
1727 #define IGP_WRITE_MCIND(addr, val) \
1728 do { \
1729 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1730 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
1731 RS690_WRITE_MCIND(addr, val); \
1732 else \
1733 RS480_WRITE_MCIND(addr, val); \
1734 } while (0)
1735
1736 #define CP_PACKET0( reg, n ) \
1737 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1738 #define CP_PACKET0_TABLE( reg, n ) \
1739 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1740 #define CP_PACKET1( reg0, reg1 ) \
1741 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1742 #define CP_PACKET2() \
1743 (RADEON_CP_PACKET2)
1744 #define CP_PACKET3( pkt, n ) \
1745 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1746
1747 /* ================================================================
1748 * Engine control helper macros
1749 */
1750
1751 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1752 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1753 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1754 RADEON_WAIT_HOST_IDLECLEAN) ); \
1755 } while (0)
1756
1757 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1758 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1759 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1760 RADEON_WAIT_HOST_IDLECLEAN) ); \
1761 } while (0)
1762
1763 #define RADEON_WAIT_UNTIL_IDLE() do { \
1764 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1765 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1766 RADEON_WAIT_3D_IDLECLEAN | \
1767 RADEON_WAIT_HOST_IDLECLEAN) ); \
1768 } while (0)
1769
1770 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1771 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1772 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1773 } while (0)
1774
1775 #define RADEON_FLUSH_CACHE() do { \
1776 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1777 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1778 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1779 } else { \
1780 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1781 OUT_RING(R300_RB3D_DC_FLUSH); \
1782 } \
1783 } while (0)
1784
1785 #define RADEON_PURGE_CACHE() do { \
1786 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1787 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1788 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \
1789 } else { \
1790 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1791 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \
1792 } \
1793 } while (0)
1794
1795 #define RADEON_FLUSH_ZCACHE() do { \
1796 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1797 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1798 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1799 } else { \
1800 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1801 OUT_RING(R300_ZC_FLUSH); \
1802 } \
1803 } while (0)
1804
1805 #define RADEON_PURGE_ZCACHE() do { \
1806 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1807 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1808 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \
1809 } else { \
1810 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1811 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \
1812 } \
1813 } while (0)
1814
1815 /* ================================================================
1816 * Misc helper macros
1817 */
1818
1819 /* Perfbox functionality only.
1820 */
1821 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1822 do { \
1823 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1824 u32 head = GET_RING_HEAD( dev_priv ); \
1825 if (head == dev_priv->ring.tail) \
1826 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1827 } \
1828 } while (0)
1829
1830 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1831 do { \
1832 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \
1833 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \
1834 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1835 int __ret = radeon_do_cp_idle( dev_priv ); \
1836 if ( __ret ) return __ret; \
1837 sarea_priv->last_dispatch = 0; \
1838 radeon_freelist_reset( dev ); \
1839 } \
1840 } while (0)
1841
1842 #define RADEON_DISPATCH_AGE( age ) do { \
1843 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1844 OUT_RING( age ); \
1845 } while (0)
1846
1847 #define RADEON_FRAME_AGE( age ) do { \
1848 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1849 OUT_RING( age ); \
1850 } while (0)
1851
1852 #define RADEON_CLEAR_AGE( age ) do { \
1853 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1854 OUT_RING( age ); \
1855 } while (0)
1856
1857 #define R600_DISPATCH_AGE(age) do { \
1858 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
1859 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
1860 OUT_RING(age); \
1861 } while (0)
1862
1863 #define R600_FRAME_AGE(age) do { \
1864 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
1865 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
1866 OUT_RING(age); \
1867 } while (0)
1868
1869 #define R600_CLEAR_AGE(age) do { \
1870 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
1871 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
1872 OUT_RING(age); \
1873 } while (0)
1874
1875 /* ================================================================
1876 * Ring control
1877 */
1878
1879 #define RADEON_VERBOSE 0
1880
1881 #define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring;
1882
1883 #define BEGIN_RING( n ) do { \
1884 if ( RADEON_VERBOSE ) { \
1885 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1886 } \
1887 _align_nr = (n + 0xf) & ~0xf; \
1888 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \
1889 COMMIT_RING(); \
1890 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \
1891 } \
1892 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1893 ring = dev_priv->ring.start; \
1894 write = dev_priv->ring.tail; \
1895 mask = dev_priv->ring.tail_mask; \
1896 } while (0)
1897
1898 #define ADVANCE_RING() do { \
1899 if ( RADEON_VERBOSE ) { \
1900 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1901 write, dev_priv->ring.tail ); \
1902 } \
1903 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1904 DRM_ERROR( \
1905 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1906 ((dev_priv->ring.tail + _nr) & mask), \
1907 write, __LINE__); \
1908 } else \
1909 dev_priv->ring.tail = write; \
1910 } while (0)
1911
1912 extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
1913
1914 #define COMMIT_RING() do { \
1915 radeon_commit_ring(dev_priv); \
1916 } while(0)
1917
1918 #define OUT_RING( x ) do { \
1919 if ( RADEON_VERBOSE ) { \
1920 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1921 (unsigned int)(x), write ); \
1922 } \
1923 ring[write++] = (x); \
1924 write &= mask; \
1925 } while (0)
1926
1927 #define OUT_RING_REG( reg, val ) do { \
1928 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1929 OUT_RING( val ); \
1930 } while (0)
1931
1932 #define OUT_RING_TABLE( tab, sz ) do { \
1933 int _size = (sz); \
1934 int *_tab = (int *)(tab); \
1935 \
1936 if (write + _size > mask) { \
1937 int _i = (mask+1) - write; \
1938 _size -= _i; \
1939 while (_i > 0 ) { \
1940 *(int *)(ring + write) = *_tab++; \
1941 write++; \
1942 _i--; \
1943 } \
1944 write = 0; \
1945 _tab += _i; \
1946 } \
1947 while (_size > 0) { \
1948 *(ring + write) = *_tab++; \
1949 write++; \
1950 _size--; \
1951 } \
1952 write &= mask; \
1953 } while (0)
1954
1955 #endif /* __RADEON_DRV_H__ */
Support for the Chinese Samsung S3C2440 based development boards