include/asm-powerpc/mpic.h

   1 #ifndef _ASM_POWERPC_MPIC_H
   2 #define _ASM_POWERPC_MPIC_H
   3 #ifdef __KERNEL__
   4
   5 #include <linux/irq.h>
   6
   7 /*
   8  * Global registers
   9  */
  10
  11 #define MPIC_GREG_BASE                  0x01000
  12
  13 #define MPIC_GREG_FEATURE_0             0x00000
  14 #define         MPIC_GREG_FEATURE_LAST_SRC_MASK         0x07ff0000
  15 #define         MPIC_GREG_FEATURE_LAST_SRC_SHIFT        16
  16 #define         MPIC_GREG_FEATURE_LAST_CPU_MASK         0x00001f00
  17 #define         MPIC_GREG_FEATURE_LAST_CPU_SHIFT        8
  18 #define         MPIC_GREG_FEATURE_VERSION_MASK          0xff
  19 #define MPIC_GREG_FEATURE_1             0x00010
  20 #define MPIC_GREG_GLOBAL_CONF_0         0x00020
  21 #define         MPIC_GREG_GCONF_RESET                   0x80000000
  22 #define         MPIC_GREG_GCONF_8259_PTHROU_DIS         0x20000000
  23 #define         MPIC_GREG_GCONF_BASE_MASK               0x000fffff
  24 #define MPIC_GREG_GLOBAL_CONF_1         0x00030
  25 #define         MPIC_GREG_GLOBAL_CONF_1_SIE             0x08000000
  26 #define         MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK  0x70000000
  27 #define         MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r)    \
  28                         (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
  29 #define MPIC_GREG_VENDOR_0              0x00040
  30 #define MPIC_GREG_VENDOR_1              0x00050
  31 #define MPIC_GREG_VENDOR_2              0x00060
  32 #define MPIC_GREG_VENDOR_3              0x00070
  33 #define MPIC_GREG_VENDOR_ID             0x00080
  34 #define         MPIC_GREG_VENDOR_ID_STEPPING_MASK       0x00ff0000
  35 #define         MPIC_GREG_VENDOR_ID_STEPPING_SHIFT      16
  36 #define         MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK      0x0000ff00
  37 #define         MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT     8
  38 #define         MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK      0x000000ff
  39 #define MPIC_GREG_PROCESSOR_INIT        0x00090
  40 #define MPIC_GREG_IPI_VECTOR_PRI_0      0x000a0
  41 #define MPIC_GREG_IPI_VECTOR_PRI_1      0x000b0
  42 #define MPIC_GREG_IPI_VECTOR_PRI_2      0x000c0
  43 #define MPIC_GREG_IPI_VECTOR_PRI_3      0x000d0
  44 #define MPIC_GREG_IPI_STRIDE            0x10
  45 #define MPIC_GREG_SPURIOUS              0x000e0
  46 #define MPIC_GREG_TIMER_FREQ            0x000f0
  47
  48 /*
  49  *
  50  * Timer registers
  51  */
  52 #define MPIC_TIMER_BASE                 0x01100
  53 #define MPIC_TIMER_STRIDE               0x40
  54
  55 #define MPIC_TIMER_CURRENT_CNT          0x00000
  56 #define MPIC_TIMER_BASE_CNT             0x00010
  57 #define MPIC_TIMER_VECTOR_PRI           0x00020
  58 #define MPIC_TIMER_DESTINATION          0x00030
  59
  60 /*
  61  * Per-Processor registers
  62  */
  63
  64 #define MPIC_CPU_THISBASE               0x00000
  65 #define MPIC_CPU_BASE                   0x20000
  66 #define MPIC_CPU_STRIDE                 0x01000
  67
  68 #define MPIC_CPU_IPI_DISPATCH_0         0x00040
  69 #define MPIC_CPU_IPI_DISPATCH_1         0x00050
  70 #define MPIC_CPU_IPI_DISPATCH_2         0x00060
  71 #define MPIC_CPU_IPI_DISPATCH_3         0x00070
  72 #define MPIC_CPU_IPI_DISPATCH_STRIDE    0x00010
  73 #define MPIC_CPU_CURRENT_TASK_PRI       0x00080
  74 #define         MPIC_CPU_TASKPRI_MASK                   0x0000000f
  75 #define MPIC_CPU_WHOAMI                 0x00090
  76 #define         MPIC_CPU_WHOAMI_MASK                    0x0000001f
  77 #define MPIC_CPU_INTACK                 0x000a0
  78 #define MPIC_CPU_EOI                    0x000b0
  79
  80 /*
  81  * Per-source registers
  82  */
  83
  84 #define MPIC_IRQ_BASE                   0x10000
  85 #define MPIC_IRQ_STRIDE                 0x00020
  86 #define MPIC_IRQ_VECTOR_PRI             0x00000
  87 #define         MPIC_VECPRI_MASK                        0x80000000
  88 #define         MPIC_VECPRI_ACTIVITY                    0x40000000      /* Read Only */
  89 #define         MPIC_VECPRI_PRIORITY_MASK               0x000f0000
  90 #define         MPIC_VECPRI_PRIORITY_SHIFT              16
  91 #define         MPIC_VECPRI_VECTOR_MASK                 0x000007ff
  92 #define         MPIC_VECPRI_POLARITY_POSITIVE           0x00800000
  93 #define         MPIC_VECPRI_POLARITY_NEGATIVE           0x00000000
  94 #define         MPIC_VECPRI_POLARITY_MASK               0x00800000
  95 #define         MPIC_VECPRI_SENSE_LEVEL                 0x00400000
  96 #define         MPIC_VECPRI_SENSE_EDGE                  0x00000000
  97 #define         MPIC_VECPRI_SENSE_MASK                  0x00400000
  98 #define MPIC_IRQ_DESTINATION            0x00010
  99
 100 #define MPIC_MAX_IRQ_SOURCES    2048
 101 #define MPIC_MAX_CPUS           32
 102 #define MPIC_MAX_ISU            32
 103
 104 /*
 105  * Special vector numbers (internal use only)
 106  */
 107 #define MPIC_VEC_SPURRIOUS      255
 108 #define MPIC_VEC_IPI_3          254
 109 #define MPIC_VEC_IPI_2          253
 110 #define MPIC_VEC_IPI_1          252
 111 #define MPIC_VEC_IPI_0          251
 112
 113 /* unused */
 114 #define MPIC_VEC_TIMER_3        250
 115 #define MPIC_VEC_TIMER_2        249
 116 #define MPIC_VEC_TIMER_1        248
 117 #define MPIC_VEC_TIMER_0        247
 118
 119 /*
 120  * Tsi108 implementation of MPIC has many differences from the original one
 121  */
 122
 123 /*
 124  * Global registers
 125  */
 126
 127 #define TSI108_GREG_BASE                0x00000
 128 #define TSI108_GREG_FEATURE_0           0x00000
 129 #define TSI108_GREG_GLOBAL_CONF_0       0x00004
 130 #define TSI108_GREG_VENDOR_ID           0x0000c
 131 #define TSI108_GREG_IPI_VECTOR_PRI_0    0x00204         /* Doorbell 0 */
 132 #define TSI108_GREG_IPI_STRIDE          0x0c
 133 #define TSI108_GREG_SPURIOUS            0x00010
 134 #define TSI108_GREG_TIMER_FREQ          0x00014
 135
 136 /*
 137  * Timer registers
 138  */
 139 #define TSI108_TIMER_BASE               0x0030
 140 #define TSI108_TIMER_STRIDE             0x10
 141 #define TSI108_TIMER_CURRENT_CNT        0x00000
 142 #define TSI108_TIMER_BASE_CNT           0x00004
 143 #define TSI108_TIMER_VECTOR_PRI         0x00008
 144 #define TSI108_TIMER_DESTINATION        0x0000c
 145
 146 /*
 147  * Per-Processor registers
 148  */
 149 #define TSI108_CPU_BASE                 0x00300
 150 #define TSI108_CPU_STRIDE               0x00040
 151 #define TSI108_CPU_IPI_DISPATCH_0       0x00200
 152 #define TSI108_CPU_IPI_DISPATCH_STRIDE  0x00000
 153 #define TSI108_CPU_CURRENT_TASK_PRI     0x00000
 154 #define TSI108_CPU_WHOAMI               0xffffffff
 155 #define TSI108_CPU_INTACK               0x00004
 156 #define TSI108_CPU_EOI                  0x00008
 157
 158 /*
 159  * Per-source registers
 160  */
 161 #define TSI108_IRQ_BASE                 0x00100
 162 #define TSI108_IRQ_STRIDE               0x00008
 163 #define TSI108_IRQ_VECTOR_PRI           0x00000
 164 #define TSI108_VECPRI_VECTOR_MASK       0x000000ff
 165 #define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
 166 #define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
 167 #define TSI108_VECPRI_SENSE_LEVEL       0x02000000
 168 #define TSI108_VECPRI_SENSE_EDGE        0x00000000
 169 #define TSI108_VECPRI_POLARITY_MASK     0x01000000
 170 #define TSI108_VECPRI_SENSE_MASK        0x02000000
 171 #define TSI108_IRQ_DESTINATION          0x00004
 172
 173 /* weird mpic register indices and mask bits in the HW info array */
 174 enum {
 175         MPIC_IDX_GREG_BASE = 0,
 176         MPIC_IDX_GREG_FEATURE_0,
 177         MPIC_IDX_GREG_GLOBAL_CONF_0,
 178         MPIC_IDX_GREG_VENDOR_ID,
 179         MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
 180         MPIC_IDX_GREG_IPI_STRIDE,
 181         MPIC_IDX_GREG_SPURIOUS,
 182         MPIC_IDX_GREG_TIMER_FREQ,
 183
 184         MPIC_IDX_TIMER_BASE,
 185         MPIC_IDX_TIMER_STRIDE,
 186         MPIC_IDX_TIMER_CURRENT_CNT,
 187         MPIC_IDX_TIMER_BASE_CNT,
 188         MPIC_IDX_TIMER_VECTOR_PRI,
 189         MPIC_IDX_TIMER_DESTINATION,
 190
 191         MPIC_IDX_CPU_BASE,
 192         MPIC_IDX_CPU_STRIDE,
 193         MPIC_IDX_CPU_IPI_DISPATCH_0,
 194         MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
 195         MPIC_IDX_CPU_CURRENT_TASK_PRI,
 196         MPIC_IDX_CPU_WHOAMI,
 197         MPIC_IDX_CPU_INTACK,
 198         MPIC_IDX_CPU_EOI,
 199
 200         MPIC_IDX_IRQ_BASE,
 201         MPIC_IDX_IRQ_STRIDE,
 202         MPIC_IDX_IRQ_VECTOR_PRI,
 203
 204         MPIC_IDX_VECPRI_VECTOR_MASK,
 205         MPIC_IDX_VECPRI_POLARITY_POSITIVE,
 206         MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
 207         MPIC_IDX_VECPRI_SENSE_LEVEL,
 208         MPIC_IDX_VECPRI_SENSE_EDGE,
 209         MPIC_IDX_VECPRI_POLARITY_MASK,
 210         MPIC_IDX_VECPRI_SENSE_MASK,
 211         MPIC_IDX_IRQ_DESTINATION,
 212         MPIC_IDX_END
 213 };
 214
 215
 216 #ifdef CONFIG_MPIC_BROKEN_U3
 217 /* Fixup table entry */
 218 struct mpic_irq_fixup
 219 {
 220         u8 __iomem      *base;
 221         u8 __iomem      *applebase;
 222         u32             data;
 223         unsigned int    index;
 224 };
 225 #endif /* CONFIG_MPIC_BROKEN_U3 */
 226
 227
 228 /* The instance data of a given MPIC */
 229 struct mpic
 230 {
 231         /* The device node of the interrupt controller */
 232         struct device_node      *of_node;
 233
 234         /* The remapper for this MPIC */
 235         struct irq_host         *irqhost;
 236
 237         /* The "linux" controller struct */
 238         struct irq_chip         hc_irq;
 239 #ifdef CONFIG_MPIC_BROKEN_U3
 240         struct irq_chip         hc_ht_irq;
 241 #endif
 242 #ifdef CONFIG_SMP
 243         struct irq_chip         hc_ipi;
 244 #endif
 245         const char              *name;
 246         /* Flags */
 247         unsigned int            flags;
 248         /* How many irq sources in a given ISU */
 249         unsigned int            isu_size;
 250         unsigned int            isu_shift;
 251         unsigned int            isu_mask;
 252         unsigned int            irq_count;
 253         /* Number of sources */
 254         unsigned int            num_sources;
 255         /* Number of CPUs */
 256         unsigned int            num_cpus;
 257         /* default senses array */
 258         unsigned char           *senses;
 259         unsigned int            senses_count;
 260
 261 #ifdef CONFIG_MPIC_BROKEN_U3
 262         /* The fixup table */
 263         struct mpic_irq_fixup   *fixups;
 264         spinlock_t              fixup_lock;
 265 #endif
 266
 267         /* The various ioremap'ed bases */
 268         volatile u32 __iomem    *gregs;
 269         volatile u32 __iomem    *tmregs;
 270         volatile u32 __iomem    *cpuregs[MPIC_MAX_CPUS];
 271         volatile u32 __iomem    *isus[MPIC_MAX_ISU];
 272
 273 #ifdef CONFIG_MPIC_WEIRD
 274         /* Pointer to HW info array */
 275         u32                     *hw_set;
 276 #endif
 277
 278         /* link */
 279         struct mpic             *next;
 280 };
 281
 282 /*
 283  * MPIC flags (passed to mpic_alloc)
 284  *
 285  * The top 4 bits contain an MPIC bhw id that is used to index the
 286  * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
 287  * Note setting any ID (leaving those bits to 0) means standard MPIC
 288  */
 289
 290 /* This is the primary controller, only that one has IPIs and
 291  * has afinity control. A non-primary MPIC always uses CPU0
 292  * registers only
 293  */
 294 #define MPIC_PRIMARY                    0x00000001
 295
 296 /* Set this for a big-endian MPIC */
 297 #define MPIC_BIG_ENDIAN                 0x00000002
 298 /* Broken U3 MPIC */
 299 #define MPIC_BROKEN_U3                  0x00000004
 300 /* Broken IPI registers (autodetected) */
 301 #define MPIC_BROKEN_IPI                 0x00000008
 302 /* MPIC wants a reset */
 303 #define MPIC_WANTS_RESET                0x00000010
 304 /* Spurious vector requires EOI */
 305 #define MPIC_SPV_EOI                    0x00000020
 306 /* No passthrough disable */
 307 #define MPIC_NO_PTHROU_DIS              0x00000040
 308
 309 /* MPIC HW modification ID */
 310 #define MPIC_REGSET_MASK                0xf0000000
 311 #define MPIC_REGSET(val)                (((val) & 0xf ) << 28)
 312 #define MPIC_GET_REGSET(flags)          (((flags) >> 28) & 0xf)
 313
 314 #define MPIC_REGSET_STANDARD            MPIC_REGSET(0)  /* Original MPIC */
 315 #define MPIC_REGSET_TSI108              MPIC_REGSET(1)  /* Tsi108/109 PIC */
 316
 317 /* Allocate the controller structure and setup the linux irq descs
 318  * for the range if interrupts passed in. No HW initialization is
 319  * actually performed.
 320  *
 321  * @phys_addr:  physial base address of the MPIC
 322  * @flags:      flags, see constants above
 323  * @isu_size:   number of interrupts in an ISU. Use 0 to use a
 324  *              standard ISU-less setup (aka powermac)
 325  * @irq_offset: first irq number to assign to this mpic
 326  * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
 327  *              to match the number of sources
 328  * @ipi_offset: first irq number to assign to this mpic IPI sources,
 329  *              used only on primary mpic
 330  * @senses:     array of sense values
 331  * @senses_num: number of entries in the array
 332  *
 333  * Note about the sense array. If none is passed, all interrupts are
 334  * setup to be level negative unless MPIC_BROKEN_U3 is set in which
 335  * case they are edge positive (and the array is ignored anyway).
 336  * The values in the array start at the first source of the MPIC,
 337  * that is senses[0] correspond to linux irq "irq_offset".
 338  */
 339 extern struct mpic *mpic_alloc(struct device_node *node,
 340                                unsigned long phys_addr,
 341                                unsigned int flags,
 342                                unsigned int isu_size,
 343                                unsigned int irq_count,
 344                                const char *name);
 345
 346 /* Assign ISUs, to call before mpic_init()
 347  *
 348  * @mpic:       controller structure as returned by mpic_alloc()
 349  * @isu_num:    ISU number
 350  * @phys_addr:  physical address of the ISU
 351  */
 352 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
 353                             unsigned long phys_addr);
 354
 355 /* Set default sense codes
 356  *
 357  * @mpic:       controller
 358  * @senses:     array of sense codes
 359  * @count:      size of above array
 360  *
 361  * Optionally provide an array (indexed on hardware interrupt numbers
 362  * for this MPIC) of default sense codes for the chip. Those are linux
 363  * sense codes IRQ_TYPE_*
 364  *
 365  * The driver gets ownership of the pointer, don't dispose of it or
 366  * anything like that. __init only.
 367  */
 368 extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
 369
 370
 371 /* Initialize the controller. After this has been called, none of the above
 372  * should be called again for this mpic
 373  */
 374 extern void mpic_init(struct mpic *mpic);
 375
 376 /*
 377  * All of the following functions must only be used after the
 378  * ISUs have been assigned and the controller fully initialized
 379  * with mpic_init()
 380  */
 381
 382
 383 /* Change/Read the priority of an interrupt. Default is 8 for irqs and
 384  * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
 385  * IPI number is then the offset'ed (linux irq number mapped to the IPI)
 386  */
 387 extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
 388 extern unsigned int mpic_irq_get_priority(unsigned int irq);
 389
 390 /* Setup a non-boot CPU */
 391 extern void mpic_setup_this_cpu(void);
 392
 393 /* Clean up for kexec (or cpu offline or ...) */
 394 extern void mpic_teardown_this_cpu(int secondary);
 395
 396 /* Get the current cpu priority for this cpu (0..15) */
 397 extern int mpic_cpu_get_priority(void);
 398
 399 /* Set the current cpu priority for this cpu */
 400 extern void mpic_cpu_set_priority(int prio);
 401
 402 /* Request IPIs on primary mpic */
 403 extern void mpic_request_ipis(void);
 404
 405 /* Send an IPI (non offseted number 0..3) */
 406 extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
 407
 408 /* Send a message (IPI) to a given target (cpu number or MSG_*) */
 409 void smp_mpic_message_pass(int target, int msg);
 410
 411 /* Fetch interrupt from a given mpic */
 412 extern unsigned int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs);
 413 /* This one gets to the primary mpic */
 414 extern unsigned int mpic_get_irq(struct pt_regs *regs);
 415
 416 /* Set the EPIC clock ratio */
 417 void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
 418
 419 /* Enable/Disable EPIC serial interrupt mode */
 420 void mpic_set_serial_int(struct mpic *mpic, int enable);
 421
 422 #endif /* __KERNEL__ */
 423 #endif  /* _ASM_POWERPC_MPIC_H */