arch/x86/kernel/genx2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/threads.h>
  13 #include <linux/cpumask.h>
  14 #include <linux/string.h>
  15 #include <linux/ctype.h>
  16 #include <linux/init.h>
  17 #include <linux/sched.h>
  18 #include <linux/module.h>
  19 #include <linux/hardirq.h>
  20 #include <asm/smp.h>
  21 #include <asm/ipi.h>
  22 #include <asm/genapic.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/uv/uv_mmrs.h>
  25 #include <asm/uv/uv_hub.h>
  26 #include <asm/uv/bios.h>
  27
  28 DEFINE_PER_CPU(int, x2apic_extra_bits);
  29
  30 static enum uv_system_type uv_system_type;
  31
  32 static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  33 {
  34         if (!strcmp(oem_id, "SGI")) {
  35                 if (!strcmp(oem_table_id, "UVL"))
  36                         uv_system_type = UV_LEGACY_APIC;
  37                 else if (!strcmp(oem_table_id, "UVX"))
  38                         uv_system_type = UV_X2APIC;
  39                 else if (!strcmp(oem_table_id, "UVH")) {
  40                         uv_system_type = UV_NON_UNIQUE_APIC;
  41                         return 1;
  42                 }
  43         }
  44         return 0;
  45 }
  46
  47 enum uv_system_type get_uv_system_type(void)
  48 {
  49         return uv_system_type;
  50 }
  51
  52 int is_uv_system(void)
  53 {
  54         return uv_system_type != UV_NONE;
  55 }
  56 EXPORT_SYMBOL_GPL(is_uv_system);
  57
  58 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  59 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  60
  61 struct uv_blade_info *uv_blade_info;
  62 EXPORT_SYMBOL_GPL(uv_blade_info);
  63
  64 short *uv_node_to_blade;
  65 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  66
  67 short *uv_cpu_to_blade;
  68 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
  69
  70 short uv_possible_blades;
  71 EXPORT_SYMBOL_GPL(uv_possible_blades);
  72
  73 unsigned long sn_rtc_cycles_per_second;
  74 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
  75
  76 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
  77
  78 static const struct cpumask *uv_target_cpus(void)
  79 {
  80         return cpumask_of(0);
  81 }
  82
  83 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
  84 {
  85         cpumask_clear(retmask);
  86         cpumask_set_cpu(cpu, retmask);
  87 }
  88
  89 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
  90 {
  91         unsigned long val;
  92         int pnode;
  93
  94         pnode = uv_apicid_to_pnode(phys_apicid);
  95         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
  96             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
  97             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
  98             APIC_DM_INIT;
  99         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 100         mdelay(10);
 101
 102         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 103             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 104             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 105             APIC_DM_STARTUP;
 106         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 107         return 0;
 108 }
 109
 110 static void uv_send_IPI_one(int cpu, int vector)
 111 {
 112         unsigned long val, apicid, lapicid;
 113         int pnode;
 114
 115         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 116         lapicid = apicid & 0x3f;                /* ZZZ macro needed */
 117         pnode = uv_apicid_to_pnode(apicid);
 118         val =
 119             (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
 120                                               UVH_IPI_INT_APIC_ID_SHFT) |
 121             (vector << UVH_IPI_INT_VECTOR_SHFT);
 122         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 123 }
 124
 125 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 126 {
 127         unsigned int cpu;
 128
 129         for_each_cpu(cpu, mask)
 130                 uv_send_IPI_one(cpu, vector);
 131 }
 132
 133 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 134 {
 135         unsigned int cpu;
 136         unsigned int this_cpu = smp_processor_id();
 137
 138         for_each_cpu(cpu, mask)
 139                 if (cpu != this_cpu)
 140                         uv_send_IPI_one(cpu, vector);
 141 }
 142
 143 static void uv_send_IPI_allbutself(int vector)
 144 {
 145         unsigned int cpu;
 146         unsigned int this_cpu = smp_processor_id();
 147
 148         for_each_online_cpu(cpu)
 149                 if (cpu != this_cpu)
 150                         uv_send_IPI_one(cpu, vector);
 151 }
 152
 153 static void uv_send_IPI_all(int vector)
 154 {
 155         uv_send_IPI_mask(cpu_online_mask, vector);
 156 }
 157
 158 static int uv_apic_id_registered(void)
 159 {
 160         return 1;
 161 }
 162
 163 static void uv_init_apic_ldr(void)
 164 {
 165 }
 166
 167 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
 168 {
 169         int cpu;
 170
 171         /*
 172          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 173          * May as well be the first.
 174          */
 175         cpu = cpumask_first(cpumask);
 176         if ((unsigned)cpu < nr_cpu_ids)
 177                 return per_cpu(x86_cpu_to_apicid, cpu);
 178         else
 179                 return BAD_APICID;
 180 }
 181
 182 static unsigned int uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 183                                               const struct cpumask *andmask)
 184 {
 185         int cpu;
 186
 187         /*
 188          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 189          * May as well be the first.
 190          */
 191         cpu = cpumask_any_and(cpumask, andmask);
 192         if (cpu < nr_cpu_ids)
 193                 return per_cpu(x86_cpu_to_apicid, cpu);
 194         return BAD_APICID;
 195 }
 196
 197 static unsigned int get_apic_id(unsigned long x)
 198 {
 199         unsigned int id;
 200
 201         WARN_ON(preemptible() && num_online_cpus() > 1);
 202         id = x | __get_cpu_var(x2apic_extra_bits);
 203
 204         return id;
 205 }
 206
 207 static unsigned long set_apic_id(unsigned int id)
 208 {
 209         unsigned long x;
 210
 211         /* maskout x2apic_extra_bits ? */
 212         x = id;
 213         return x;
 214 }
 215
 216 static unsigned int uv_read_apic_id(void)
 217 {
 218
 219         return get_apic_id(apic_read(APIC_ID));
 220 }
 221
 222 static unsigned int phys_pkg_id(int index_msb)
 223 {
 224         return uv_read_apic_id() >> index_msb;
 225 }
 226
 227 static void uv_send_IPI_self(int vector)
 228 {
 229         apic_write(APIC_SELF_IPI, vector);
 230 }
 231
 232 struct genapic apic_x2apic_uv_x = {
 233         .name = "UV large system",
 234         .acpi_madt_oem_check = uv_acpi_madt_oem_check,
 235         .int_delivery_mode = dest_Fixed,
 236         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
 237         .target_cpus = uv_target_cpus,
 238         .vector_allocation_domain = uv_vector_allocation_domain,
 239         .apic_id_registered = uv_apic_id_registered,
 240         .init_apic_ldr = uv_init_apic_ldr,
 241         .send_IPI_all = uv_send_IPI_all,
 242         .send_IPI_allbutself = uv_send_IPI_allbutself,
 243         .send_IPI_mask = uv_send_IPI_mask,
 244         .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
 245         .send_IPI_self = uv_send_IPI_self,
 246         .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
 247         .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
 248         .phys_pkg_id = phys_pkg_id,
 249         .get_apic_id = get_apic_id,
 250         .set_apic_id = set_apic_id,
 251         .apic_id_mask = (0xFFFFFFFFu),
 252 };
 253
 254 static __cpuinit void set_x2apic_extra_bits(int pnode)
 255 {
 256         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 257 }
 258
 259 /*
 260  * Called on boot cpu.
 261  */
 262 static __init int boot_pnode_to_blade(int pnode)
 263 {
 264         int blade;
 265
 266         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 267                 if (pnode == uv_blade_info[blade].pnode)
 268                         return blade;
 269         BUG();
 270 }
 271
 272 struct redir_addr {
 273         unsigned long redirect;
 274         unsigned long alias;
 275 };
 276
 277 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 278
 279 static __initdata struct redir_addr redir_addrs[] = {
 280         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 281         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 282         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 283 };
 284
 285 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 286 {
 287         union uvh_si_alias0_overlay_config_u alias;
 288         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 289         int i;
 290
 291         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 292                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 293                 if (alias.s.base == 0) {
 294                         *size = (1UL << alias.s.m_alias);
 295                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 296                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 297                         return;
 298                 }
 299         }
 300         BUG();
 301 }
 302
 303 static __init void map_low_mmrs(void)
 304 {
 305         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 306         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 307 }
 308
 309 enum map_type {map_wb, map_uc};
 310
 311 static __init void map_high(char *id, unsigned long base, int shift,
 312                             int max_pnode, enum map_type map_type)
 313 {
 314         unsigned long bytes, paddr;
 315
 316         paddr = base << shift;
 317         bytes = (1UL << shift) * (max_pnode + 1);
 318         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 319                                                 paddr + bytes);
 320         if (map_type == map_uc)
 321                 init_extra_mapping_uc(paddr, bytes);
 322         else
 323                 init_extra_mapping_wb(paddr, bytes);
 324
 325 }
 326 static __init void map_gru_high(int max_pnode)
 327 {
 328         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 329         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 330
 331         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 332         if (gru.s.enable)
 333                 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
 334 }
 335
 336 static __init void map_config_high(int max_pnode)
 337 {
 338         union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
 339         int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
 340
 341         cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
 342         if (cfg.s.enable)
 343                 map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
 344 }
 345
 346 static __init void map_mmr_high(int max_pnode)
 347 {
 348         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 349         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 350
 351         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 352         if (mmr.s.enable)
 353                 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
 354 }
 355
 356 static __init void map_mmioh_high(int max_pnode)
 357 {
 358         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 359         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 360
 361         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 362         if (mmioh.s.enable)
 363                 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
 364 }
 365
 366 static __init void uv_rtc_init(void)
 367 {
 368         long status;
 369         u64 ticks_per_sec;
 370
 371         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 372                                         &ticks_per_sec);
 373         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 374                 printk(KERN_WARNING
 375                         "unable to determine platform RTC clock frequency, "
 376                         "guessing.\n");
 377                 /* BIOS gives wrong value for clock freq. so guess */
 378                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 379         } else
 380                 sn_rtc_cycles_per_second = ticks_per_sec;
 381 }
 382
 383 /*
 384  * Called on each cpu to initialize the per_cpu UV data area.
 385  *      ZZZ hotplug not supported yet
 386  */
 387 void __cpuinit uv_cpu_init(void)
 388 {
 389         /* CPU 0 initilization will be done via uv_system_init. */
 390         if (!uv_blade_info)
 391                 return;
 392
 393         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 394
 395         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 396                 set_x2apic_extra_bits(uv_hub_info->pnode);
 397 }
 398
 399
 400 void __init uv_system_init(void)
 401 {
 402         union uvh_si_addr_map_config_u m_n_config;
 403         union uvh_node_id_u node_id;
 404         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 405         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 406         int max_pnode = 0;
 407         unsigned long mmr_base, present;
 408
 409         map_low_mmrs();
 410
 411         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 412         m_val = m_n_config.s.m_skt;
 413         n_val = m_n_config.s.n_skt;
 414         mmr_base =
 415             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 416             ~UV_MMR_ENABLE;
 417         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 418
 419         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 420                 uv_possible_blades +=
 421                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 422         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 423
 424         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 425         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 426
 427         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 428
 429         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 430         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 431         memset(uv_node_to_blade, 255, bytes);
 432
 433         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 434         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 435         memset(uv_cpu_to_blade, 255, bytes);
 436
 437         blade = 0;
 438         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 439                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 440                 for (j = 0; j < 64; j++) {
 441                         if (!test_bit(j, &present))
 442                                 continue;
 443                         uv_blade_info[blade].pnode = (i * 64 + j);
 444                         uv_blade_info[blade].nr_possible_cpus = 0;
 445                         uv_blade_info[blade].nr_online_cpus = 0;
 446                         blade++;
 447                 }
 448         }
 449
 450         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 451         gnode_upper = (((unsigned long)node_id.s.node_id) &
 452                        ~((1 << n_val) - 1)) << m_val;
 453
 454         uv_bios_init();
 455         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
 456                             &uv_coherency_id, &uv_region_size);
 457         uv_rtc_init();
 458
 459         for_each_present_cpu(cpu) {
 460                 nid = cpu_to_node(cpu);
 461                 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
 462                 blade = boot_pnode_to_blade(pnode);
 463                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 464                 uv_blade_info[blade].nr_possible_cpus++;
 465
 466                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 467                 uv_cpu_hub_info(cpu)->lowmem_remap_top =
 468                                         lowmem_redir_base + lowmem_redir_size;
 469                 uv_cpu_hub_info(cpu)->m_val = m_val;
 470                 uv_cpu_hub_info(cpu)->n_val = m_val;
 471                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 472                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 473                 uv_cpu_hub_info(cpu)->pnode = pnode;
 474                 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
 475                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
 476                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 477                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 478                 uv_cpu_hub_info(cpu)->coherency_domain_number = uv_coherency_id;
 479                 uv_node_to_blade[nid] = blade;
 480                 uv_cpu_to_blade[cpu] = blade;
 481                 max_pnode = max(pnode, max_pnode);
 482
 483                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
 484                         "lcpu %d, blade %d\n",
 485                         cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
 486                         lcpu, blade);
 487         }
 488
 489         map_gru_high(max_pnode);
 490         map_mmr_high(max_pnode);
 491         map_config_high(max_pnode);
 492         map_mmioh_high(max_pnode);
 493
 494         uv_cpu_init();
 495 }