2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
34 #include <linux/lmb.h>
36 #include <asm/processor.h>
37 #include <asm/pgtable.h>
39 #include <asm/mmu_context.h>
41 #include <asm/types.h>
42 #include <asm/system.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
46 #include <asm/abs_addr.h>
47 #include <asm/tlbflush.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
58 #define DBG(fmt...) udbg_printf(fmt)
64 #define DBG_LOW(fmt...) udbg_printf(fmt)
66 #define DBG_LOW(fmt...)
74 * Note: pte --> Linux PTE
75 * HPTE --> PowerPC Hashed Page Table Entry
78 * htab_initialize is called with the MMU off (of course), but
79 * the kernel has been copied down to zero so it can directly
80 * reference global data. At this point it is very difficult
81 * to print debug info.
86 extern unsigned long dart_tablebase
;
87 #endif /* CONFIG_U3_DART */
89 static unsigned long _SDR1
;
90 struct mmu_psize_def mmu_psize_defs
[MMU_PAGE_COUNT
];
92 struct hash_pte
*htab_address
;
93 unsigned long htab_size_bytes
;
94 unsigned long htab_hash_mask
;
95 int mmu_linear_psize
= MMU_PAGE_4K
;
96 int mmu_virtual_psize
= MMU_PAGE_4K
;
97 int mmu_vmalloc_psize
= MMU_PAGE_4K
;
98 #ifdef CONFIG_SPARSEMEM_VMEMMAP
99 int mmu_vmemmap_psize
= MMU_PAGE_4K
;
101 int mmu_io_psize
= MMU_PAGE_4K
;
102 int mmu_kernel_ssize
= MMU_SEGSIZE_256M
;
103 int mmu_highuser_ssize
= MMU_SEGSIZE_256M
;
104 u16 mmu_slb_size
= 64;
105 #ifdef CONFIG_HUGETLB_PAGE
106 unsigned int HPAGE_SHIFT
;
108 #ifdef CONFIG_PPC_64K_PAGES
109 int mmu_ci_restrictions
;
111 #ifdef CONFIG_DEBUG_PAGEALLOC
112 static u8
*linear_map_hash_slots
;
113 static unsigned long linear_map_hash_count
;
114 static DEFINE_SPINLOCK(linear_map_hash_lock
);
115 #endif /* CONFIG_DEBUG_PAGEALLOC */
117 /* There are definitions of page sizes arrays to be used when none
118 * is provided by the firmware.
121 /* Pre-POWER4 CPUs (4k pages only)
123 static struct mmu_psize_def mmu_psize_defaults_old
[] = {
133 /* POWER4, GPUL, POWER5
135 * Support for 16Mb large pages
137 static struct mmu_psize_def mmu_psize_defaults_gp
[] = {
154 static unsigned long htab_convert_pte_flags(unsigned long pteflags
)
156 unsigned long rflags
= pteflags
& 0x1fa;
158 /* _PAGE_EXEC -> NOEXEC */
159 if ((pteflags
& _PAGE_EXEC
) == 0)
162 /* PP bits. PAGE_USER is already PP bit 0x2, so we only
163 * need to add in 0x1 if it's a read-only user page
165 if ((pteflags
& _PAGE_USER
) && !((pteflags
& _PAGE_RW
) &&
166 (pteflags
& _PAGE_DIRTY
)))
170 return rflags
| HPTE_R_C
;
173 int htab_bolt_mapping(unsigned long vstart
, unsigned long vend
,
174 unsigned long pstart
, unsigned long prot
,
175 int psize
, int ssize
)
177 unsigned long vaddr
, paddr
;
178 unsigned int step
, shift
;
181 shift
= mmu_psize_defs
[psize
].shift
;
184 prot
= htab_convert_pte_flags(prot
);
186 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
187 vstart
, vend
, pstart
, prot
, psize
, ssize
);
189 for (vaddr
= vstart
, paddr
= pstart
; vaddr
< vend
;
190 vaddr
+= step
, paddr
+= step
) {
191 unsigned long hash
, hpteg
;
192 unsigned long vsid
= get_kernel_vsid(vaddr
, ssize
);
193 unsigned long va
= hpt_va(vaddr
, vsid
, ssize
);
195 hash
= hpt_hash(va
, shift
, ssize
);
196 hpteg
= ((hash
& htab_hash_mask
) * HPTES_PER_GROUP
);
198 BUG_ON(!ppc_md
.hpte_insert
);
199 ret
= ppc_md
.hpte_insert(hpteg
, va
, paddr
, prot
,
200 HPTE_V_BOLTED
, psize
, ssize
);
204 #ifdef CONFIG_DEBUG_PAGEALLOC
205 if ((paddr
>> PAGE_SHIFT
) < linear_map_hash_count
)
206 linear_map_hash_slots
[paddr
>> PAGE_SHIFT
] = ret
| 0x80;
207 #endif /* CONFIG_DEBUG_PAGEALLOC */
209 return ret
< 0 ? ret
: 0;
212 #ifdef CONFIG_MEMORY_HOTPLUG
213 static int htab_remove_mapping(unsigned long vstart
, unsigned long vend
,
214 int psize
, int ssize
)
217 unsigned int step
, shift
;
219 shift
= mmu_psize_defs
[psize
].shift
;
222 if (!ppc_md
.hpte_removebolted
) {
223 printk(KERN_WARNING
"Platform doesn't implement "
224 "hpte_removebolted\n");
228 for (vaddr
= vstart
; vaddr
< vend
; vaddr
+= step
)
229 ppc_md
.hpte_removebolted(vaddr
, psize
, ssize
);
233 #endif /* CONFIG_MEMORY_HOTPLUG */
235 static int __init
htab_dt_scan_seg_sizes(unsigned long node
,
236 const char *uname
, int depth
,
239 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
241 unsigned long size
= 0;
243 /* We are scanning "cpu" nodes only */
244 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
247 prop
= (u32
*)of_get_flat_dt_prop(node
, "ibm,processor-segment-sizes",
251 for (; size
>= 4; size
-= 4, ++prop
) {
253 DBG("1T segment support detected\n");
254 cur_cpu_spec
->cpu_features
|= CPU_FTR_1T_SEGMENT
;
258 cur_cpu_spec
->cpu_features
&= ~CPU_FTR_NO_SLBIE_B
;
262 static void __init
htab_init_seg_sizes(void)
264 of_scan_flat_dt(htab_dt_scan_seg_sizes
, NULL
);
267 static int __init
htab_dt_scan_page_sizes(unsigned long node
,
268 const char *uname
, int depth
,
271 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
273 unsigned long size
= 0;
275 /* We are scanning "cpu" nodes only */
276 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
279 prop
= (u32
*)of_get_flat_dt_prop(node
,
280 "ibm,segment-page-sizes", &size
);
282 DBG("Page sizes from device-tree:\n");
284 cur_cpu_spec
->cpu_features
&= ~(CPU_FTR_16M_PAGE
);
286 unsigned int shift
= prop
[0];
287 unsigned int slbenc
= prop
[1];
288 unsigned int lpnum
= prop
[2];
289 unsigned int lpenc
= 0;
290 struct mmu_psize_def
*def
;
293 size
-= 3; prop
+= 3;
294 while(size
> 0 && lpnum
) {
295 if (prop
[0] == shift
)
297 prop
+= 2; size
-= 2;
312 cur_cpu_spec
->cpu_features
|= CPU_FTR_16M_PAGE
;
320 def
= &mmu_psize_defs
[idx
];
325 def
->avpnm
= (1 << (shift
- 23)) - 1;
328 /* We don't know for sure what's up with tlbiel, so
329 * for now we only set it for 4K and 64K pages
331 if (idx
== MMU_PAGE_4K
|| idx
== MMU_PAGE_64K
)
336 DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
337 "tlbiel=%d, penc=%d\n",
338 idx
, shift
, def
->sllp
, def
->avpnm
, def
->tlbiel
,
346 /* Scan for 16G memory blocks that have been set aside for huge pages
347 * and reserve those blocks for 16G huge pages.
349 static int __init
htab_dt_scan_hugepage_blocks(unsigned long node
,
350 const char *uname
, int depth
,
352 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
353 unsigned long *addr_prop
;
354 u32
*page_count_prop
;
355 unsigned int expected_pages
;
356 long unsigned int phys_addr
;
357 long unsigned int block_size
;
359 /* We are scanning "memory" nodes only */
360 if (type
== NULL
|| strcmp(type
, "memory") != 0)
363 /* This property is the log base 2 of the number of virtual pages that
364 * will represent this memory block. */
365 page_count_prop
= of_get_flat_dt_prop(node
, "ibm,expected#pages", NULL
);
366 if (page_count_prop
== NULL
)
368 expected_pages
= (1 << page_count_prop
[0]);
369 addr_prop
= of_get_flat_dt_prop(node
, "reg", NULL
);
370 if (addr_prop
== NULL
)
372 phys_addr
= addr_prop
[0];
373 block_size
= addr_prop
[1];
374 if (block_size
!= (16 * GB
))
376 printk(KERN_INFO
"Huge page(16GB) memory: "
377 "addr = 0x%lX size = 0x%lX pages = %d\n",
378 phys_addr
, block_size
, expected_pages
);
379 lmb_reserve(phys_addr
, block_size
* expected_pages
);
380 add_gpage(phys_addr
, block_size
, expected_pages
);
384 static void __init
htab_init_page_sizes(void)
388 /* Default to 4K pages only */
389 memcpy(mmu_psize_defs
, mmu_psize_defaults_old
,
390 sizeof(mmu_psize_defaults_old
));
393 * Try to find the available page sizes in the device-tree
395 rc
= of_scan_flat_dt(htab_dt_scan_page_sizes
, NULL
);
396 if (rc
!= 0) /* Found */
400 * Not in the device-tree, let's fallback on known size
401 * list for 16M capable GP & GR
403 if (cpu_has_feature(CPU_FTR_16M_PAGE
))
404 memcpy(mmu_psize_defs
, mmu_psize_defaults_gp
,
405 sizeof(mmu_psize_defaults_gp
));
407 #ifndef CONFIG_DEBUG_PAGEALLOC
409 * Pick a size for the linear mapping. Currently, we only support
410 * 16M, 1M and 4K which is the default
412 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
)
413 mmu_linear_psize
= MMU_PAGE_16M
;
414 else if (mmu_psize_defs
[MMU_PAGE_1M
].shift
)
415 mmu_linear_psize
= MMU_PAGE_1M
;
416 #endif /* CONFIG_DEBUG_PAGEALLOC */
418 #ifdef CONFIG_PPC_64K_PAGES
420 * Pick a size for the ordinary pages. Default is 4K, we support
421 * 64K for user mappings and vmalloc if supported by the processor.
422 * We only use 64k for ioremap if the processor
423 * (and firmware) support cache-inhibited large pages.
424 * If not, we use 4k and set mmu_ci_restrictions so that
425 * hash_page knows to switch processes that use cache-inhibited
426 * mappings to 4k pages.
428 if (mmu_psize_defs
[MMU_PAGE_64K
].shift
) {
429 mmu_virtual_psize
= MMU_PAGE_64K
;
430 mmu_vmalloc_psize
= MMU_PAGE_64K
;
431 if (mmu_linear_psize
== MMU_PAGE_4K
)
432 mmu_linear_psize
= MMU_PAGE_64K
;
433 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE
)) {
435 * Don't use 64k pages for ioremap on pSeries, since
436 * that would stop us accessing the HEA ethernet.
438 if (!machine_is(pseries
))
439 mmu_io_psize
= MMU_PAGE_64K
;
441 mmu_ci_restrictions
= 1;
443 #endif /* CONFIG_PPC_64K_PAGES */
445 #ifdef CONFIG_SPARSEMEM_VMEMMAP
446 /* We try to use 16M pages for vmemmap if that is supported
447 * and we have at least 1G of RAM at boot
449 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
&&
450 lmb_phys_mem_size() >= 0x40000000)
451 mmu_vmemmap_psize
= MMU_PAGE_16M
;
452 else if (mmu_psize_defs
[MMU_PAGE_64K
].shift
)
453 mmu_vmemmap_psize
= MMU_PAGE_64K
;
455 mmu_vmemmap_psize
= MMU_PAGE_4K
;
456 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
458 printk(KERN_DEBUG
"Page orders: linear mapping = %d, "
459 "virtual = %d, io = %d"
460 #ifdef CONFIG_SPARSEMEM_VMEMMAP
464 mmu_psize_defs
[mmu_linear_psize
].shift
,
465 mmu_psize_defs
[mmu_virtual_psize
].shift
,
466 mmu_psize_defs
[mmu_io_psize
].shift
467 #ifdef CONFIG_SPARSEMEM_VMEMMAP
468 ,mmu_psize_defs
[mmu_vmemmap_psize
].shift
472 #ifdef CONFIG_HUGETLB_PAGE
473 /* Reserve 16G huge page memory sections for huge pages */
474 of_scan_flat_dt(htab_dt_scan_hugepage_blocks
, NULL
);
476 /* Set default large page size. Currently, we pick 16M or 1M depending
477 * on what is available
479 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
)
480 HPAGE_SHIFT
= mmu_psize_defs
[MMU_PAGE_16M
].shift
;
481 /* With 4k/4level pagetables, we can't (for now) cope with a
482 * huge page size < PMD_SIZE */
483 else if (mmu_psize_defs
[MMU_PAGE_1M
].shift
)
484 HPAGE_SHIFT
= mmu_psize_defs
[MMU_PAGE_1M
].shift
;
485 #endif /* CONFIG_HUGETLB_PAGE */
488 static int __init
htab_dt_scan_pftsize(unsigned long node
,
489 const char *uname
, int depth
,
492 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
495 /* We are scanning "cpu" nodes only */
496 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
499 prop
= (u32
*)of_get_flat_dt_prop(node
, "ibm,pft-size", NULL
);
501 /* pft_size[0] is the NUMA CEC cookie */
502 ppc64_pft_size
= prop
[1];
508 static unsigned long __init
htab_get_table_size(void)
510 unsigned long mem_size
, rnd_mem_size
, pteg_count
;
512 /* If hash size isn't already provided by the platform, we try to
513 * retrieve it from the device-tree. If it's not there neither, we
514 * calculate it now based on the total RAM size
516 if (ppc64_pft_size
== 0)
517 of_scan_flat_dt(htab_dt_scan_pftsize
, NULL
);
519 return 1UL << ppc64_pft_size
;
521 /* round mem_size up to next power of 2 */
522 mem_size
= lmb_phys_mem_size();
523 rnd_mem_size
= 1UL << __ilog2(mem_size
);
524 if (rnd_mem_size
< mem_size
)
528 pteg_count
= max(rnd_mem_size
>> (12 + 1), 1UL << 11);
530 return pteg_count
<< 7;
533 #ifdef CONFIG_MEMORY_HOTPLUG
534 void create_section_mapping(unsigned long start
, unsigned long end
)
536 BUG_ON(htab_bolt_mapping(start
, end
, __pa(start
),
537 PAGE_KERNEL
, mmu_linear_psize
,
541 int remove_section_mapping(unsigned long start
, unsigned long end
)
543 return htab_remove_mapping(start
, end
, mmu_linear_psize
,
546 #endif /* CONFIG_MEMORY_HOTPLUG */
548 static inline void make_bl(unsigned int *insn_addr
, void *func
)
550 unsigned long funcp
= *((unsigned long *)func
);
551 int offset
= funcp
- (unsigned long)insn_addr
;
553 *insn_addr
= (unsigned int)(0x48000001 | (offset
& 0x03fffffc));
554 flush_icache_range((unsigned long)insn_addr
, 4+
555 (unsigned long)insn_addr
);
558 static void __init
htab_finish_init(void)
560 extern unsigned int *htab_call_hpte_insert1
;
561 extern unsigned int *htab_call_hpte_insert2
;
562 extern unsigned int *htab_call_hpte_remove
;
563 extern unsigned int *htab_call_hpte_updatepp
;
565 #ifdef CONFIG_PPC_HAS_HASH_64K
566 extern unsigned int *ht64_call_hpte_insert1
;
567 extern unsigned int *ht64_call_hpte_insert2
;
568 extern unsigned int *ht64_call_hpte_remove
;
569 extern unsigned int *ht64_call_hpte_updatepp
;
571 make_bl(ht64_call_hpte_insert1
, ppc_md
.hpte_insert
);
572 make_bl(ht64_call_hpte_insert2
, ppc_md
.hpte_insert
);
573 make_bl(ht64_call_hpte_remove
, ppc_md
.hpte_remove
);
574 make_bl(ht64_call_hpte_updatepp
, ppc_md
.hpte_updatepp
);
575 #endif /* CONFIG_PPC_HAS_HASH_64K */
577 make_bl(htab_call_hpte_insert1
, ppc_md
.hpte_insert
);
578 make_bl(htab_call_hpte_insert2
, ppc_md
.hpte_insert
);
579 make_bl(htab_call_hpte_remove
, ppc_md
.hpte_remove
);
580 make_bl(htab_call_hpte_updatepp
, ppc_md
.hpte_updatepp
);
583 void __init
htab_initialize(void)
586 unsigned long pteg_count
;
587 unsigned long prot
, tprot
;
588 unsigned long base
= 0, size
= 0, limit
;
591 DBG(" -> htab_initialize()\n");
593 /* Initialize segment sizes */
594 htab_init_seg_sizes();
596 /* Initialize page sizes */
597 htab_init_page_sizes();
599 if (cpu_has_feature(CPU_FTR_1T_SEGMENT
)) {
600 mmu_kernel_ssize
= MMU_SEGSIZE_1T
;
601 mmu_highuser_ssize
= MMU_SEGSIZE_1T
;
602 printk(KERN_INFO
"Using 1TB segments\n");
606 * Calculate the required size of the htab. We want the number of
607 * PTEGs to equal one half the number of real pages.
609 htab_size_bytes
= htab_get_table_size();
610 pteg_count
= htab_size_bytes
>> 7;
612 htab_hash_mask
= pteg_count
- 1;
614 if (firmware_has_feature(FW_FEATURE_LPAR
)) {
615 /* Using a hypervisor which owns the htab */
619 /* Find storage for the HPT. Must be contiguous in
620 * the absolute address space. On cell we want it to be
621 * in the first 2 Gig so we can use it for IOMMU hacks.
623 if (machine_is(cell
))
628 table
= lmb_alloc_base(htab_size_bytes
, htab_size_bytes
, limit
);
630 DBG("Hash table allocated at %lx, size: %lx\n", table
,
633 htab_address
= abs_to_virt(table
);
635 /* htab absolute addr + encoded htabsize */
636 _SDR1
= table
+ __ilog2(pteg_count
) - 11;
638 /* Initialize the HPT with no entries */
639 memset((void *)table
, 0, htab_size_bytes
);
642 mtspr(SPRN_SDR1
, _SDR1
);
647 #ifdef CONFIG_DEBUG_PAGEALLOC
648 linear_map_hash_count
= lmb_end_of_DRAM() >> PAGE_SHIFT
;
649 linear_map_hash_slots
= __va(lmb_alloc_base(linear_map_hash_count
,
651 memset(linear_map_hash_slots
, 0, linear_map_hash_count
);
652 #endif /* CONFIG_DEBUG_PAGEALLOC */
654 /* On U3 based machines, we need to reserve the DART area and
655 * _NOT_ map it to avoid cache paradoxes as it's remapped non
659 /* create bolted the linear mapping in the hash table */
660 for (i
=0; i
< lmb
.memory
.cnt
; i
++) {
661 base
= (unsigned long)__va(lmb
.memory
.region
[i
].base
);
662 size
= lmb
.memory
.region
[i
].size
;
663 tprot
= prot
| (in_kernel_text(base
) ? _PAGE_EXEC
: 0);
665 DBG("creating mapping for region: %lx..%lx (prot: %x)\n",
668 #ifdef CONFIG_U3_DART
669 /* Do not map the DART space. Fortunately, it will be aligned
670 * in such a way that it will not cross two lmb regions and
671 * will fit within a single 16Mb page.
672 * The DART space is assumed to be a full 16Mb region even if
673 * we only use 2Mb of that space. We will use more of it later
674 * for AGP GART. We have to use a full 16Mb large page.
676 DBG("DART base: %lx\n", dart_tablebase
);
678 if (dart_tablebase
!= 0 && dart_tablebase
>= base
679 && dart_tablebase
< (base
+ size
)) {
680 unsigned long dart_table_end
= dart_tablebase
+ 16 * MB
;
681 if (base
!= dart_tablebase
)
682 BUG_ON(htab_bolt_mapping(base
, dart_tablebase
,
686 if ((base
+ size
) > dart_table_end
)
687 BUG_ON(htab_bolt_mapping(dart_tablebase
+16*MB
,
689 __pa(dart_table_end
),
695 #endif /* CONFIG_U3_DART */
696 BUG_ON(htab_bolt_mapping(base
, base
+ size
, __pa(base
),
697 tprot
, mmu_linear_psize
, mmu_kernel_ssize
));
701 * If we have a memory_limit and we've allocated TCEs then we need to
702 * explicitly map the TCE area at the top of RAM. We also cope with the
703 * case that the TCEs start below memory_limit.
704 * tce_alloc_start/end are 16MB aligned so the mapping should work
705 * for either 4K or 16MB pages.
707 if (tce_alloc_start
) {
708 tce_alloc_start
= (unsigned long)__va(tce_alloc_start
);
709 tce_alloc_end
= (unsigned long)__va(tce_alloc_end
);
711 if (base
+ size
>= tce_alloc_start
)
712 tce_alloc_start
= base
+ size
+ 1;
714 BUG_ON(htab_bolt_mapping(tce_alloc_start
, tce_alloc_end
,
715 __pa(tce_alloc_start
), prot
,
716 mmu_linear_psize
, mmu_kernel_ssize
));
721 DBG(" <- htab_initialize()\n");
726 void htab_initialize_secondary(void)
728 if (!firmware_has_feature(FW_FEATURE_LPAR
))
729 mtspr(SPRN_SDR1
, _SDR1
);
733 * Called by asm hashtable.S for doing lazy icache flush
735 unsigned int hash_page_do_lazy_icache(unsigned int pp
, pte_t pte
, int trap
)
739 if (!pfn_valid(pte_pfn(pte
)))
742 page
= pte_page(pte
);
745 if (!test_bit(PG_arch_1
, &page
->flags
) && !PageReserved(page
)) {
747 __flush_dcache_icache(page_address(page
));
748 set_bit(PG_arch_1
, &page
->flags
);
755 #ifdef CONFIG_PPC_MM_SLICES
756 unsigned int get_paca_psize(unsigned long addr
)
758 unsigned long index
, slices
;
760 if (addr
< SLICE_LOW_TOP
) {
761 slices
= get_paca()->context
.low_slices_psize
;
762 index
= GET_LOW_SLICE_INDEX(addr
);
764 slices
= get_paca()->context
.high_slices_psize
;
765 index
= GET_HIGH_SLICE_INDEX(addr
);
767 return (slices
>> (index
* 4)) & 0xF;
771 unsigned int get_paca_psize(unsigned long addr
)
773 return get_paca()->context
.user_psize
;
778 * Demote a segment to using 4k pages.
779 * For now this makes the whole process use 4k pages.
781 #ifdef CONFIG_PPC_64K_PAGES
782 void demote_segment_4k(struct mm_struct
*mm
, unsigned long addr
)
784 if (get_slice_psize(mm
, addr
) == MMU_PAGE_4K
)
786 slice_set_range_psize(mm
, addr
, 1, MMU_PAGE_4K
);
787 #ifdef CONFIG_SPU_BASE
788 spu_flush_all_slbs(mm
);
790 if (get_paca_psize(addr
) != MMU_PAGE_4K
) {
791 get_paca()->context
= mm
->context
;
792 slb_flush_and_rebolt();
795 #endif /* CONFIG_PPC_64K_PAGES */
797 #ifdef CONFIG_PPC_SUBPAGE_PROT
799 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
800 * Userspace sets the subpage permissions using the subpage_prot system call.
802 * Result is 0: full permissions, _PAGE_RW: read-only,
803 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
805 static int subpage_protection(pgd_t
*pgdir
, unsigned long ea
)
807 struct subpage_prot_table
*spt
= pgd_subpage_prot(pgdir
);
811 if (ea
>= spt
->maxaddr
)
813 if (ea
< 0x100000000) {
814 /* addresses below 4GB use spt->low_prot */
815 sbpm
= spt
->low_prot
;
817 sbpm
= spt
->protptrs
[ea
>> SBP_L3_SHIFT
];
821 sbpp
= sbpm
[(ea
>> SBP_L2_SHIFT
) & (SBP_L2_COUNT
- 1)];
824 spp
= sbpp
[(ea
>> PAGE_SHIFT
) & (SBP_L1_COUNT
- 1)];
826 /* extract 2-bit bitfield for this 4k subpage */
827 spp
>>= 30 - 2 * ((ea
>> 12) & 0xf);
829 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
830 spp
= ((spp
& 2) ? _PAGE_USER
: 0) | ((spp
& 1) ? _PAGE_RW
: 0);
834 #else /* CONFIG_PPC_SUBPAGE_PROT */
835 static inline int subpage_protection(pgd_t
*pgdir
, unsigned long ea
)
843 * 1 - normal page fault
844 * -1 - critical hash insertion error
845 * -2 - access not permitted by subpage protection mechanism
847 int hash_page(unsigned long ea
, unsigned long access
, unsigned long trap
)
851 struct mm_struct
*mm
;
854 int rc
, user_region
= 0, local
= 0;
857 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
860 if ((ea
& ~REGION_MASK
) >= PGTABLE_RANGE
) {
861 DBG_LOW(" out of pgtable range !\n");
865 /* Get region & vsid */
866 switch (REGION_ID(ea
)) {
871 DBG_LOW(" user region with no mm !\n");
874 psize
= get_slice_psize(mm
, ea
);
875 ssize
= user_segment_size(ea
);
876 vsid
= get_vsid(mm
->context
.id
, ea
, ssize
);
878 case VMALLOC_REGION_ID
:
880 vsid
= get_kernel_vsid(ea
, mmu_kernel_ssize
);
881 if (ea
< VMALLOC_END
)
882 psize
= mmu_vmalloc_psize
;
884 psize
= mmu_io_psize
;
885 ssize
= mmu_kernel_ssize
;
889 * Send the problem up to do_page_fault
893 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm
, mm
->pgd
, vsid
);
900 /* Check CPU locality */
901 tmp
= cpumask_of_cpu(smp_processor_id());
902 if (user_region
&& cpus_equal(mm
->cpu_vm_mask
, tmp
))
905 #ifdef CONFIG_HUGETLB_PAGE
906 /* Handle hugepage regions */
907 if (HPAGE_SHIFT
&& mmu_huge_psizes
[psize
]) {
908 DBG_LOW(" -> huge page !\n");
909 return hash_huge_page(mm
, access
, ea
, vsid
, local
, trap
);
911 #endif /* CONFIG_HUGETLB_PAGE */
913 #ifndef CONFIG_PPC_64K_PAGES
914 /* If we use 4K pages and our psize is not 4K, then we are hitting
915 * a special driver mapping, we need to align the address before
918 if (psize
!= MMU_PAGE_4K
)
919 ea
&= ~((1ul << mmu_psize_defs
[psize
].shift
) - 1);
920 #endif /* CONFIG_PPC_64K_PAGES */
922 /* Get PTE and page size from page tables */
923 ptep
= find_linux_pte(pgdir
, ea
);
924 if (ptep
== NULL
|| !pte_present(*ptep
)) {
925 DBG_LOW(" no PTE !\n");
929 #ifndef CONFIG_PPC_64K_PAGES
930 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep
));
932 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep
),
933 pte_val(*(ptep
+ PTRS_PER_PTE
)));
935 /* Pre-check access permissions (will be re-checked atomically
936 * in __hash_page_XX but this pre-check is a fast path
938 if (access
& ~pte_val(*ptep
)) {
939 DBG_LOW(" no access !\n");
943 /* Do actual hashing */
944 #ifdef CONFIG_PPC_64K_PAGES
945 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
946 if ((pte_val(*ptep
) & _PAGE_4K_PFN
) && psize
== MMU_PAGE_64K
) {
947 demote_segment_4k(mm
, ea
);
951 /* If this PTE is non-cacheable and we have restrictions on
952 * using non cacheable large pages, then we switch to 4k
954 if (mmu_ci_restrictions
&& psize
== MMU_PAGE_64K
&&
955 (pte_val(*ptep
) & _PAGE_NO_CACHE
)) {
957 demote_segment_4k(mm
, ea
);
959 } else if (ea
< VMALLOC_END
) {
961 * some driver did a non-cacheable mapping
962 * in vmalloc space, so switch vmalloc
965 printk(KERN_ALERT
"Reducing vmalloc segment "
966 "to 4kB pages because of "
967 "non-cacheable mapping\n");
968 psize
= mmu_vmalloc_psize
= MMU_PAGE_4K
;
969 #ifdef CONFIG_SPU_BASE
970 spu_flush_all_slbs(mm
);
975 if (psize
!= get_paca_psize(ea
)) {
976 get_paca()->context
= mm
->context
;
977 slb_flush_and_rebolt();
979 } else if (get_paca()->vmalloc_sllp
!=
980 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
) {
981 get_paca()->vmalloc_sllp
=
982 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
;
983 slb_vmalloc_update();
985 #endif /* CONFIG_PPC_64K_PAGES */
987 #ifdef CONFIG_PPC_HAS_HASH_64K
988 if (psize
== MMU_PAGE_64K
)
989 rc
= __hash_page_64K(ea
, access
, vsid
, ptep
, trap
, local
, ssize
);
991 #endif /* CONFIG_PPC_HAS_HASH_64K */
993 int spp
= subpage_protection(pgdir
, ea
);
997 rc
= __hash_page_4K(ea
, access
, vsid
, ptep
, trap
,
1001 #ifndef CONFIG_PPC_64K_PAGES
1002 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep
));
1004 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep
),
1005 pte_val(*(ptep
+ PTRS_PER_PTE
)));
1007 DBG_LOW(" -> rc=%d\n", rc
);
1010 EXPORT_SYMBOL_GPL(hash_page
);
1012 void hash_preload(struct mm_struct
*mm
, unsigned long ea
,
1013 unsigned long access
, unsigned long trap
)
1019 unsigned long flags
;
1023 BUG_ON(REGION_ID(ea
) != USER_REGION_ID
);
1025 #ifdef CONFIG_PPC_MM_SLICES
1026 /* We only prefault standard pages for now */
1027 if (unlikely(get_slice_psize(mm
, ea
) != mm
->context
.user_psize
))
1031 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1032 " trap=%lx\n", mm
, mm
->pgd
, ea
, access
, trap
);
1034 /* Get Linux PTE if available */
1038 ptep
= find_linux_pte(pgdir
, ea
);
1042 #ifdef CONFIG_PPC_64K_PAGES
1043 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1044 * a 64K kernel), then we don't preload, hash_page() will take
1045 * care of it once we actually try to access the page.
1046 * That way we don't have to duplicate all of the logic for segment
1047 * page size demotion here
1049 if (pte_val(*ptep
) & (_PAGE_4K_PFN
| _PAGE_NO_CACHE
))
1051 #endif /* CONFIG_PPC_64K_PAGES */
1054 ssize
= user_segment_size(ea
);
1055 vsid
= get_vsid(mm
->context
.id
, ea
, ssize
);
1057 /* Hash doesn't like irqs */
1058 local_irq_save(flags
);
1060 /* Is that local to this CPU ? */
1061 mask
= cpumask_of_cpu(smp_processor_id());
1062 if (cpus_equal(mm
->cpu_vm_mask
, mask
))
1066 #ifdef CONFIG_PPC_HAS_HASH_64K
1067 if (mm
->context
.user_psize
== MMU_PAGE_64K
)
1068 __hash_page_64K(ea
, access
, vsid
, ptep
, trap
, local
, ssize
);
1070 #endif /* CONFIG_PPC_HAS_HASH_64K */
1071 __hash_page_4K(ea
, access
, vsid
, ptep
, trap
, local
, ssize
,
1072 subpage_protection(pgdir
, ea
));
1074 local_irq_restore(flags
);
1077 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1078 * do not forget to update the assembly call site !
1080 void flush_hash_page(unsigned long va
, real_pte_t pte
, int psize
, int ssize
,
1083 unsigned long hash
, index
, shift
, hidx
, slot
;
1085 DBG_LOW("flush_hash_page(va=%016x)\n", va
);
1086 pte_iterate_hashed_subpages(pte
, psize
, va
, index
, shift
) {
1087 hash
= hpt_hash(va
, shift
, ssize
);
1088 hidx
= __rpte_to_hidx(pte
, index
);
1089 if (hidx
& _PTEIDX_SECONDARY
)
1091 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
1092 slot
+= hidx
& _PTEIDX_GROUP_IX
;
1093 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index
, slot
, hidx
);
1094 ppc_md
.hpte_invalidate(slot
, va
, psize
, ssize
, local
);
1095 } pte_iterate_hashed_end();
1098 void flush_hash_range(unsigned long number
, int local
)
1100 if (ppc_md
.flush_hash_range
)
1101 ppc_md
.flush_hash_range(number
, local
);
1104 struct ppc64_tlb_batch
*batch
=
1105 &__get_cpu_var(ppc64_tlb_batch
);
1107 for (i
= 0; i
< number
; i
++)
1108 flush_hash_page(batch
->vaddr
[i
], batch
->pte
[i
],
1109 batch
->psize
, batch
->ssize
, local
);
1114 * low_hash_fault is called when we the low level hash code failed
1115 * to instert a PTE due to an hypervisor error
1117 void low_hash_fault(struct pt_regs
*regs
, unsigned long address
, int rc
)
1119 if (user_mode(regs
)) {
1120 #ifdef CONFIG_PPC_SUBPAGE_PROT
1122 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, address
);
1125 _exception(SIGBUS
, regs
, BUS_ADRERR
, address
);
1127 bad_page_fault(regs
, address
, SIGBUS
);
1130 #ifdef CONFIG_DEBUG_PAGEALLOC
1131 static void kernel_map_linear_page(unsigned long vaddr
, unsigned long lmi
)
1133 unsigned long hash
, hpteg
;
1134 unsigned long vsid
= get_kernel_vsid(vaddr
, mmu_kernel_ssize
);
1135 unsigned long va
= hpt_va(vaddr
, vsid
, mmu_kernel_ssize
);
1136 unsigned long mode
= htab_convert_pte_flags(PAGE_KERNEL
);
1139 hash
= hpt_hash(va
, PAGE_SHIFT
, mmu_kernel_ssize
);
1140 hpteg
= ((hash
& htab_hash_mask
) * HPTES_PER_GROUP
);
1142 ret
= ppc_md
.hpte_insert(hpteg
, va
, __pa(vaddr
),
1143 mode
, HPTE_V_BOLTED
,
1144 mmu_linear_psize
, mmu_kernel_ssize
);
1146 spin_lock(&linear_map_hash_lock
);
1147 BUG_ON(linear_map_hash_slots
[lmi
] & 0x80);
1148 linear_map_hash_slots
[lmi
] = ret
| 0x80;
1149 spin_unlock(&linear_map_hash_lock
);
1152 static void kernel_unmap_linear_page(unsigned long vaddr
, unsigned long lmi
)
1154 unsigned long hash
, hidx
, slot
;
1155 unsigned long vsid
= get_kernel_vsid(vaddr
, mmu_kernel_ssize
);
1156 unsigned long va
= hpt_va(vaddr
, vsid
, mmu_kernel_ssize
);
1158 hash
= hpt_hash(va
, PAGE_SHIFT
, mmu_kernel_ssize
);
1159 spin_lock(&linear_map_hash_lock
);
1160 BUG_ON(!(linear_map_hash_slots
[lmi
] & 0x80));
1161 hidx
= linear_map_hash_slots
[lmi
] & 0x7f;
1162 linear_map_hash_slots
[lmi
] = 0;
1163 spin_unlock(&linear_map_hash_lock
);
1164 if (hidx
& _PTEIDX_SECONDARY
)
1166 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
1167 slot
+= hidx
& _PTEIDX_GROUP_IX
;
1168 ppc_md
.hpte_invalidate(slot
, va
, mmu_linear_psize
, mmu_kernel_ssize
, 0);
1171 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1173 unsigned long flags
, vaddr
, lmi
;
1176 local_irq_save(flags
);
1177 for (i
= 0; i
< numpages
; i
++, page
++) {
1178 vaddr
= (unsigned long)page_address(page
);
1179 lmi
= __pa(vaddr
) >> PAGE_SHIFT
;
1180 if (lmi
>= linear_map_hash_count
)
1183 kernel_map_linear_page(vaddr
, lmi
);
1185 kernel_unmap_linear_page(vaddr
, lmi
);
1187 local_irq_restore(flags
);
1189 #endif /* CONFIG_DEBUG_PAGEALLOC */