2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/interrupt.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/kernel_stat.h>
26 #include <linux/sysdev.h>
27 #include <linux/cpu.h>
28 #include <linux/module.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
35 #include <asm/arch_hooks.h>
37 #include <asm/i8253.h>
40 #include <mach_apic.h>
41 #include <mach_apicdef.h>
47 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
48 * IPIs in place of local APIC timers
50 static cpumask_t timer_bcast_ipi
;
53 * Knob to control our willingness to enable the local APIC.
55 static int enable_local_apic __initdata
= 0; /* -1=force-disable, +1=force-enable */
57 static inline void lapic_disable(void)
59 enable_local_apic
= -1;
60 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
63 static inline void lapic_enable(void)
65 enable_local_apic
= 1;
74 static void apic_pm_activate(void);
76 static int modern_apic(void)
78 unsigned int lvr
, version
;
79 /* AMD systems use old APIC versions, so check the CPU */
80 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
81 boot_cpu_data
.x86
>= 0xf)
83 lvr
= apic_read(APIC_LVR
);
84 version
= GET_APIC_VERSION(lvr
);
85 return version
>= 0x14;
89 * 'what should we do if we get a hw irq event on an illegal vector'.
90 * each architecture has to answer this themselves.
92 void ack_bad_irq(unsigned int irq
)
94 printk("unexpected IRQ trap at vector %02x\n", irq
);
96 * Currently unexpected vectors happen only on SMP and APIC.
97 * We _must_ ack these because every local APIC has only N
98 * irq slots per priority level, and a 'hanging, unacked' IRQ
99 * holds up an irq slot - in excessive cases (when multiple
100 * unexpected vectors occur) that might lock up the APIC
102 * But only ack when the APIC is enabled -AK
108 void __init
apic_intr_init(void)
113 /* self generated IPI for local APIC timer */
114 set_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
116 /* IPI vectors for APIC spurious and error interrupts */
117 set_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
118 set_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
120 /* thermal monitor LVT interrupt */
121 #ifdef CONFIG_X86_MCE_P4THERMAL
122 set_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
126 /* Using APIC to generate smp_local_timer_interrupt? */
127 int using_apic_timer __read_mostly
= 0;
129 static int enabled_via_apicbase
;
131 void enable_NMI_through_LVT0 (void * dummy
)
135 ver
= apic_read(APIC_LVR
);
136 ver
= GET_APIC_VERSION(ver
);
137 v
= APIC_DM_NMI
; /* unmask and set to NMI */
138 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
139 v
|= APIC_LVT_LEVEL_TRIGGER
;
140 apic_write_around(APIC_LVT0
, v
);
143 int get_physical_broadcast(void)
153 unsigned int v
, ver
, maxlvt
;
155 v
= apic_read(APIC_LVR
);
156 ver
= GET_APIC_VERSION(v
);
157 /* 82489DXs do not report # of LVT entries. */
158 maxlvt
= APIC_INTEGRATED(ver
) ? GET_APIC_MAXLVT(v
) : 2;
162 void clear_local_APIC(void)
167 maxlvt
= get_maxlvt();
170 * Masking an LVT entry can trigger a local APIC error
171 * if the vector is zero. Mask LVTERR first to prevent this.
174 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
175 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
178 * Careful: we have to set masks only first to deassert
179 * any level-triggered sources.
181 v
= apic_read(APIC_LVTT
);
182 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
183 v
= apic_read(APIC_LVT0
);
184 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
185 v
= apic_read(APIC_LVT1
);
186 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
188 v
= apic_read(APIC_LVTPC
);
189 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
192 /* lets not touch this if we didn't frob it */
193 #ifdef CONFIG_X86_MCE_P4THERMAL
195 v
= apic_read(APIC_LVTTHMR
);
196 apic_write_around(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
200 * Clean APIC state for other OSs:
202 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
203 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
204 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
206 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
208 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
210 #ifdef CONFIG_X86_MCE_P4THERMAL
212 apic_write_around(APIC_LVTTHMR
, APIC_LVT_MASKED
);
214 v
= GET_APIC_VERSION(apic_read(APIC_LVR
));
215 if (APIC_INTEGRATED(v
)) { /* !82489DX */
216 if (maxlvt
> 3) /* Due to Pentium errata 3AP and 11AP. */
217 apic_write(APIC_ESR
, 0);
222 void __init
connect_bsp_APIC(void)
226 * Do not trust the local APIC being empty at bootup.
230 * PIC mode, enable APIC mode in the IMCR, i.e.
231 * connect BSP's local APIC to INT and NMI lines.
233 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
234 "enabling APIC mode.\n");
241 void disconnect_bsp_APIC(int virt_wire_setup
)
245 * Put the board back into PIC mode (has an effect
246 * only on certain older boards). Note that APIC
247 * interrupts, including IPIs, won't work beyond
248 * this point! The only exception are INIT IPIs.
250 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
251 "entering PIC mode.\n");
256 /* Go back to Virtual Wire compatibility mode */
259 /* For the spurious interrupt use vector F, and enable it */
260 value
= apic_read(APIC_SPIV
);
261 value
&= ~APIC_VECTOR_MASK
;
262 value
|= APIC_SPIV_APIC_ENABLED
;
264 apic_write_around(APIC_SPIV
, value
);
266 if (!virt_wire_setup
) {
267 /* For LVT0 make it edge triggered, active high, external and enabled */
268 value
= apic_read(APIC_LVT0
);
269 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
270 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
271 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
272 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
273 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
274 apic_write_around(APIC_LVT0
, value
);
278 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
281 /* For LVT1 make it edge triggered, active high, nmi and enabled */
282 value
= apic_read(APIC_LVT1
);
284 APIC_MODE_MASK
| APIC_SEND_PENDING
|
285 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
286 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
287 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
288 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
289 apic_write_around(APIC_LVT1
, value
);
293 void disable_local_APIC(void)
300 * Disable APIC (implies clearing of registers
303 value
= apic_read(APIC_SPIV
);
304 value
&= ~APIC_SPIV_APIC_ENABLED
;
305 apic_write_around(APIC_SPIV
, value
);
307 if (enabled_via_apicbase
) {
309 rdmsr(MSR_IA32_APICBASE
, l
, h
);
310 l
&= ~MSR_IA32_APICBASE_ENABLE
;
311 wrmsr(MSR_IA32_APICBASE
, l
, h
);
316 * This is to verify that we're looking at a real local APIC.
317 * Check these against your board if the CPUs aren't getting
318 * started for no apparent reason.
320 int __init
verify_local_APIC(void)
322 unsigned int reg0
, reg1
;
325 * The version register is read-only in a real APIC.
327 reg0
= apic_read(APIC_LVR
);
328 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
329 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
330 reg1
= apic_read(APIC_LVR
);
331 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
334 * The two version reads above should print the same
335 * numbers. If the second one is different, then we
336 * poke at a non-APIC.
342 * Check if the version looks reasonably.
344 reg1
= GET_APIC_VERSION(reg0
);
345 if (reg1
== 0x00 || reg1
== 0xff)
348 if (reg1
< 0x02 || reg1
== 0xff)
352 * The ID register is read/write in a real APIC.
354 reg0
= apic_read(APIC_ID
);
355 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
358 * The next two are just to see if we have sane values.
359 * They're only really relevant if we're in Virtual Wire
360 * compatibility mode, but most boxes are anymore.
362 reg0
= apic_read(APIC_LVT0
);
363 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
364 reg1
= apic_read(APIC_LVT1
);
365 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
370 void __init
sync_Arb_IDs(void)
372 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1
373 And not needed on AMD */
379 apic_wait_icr_idle();
381 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
382 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
386 extern void __error_in_apic_c (void);
389 * An initial setup of the virtual wire mode.
391 void __init
init_bsp_APIC(void)
393 unsigned long value
, ver
;
396 * Don't do the setup now if we have a SMP BIOS as the
397 * through-I/O-APIC virtual wire mode might be active.
399 if (smp_found_config
|| !cpu_has_apic
)
402 value
= apic_read(APIC_LVR
);
403 ver
= GET_APIC_VERSION(value
);
406 * Do not trust the local APIC being empty at bootup.
413 value
= apic_read(APIC_SPIV
);
414 value
&= ~APIC_VECTOR_MASK
;
415 value
|= APIC_SPIV_APIC_ENABLED
;
417 /* This bit is reserved on P4/Xeon and should be cleared */
418 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 15))
419 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
421 value
|= APIC_SPIV_FOCUS_DISABLED
;
422 value
|= SPURIOUS_APIC_VECTOR
;
423 apic_write_around(APIC_SPIV
, value
);
426 * Set up the virtual wire mode.
428 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
430 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
431 value
|= APIC_LVT_LEVEL_TRIGGER
;
432 apic_write_around(APIC_LVT1
, value
);
435 void __devinit
setup_local_APIC(void)
437 unsigned long oldvalue
, value
, ver
, maxlvt
;
440 /* Pound the ESR really hard over the head with a big hammer - mbligh */
442 apic_write(APIC_ESR
, 0);
443 apic_write(APIC_ESR
, 0);
444 apic_write(APIC_ESR
, 0);
445 apic_write(APIC_ESR
, 0);
448 value
= apic_read(APIC_LVR
);
449 ver
= GET_APIC_VERSION(value
);
451 if ((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f)
455 * Double-check whether this APIC is really registered.
457 if (!apic_id_registered())
461 * Intel recommends to set DFR, LDR and TPR before enabling
462 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
463 * document number 292116). So here it goes...
468 * Set Task Priority to 'accept all'. We never change this
471 value
= apic_read(APIC_TASKPRI
);
472 value
&= ~APIC_TPRI_MASK
;
473 apic_write_around(APIC_TASKPRI
, value
);
476 * After a crash, we no longer service the interrupts and a pending
477 * interrupt from previous kernel might still have ISR bit set.
479 * Most probably by now CPU has serviced that pending interrupt and
480 * it might not have done the ack_APIC_irq() because it thought,
481 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
482 * does not clear the ISR bit and cpu thinks it has already serivced
483 * the interrupt. Hence a vector might get locked. It was noticed
484 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
486 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
487 value
= apic_read(APIC_ISR
+ i
*0x10);
488 for (j
= 31; j
>= 0; j
--) {
495 * Now that we are all set up, enable the APIC
497 value
= apic_read(APIC_SPIV
);
498 value
&= ~APIC_VECTOR_MASK
;
502 value
|= APIC_SPIV_APIC_ENABLED
;
505 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
506 * certain networking cards. If high frequency interrupts are
507 * happening on a particular IOAPIC pin, plus the IOAPIC routing
508 * entry is masked/unmasked at a high rate as well then sooner or
509 * later IOAPIC line gets 'stuck', no more interrupts are received
510 * from the device. If focus CPU is disabled then the hang goes
513 * [ This bug can be reproduced easily with a level-triggered
514 * PCI Ne2000 networking cards and PII/PIII processors, dual
518 * Actually disabling the focus CPU check just makes the hang less
519 * frequent as it makes the interrupt distributon model be more
520 * like LRU than MRU (the short-term load is more even across CPUs).
521 * See also the comment in end_level_ioapic_irq(). --macro
524 /* Enable focus processor (bit==0) */
525 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
527 /* Disable focus processor (bit==1) */
528 value
|= APIC_SPIV_FOCUS_DISABLED
;
531 * Set spurious IRQ vector
533 value
|= SPURIOUS_APIC_VECTOR
;
534 apic_write_around(APIC_SPIV
, value
);
539 * set up through-local-APIC on the BP's LINT0. This is not
540 * strictly necessery in pure symmetric-IO mode, but sometimes
541 * we delegate interrupts to the 8259A.
544 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
546 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
547 if (!smp_processor_id() && (pic_mode
|| !value
)) {
548 value
= APIC_DM_EXTINT
;
549 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
552 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
553 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
556 apic_write_around(APIC_LVT0
, value
);
559 * only the BP should see the LINT1 NMI signal, obviously.
561 if (!smp_processor_id())
564 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
565 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
566 value
|= APIC_LVT_LEVEL_TRIGGER
;
567 apic_write_around(APIC_LVT1
, value
);
569 if (APIC_INTEGRATED(ver
) && !esr_disable
) { /* !82489DX */
570 maxlvt
= get_maxlvt();
571 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
572 apic_write(APIC_ESR
, 0);
573 oldvalue
= apic_read(APIC_ESR
);
575 value
= ERROR_APIC_VECTOR
; // enables sending errors
576 apic_write_around(APIC_LVTERR
, value
);
578 * spec says clear errors after enabling vector.
581 apic_write(APIC_ESR
, 0);
582 value
= apic_read(APIC_ESR
);
583 if (value
!= oldvalue
)
584 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
585 "vector: 0x%08lx after: 0x%08lx\n",
590 * Something untraceble is creating bad interrupts on
591 * secondary quads ... for the moment, just leave the
592 * ESR disabled - we can't do anything useful with the
593 * errors anyway - mbligh
595 printk("Leaving ESR disabled.\n");
597 printk("No ESR for 82489DX.\n");
600 setup_apic_nmi_watchdog(NULL
);
605 * If Linux enabled the LAPIC against the BIOS default
606 * disable it down before re-entering the BIOS on shutdown.
607 * Otherwise the BIOS may get confused and not power-off.
608 * Additionally clear all LVT entries before disable_local_APIC
609 * for the case where Linux didn't enable the LAPIC.
611 void lapic_shutdown(void)
618 local_irq_save(flags
);
621 if (enabled_via_apicbase
)
622 disable_local_APIC();
624 local_irq_restore(flags
);
631 /* r/w apic fields */
632 unsigned int apic_id
;
633 unsigned int apic_taskpri
;
634 unsigned int apic_ldr
;
635 unsigned int apic_dfr
;
636 unsigned int apic_spiv
;
637 unsigned int apic_lvtt
;
638 unsigned int apic_lvtpc
;
639 unsigned int apic_lvt0
;
640 unsigned int apic_lvt1
;
641 unsigned int apic_lvterr
;
642 unsigned int apic_tmict
;
643 unsigned int apic_tdcr
;
644 unsigned int apic_thmr
;
647 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
652 if (!apic_pm_state
.active
)
655 maxlvt
= get_maxlvt();
657 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
658 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
659 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
660 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
661 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
662 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
664 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
665 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
666 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
667 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
668 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
669 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
670 #ifdef CONFIG_X86_MCE_P4THERMAL
672 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
675 local_irq_save(flags
);
676 disable_local_APIC();
677 local_irq_restore(flags
);
681 static int lapic_resume(struct sys_device
*dev
)
687 if (!apic_pm_state
.active
)
690 maxlvt
= get_maxlvt();
692 local_irq_save(flags
);
695 * Make sure the APICBASE points to the right address
697 * FIXME! This will be wrong if we ever support suspend on
698 * SMP! We'll need to do this as part of the CPU restore!
700 rdmsr(MSR_IA32_APICBASE
, l
, h
);
701 l
&= ~MSR_IA32_APICBASE_BASE
;
702 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
703 wrmsr(MSR_IA32_APICBASE
, l
, h
);
705 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
706 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
707 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
708 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
709 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
710 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
711 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
712 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
713 #ifdef CONFIG_X86_MCE_P4THERMAL
715 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
718 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
719 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
720 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
721 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
722 apic_write(APIC_ESR
, 0);
724 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
725 apic_write(APIC_ESR
, 0);
727 local_irq_restore(flags
);
732 * This device has no shutdown method - fully functioning local APICs
733 * are needed on every CPU up until machine_halt/restart/poweroff.
736 static struct sysdev_class lapic_sysclass
= {
737 set_kset_name("lapic"),
738 .resume
= lapic_resume
,
739 .suspend
= lapic_suspend
,
742 static struct sys_device device_lapic
= {
744 .cls
= &lapic_sysclass
,
747 static void __devinit
apic_pm_activate(void)
749 apic_pm_state
.active
= 1;
752 static int __init
init_lapic_sysfs(void)
758 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
760 error
= sysdev_class_register(&lapic_sysclass
);
762 error
= sysdev_register(&device_lapic
);
765 device_initcall(init_lapic_sysfs
);
767 #else /* CONFIG_PM */
769 static void apic_pm_activate(void) { }
771 #endif /* CONFIG_PM */
774 * Detect and enable local APICs on non-SMP boards.
775 * Original code written by Keir Fraser.
778 static int __init
apic_set_verbosity(char *str
)
780 if (strcmp("debug", str
) == 0)
781 apic_verbosity
= APIC_DEBUG
;
782 else if (strcmp("verbose", str
) == 0)
783 apic_verbosity
= APIC_VERBOSE
;
787 __setup("apic=", apic_set_verbosity
);
789 static int __init
detect_init_APIC (void)
793 /* Disabled by kernel option? */
794 if (enable_local_apic
< 0)
797 switch (boot_cpu_data
.x86_vendor
) {
799 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
800 (boot_cpu_data
.x86
== 15))
803 case X86_VENDOR_INTEL
:
804 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
805 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
814 * Over-ride BIOS and try to enable the local
815 * APIC only if "lapic" specified.
817 if (enable_local_apic
<= 0) {
818 printk("Local APIC disabled by BIOS -- "
819 "you can enable it with \"lapic\"\n");
823 * Some BIOSes disable the local APIC in the
824 * APIC_BASE MSR. This can only be done in
825 * software for Intel P6 or later and AMD K7
826 * (Model > 1) or later.
828 rdmsr(MSR_IA32_APICBASE
, l
, h
);
829 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
830 printk("Local APIC disabled by BIOS -- reenabling.\n");
831 l
&= ~MSR_IA32_APICBASE_BASE
;
832 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
833 wrmsr(MSR_IA32_APICBASE
, l
, h
);
834 enabled_via_apicbase
= 1;
838 * The APIC feature bit should now be enabled
841 features
= cpuid_edx(1);
842 if (!(features
& (1 << X86_FEATURE_APIC
))) {
843 printk("Could not enable APIC!\n");
846 set_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
847 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
849 /* The BIOS may have set up the APIC at some other address */
850 rdmsr(MSR_IA32_APICBASE
, l
, h
);
851 if (l
& MSR_IA32_APICBASE_ENABLE
)
852 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
854 if (nmi_watchdog
!= NMI_NONE
)
855 nmi_watchdog
= NMI_LOCAL_APIC
;
857 printk("Found and enabled local APIC!\n");
864 printk("No local APIC present or hardware disabled\n");
868 void __init
init_apic_mappings(void)
870 unsigned long apic_phys
;
873 * If no local APIC can be found then set up a fake all
874 * zeroes page to simulate the local APIC and another
875 * one for the IO-APIC.
877 if (!smp_found_config
&& detect_init_APIC()) {
878 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
879 apic_phys
= __pa(apic_phys
);
881 apic_phys
= mp_lapic_addr
;
883 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
884 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
888 * Fetch the APIC ID of the BSP in case we have a
889 * default configuration (or the MP table is broken).
891 if (boot_cpu_physical_apicid
== -1U)
892 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
894 #ifdef CONFIG_X86_IO_APIC
896 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
899 for (i
= 0; i
< nr_ioapics
; i
++) {
900 if (smp_found_config
) {
901 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
904 "WARNING: bogus zero IO-APIC "
905 "address found in MPTABLE, "
906 "disabling IO/APIC support!\n");
907 smp_found_config
= 0;
908 skip_ioapic_setup
= 1;
909 goto fake_ioapic_page
;
913 ioapic_phys
= (unsigned long)
914 alloc_bootmem_pages(PAGE_SIZE
);
915 ioapic_phys
= __pa(ioapic_phys
);
917 set_fixmap_nocache(idx
, ioapic_phys
);
918 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
919 __fix_to_virt(idx
), ioapic_phys
);
927 * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
928 * per second. We assume that the caller has already set up the local
931 * The APIC timer is not exactly sync with the external timer chip, it
932 * closely follows bus clocks.
936 * The timer chip is already set up at HZ interrupts per second here,
937 * but we do not accept timer interrupts yet. We only allow the BP
940 static unsigned int __devinit
get_8254_timer_count(void)
946 spin_lock_irqsave(&i8253_lock
, flags
);
948 outb_p(0x00, PIT_MODE
);
949 count
= inb_p(PIT_CH0
);
950 count
|= inb_p(PIT_CH0
) << 8;
952 spin_unlock_irqrestore(&i8253_lock
, flags
);
957 /* next tick in 8254 can be caught by catching timer wraparound */
958 static void __devinit
wait_8254_wraparound(void)
960 unsigned int curr_count
, prev_count
;
962 curr_count
= get_8254_timer_count();
964 prev_count
= curr_count
;
965 curr_count
= get_8254_timer_count();
967 /* workaround for broken Mercury/Neptune */
968 if (prev_count
>= curr_count
+ 0x100)
969 curr_count
= get_8254_timer_count();
971 } while (prev_count
>= curr_count
);
975 * Default initialization for 8254 timers. If we use other timers like HPET,
976 * we override this later
978 void (*wait_timer_tick
)(void) __devinitdata
= wait_8254_wraparound
;
981 * This function sets up the local APIC timer, with a timeout of
982 * 'clocks' APIC bus clock. During calibration we actually call
983 * this function twice on the boot CPU, once with a bogus timeout
984 * value, second time for real. The other (noncalibrating) CPUs
985 * call this function only once, with the real, calibrated value.
987 * We do reads before writes even if unnecessary, to get around the
988 * P5 APIC double write bug.
991 #define APIC_DIVISOR 16
993 static void __setup_APIC_LVTT(unsigned int clocks
)
995 unsigned int lvtt_value
, tmp_value
, ver
;
996 int cpu
= smp_processor_id();
998 ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
999 lvtt_value
= APIC_LVT_TIMER_PERIODIC
| LOCAL_TIMER_VECTOR
;
1000 if (!APIC_INTEGRATED(ver
))
1001 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
1003 if (cpu_isset(cpu
, timer_bcast_ipi
))
1004 lvtt_value
|= APIC_LVT_MASKED
;
1006 apic_write_around(APIC_LVTT
, lvtt_value
);
1009 * Divide PICLK by 16
1011 tmp_value
= apic_read(APIC_TDCR
);
1012 apic_write_around(APIC_TDCR
, (tmp_value
1013 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
1016 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
1019 static void __devinit
setup_APIC_timer(unsigned int clocks
)
1021 unsigned long flags
;
1023 local_irq_save(flags
);
1026 * Wait for IRQ0's slice:
1030 __setup_APIC_LVTT(clocks
);
1032 local_irq_restore(flags
);
1036 * In this function we calibrate APIC bus clocks to the external
1037 * timer. Unfortunately we cannot use jiffies and the timer irq
1038 * to calibrate, since some later bootup code depends on getting
1039 * the first irq? Ugh.
1041 * We want to do the calibration only once since we
1042 * want to have local timer irqs syncron. CPUs connected
1043 * by the same APIC bus have the very same bus frequency.
1044 * And we want to have irqs off anyways, no accidental
1045 * APIC irq that way.
1048 static int __init
calibrate_APIC_clock(void)
1050 unsigned long long t1
= 0, t2
= 0;
1054 const int LOOPS
= HZ
/10;
1056 apic_printk(APIC_VERBOSE
, "calibrating APIC timer ...\n");
1059 * Put whatever arbitrary (but long enough) timeout
1060 * value into the APIC clock, we just want to get the
1061 * counter running for calibration.
1063 __setup_APIC_LVTT(1000000000);
1066 * The timer chip counts down to zero. Let's wait
1067 * for a wraparound to start exact measurement:
1068 * (the current tick might have been already half done)
1074 * We wrapped around just now. Let's start:
1078 tt1
= apic_read(APIC_TMCCT
);
1081 * Let's wait LOOPS wraprounds:
1083 for (i
= 0; i
< LOOPS
; i
++)
1086 tt2
= apic_read(APIC_TMCCT
);
1091 * The APIC bus clock counter is 32 bits only, it
1092 * might have overflown, but note that we use signed
1093 * longs, thus no extra care needed.
1095 * underflown to be exact, as the timer counts down ;)
1098 result
= (tt1
-tt2
)*APIC_DIVISOR
/LOOPS
;
1101 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
1103 ((long)(t2
-t1
)/LOOPS
)/(1000000/HZ
),
1104 ((long)(t2
-t1
)/LOOPS
)%(1000000/HZ
));
1106 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
1108 result
/(1000000/HZ
),
1109 result
%(1000000/HZ
));
1114 static unsigned int calibration_result
;
1116 void __init
setup_boot_APIC_clock(void)
1118 unsigned long flags
;
1119 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n");
1120 using_apic_timer
= 1;
1122 local_irq_save(flags
);
1124 calibration_result
= calibrate_APIC_clock();
1126 * Now set up the timer for real.
1128 setup_APIC_timer(calibration_result
);
1130 local_irq_restore(flags
);
1133 void __devinit
setup_secondary_APIC_clock(void)
1135 setup_APIC_timer(calibration_result
);
1138 void disable_APIC_timer(void)
1140 if (using_apic_timer
) {
1143 v
= apic_read(APIC_LVTT
);
1145 * When an illegal vector value (0-15) is written to an LVT
1146 * entry and delivery mode is Fixed, the APIC may signal an
1147 * illegal vector error, with out regard to whether the mask
1148 * bit is set or whether an interrupt is actually seen on input.
1150 * Boot sequence might call this function when the LVTT has
1151 * '0' vector value. So make sure vector field is set to
1154 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1155 apic_write_around(APIC_LVTT
, v
);
1159 void enable_APIC_timer(void)
1161 int cpu
= smp_processor_id();
1163 if (using_apic_timer
&&
1164 !cpu_isset(cpu
, timer_bcast_ipi
)) {
1167 v
= apic_read(APIC_LVTT
);
1168 apic_write_around(APIC_LVTT
, v
& ~APIC_LVT_MASKED
);
1172 void switch_APIC_timer_to_ipi(void *cpumask
)
1174 cpumask_t mask
= *(cpumask_t
*)cpumask
;
1175 int cpu
= smp_processor_id();
1177 if (cpu_isset(cpu
, mask
) &&
1178 !cpu_isset(cpu
, timer_bcast_ipi
)) {
1179 disable_APIC_timer();
1180 cpu_set(cpu
, timer_bcast_ipi
);
1183 EXPORT_SYMBOL(switch_APIC_timer_to_ipi
);
1185 void switch_ipi_to_APIC_timer(void *cpumask
)
1187 cpumask_t mask
= *(cpumask_t
*)cpumask
;
1188 int cpu
= smp_processor_id();
1190 if (cpu_isset(cpu
, mask
) &&
1191 cpu_isset(cpu
, timer_bcast_ipi
)) {
1192 cpu_clear(cpu
, timer_bcast_ipi
);
1193 enable_APIC_timer();
1196 EXPORT_SYMBOL(switch_ipi_to_APIC_timer
);
1201 * Local timer interrupt handler. It does both profiling and
1202 * process statistics/rescheduling.
1204 * We do profiling in every local tick, statistics/rescheduling
1205 * happen only every 'profiling multiplier' ticks. The default
1206 * multiplier is 1 and it can be changed by writing the new multiplier
1207 * value into /proc/profile.
1210 inline void smp_local_timer_interrupt(void)
1212 profile_tick(CPU_PROFILING
);
1214 update_process_times(user_mode_vm(get_irq_regs()));
1218 * We take the 'long' return path, and there every subsystem
1219 * grabs the apropriate locks (kernel lock/ irq lock).
1221 * we might want to decouple profiling from the 'long path',
1222 * and do the profiling totally in assembly.
1224 * Currently this isn't too much of an issue (performance wise),
1225 * we can take more than 100K local irqs per second on a 100 MHz P5.
1230 * Local APIC timer interrupt. This is the most natural way for doing
1231 * local interrupts, but local timer interrupts can be emulated by
1232 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1234 * [ if a single-CPU system runs an SMP kernel then we call the local
1235 * interrupt as well. Thus we cannot inline the local irq ... ]
1238 fastcall
void smp_apic_timer_interrupt(struct pt_regs
*regs
)
1240 struct pt_regs
*old_regs
= set_irq_regs(regs
);
1241 int cpu
= smp_processor_id();
1244 * the NMI deadlock-detector uses this.
1246 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
1249 * NOTE! We'd better ACK the irq immediately,
1250 * because timer handling can be slow.
1254 * update_process_times() expects us to have done irq_enter().
1255 * Besides, if we don't timer interrupts ignore the global
1256 * interrupt lock, which is the WrongThing (tm) to do.
1259 smp_local_timer_interrupt();
1261 set_irq_regs(old_regs
);
1265 static void up_apic_timer_interrupt_call(void)
1267 int cpu
= smp_processor_id();
1270 * the NMI deadlock-detector uses this.
1272 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
1274 smp_local_timer_interrupt();
1278 void smp_send_timer_broadcast_ipi(void)
1282 cpus_and(mask
, cpu_online_map
, timer_bcast_ipi
);
1283 if (!cpus_empty(mask
)) {
1285 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
1288 * We can directly call the apic timer interrupt handler
1289 * in UP case. Minus all irq related functions
1291 up_apic_timer_interrupt_call();
1296 int setup_profiling_timer(unsigned int multiplier
)
1302 * This interrupt should _never_ happen with our APIC/SMP architecture
1304 fastcall
void smp_spurious_interrupt(struct pt_regs
*regs
)
1310 * Check if this really is a spurious interrupt and ACK it
1311 * if it is a vectored one. Just in case...
1312 * Spurious interrupts should not be ACKed.
1314 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1315 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1318 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1319 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, should never happen.\n",
1320 smp_processor_id());
1325 * This interrupt should never happen with our APIC/SMP architecture
1328 fastcall
void smp_error_interrupt(struct pt_regs
*regs
)
1330 unsigned long v
, v1
;
1333 /* First tickle the hardware, only then report what went on. -- REW */
1334 v
= apic_read(APIC_ESR
);
1335 apic_write(APIC_ESR
, 0);
1336 v1
= apic_read(APIC_ESR
);
1338 atomic_inc(&irq_err_count
);
1340 /* Here is what the APIC error bits mean:
1343 2: Send accept error
1344 3: Receive accept error
1346 5: Send illegal vector
1347 6: Received illegal vector
1348 7: Illegal register address
1350 printk (KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1351 smp_processor_id(), v
, v1
);
1356 * This initializes the IO-APIC and APIC hardware if this is
1359 int __init
APIC_init_uniprocessor (void)
1361 if (enable_local_apic
< 0)
1362 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1364 if (!smp_found_config
&& !cpu_has_apic
)
1368 * Complain if the BIOS pretends there is one.
1370 if (!cpu_has_apic
&& APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1371 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1372 boot_cpu_physical_apicid
);
1373 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1377 verify_local_APIC();
1382 * Hack: In case of kdump, after a crash, kernel might be booting
1383 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1384 * might be zero if read from MP tables. Get it from LAPIC.
1386 #ifdef CONFIG_CRASH_DUMP
1387 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1389 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
1393 #ifdef CONFIG_X86_IO_APIC
1394 if (smp_found_config
)
1395 if (!skip_ioapic_setup
&& nr_ioapics
)
1403 static int __init
parse_lapic(char *arg
)
1408 early_param("lapic", parse_lapic
);
1410 static int __init
parse_nolapic(char *arg
)
1415 early_param("nolapic", parse_nolapic
);