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[SCSI] qla2xxx: Collapse EFT/FCE copy procedures during a firmware dump.
[linux-2.6/mini2440.git] / drivers / scsi / qla2xxx / qla_dbg.c
blob49040ed3cea8b47aa4ace2e8ed3822616db45590
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/delay.h>
10
11 static inline void
12 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
13 {
14 fw_dump->fw_major_version = htonl(ha->fw_major_version);
15 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
16 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
17 fw_dump->fw_attributes = htonl(ha->fw_attributes);
18
19 fw_dump->vendor = htonl(ha->pdev->vendor);
20 fw_dump->device = htonl(ha->pdev->device);
21 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
22 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
23 }
24
25 static inline void *
26 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
27 {
28 struct req_que *req = ha->req_q_map[0];
29 struct rsp_que *rsp = ha->rsp_q_map[0];
30 /* Request queue. */
31 memcpy(ptr, req->ring, req->length *
32 sizeof(request_t));
33
34 /* Response queue. */
35 ptr += req->length * sizeof(request_t);
36 memcpy(ptr, rsp->ring, rsp->length *
37 sizeof(response_t));
38
39 return ptr + (rsp->length * sizeof(response_t));
40 }
41
42 static int
43 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
44 uint32_t ram_dwords, void **nxt)
45 {
46 int rval;
47 uint32_t cnt, stat, timer, dwords, idx;
48 uint16_t mb0;
49 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
50 dma_addr_t dump_dma = ha->gid_list_dma;
51 uint32_t *dump = (uint32_t *)ha->gid_list;
52
53 rval = QLA_SUCCESS;
54 mb0 = 0;
55
56 WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
57 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
58
59 dwords = GID_LIST_SIZE / 4;
60 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
61 cnt += dwords, addr += dwords) {
62 if (cnt + dwords > ram_dwords)
63 dwords = ram_dwords - cnt;
64
65 WRT_REG_WORD(&reg->mailbox1, LSW(addr));
66 WRT_REG_WORD(&reg->mailbox8, MSW(addr));
67
68 WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
69 WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
70 WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
71 WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
72
73 WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
74 WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
75 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
76
77 for (timer = 6000000; timer; timer--) {
78 /* Check for pending interrupts. */
79 stat = RD_REG_DWORD(&reg->host_status);
80 if (stat & HSRX_RISC_INT) {
81 stat &= 0xff;
82
83 if (stat == 0x1 || stat == 0x2 ||
84 stat == 0x10 || stat == 0x11) {
85 set_bit(MBX_INTERRUPT,
86 &ha->mbx_cmd_flags);
87
88 mb0 = RD_REG_WORD(&reg->mailbox0);
89
90 WRT_REG_DWORD(&reg->hccr,
91 HCCRX_CLR_RISC_INT);
92 RD_REG_DWORD(&reg->hccr);
93 break;
94 }
95
96 /* Clear this intr; it wasn't a mailbox intr */
97 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
98 RD_REG_DWORD(&reg->hccr);
99 }
100 udelay(5);
101 }
102
103 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
104 rval = mb0 & MBS_MASK;
105 for (idx = 0; idx < dwords; idx++)
106 ram[cnt + idx] = swab32(dump[idx]);
107 } else {
108 rval = QLA_FUNCTION_FAILED;
109 }
110 }
111
112 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
113 return rval;
114 }
115
116 static int
117 qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
118 uint32_t cram_size, void **nxt)
119 {
120 int rval;
121
122 /* Code RAM. */
123 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
124 if (rval != QLA_SUCCESS)
125 return rval;
126
127 /* External Memory. */
128 return qla24xx_dump_ram(ha, 0x100000, *nxt,
129 ha->fw_memory_size - 0x100000 + 1, nxt);
130 }
131
132 static uint32_t *
133 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
134 uint32_t count, uint32_t *buf)
135 {
136 uint32_t __iomem *dmp_reg;
137
138 WRT_REG_DWORD(&reg->iobase_addr, iobase);
139 dmp_reg = &reg->iobase_window;
140 while (count--)
141 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
142
143 return buf;
144 }
145
146 static inline int
147 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
148 {
149 int rval = QLA_SUCCESS;
150 uint32_t cnt;
151
152 if (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE)
153 return rval;
154
155 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
156 for (cnt = 30000; (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 &&
157 rval == QLA_SUCCESS; cnt--) {
158 if (cnt)
159 udelay(100);
160 else
161 rval = QLA_FUNCTION_TIMEOUT;
162 }
163
164 return rval;
165 }
166
167 static int
168 qla24xx_soft_reset(struct qla_hw_data *ha)
169 {
170 int rval = QLA_SUCCESS;
171 uint32_t cnt;
172 uint16_t mb0, wd;
173 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
174
175 /* Reset RISC. */
176 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
177 for (cnt = 0; cnt < 30000; cnt++) {
178 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
179 break;
180
181 udelay(10);
182 }
183
184 WRT_REG_DWORD(&reg->ctrl_status,
185 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
186 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
187
188 udelay(100);
189 /* Wait for firmware to complete NVRAM accesses. */
190 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
191 for (cnt = 10000 ; cnt && mb0; cnt--) {
192 udelay(5);
193 mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
194 barrier();
195 }
196
197 /* Wait for soft-reset to complete. */
198 for (cnt = 0; cnt < 30000; cnt++) {
199 if ((RD_REG_DWORD(&reg->ctrl_status) &
200 CSRX_ISP_SOFT_RESET) == 0)
201 break;
202
203 udelay(10);
204 }
205 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
206 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
207
208 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
209 rval == QLA_SUCCESS; cnt--) {
210 if (cnt)
211 udelay(100);
212 else
213 rval = QLA_FUNCTION_TIMEOUT;
214 }
215
216 return rval;
217 }
218
219 static int
220 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
221 uint16_t ram_words, void **nxt)
222 {
223 int rval;
224 uint32_t cnt, stat, timer, words, idx;
225 uint16_t mb0;
226 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
227 dma_addr_t dump_dma = ha->gid_list_dma;
228 uint16_t *dump = (uint16_t *)ha->gid_list;
229
230 rval = QLA_SUCCESS;
231 mb0 = 0;
232
233 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
234 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
235
236 words = GID_LIST_SIZE / 2;
237 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
238 cnt += words, addr += words) {
239 if (cnt + words > ram_words)
240 words = ram_words - cnt;
241
242 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
243 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
244
245 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
246 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
247 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
248 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
249
250 WRT_MAILBOX_REG(ha, reg, 4, words);
251 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
252
253 for (timer = 6000000; timer; timer--) {
254 /* Check for pending interrupts. */
255 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
256 if (stat & HSR_RISC_INT) {
257 stat &= 0xff;
258
259 if (stat == 0x1 || stat == 0x2) {
260 set_bit(MBX_INTERRUPT,
261 &ha->mbx_cmd_flags);
262
263 mb0 = RD_MAILBOX_REG(ha, reg, 0);
264
265 /* Release mailbox registers. */
266 WRT_REG_WORD(&reg->semaphore, 0);
267 WRT_REG_WORD(&reg->hccr,
268 HCCR_CLR_RISC_INT);
269 RD_REG_WORD(&reg->hccr);
270 break;
271 } else if (stat == 0x10 || stat == 0x11) {
272 set_bit(MBX_INTERRUPT,
273 &ha->mbx_cmd_flags);
274
275 mb0 = RD_MAILBOX_REG(ha, reg, 0);
276
277 WRT_REG_WORD(&reg->hccr,
278 HCCR_CLR_RISC_INT);
279 RD_REG_WORD(&reg->hccr);
280 break;
281 }
282
283 /* clear this intr; it wasn't a mailbox intr */
284 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
285 RD_REG_WORD(&reg->hccr);
286 }
287 udelay(5);
288 }
289
290 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
291 rval = mb0 & MBS_MASK;
292 for (idx = 0; idx < words; idx++)
293 ram[cnt + idx] = swab16(dump[idx]);
294 } else {
295 rval = QLA_FUNCTION_FAILED;
296 }
297 }
298
299 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
300 return rval;
301 }
302
303 static inline void
304 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
305 uint16_t *buf)
306 {
307 uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
308
309 while (count--)
310 *buf++ = htons(RD_REG_WORD(dmp_reg++));
311 }
312
313 static inline void *
314 qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
315 {
316 if (!ha->eft)
317 return ptr;
318
319 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
320 return ptr + ntohl(ha->fw_dump->eft_size);
321 }
322
323 static inline void *
324 qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
325 {
326 uint32_t cnt;
327 uint32_t *iter_reg;
328 struct qla2xxx_fce_chain *fcec = ptr;
329
330 if (!ha->fce)
331 return ptr;
332
333 *last_chain = &fcec->type;
334 fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
335 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
336 fce_calc_size(ha->fce_bufs));
337 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
338 fcec->addr_l = htonl(LSD(ha->fce_dma));
339 fcec->addr_h = htonl(MSD(ha->fce_dma));
340
341 iter_reg = fcec->eregs;
342 for (cnt = 0; cnt < 8; cnt++)
343 *iter_reg++ = htonl(ha->fce_mb[cnt]);
344
345 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
346
347 return iter_reg;
348 }
349
350 /**
351 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
352 * @ha: HA context
353 * @hardware_locked: Called with the hardware_lock
354 */
355 void
356 qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
357 {
358 int rval;
359 uint32_t cnt;
360 struct qla_hw_data *ha = vha->hw;
361 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
362 uint16_t __iomem *dmp_reg;
363 unsigned long flags;
364 struct qla2300_fw_dump *fw;
365 void *nxt;
366 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
367
368 flags = 0;
369
370 if (!hardware_locked)
371 spin_lock_irqsave(&ha->hardware_lock, flags);
372
373 if (!ha->fw_dump) {
374 qla_printk(KERN_WARNING, ha,
375 "No buffer available for dump!!!\n");
376 goto qla2300_fw_dump_failed;
377 }
378
379 if (ha->fw_dumped) {
380 qla_printk(KERN_WARNING, ha,
381 "Firmware has been previously dumped (%p) -- ignoring "
382 "request...\n", ha->fw_dump);
383 goto qla2300_fw_dump_failed;
384 }
385 fw = &ha->fw_dump->isp.isp23;
386 qla2xxx_prep_dump(ha, ha->fw_dump);
387
388 rval = QLA_SUCCESS;
389 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
390
391 /* Pause RISC. */
392 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
393 if (IS_QLA2300(ha)) {
394 for (cnt = 30000;
395 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
396 rval == QLA_SUCCESS; cnt--) {
397 if (cnt)
398 udelay(100);
399 else
400 rval = QLA_FUNCTION_TIMEOUT;
401 }
402 } else {
403 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
404 udelay(10);
405 }
406
407 if (rval == QLA_SUCCESS) {
408 dmp_reg = &reg->flash_address;
409 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
410 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
411
412 dmp_reg = &reg->u.isp2300.req_q_in;
413 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
414 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
415
416 dmp_reg = &reg->u.isp2300.mailbox0;
417 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
418 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
419
420 WRT_REG_WORD(&reg->ctrl_status, 0x40);
421 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
422
423 WRT_REG_WORD(&reg->ctrl_status, 0x50);
424 qla2xxx_read_window(reg, 48, fw->dma_reg);
425
426 WRT_REG_WORD(&reg->ctrl_status, 0x00);
427 dmp_reg = &reg->risc_hw;
428 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
429 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
430
431 WRT_REG_WORD(&reg->pcr, 0x2000);
432 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
433
434 WRT_REG_WORD(&reg->pcr, 0x2200);
435 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
436
437 WRT_REG_WORD(&reg->pcr, 0x2400);
438 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
439
440 WRT_REG_WORD(&reg->pcr, 0x2600);
441 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
442
443 WRT_REG_WORD(&reg->pcr, 0x2800);
444 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
445
446 WRT_REG_WORD(&reg->pcr, 0x2A00);
447 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
448
449 WRT_REG_WORD(&reg->pcr, 0x2C00);
450 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
451
452 WRT_REG_WORD(&reg->pcr, 0x2E00);
453 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
454
455 WRT_REG_WORD(&reg->ctrl_status, 0x10);
456 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
457
458 WRT_REG_WORD(&reg->ctrl_status, 0x20);
459 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
460
461 WRT_REG_WORD(&reg->ctrl_status, 0x30);
462 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
463
464 /* Reset RISC. */
465 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
466 for (cnt = 0; cnt < 30000; cnt++) {
467 if ((RD_REG_WORD(&reg->ctrl_status) &
468 CSR_ISP_SOFT_RESET) == 0)
469 break;
470
471 udelay(10);
472 }
473 }
474
475 if (!IS_QLA2300(ha)) {
476 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
477 rval == QLA_SUCCESS; cnt--) {
478 if (cnt)
479 udelay(100);
480 else
481 rval = QLA_FUNCTION_TIMEOUT;
482 }
483 }
484
485 /* Get RISC SRAM. */
486 if (rval == QLA_SUCCESS)
487 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
488 sizeof(fw->risc_ram) / 2, &nxt);
489
490 /* Get stack SRAM. */
491 if (rval == QLA_SUCCESS)
492 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
493 sizeof(fw->stack_ram) / 2, &nxt);
494
495 /* Get data SRAM. */
496 if (rval == QLA_SUCCESS)
497 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
498 ha->fw_memory_size - 0x11000 + 1, &nxt);
499
500 if (rval == QLA_SUCCESS)
501 qla2xxx_copy_queues(ha, nxt);
502
503 if (rval != QLA_SUCCESS) {
504 qla_printk(KERN_WARNING, ha,
505 "Failed to dump firmware (%x)!!!\n", rval);
506 ha->fw_dumped = 0;
507
508 } else {
509 qla_printk(KERN_INFO, ha,
510 "Firmware dump saved to temp buffer (%ld/%p).\n",
511 base_vha->host_no, ha->fw_dump);
512 ha->fw_dumped = 1;
513 }
514
515 qla2300_fw_dump_failed:
516 if (!hardware_locked)
517 spin_unlock_irqrestore(&ha->hardware_lock, flags);
518 }
519
520 /**
521 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
522 * @ha: HA context
523 * @hardware_locked: Called with the hardware_lock
524 */
525 void
526 qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
527 {
528 int rval;
529 uint32_t cnt, timer;
530 uint16_t risc_address;
531 uint16_t mb0, mb2;
532 struct qla_hw_data *ha = vha->hw;
533 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
534 uint16_t __iomem *dmp_reg;
535 unsigned long flags;
536 struct qla2100_fw_dump *fw;
537 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
538
539 risc_address = 0;
540 mb0 = mb2 = 0;
541 flags = 0;
542
543 if (!hardware_locked)
544 spin_lock_irqsave(&ha->hardware_lock, flags);
545
546 if (!ha->fw_dump) {
547 qla_printk(KERN_WARNING, ha,
548 "No buffer available for dump!!!\n");
549 goto qla2100_fw_dump_failed;
550 }
551
552 if (ha->fw_dumped) {
553 qla_printk(KERN_WARNING, ha,
554 "Firmware has been previously dumped (%p) -- ignoring "
555 "request...\n", ha->fw_dump);
556 goto qla2100_fw_dump_failed;
557 }
558 fw = &ha->fw_dump->isp.isp21;
559 qla2xxx_prep_dump(ha, ha->fw_dump);
560
561 rval = QLA_SUCCESS;
562 fw->hccr = htons(RD_REG_WORD(&reg->hccr));
563
564 /* Pause RISC. */
565 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
566 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
567 rval == QLA_SUCCESS; cnt--) {
568 if (cnt)
569 udelay(100);
570 else
571 rval = QLA_FUNCTION_TIMEOUT;
572 }
573 if (rval == QLA_SUCCESS) {
574 dmp_reg = &reg->flash_address;
575 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
576 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
577
578 dmp_reg = &reg->u.isp2100.mailbox0;
579 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
580 if (cnt == 8)
581 dmp_reg = &reg->u_end.isp2200.mailbox8;
582
583 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
584 }
585
586 dmp_reg = &reg->u.isp2100.unused_2[0];
587 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
588 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
589
590 WRT_REG_WORD(&reg->ctrl_status, 0x00);
591 dmp_reg = &reg->risc_hw;
592 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
593 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
594
595 WRT_REG_WORD(&reg->pcr, 0x2000);
596 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
597
598 WRT_REG_WORD(&reg->pcr, 0x2100);
599 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
600
601 WRT_REG_WORD(&reg->pcr, 0x2200);
602 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
603
604 WRT_REG_WORD(&reg->pcr, 0x2300);
605 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
606
607 WRT_REG_WORD(&reg->pcr, 0x2400);
608 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
609
610 WRT_REG_WORD(&reg->pcr, 0x2500);
611 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
612
613 WRT_REG_WORD(&reg->pcr, 0x2600);
614 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
615
616 WRT_REG_WORD(&reg->pcr, 0x2700);
617 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
618
619 WRT_REG_WORD(&reg->ctrl_status, 0x10);
620 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
621
622 WRT_REG_WORD(&reg->ctrl_status, 0x20);
623 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
624
625 WRT_REG_WORD(&reg->ctrl_status, 0x30);
626 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
627
628 /* Reset the ISP. */
629 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
630 }
631
632 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
633 rval == QLA_SUCCESS; cnt--) {
634 if (cnt)
635 udelay(100);
636 else
637 rval = QLA_FUNCTION_TIMEOUT;
638 }
639
640 /* Pause RISC. */
641 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
642 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
643
644 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
645 for (cnt = 30000;
646 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
647 rval == QLA_SUCCESS; cnt--) {
648 if (cnt)
649 udelay(100);
650 else
651 rval = QLA_FUNCTION_TIMEOUT;
652 }
653 if (rval == QLA_SUCCESS) {
654 /* Set memory configuration and timing. */
655 if (IS_QLA2100(ha))
656 WRT_REG_WORD(&reg->mctr, 0xf1);
657 else
658 WRT_REG_WORD(&reg->mctr, 0xf2);
659 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
660
661 /* Release RISC. */
662 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
663 }
664 }
665
666 if (rval == QLA_SUCCESS) {
667 /* Get RISC SRAM. */
668 risc_address = 0x1000;
669 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
670 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
671 }
672 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
673 cnt++, risc_address++) {
674 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
675 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
676
677 for (timer = 6000000; timer != 0; timer--) {
678 /* Check for pending interrupts. */
679 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
680 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
681 set_bit(MBX_INTERRUPT,
682 &ha->mbx_cmd_flags);
683
684 mb0 = RD_MAILBOX_REG(ha, reg, 0);
685 mb2 = RD_MAILBOX_REG(ha, reg, 2);
686
687 WRT_REG_WORD(&reg->semaphore, 0);
688 WRT_REG_WORD(&reg->hccr,
689 HCCR_CLR_RISC_INT);
690 RD_REG_WORD(&reg->hccr);
691 break;
692 }
693 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
694 RD_REG_WORD(&reg->hccr);
695 }
696 udelay(5);
697 }
698
699 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
700 rval = mb0 & MBS_MASK;
701 fw->risc_ram[cnt] = htons(mb2);
702 } else {
703 rval = QLA_FUNCTION_FAILED;
704 }
705 }
706
707 if (rval == QLA_SUCCESS)
708 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
709
710 if (rval != QLA_SUCCESS) {
711 qla_printk(KERN_WARNING, ha,
712 "Failed to dump firmware (%x)!!!\n", rval);
713 ha->fw_dumped = 0;
714
715 } else {
716 qla_printk(KERN_INFO, ha,
717 "Firmware dump saved to temp buffer (%ld/%p).\n",
718 base_vha->host_no, ha->fw_dump);
719 ha->fw_dumped = 1;
720 }
721
722 qla2100_fw_dump_failed:
723 if (!hardware_locked)
724 spin_unlock_irqrestore(&ha->hardware_lock, flags);
725 }
726
727 void
728 qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
729 {
730 int rval;
731 uint32_t cnt;
732 uint32_t risc_address;
733 struct qla_hw_data *ha = vha->hw;
734 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
735 uint32_t __iomem *dmp_reg;
736 uint32_t *iter_reg;
737 uint16_t __iomem *mbx_reg;
738 unsigned long flags;
739 struct qla24xx_fw_dump *fw;
740 uint32_t ext_mem_cnt;
741 void *nxt;
742 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
743
744 risc_address = ext_mem_cnt = 0;
745 flags = 0;
746
747 if (!hardware_locked)
748 spin_lock_irqsave(&ha->hardware_lock, flags);
749
750 if (!ha->fw_dump) {
751 qla_printk(KERN_WARNING, ha,
752 "No buffer available for dump!!!\n");
753 goto qla24xx_fw_dump_failed;
754 }
755
756 if (ha->fw_dumped) {
757 qla_printk(KERN_WARNING, ha,
758 "Firmware has been previously dumped (%p) -- ignoring "
759 "request...\n", ha->fw_dump);
760 goto qla24xx_fw_dump_failed;
761 }
762 fw = &ha->fw_dump->isp.isp24;
763 qla2xxx_prep_dump(ha, ha->fw_dump);
764
765 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
766
767 /* Pause RISC. */
768 rval = qla24xx_pause_risc(reg);
769 if (rval != QLA_SUCCESS)
770 goto qla24xx_fw_dump_failed_0;
771
772 /* Host interface registers. */
773 dmp_reg = &reg->flash_addr;
774 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
775 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
776
777 /* Disable interrupts. */
778 WRT_REG_DWORD(&reg->ictrl, 0);
779 RD_REG_DWORD(&reg->ictrl);
780
781 /* Shadow registers. */
782 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
783 RD_REG_DWORD(&reg->iobase_addr);
784 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
785 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
786
787 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
788 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
789
790 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
791 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
792
793 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
794 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
795
796 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
797 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
798
799 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
800 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
801
802 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
803 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
804
805 /* Mailbox registers. */
806 mbx_reg = &reg->mailbox0;
807 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
808 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
809
810 /* Transfer sequence registers. */
811 iter_reg = fw->xseq_gp_reg;
812 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
813 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
814 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
815 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
816 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
817 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
818 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
819 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
820
821 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
822 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
823
824 /* Receive sequence registers. */
825 iter_reg = fw->rseq_gp_reg;
826 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
827 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
828 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
829 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
830 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
831 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
832 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
833 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
834
835 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
836 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
837 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
838
839 /* Command DMA registers. */
840 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
841
842 /* Queues. */
843 iter_reg = fw->req0_dma_reg;
844 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
845 dmp_reg = &reg->iobase_q;
846 for (cnt = 0; cnt < 7; cnt++)
847 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
848
849 iter_reg = fw->resp0_dma_reg;
850 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
851 dmp_reg = &reg->iobase_q;
852 for (cnt = 0; cnt < 7; cnt++)
853 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
854
855 iter_reg = fw->req1_dma_reg;
856 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
857 dmp_reg = &reg->iobase_q;
858 for (cnt = 0; cnt < 7; cnt++)
859 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
860
861 /* Transmit DMA registers. */
862 iter_reg = fw->xmt0_dma_reg;
863 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
864 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
865
866 iter_reg = fw->xmt1_dma_reg;
867 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
868 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
869
870 iter_reg = fw->xmt2_dma_reg;
871 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
872 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
873
874 iter_reg = fw->xmt3_dma_reg;
875 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
876 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
877
878 iter_reg = fw->xmt4_dma_reg;
879 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
880 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
881
882 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
883
884 /* Receive DMA registers. */
885 iter_reg = fw->rcvt0_data_dma_reg;
886 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
887 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
888
889 iter_reg = fw->rcvt1_data_dma_reg;
890 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
891 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
892
893 /* RISC registers. */
894 iter_reg = fw->risc_gp_reg;
895 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
896 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
897 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
898 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
899 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
900 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
901 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
902 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
903
904 /* Local memory controller registers. */
905 iter_reg = fw->lmc_reg;
906 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
907 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
908 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
909 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
910 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
911 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
912 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
913
914 /* Fibre Protocol Module registers. */
915 iter_reg = fw->fpm_hdw_reg;
916 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
917 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
918 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
919 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
920 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
921 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
922 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
923 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
924 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
925 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
926 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
927 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
928
929 /* Frame Buffer registers. */
930 iter_reg = fw->fb_hdw_reg;
931 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
932 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
933 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
934 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
935 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
936 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
937 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
938 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
939 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
940 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
941 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
942
943 rval = qla24xx_soft_reset(ha);
944 if (rval != QLA_SUCCESS)
945 goto qla24xx_fw_dump_failed_0;
946
947 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
948 &nxt);
949 if (rval != QLA_SUCCESS)
950 goto qla24xx_fw_dump_failed_0;
951
952 nxt = qla2xxx_copy_queues(ha, nxt);
953
954 qla24xx_copy_eft(ha, nxt);
955
956 qla24xx_fw_dump_failed_0:
957 if (rval != QLA_SUCCESS) {
958 qla_printk(KERN_WARNING, ha,
959 "Failed to dump firmware (%x)!!!\n", rval);
960 ha->fw_dumped = 0;
961
962 } else {
963 qla_printk(KERN_INFO, ha,
964 "Firmware dump saved to temp buffer (%ld/%p).\n",
965 base_vha->host_no, ha->fw_dump);
966 ha->fw_dumped = 1;
967 }
968
969 qla24xx_fw_dump_failed:
970 if (!hardware_locked)
971 spin_unlock_irqrestore(&ha->hardware_lock, flags);
972 }
973
974 void
975 qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
976 {
977 int rval;
978 uint32_t cnt;
979 uint32_t risc_address;
980 struct qla_hw_data *ha = vha->hw;
981 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
982 struct device_reg_25xxmq __iomem *reg25;
983 uint32_t __iomem *dmp_reg;
984 uint32_t *iter_reg;
985 uint16_t __iomem *mbx_reg;
986 unsigned long flags;
987 struct qla25xx_fw_dump *fw;
988 uint32_t ext_mem_cnt;
989 void *nxt;
990 uint32_t *last_chain = NULL;
991 struct qla2xxx_mq_chain *mq = NULL;
992 uint32_t qreg_size;
993 uint8_t req_cnt, rsp_cnt, que_cnt;
994 uint32_t que_idx;
995 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
996
997 risc_address = ext_mem_cnt = 0;
998 flags = 0;
999
1000 if (!hardware_locked)
1001 spin_lock_irqsave(&ha->hardware_lock, flags);
1002
1003 if (!ha->fw_dump) {
1004 qla_printk(KERN_WARNING, ha,
1005 "No buffer available for dump!!!\n");
1006 goto qla25xx_fw_dump_failed;
1007 }
1008
1009 if (ha->fw_dumped) {
1010 qla_printk(KERN_WARNING, ha,
1011 "Firmware has been previously dumped (%p) -- ignoring "
1012 "request...\n", ha->fw_dump);
1013 goto qla25xx_fw_dump_failed;
1014 }
1015 fw = &ha->fw_dump->isp.isp25;
1016 qla2xxx_prep_dump(ha, ha->fw_dump);
1017 ha->fw_dump->version = __constant_htonl(2);
1018
1019 fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
1020
1021 /* Pause RISC. */
1022 rval = qla24xx_pause_risc(reg);
1023 if (rval != QLA_SUCCESS)
1024 goto qla25xx_fw_dump_failed_0;
1025
1026 /* Host/Risc registers. */
1027 iter_reg = fw->host_risc_reg;
1028 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1029 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1030
1031 /* PCIe registers. */
1032 WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
1033 RD_REG_DWORD(&reg->iobase_addr);
1034 WRT_REG_DWORD(&reg->iobase_window, 0x01);
1035 dmp_reg = &reg->iobase_c4;
1036 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1037 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1038 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1039 fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
1040
1041 /* Multi queue registers */
1042 if (ha->mqenable) {
1043 qreg_size = sizeof(struct qla2xxx_mq_chain);
1044 mq = kzalloc(qreg_size, GFP_KERNEL);
1045 if (!mq)
1046 goto qla25xx_fw_dump_failed_0;
1047 req_cnt = find_first_zero_bit(ha->req_qid_map, ha->max_queues);
1048 rsp_cnt = find_first_zero_bit(ha->rsp_qid_map, ha->max_queues);
1049 que_cnt = req_cnt > rsp_cnt ? req_cnt : rsp_cnt;
1050 mq->count = htonl(que_cnt);
1051 mq->chain_size = htonl(qreg_size);
1052 last_chain = &mq->type;
1053 mq->type = __constant_htonl(DUMP_CHAIN_MQ);
1054 for (cnt = 0; cnt < que_cnt; cnt++) {
1055 reg25 = (struct device_reg_25xxmq *) ((void *)
1056 ha->mqiobase + cnt * QLA_QUE_PAGE);
1057 que_idx = cnt * 4;
1058 mq->qregs[que_idx] = htonl(reg25->req_q_in);
1059 mq->qregs[que_idx+1] = htonl(reg25->req_q_out);
1060 mq->qregs[que_idx+2] = htonl(reg25->rsp_q_in);
1061 mq->qregs[que_idx+3] = htonl(reg25->rsp_q_out);
1062 }
1063 }
1064 WRT_REG_DWORD(&reg->iobase_window, 0x00);
1065 RD_REG_DWORD(&reg->iobase_window);
1066
1067 /* Host interface registers. */
1068 dmp_reg = &reg->flash_addr;
1069 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1070 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1071
1072 /* Disable interrupts. */
1073 WRT_REG_DWORD(&reg->ictrl, 0);
1074 RD_REG_DWORD(&reg->ictrl);
1075
1076 /* Shadow registers. */
1077 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1078 RD_REG_DWORD(&reg->iobase_addr);
1079 WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
1080 fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1081
1082 WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
1083 fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1084
1085 WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
1086 fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1087
1088 WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
1089 fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1090
1091 WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
1092 fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1093
1094 WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
1095 fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1096
1097 WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
1098 fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1099
1100 WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
1101 fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1102
1103 WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
1104 fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1105
1106 WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
1107 fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1108
1109 WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
1110 fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
1111
1112 /* RISC I/O register. */
1113 WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
1114 fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
1115
1116 /* Mailbox registers. */
1117 mbx_reg = &reg->mailbox0;
1118 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1119 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1120
1121 /* Transfer sequence registers. */
1122 iter_reg = fw->xseq_gp_reg;
1123 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1124 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1125 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1126 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1127 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1128 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1129 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1130 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1131
1132 iter_reg = fw->xseq_0_reg;
1133 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1134 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1135 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1136
1137 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1138
1139 /* Receive sequence registers. */
1140 iter_reg = fw->rseq_gp_reg;
1141 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1142 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1143 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1144 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1145 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1146 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1147 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1148 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1149
1150 iter_reg = fw->rseq_0_reg;
1151 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1152 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1153
1154 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1155 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1156
1157 /* Auxiliary sequence registers. */
1158 iter_reg = fw->aseq_gp_reg;
1159 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1160 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1161 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1162 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1163 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1164 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1165 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1166 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1167
1168 iter_reg = fw->aseq_0_reg;
1169 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1170 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1171
1172 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1173 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1174
1175 /* Command DMA registers. */
1176 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1177
1178 /* Queues. */
1179 iter_reg = fw->req0_dma_reg;
1180 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1181 dmp_reg = &reg->iobase_q;
1182 for (cnt = 0; cnt < 7; cnt++)
1183 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1184
1185 iter_reg = fw->resp0_dma_reg;
1186 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1187 dmp_reg = &reg->iobase_q;
1188 for (cnt = 0; cnt < 7; cnt++)
1189 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1190
1191 iter_reg = fw->req1_dma_reg;
1192 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1193 dmp_reg = &reg->iobase_q;
1194 for (cnt = 0; cnt < 7; cnt++)
1195 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1196
1197 /* Transmit DMA registers. */
1198 iter_reg = fw->xmt0_dma_reg;
1199 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1200 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1201
1202 iter_reg = fw->xmt1_dma_reg;
1203 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1204 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1205
1206 iter_reg = fw->xmt2_dma_reg;
1207 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1208 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1209
1210 iter_reg = fw->xmt3_dma_reg;
1211 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1212 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1213
1214 iter_reg = fw->xmt4_dma_reg;
1215 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1216 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1217
1218 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1219
1220 /* Receive DMA registers. */
1221 iter_reg = fw->rcvt0_data_dma_reg;
1222 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1223 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1224
1225 iter_reg = fw->rcvt1_data_dma_reg;
1226 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1227 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1228
1229 /* RISC registers. */
1230 iter_reg = fw->risc_gp_reg;
1231 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1232 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1233 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1234 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1235 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1236 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1237 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1238 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1239
1240 /* Local memory controller registers. */
1241 iter_reg = fw->lmc_reg;
1242 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1243 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1244 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1245 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1246 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1247 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1248 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1249 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1250
1251 /* Fibre Protocol Module registers. */
1252 iter_reg = fw->fpm_hdw_reg;
1253 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1254 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1255 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1256 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1257 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1258 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1259 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1260 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1261 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1262 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1263 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1264 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1265
1266 /* Frame Buffer registers. */
1267 iter_reg = fw->fb_hdw_reg;
1268 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1269 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1270 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1271 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1272 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1273 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1274 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1275 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1276 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1277 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1278 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1279 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1280
1281 rval = qla24xx_soft_reset(ha);
1282 if (rval != QLA_SUCCESS)
1283 goto qla25xx_fw_dump_failed_0;
1284
1285 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1286 &nxt);
1287 if (rval != QLA_SUCCESS)
1288 goto qla25xx_fw_dump_failed_0;
1289
1290 nxt = qla2xxx_copy_queues(ha, nxt);
1291
1292 nxt = qla24xx_copy_eft(ha, nxt);
1293
1294 /* Chain entries. */
1295 if (ha->mqenable) {
1296 memcpy(nxt, mq, qreg_size);
1297 kfree(mq);
1298 nxt += qreg_size;
1299 }
1300
1301 qla25xx_copy_fce(ha, nxt, &last_chain);
1302 if (last_chain) {
1303 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1304 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1305 }
1306
1307 qla25xx_fw_dump_failed_0:
1308 if (rval != QLA_SUCCESS) {
1309 qla_printk(KERN_WARNING, ha,
1310 "Failed to dump firmware (%x)!!!\n", rval);
1311 ha->fw_dumped = 0;
1312
1313 } else {
1314 qla_printk(KERN_INFO, ha,
1315 "Firmware dump saved to temp buffer (%ld/%p).\n",
1316 base_vha->host_no, ha->fw_dump);
1317 ha->fw_dumped = 1;
1318 }
1319
1320 qla25xx_fw_dump_failed:
1321 if (!hardware_locked)
1322 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1323 }
1324 /****************************************************************************/
1325 /* Driver Debug Functions. */
1326 /****************************************************************************/
1327
1328 void
1329 qla2x00_dump_regs(scsi_qla_host_t *vha)
1330 {
1331 int i;
1332 struct qla_hw_data *ha = vha->hw;
1333 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1334 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
1335 uint16_t __iomem *mbx_reg;
1336
1337 mbx_reg = IS_FWI2_CAPABLE(ha) ? &reg24->mailbox0:
1338 MAILBOX_REG(ha, reg, 0);
1339
1340 printk("Mailbox registers:\n");
1341 for (i = 0; i < 6; i++)
1342 printk("scsi(%ld): mbox %d 0x%04x \n", vha->host_no, i,
1343 RD_REG_WORD(mbx_reg++));
1344 }
1345
1346
1347 void
1348 qla2x00_dump_buffer(uint8_t * b, uint32_t size)
1349 {
1350 uint32_t cnt;
1351 uint8_t c;
1352
1353 printk(" 0 1 2 3 4 5 6 7 8 9 "
1354 "Ah Bh Ch Dh Eh Fh\n");
1355 printk("----------------------------------------"
1356 "----------------------\n");
1357
1358 for (cnt = 0; cnt < size;) {
1359 c = *b++;
1360 printk("%02x",(uint32_t) c);
1361 cnt++;
1362 if (!(cnt % 16))
1363 printk("\n");
1364 else
1365 printk(" ");
1366 }
1367 if (cnt % 16)
1368 printk("\n");
1369 }
1370
1371
Support for the Chinese Samsung S3C2440 based development boards