?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ixgbe: remove device ID for unsupported device
[linux-2.6/mini2440.git] / sound / arm / aaci.c
blobb0a474494966d42b97b5547c4b250b65e4face8e
1 /*
2 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Documentation: ARM DDI 0173B
11 */
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/ioport.h>
16 #include <linux/device.h>
17 #include <linux/spinlock.h>
18 #include <linux/interrupt.h>
19 #include <linux/err.h>
20 #include <linux/amba/bus.h>
21
22 #include <asm/io.h>
23 #include <asm/irq.h>
24 #include <asm/sizes.h>
25
26 #include <sound/core.h>
27 #include <sound/initval.h>
28 #include <sound/ac97_codec.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31
32 #include "aaci.h"
33 #include "devdma.h"
34
35 #define DRIVER_NAME "aaci-pl041"
36
37 /*
38 * PM support is not complete. Turn it off.
39 */
40 #undef CONFIG_PM
41
42 static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97)
43 {
44 u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num);
45
46 /*
47 * Ensure that the slot 1/2 RX registers are empty.
48 */
49 v = readl(aaci->base + AACI_SLFR);
50 if (v & SLFR_2RXV)
51 readl(aaci->base + AACI_SL2RX);
52 if (v & SLFR_1RXV)
53 readl(aaci->base + AACI_SL1RX);
54
55 writel(maincr, aaci->base + AACI_MAINCR);
56 }
57
58 /*
59 * P29:
60 * The recommended use of programming the external codec through slot 1
61 * and slot 2 data is to use the channels during setup routines and the
62 * slot register at any other time. The data written into slot 1, slot 2
63 * and slot 12 registers is transmitted only when their corresponding
64 * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR
65 * register.
66 */
67 static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
68 unsigned short val)
69 {
70 struct aaci *aaci = ac97->private_data;
71 u32 v;
72 int timeout = 5000;
73
74 if (ac97->num >= 4)
75 return;
76
77 mutex_lock(&aaci->ac97_sem);
78
79 aaci_ac97_select_codec(aaci, ac97);
80
81 /*
82 * P54: You must ensure that AACI_SL2TX is always written
83 * to, if required, before data is written to AACI_SL1TX.
84 */
85 writel(val << 4, aaci->base + AACI_SL2TX);
86 writel(reg << 12, aaci->base + AACI_SL1TX);
87
88 /*
89 * Wait for the transmission of both slots to complete.
90 */
91 do {
92 v = readl(aaci->base + AACI_SLFR);
93 } while ((v & (SLFR_1TXB|SLFR_2TXB)) && timeout--);
94
95 if (!timeout)
96 dev_err(&aaci->dev->dev,
97 "timeout waiting for write to complete\n");
98
99 mutex_unlock(&aaci->ac97_sem);
100 }
101
102 /*
103 * Read an AC'97 register.
104 */
105 static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
106 {
107 struct aaci *aaci = ac97->private_data;
108 u32 v;
109 int timeout = 5000;
110 int retries = 10;
111
112 if (ac97->num >= 4)
113 return ~0;
114
115 mutex_lock(&aaci->ac97_sem);
116
117 aaci_ac97_select_codec(aaci, ac97);
118
119 /*
120 * Write the register address to slot 1.
121 */
122 writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
123
124 /*
125 * Wait for the transmission to complete.
126 */
127 do {
128 v = readl(aaci->base + AACI_SLFR);
129 } while ((v & SLFR_1TXB) && timeout--);
130
131 if (!timeout) {
132 dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n");
133 v = ~0;
134 goto out;
135 }
136
137 /*
138 * Give the AC'97 codec more than enough time
139 * to respond. (42us = ~2 frames at 48kHz.)
140 */
141 udelay(42);
142
143 /*
144 * Wait for slot 2 to indicate data.
145 */
146 timeout = 5000;
147 do {
148 cond_resched();
149 v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
150 } while ((v != (SLFR_1RXV|SLFR_2RXV)) && timeout--);
151
152 if (!timeout) {
153 dev_err(&aaci->dev->dev, "timeout on RX valid\n");
154 v = ~0;
155 goto out;
156 }
157
158 do {
159 v = readl(aaci->base + AACI_SL1RX) >> 12;
160 if (v == reg) {
161 v = readl(aaci->base + AACI_SL2RX) >> 4;
162 break;
163 } else if (--retries) {
164 dev_warn(&aaci->dev->dev,
165 "ac97 read back fail. retry\n");
166 continue;
167 } else {
168 dev_warn(&aaci->dev->dev,
169 "wrong ac97 register read back (%x != %x)\n",
170 v, reg);
171 v = ~0;
172 }
173 } while (retries);
174 out:
175 mutex_unlock(&aaci->ac97_sem);
176 return v;
177 }
178
179 static inline void aaci_chan_wait_ready(struct aaci_runtime *aacirun)
180 {
181 u32 val;
182 int timeout = 5000;
183
184 do {
185 val = readl(aacirun->base + AACI_SR);
186 } while (val & (SR_TXB|SR_RXB) && timeout--);
187 }
188
189
190
191 /*
192 * Interrupt support.
193 */
194 static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask)
195 {
196 if (mask & ISR_ORINTR) {
197 dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel);
198 writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR);
199 }
200
201 if (mask & ISR_RXTOINTR) {
202 dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel);
203 writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR);
204 }
205
206 if (mask & ISR_RXINTR) {
207 struct aaci_runtime *aacirun = &aaci->capture;
208 void *ptr;
209
210 if (!aacirun->substream || !aacirun->start) {
211 dev_warn(&aaci->dev->dev, "RX interrupt???\n");
212 writel(0, aacirun->base + AACI_IE);
213 return;
214 }
215 ptr = aacirun->ptr;
216
217 do {
218 unsigned int len = aacirun->fifosz;
219 u32 val;
220
221 if (aacirun->bytes <= 0) {
222 aacirun->bytes += aacirun->period;
223 aacirun->ptr = ptr;
224 spin_unlock(&aaci->lock);
225 snd_pcm_period_elapsed(aacirun->substream);
226 spin_lock(&aaci->lock);
227 }
228 if (!(aacirun->cr & CR_EN))
229 break;
230
231 val = readl(aacirun->base + AACI_SR);
232 if (!(val & SR_RXHF))
233 break;
234 if (!(val & SR_RXFF))
235 len >>= 1;
236
237 aacirun->bytes -= len;
238
239 /* reading 16 bytes at a time */
240 for( ; len > 0; len -= 16) {
241 asm(
242 "ldmia %1, {r0, r1, r2, r3}\n\t"
243 "stmia %0!, {r0, r1, r2, r3}"
244 : "+r" (ptr)
245 : "r" (aacirun->fifo)
246 : "r0", "r1", "r2", "r3", "cc");
247
248 if (ptr >= aacirun->end)
249 ptr = aacirun->start;
250 }
251 } while(1);
252 aacirun->ptr = ptr;
253 }
254
255 if (mask & ISR_URINTR) {
256 dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel);
257 writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR);
258 }
259
260 if (mask & ISR_TXINTR) {
261 struct aaci_runtime *aacirun = &aaci->playback;
262 void *ptr;
263
264 if (!aacirun->substream || !aacirun->start) {
265 dev_warn(&aaci->dev->dev, "TX interrupt???\n");
266 writel(0, aacirun->base + AACI_IE);
267 return;
268 }
269
270 ptr = aacirun->ptr;
271 do {
272 unsigned int len = aacirun->fifosz;
273 u32 val;
274
275 if (aacirun->bytes <= 0) {
276 aacirun->bytes += aacirun->period;
277 aacirun->ptr = ptr;
278 spin_unlock(&aaci->lock);
279 snd_pcm_period_elapsed(aacirun->substream);
280 spin_lock(&aaci->lock);
281 }
282 if (!(aacirun->cr & CR_EN))
283 break;
284
285 val = readl(aacirun->base + AACI_SR);
286 if (!(val & SR_TXHE))
287 break;
288 if (!(val & SR_TXFE))
289 len >>= 1;
290
291 aacirun->bytes -= len;
292
293 /* writing 16 bytes at a time */
294 for ( ; len > 0; len -= 16) {
295 asm(
296 "ldmia %0!, {r0, r1, r2, r3}\n\t"
297 "stmia %1, {r0, r1, r2, r3}"
298 : "+r" (ptr)
299 : "r" (aacirun->fifo)
300 : "r0", "r1", "r2", "r3", "cc");
301
302 if (ptr >= aacirun->end)
303 ptr = aacirun->start;
304 }
305 } while (1);
306
307 aacirun->ptr = ptr;
308 }
309 }
310
311 static irqreturn_t aaci_irq(int irq, void *devid)
312 {
313 struct aaci *aaci = devid;
314 u32 mask;
315 int i;
316
317 spin_lock(&aaci->lock);
318 mask = readl(aaci->base + AACI_ALLINTS);
319 if (mask) {
320 u32 m = mask;
321 for (i = 0; i < 4; i++, m >>= 7) {
322 if (m & 0x7f) {
323 aaci_fifo_irq(aaci, i, m);
324 }
325 }
326 }
327 spin_unlock(&aaci->lock);
328
329 return mask ? IRQ_HANDLED : IRQ_NONE;
330 }
331
332
333
334 /*
335 * ALSA support.
336 */
337
338 struct aaci_stream {
339 unsigned char codec_idx;
340 unsigned char rate_idx;
341 };
342
343 static struct aaci_stream aaci_streams[] = {
344 [ACSTREAM_FRONT] = {
345 .codec_idx = 0,
346 .rate_idx = AC97_RATES_FRONT_DAC,
347 },
348 [ACSTREAM_SURROUND] = {
349 .codec_idx = 0,
350 .rate_idx = AC97_RATES_SURR_DAC,
351 },
352 [ACSTREAM_LFE] = {
353 .codec_idx = 0,
354 .rate_idx = AC97_RATES_LFE_DAC,
355 },
356 };
357
358 static inline unsigned int aaci_rate_mask(struct aaci *aaci, int streamid)
359 {
360 struct aaci_stream *s = aaci_streams + streamid;
361 return aaci->ac97_bus->codec[s->codec_idx]->rates[s->rate_idx];
362 }
363
364 static unsigned int rate_list[] = {
365 5512, 8000, 11025, 16000, 22050, 32000, 44100,
366 48000, 64000, 88200, 96000, 176400, 192000
367 };
368
369 /*
370 * Double-rate rule: we can support double rate iff channels == 2
371 * (unimplemented)
372 */
373 static int
374 aaci_rule_rate_by_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
375 {
376 struct aaci *aaci = rule->private;
377 unsigned int rate_mask = SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_5512;
378 struct snd_interval *c = hw_param_interval(p, SNDRV_PCM_HW_PARAM_CHANNELS);
379
380 switch (c->max) {
381 case 6:
382 rate_mask &= aaci_rate_mask(aaci, ACSTREAM_LFE);
383 case 4:
384 rate_mask &= aaci_rate_mask(aaci, ACSTREAM_SURROUND);
385 case 2:
386 rate_mask &= aaci_rate_mask(aaci, ACSTREAM_FRONT);
387 }
388
389 return snd_interval_list(hw_param_interval(p, rule->var),
390 ARRAY_SIZE(rate_list), rate_list,
391 rate_mask);
392 }
393
394 static struct snd_pcm_hardware aaci_hw_info = {
395 .info = SNDRV_PCM_INFO_MMAP |
396 SNDRV_PCM_INFO_MMAP_VALID |
397 SNDRV_PCM_INFO_INTERLEAVED |
398 SNDRV_PCM_INFO_BLOCK_TRANSFER |
399 SNDRV_PCM_INFO_RESUME,
400
401 /*
402 * ALSA doesn't support 18-bit or 20-bit packed into 32-bit
403 * words. It also doesn't support 12-bit at all.
404 */
405 .formats = SNDRV_PCM_FMTBIT_S16_LE,
406
407 /* should this be continuous or knot? */
408 .rates = SNDRV_PCM_RATE_CONTINUOUS,
409 .rate_max = 48000,
410 .rate_min = 4000,
411 .channels_min = 2,
412 .channels_max = 6,
413 .buffer_bytes_max = 64 * 1024,
414 .period_bytes_min = 256,
415 .period_bytes_max = PAGE_SIZE,
416 .periods_min = 4,
417 .periods_max = PAGE_SIZE / 16,
418 };
419
420 static int __aaci_pcm_open(struct aaci *aaci,
421 struct snd_pcm_substream *substream,
422 struct aaci_runtime *aacirun)
423 {
424 struct snd_pcm_runtime *runtime = substream->runtime;
425 int ret;
426
427 aacirun->substream = substream;
428 runtime->private_data = aacirun;
429 runtime->hw = aaci_hw_info;
430
431 /*
432 * FIXME: ALSA specifies fifo_size in bytes. If we're in normal
433 * mode, each 32-bit word contains one sample. If we're in
434 * compact mode, each 32-bit word contains two samples, effectively
435 * halving the FIFO size. However, we don't know for sure which
436 * we'll be using at this point. We set this to the lower limit.
437 */
438 runtime->hw.fifo_size = aaci->fifosize * 2;
439
440 /*
441 * Add rule describing hardware rate dependency
442 * on the number of channels.
443 */
444 ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
445 aaci_rule_rate_by_channels, aaci,
446 SNDRV_PCM_HW_PARAM_CHANNELS,
447 SNDRV_PCM_HW_PARAM_RATE, -1);
448 if (ret)
449 goto out;
450
451 ret = request_irq(aaci->dev->irq[0], aaci_irq, IRQF_SHARED|IRQF_DISABLED,
452 DRIVER_NAME, aaci);
453 if (ret)
454 goto out;
455
456 return 0;
457
458 out:
459 return ret;
460 }
461
462
463 /*
464 * Common ALSA stuff
465 */
466 static int aaci_pcm_close(struct snd_pcm_substream *substream)
467 {
468 struct aaci *aaci = substream->private_data;
469 struct aaci_runtime *aacirun = substream->runtime->private_data;
470
471 WARN_ON(aacirun->cr & CR_EN);
472
473 aacirun->substream = NULL;
474 free_irq(aaci->dev->irq[0], aaci);
475
476 return 0;
477 }
478
479 static int aaci_pcm_hw_free(struct snd_pcm_substream *substream)
480 {
481 struct aaci_runtime *aacirun = substream->runtime->private_data;
482
483 /*
484 * This must not be called with the device enabled.
485 */
486 WARN_ON(aacirun->cr & CR_EN);
487
488 if (aacirun->pcm_open)
489 snd_ac97_pcm_close(aacirun->pcm);
490 aacirun->pcm_open = 0;
491
492 /*
493 * Clear out the DMA and any allocated buffers.
494 */
495 devdma_hw_free(NULL, substream);
496
497 return 0;
498 }
499
500 static int aaci_pcm_hw_params(struct snd_pcm_substream *substream,
501 struct aaci_runtime *aacirun,
502 struct snd_pcm_hw_params *params)
503 {
504 int err;
505
506 aaci_pcm_hw_free(substream);
507
508 err = devdma_hw_alloc(NULL, substream,
509 params_buffer_bytes(params));
510 if (err < 0)
511 goto out;
512
513 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
514 err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
515 params_channels(params),
516 aacirun->pcm->r[0].slots);
517 else
518 err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
519 params_channels(params),
520 aacirun->pcm->r[1].slots);
521
522 if (err)
523 goto out;
524
525 aacirun->pcm_open = 1;
526
527 out:
528 return err;
529 }
530
531 static int aaci_pcm_prepare(struct snd_pcm_substream *substream)
532 {
533 struct snd_pcm_runtime *runtime = substream->runtime;
534 struct aaci_runtime *aacirun = runtime->private_data;
535
536 aacirun->start = (void *)runtime->dma_area;
537 aacirun->end = aacirun->start + runtime->dma_bytes;
538 aacirun->ptr = aacirun->start;
539 aacirun->period =
540 aacirun->bytes = frames_to_bytes(runtime, runtime->period_size);
541
542 return 0;
543 }
544
545 static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream)
546 {
547 struct snd_pcm_runtime *runtime = substream->runtime;
548 struct aaci_runtime *aacirun = runtime->private_data;
549 ssize_t bytes = aacirun->ptr - aacirun->start;
550
551 return bytes_to_frames(runtime, bytes);
552 }
553
554 static int aaci_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma)
555 {
556 return devdma_mmap(NULL, substream, vma);
557 }
558
559
560 /*
561 * Playback specific ALSA stuff
562 */
563 static const u32 channels_to_txmask[] = {
564 [2] = CR_SL3 | CR_SL4,
565 [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8,
566 [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9,
567 };
568
569 /*
570 * We can support two and four channel audio. Unfortunately
571 * six channel audio requires a non-standard channel ordering:
572 * 2 -> FL(3), FR(4)
573 * 4 -> FL(3), FR(4), SL(7), SR(8)
574 * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required)
575 * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
576 * This requires an ALSA configuration file to correct.
577 */
578 static unsigned int channel_list[] = { 2, 4, 6 };
579
580 static int
581 aaci_rule_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
582 {
583 struct aaci *aaci = rule->private;
584 unsigned int chan_mask = 1 << 0, slots;
585
586 /*
587 * pcms[0] is the our 5.1 PCM instance.
588 */
589 slots = aaci->ac97_bus->pcms[0].r[0].slots;
590 if (slots & (1 << AC97_SLOT_PCM_SLEFT)) {
591 chan_mask |= 1 << 1;
592 if (slots & (1 << AC97_SLOT_LFE))
593 chan_mask |= 1 << 2;
594 }
595
596 return snd_interval_list(hw_param_interval(p, rule->var),
597 ARRAY_SIZE(channel_list), channel_list,
598 chan_mask);
599 }
600
601 static int aaci_pcm_open(struct snd_pcm_substream *substream)
602 {
603 struct aaci *aaci = substream->private_data;
604 int ret;
605
606 /*
607 * Add rule describing channel dependency.
608 */
609 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
610 SNDRV_PCM_HW_PARAM_CHANNELS,
611 aaci_rule_channels, aaci,
612 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
613 if (ret)
614 return ret;
615
616 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
617 ret = __aaci_pcm_open(aaci, substream, &aaci->playback);
618 } else {
619 ret = __aaci_pcm_open(aaci, substream, &aaci->capture);
620 }
621 return ret;
622 }
623
624 static int aaci_pcm_playback_hw_params(struct snd_pcm_substream *substream,
625 struct snd_pcm_hw_params *params)
626 {
627 struct aaci *aaci = substream->private_data;
628 struct aaci_runtime *aacirun = substream->runtime->private_data;
629 unsigned int channels = params_channels(params);
630 int ret;
631
632 WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) ||
633 !channels_to_txmask[channels]);
634
635 ret = aaci_pcm_hw_params(substream, aacirun, params);
636
637 /*
638 * Enable FIFO, compact mode, 16 bits per sample.
639 * FIXME: double rate slots?
640 */
641 if (ret >= 0) {
642 aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
643 aacirun->cr |= channels_to_txmask[channels];
644
645 aacirun->fifosz = aaci->fifosize * 4;
646 if (aacirun->cr & CR_COMPACT)
647 aacirun->fifosz >>= 1;
648 }
649 return ret;
650 }
651
652 static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun)
653 {
654 u32 ie;
655
656 ie = readl(aacirun->base + AACI_IE);
657 ie &= ~(IE_URIE|IE_TXIE);
658 writel(ie, aacirun->base + AACI_IE);
659 aacirun->cr &= ~CR_EN;
660 aaci_chan_wait_ready(aacirun);
661 writel(aacirun->cr, aacirun->base + AACI_TXCR);
662 }
663
664 static void aaci_pcm_playback_start(struct aaci_runtime *aacirun)
665 {
666 u32 ie;
667
668 aaci_chan_wait_ready(aacirun);
669 aacirun->cr |= CR_EN;
670
671 ie = readl(aacirun->base + AACI_IE);
672 ie |= IE_URIE | IE_TXIE;
673 writel(ie, aacirun->base + AACI_IE);
674 writel(aacirun->cr, aacirun->base + AACI_TXCR);
675 }
676
677 static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd)
678 {
679 struct aaci *aaci = substream->private_data;
680 struct aaci_runtime *aacirun = substream->runtime->private_data;
681 unsigned long flags;
682 int ret = 0;
683
684 spin_lock_irqsave(&aaci->lock, flags);
685 switch (cmd) {
686 case SNDRV_PCM_TRIGGER_START:
687 aaci_pcm_playback_start(aacirun);
688 break;
689
690 case SNDRV_PCM_TRIGGER_RESUME:
691 aaci_pcm_playback_start(aacirun);
692 break;
693
694 case SNDRV_PCM_TRIGGER_STOP:
695 aaci_pcm_playback_stop(aacirun);
696 break;
697
698 case SNDRV_PCM_TRIGGER_SUSPEND:
699 aaci_pcm_playback_stop(aacirun);
700 break;
701
702 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
703 break;
704
705 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
706 break;
707
708 default:
709 ret = -EINVAL;
710 }
711 spin_unlock_irqrestore(&aaci->lock, flags);
712
713 return ret;
714 }
715
716 static struct snd_pcm_ops aaci_playback_ops = {
717 .open = aaci_pcm_open,
718 .close = aaci_pcm_close,
719 .ioctl = snd_pcm_lib_ioctl,
720 .hw_params = aaci_pcm_playback_hw_params,
721 .hw_free = aaci_pcm_hw_free,
722 .prepare = aaci_pcm_prepare,
723 .trigger = aaci_pcm_playback_trigger,
724 .pointer = aaci_pcm_pointer,
725 .mmap = aaci_pcm_mmap,
726 };
727
728 static int aaci_pcm_capture_hw_params(struct snd_pcm_substream *substream,
729 struct snd_pcm_hw_params *params)
730 {
731 struct aaci *aaci = substream->private_data;
732 struct aaci_runtime *aacirun = substream->runtime->private_data;
733 int ret;
734
735 ret = aaci_pcm_hw_params(substream, aacirun, params);
736
737 if (ret >= 0) {
738 aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
739
740 /* Line in record: slot 3 and 4 */
741 aacirun->cr |= CR_SL3 | CR_SL4;
742
743 aacirun->fifosz = aaci->fifosize * 4;
744
745 if (aacirun->cr & CR_COMPACT)
746 aacirun->fifosz >>= 1;
747 }
748 return ret;
749 }
750
751 static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun)
752 {
753 u32 ie;
754
755 aaci_chan_wait_ready(aacirun);
756
757 ie = readl(aacirun->base + AACI_IE);
758 ie &= ~(IE_ORIE | IE_RXIE);
759 writel(ie, aacirun->base+AACI_IE);
760
761 aacirun->cr &= ~CR_EN;
762
763 writel(aacirun->cr, aacirun->base + AACI_RXCR);
764 }
765
766 static void aaci_pcm_capture_start(struct aaci_runtime *aacirun)
767 {
768 u32 ie;
769
770 aaci_chan_wait_ready(aacirun);
771
772 #ifdef DEBUG
773 /* RX Timeout value: bits 28:17 in RXCR */
774 aacirun->cr |= 0xf << 17;
775 #endif
776
777 aacirun->cr |= CR_EN;
778 writel(aacirun->cr, aacirun->base + AACI_RXCR);
779
780 ie = readl(aacirun->base + AACI_IE);
781 ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full
782 writel(ie, aacirun->base + AACI_IE);
783 }
784
785 static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd)
786 {
787 struct aaci *aaci = substream->private_data;
788 struct aaci_runtime *aacirun = substream->runtime->private_data;
789 unsigned long flags;
790 int ret = 0;
791
792 spin_lock_irqsave(&aaci->lock, flags);
793
794 switch (cmd) {
795 case SNDRV_PCM_TRIGGER_START:
796 aaci_pcm_capture_start(aacirun);
797 break;
798
799 case SNDRV_PCM_TRIGGER_RESUME:
800 aaci_pcm_capture_start(aacirun);
801 break;
802
803 case SNDRV_PCM_TRIGGER_STOP:
804 aaci_pcm_capture_stop(aacirun);
805 break;
806
807 case SNDRV_PCM_TRIGGER_SUSPEND:
808 aaci_pcm_capture_stop(aacirun);
809 break;
810
811 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
812 break;
813
814 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
815 break;
816
817 default:
818 ret = -EINVAL;
819 }
820
821 spin_unlock_irqrestore(&aaci->lock, flags);
822
823 return ret;
824 }
825
826 static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream)
827 {
828 struct snd_pcm_runtime *runtime = substream->runtime;
829 struct aaci *aaci = substream->private_data;
830
831 aaci_pcm_prepare(substream);
832
833 /* allow changing of sample rate */
834 aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */
835 aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
836 aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate);
837
838 /* Record select: Mic: 0, Aux: 3, Line: 4 */
839 aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404);
840
841 return 0;
842 }
843
844 static struct snd_pcm_ops aaci_capture_ops = {
845 .open = aaci_pcm_open,
846 .close = aaci_pcm_close,
847 .ioctl = snd_pcm_lib_ioctl,
848 .hw_params = aaci_pcm_capture_hw_params,
849 .hw_free = aaci_pcm_hw_free,
850 .prepare = aaci_pcm_capture_prepare,
851 .trigger = aaci_pcm_capture_trigger,
852 .pointer = aaci_pcm_pointer,
853 .mmap = aaci_pcm_mmap,
854 };
855
856 /*
857 * Power Management.
858 */
859 #ifdef CONFIG_PM
860 static int aaci_do_suspend(struct snd_card *card, unsigned int state)
861 {
862 struct aaci *aaci = card->private_data;
863 snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
864 snd_pcm_suspend_all(aaci->pcm);
865 return 0;
866 }
867
868 static int aaci_do_resume(struct snd_card *card, unsigned int state)
869 {
870 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
871 return 0;
872 }
873
874 static int aaci_suspend(struct amba_device *dev, pm_message_t state)
875 {
876 struct snd_card *card = amba_get_drvdata(dev);
877 return card ? aaci_do_suspend(card) : 0;
878 }
879
880 static int aaci_resume(struct amba_device *dev)
881 {
882 struct snd_card *card = amba_get_drvdata(dev);
883 return card ? aaci_do_resume(card) : 0;
884 }
885 #else
886 #define aaci_do_suspend NULL
887 #define aaci_do_resume NULL
888 #define aaci_suspend NULL
889 #define aaci_resume NULL
890 #endif
891
892
893 static struct ac97_pcm ac97_defs[] __devinitdata = {
894 [0] = { /* Front PCM */
895 .exclusive = 1,
896 .r = {
897 [0] = {
898 .slots = (1 << AC97_SLOT_PCM_LEFT) |
899 (1 << AC97_SLOT_PCM_RIGHT) |
900 (1 << AC97_SLOT_PCM_CENTER) |
901 (1 << AC97_SLOT_PCM_SLEFT) |
902 (1 << AC97_SLOT_PCM_SRIGHT) |
903 (1 << AC97_SLOT_LFE),
904 },
905 },
906 },
907 [1] = { /* PCM in */
908 .stream = 1,
909 .exclusive = 1,
910 .r = {
911 [0] = {
912 .slots = (1 << AC97_SLOT_PCM_LEFT) |
913 (1 << AC97_SLOT_PCM_RIGHT),
914 },
915 },
916 },
917 [2] = { /* Mic in */
918 .stream = 1,
919 .exclusive = 1,
920 .r = {
921 [0] = {
922 .slots = (1 << AC97_SLOT_MIC),
923 },
924 },
925 }
926 };
927
928 static struct snd_ac97_bus_ops aaci_bus_ops = {
929 .write = aaci_ac97_write,
930 .read = aaci_ac97_read,
931 };
932
933 static int __devinit aaci_probe_ac97(struct aaci *aaci)
934 {
935 struct snd_ac97_template ac97_template;
936 struct snd_ac97_bus *ac97_bus;
937 struct snd_ac97 *ac97;
938 int ret;
939
940 /*
941 * Assert AACIRESET for 2us
942 */
943 writel(0, aaci->base + AACI_RESET);
944 udelay(2);
945 writel(RESET_NRST, aaci->base + AACI_RESET);
946
947 /*
948 * Give the AC'97 codec more than enough time
949 * to wake up. (42us = ~2 frames at 48kHz.)
950 */
951 udelay(42);
952
953 ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus);
954 if (ret)
955 goto out;
956
957 ac97_bus->clock = 48000;
958 aaci->ac97_bus = ac97_bus;
959
960 memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
961 ac97_template.private_data = aaci;
962 ac97_template.num = 0;
963 ac97_template.scaps = AC97_SCAP_SKIP_MODEM;
964
965 ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97);
966 if (ret)
967 goto out;
968 aaci->ac97 = ac97;
969
970 /*
971 * Disable AC97 PC Beep input on audio codecs.
972 */
973 if (ac97_is_audio(ac97))
974 snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e);
975
976 ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs);
977 if (ret)
978 goto out;
979
980 aaci->playback.pcm = &ac97_bus->pcms[0];
981 aaci->capture.pcm = &ac97_bus->pcms[1];
982
983 out:
984 return ret;
985 }
986
987 static void aaci_free_card(struct snd_card *card)
988 {
989 struct aaci *aaci = card->private_data;
990 if (aaci->base)
991 iounmap(aaci->base);
992 }
993
994 static struct aaci * __devinit aaci_init_card(struct amba_device *dev)
995 {
996 struct aaci *aaci;
997 struct snd_card *card;
998
999 card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
1000 THIS_MODULE, sizeof(struct aaci));
1001 if (card == NULL)
1002 return ERR_PTR(-ENOMEM);
1003
1004 card->private_free = aaci_free_card;
1005
1006 strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
1007 strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname));
1008 snprintf(card->longname, sizeof(card->longname),
1009 "%s at 0x%016llx, irq %d",
1010 card->shortname, (unsigned long long)dev->res.start,
1011 dev->irq[0]);
1012
1013 aaci = card->private_data;
1014 mutex_init(&aaci->ac97_sem);
1015 spin_lock_init(&aaci->lock);
1016 aaci->card = card;
1017 aaci->dev = dev;
1018
1019 /* Set MAINCR to allow slot 1 and 2 data IO */
1020 aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN |
1021 MAINCR_SL2RXEN | MAINCR_SL2TXEN;
1022
1023 return aaci;
1024 }
1025
1026 static int __devinit aaci_init_pcm(struct aaci *aaci)
1027 {
1028 struct snd_pcm *pcm;
1029 int ret;
1030
1031 ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm);
1032 if (ret == 0) {
1033 aaci->pcm = pcm;
1034 pcm->private_data = aaci;
1035 pcm->info_flags = 0;
1036
1037 strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
1038
1039 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops);
1040 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops);
1041 }
1042
1043 return ret;
1044 }
1045
1046 static unsigned int __devinit aaci_size_fifo(struct aaci *aaci)
1047 {
1048 struct aaci_runtime *aacirun = &aaci->playback;
1049 int i;
1050
1051 writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR);
1052
1053 for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++)
1054 writel(0, aacirun->fifo);
1055
1056 writel(0, aacirun->base + AACI_TXCR);
1057
1058 /*
1059 * Re-initialise the AACI after the FIFO depth test, to
1060 * ensure that the FIFOs are empty. Unfortunately, merely
1061 * disabling the channel doesn't clear the FIFO.
1062 */
1063 writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);
1064 writel(aaci->maincr, aaci->base + AACI_MAINCR);
1065
1066 /*
1067 * If we hit 4096, we failed. Go back to the specified
1068 * fifo depth.
1069 */
1070 if (i == 4096)
1071 i = 8;
1072
1073 return i;
1074 }
1075
1076 static int __devinit aaci_probe(struct amba_device *dev, void *id)
1077 {
1078 struct aaci *aaci;
1079 int ret, i;
1080
1081 ret = amba_request_regions(dev, NULL);
1082 if (ret)
1083 return ret;
1084
1085 aaci = aaci_init_card(dev);
1086 if (IS_ERR(aaci)) {
1087 ret = PTR_ERR(aaci);
1088 goto out;
1089 }
1090
1091 aaci->base = ioremap(dev->res.start, SZ_4K);
1092 if (!aaci->base) {
1093 ret = -ENOMEM;
1094 goto out;
1095 }
1096
1097 /*
1098 * Playback uses AACI channel 0
1099 */
1100 aaci->playback.base = aaci->base + AACI_CSCH1;
1101 aaci->playback.fifo = aaci->base + AACI_DR1;
1102
1103 /*
1104 * Capture uses AACI channel 0
1105 */
1106 aaci->capture.base = aaci->base + AACI_CSCH1;
1107 aaci->capture.fifo = aaci->base + AACI_DR1;
1108
1109 for (i = 0; i < 4; i++) {
1110 void __iomem *base = aaci->base + i * 0x14;
1111
1112 writel(0, base + AACI_IE);
1113 writel(0, base + AACI_TXCR);
1114 writel(0, base + AACI_RXCR);
1115 }
1116
1117 writel(0x1fff, aaci->base + AACI_INTCLR);
1118 writel(aaci->maincr, aaci->base + AACI_MAINCR);
1119
1120 ret = aaci_probe_ac97(aaci);
1121 if (ret)
1122 goto out;
1123
1124 /*
1125 * Size the FIFOs (must be multiple of 16).
1126 */
1127 aaci->fifosize = aaci_size_fifo(aaci);
1128 if (aaci->fifosize & 15) {
1129 printk(KERN_WARNING "AACI: fifosize = %d not supported\n",
1130 aaci->fifosize);
1131 ret = -ENODEV;
1132 goto out;
1133 }
1134
1135 ret = aaci_init_pcm(aaci);
1136 if (ret)
1137 goto out;
1138
1139 snd_card_set_dev(aaci->card, &dev->dev);
1140
1141 ret = snd_card_register(aaci->card);
1142 if (ret == 0) {
1143 dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname,
1144 aaci->fifosize);
1145 amba_set_drvdata(dev, aaci->card);
1146 return ret;
1147 }
1148
1149 out:
1150 if (aaci)
1151 snd_card_free(aaci->card);
1152 amba_release_regions(dev);
1153 return ret;
1154 }
1155
1156 static int __devexit aaci_remove(struct amba_device *dev)
1157 {
1158 struct snd_card *card = amba_get_drvdata(dev);
1159
1160 amba_set_drvdata(dev, NULL);
1161
1162 if (card) {
1163 struct aaci *aaci = card->private_data;
1164 writel(0, aaci->base + AACI_MAINCR);
1165
1166 snd_card_free(card);
1167 amba_release_regions(dev);
1168 }
1169
1170 return 0;
1171 }
1172
1173 static struct amba_id aaci_ids[] = {
1174 {
1175 .id = 0x00041041,
1176 .mask = 0x000fffff,
1177 },
1178 { 0, 0 },
1179 };
1180
1181 static struct amba_driver aaci_driver = {
1182 .drv = {
1183 .name = DRIVER_NAME,
1184 },
1185 .probe = aaci_probe,
1186 .remove = __devexit_p(aaci_remove),
1187 .suspend = aaci_suspend,
1188 .resume = aaci_resume,
1189 .id_table = aaci_ids,
1190 };
1191
1192 static int __init aaci_init(void)
1193 {
1194 return amba_driver_register(&aaci_driver);
1195 }
1196
1197 static void __exit aaci_exit(void)
1198 {
1199 amba_driver_unregister(&aaci_driver);
1200 }
1201
1202 module_init(aaci_init);
1203 module_exit(aaci_exit);
1204
1205 MODULE_LICENSE("GPL");
1206 MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");
Support for the Chinese Samsung S3C2440 based development boards