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synclink_gt: fix transmit DMA stall
[linux-2.6/mini2440.git] / drivers / char / synclink_gt.c
blobbbb7f1292665267bf22f3a59afb455abfb5aaf00
1 /*
2 * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink GT serial adapters.
5 *
6 * written by Paul Fulghum for Microgate Corporation
7 * paulkf@microgate.com
8 *
9 * Microgate and SyncLink are trademarks of Microgate Corporation
10 *
11 * This code is released under the GNU General Public License (GPL)
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
17 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
21 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
23 * OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26 /*
27 * DEBUG OUTPUT DEFINITIONS
28 *
29 * uncomment lines below to enable specific types of debug output
30 *
31 * DBGINFO information - most verbose output
32 * DBGERR serious errors
33 * DBGBH bottom half service routine debugging
34 * DBGISR interrupt service routine debugging
35 * DBGDATA output receive and transmit data
36 * DBGTBUF output transmit DMA buffers and registers
37 * DBGRBUF output receive DMA buffers and registers
38 */
39
40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
45 //#define DBGTBUF(info) dump_tbufs(info)
46 //#define DBGRBUF(info) dump_rbufs(info)
47
48
49 #include <linux/module.h>
50 #include <linux/version.h>
51 #include <linux/errno.h>
52 #include <linux/signal.h>
53 #include <linux/sched.h>
54 #include <linux/timer.h>
55 #include <linux/interrupt.h>
56 #include <linux/pci.h>
57 #include <linux/tty.h>
58 #include <linux/tty_flip.h>
59 #include <linux/serial.h>
60 #include <linux/major.h>
61 #include <linux/string.h>
62 #include <linux/fcntl.h>
63 #include <linux/ptrace.h>
64 #include <linux/ioport.h>
65 #include <linux/mm.h>
66 #include <linux/slab.h>
67 #include <linux/netdevice.h>
68 #include <linux/vmalloc.h>
69 #include <linux/init.h>
70 #include <linux/delay.h>
71 #include <linux/ioctl.h>
72 #include <linux/termios.h>
73 #include <linux/bitops.h>
74 #include <linux/workqueue.h>
75 #include <linux/hdlc.h>
76
77 #include <asm/system.h>
78 #include <asm/io.h>
79 #include <asm/irq.h>
80 #include <asm/dma.h>
81 #include <asm/types.h>
82 #include <asm/uaccess.h>
83
84 #include "linux/synclink.h"
85
86 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
87 #define SYNCLINK_GENERIC_HDLC 1
88 #else
89 #define SYNCLINK_GENERIC_HDLC 0
90 #endif
91
92 /*
93 * module identification
94 */
95 static char *driver_name = "SyncLink GT";
96 static char *driver_version = "$Revision: 4.50 $";
97 static char *tty_driver_name = "synclink_gt";
98 static char *tty_dev_prefix = "ttySLG";
99 MODULE_LICENSE("GPL");
100 #define MGSL_MAGIC 0x5401
101 #define MAX_DEVICES 32
102
103 static struct pci_device_id pci_table[] = {
104 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
105 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
106 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
107 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
108 {0,}, /* terminate list */
109 };
110 MODULE_DEVICE_TABLE(pci, pci_table);
111
112 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
113 static void remove_one(struct pci_dev *dev);
114 static struct pci_driver pci_driver = {
115 .name = "synclink_gt",
116 .id_table = pci_table,
117 .probe = init_one,
118 .remove = __devexit_p(remove_one),
119 };
120
121 static int pci_registered;
122
123 /*
124 * module configuration and status
125 */
126 static struct slgt_info *slgt_device_list;
127 static int slgt_device_count;
128
129 static int ttymajor;
130 static int debug_level;
131 static int maxframe[MAX_DEVICES];
132 static int dosyncppp[MAX_DEVICES];
133
134 module_param(ttymajor, int, 0);
135 module_param(debug_level, int, 0);
136 module_param_array(maxframe, int, NULL, 0);
137 module_param_array(dosyncppp, int, NULL, 0);
138
139 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
140 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
141 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
142 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
143
144 /*
145 * tty support and callbacks
146 */
147 static struct tty_driver *serial_driver;
148
149 static int open(struct tty_struct *tty, struct file * filp);
150 static void close(struct tty_struct *tty, struct file * filp);
151 static void hangup(struct tty_struct *tty);
152 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
153
154 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
155 static void put_char(struct tty_struct *tty, unsigned char ch);
156 static void send_xchar(struct tty_struct *tty, char ch);
157 static void wait_until_sent(struct tty_struct *tty, int timeout);
158 static int write_room(struct tty_struct *tty);
159 static void flush_chars(struct tty_struct *tty);
160 static void flush_buffer(struct tty_struct *tty);
161 static void tx_hold(struct tty_struct *tty);
162 static void tx_release(struct tty_struct *tty);
163
164 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
165 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
166 static int chars_in_buffer(struct tty_struct *tty);
167 static void throttle(struct tty_struct * tty);
168 static void unthrottle(struct tty_struct * tty);
169 static void set_break(struct tty_struct *tty, int break_state);
170
171 /*
172 * generic HDLC support and callbacks
173 */
174 #if SYNCLINK_GENERIC_HDLC
175 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
176 static void hdlcdev_tx_done(struct slgt_info *info);
177 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
178 static int hdlcdev_init(struct slgt_info *info);
179 static void hdlcdev_exit(struct slgt_info *info);
180 #endif
181
182
183 /*
184 * device specific structures, macros and functions
185 */
186
187 #define SLGT_MAX_PORTS 4
188 #define SLGT_REG_SIZE 256
189
190 /*
191 * conditional wait facility
192 */
193 struct cond_wait {
194 struct cond_wait *next;
195 wait_queue_head_t q;
196 wait_queue_t wait;
197 unsigned int data;
198 };
199 static void init_cond_wait(struct cond_wait *w, unsigned int data);
200 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
201 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
202 static void flush_cond_wait(struct cond_wait **head);
203
204 /*
205 * DMA buffer descriptor and access macros
206 */
207 struct slgt_desc
208 {
209 unsigned short count;
210 unsigned short status;
211 unsigned int pbuf; /* physical address of data buffer */
212 unsigned int next; /* physical address of next descriptor */
213
214 /* driver book keeping */
215 char *buf; /* virtual address of data buffer */
216 unsigned int pdesc; /* physical address of this descriptor */
217 dma_addr_t buf_dma_addr;
218 };
219
220 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
221 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
222 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
223 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
224 #define desc_count(a) (le16_to_cpu((a).count))
225 #define desc_status(a) (le16_to_cpu((a).status))
226 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
227 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
228 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
229 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
230 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
231
232 struct _input_signal_events {
233 int ri_up;
234 int ri_down;
235 int dsr_up;
236 int dsr_down;
237 int dcd_up;
238 int dcd_down;
239 int cts_up;
240 int cts_down;
241 };
242
243 /*
244 * device instance data structure
245 */
246 struct slgt_info {
247 void *if_ptr; /* General purpose pointer (used by SPPP) */
248
249 struct slgt_info *next_device; /* device list link */
250
251 int magic;
252 int flags;
253
254 char device_name[25];
255 struct pci_dev *pdev;
256
257 int port_count; /* count of ports on adapter */
258 int adapter_num; /* adapter instance number */
259 int port_num; /* port instance number */
260
261 /* array of pointers to port contexts on this adapter */
262 struct slgt_info *port_array[SLGT_MAX_PORTS];
263
264 int count; /* count of opens */
265 int line; /* tty line instance number */
266 unsigned short close_delay;
267 unsigned short closing_wait; /* time to wait before closing */
268
269 struct mgsl_icount icount;
270
271 struct tty_struct *tty;
272 int timeout;
273 int x_char; /* xon/xoff character */
274 int blocked_open; /* # of blocked opens */
275 unsigned int read_status_mask;
276 unsigned int ignore_status_mask;
277
278 wait_queue_head_t open_wait;
279 wait_queue_head_t close_wait;
280
281 wait_queue_head_t status_event_wait_q;
282 wait_queue_head_t event_wait_q;
283 struct timer_list tx_timer;
284 struct timer_list rx_timer;
285
286 unsigned int gpio_present;
287 struct cond_wait *gpio_wait_q;
288
289 spinlock_t lock; /* spinlock for synchronizing with ISR */
290
291 struct work_struct task;
292 u32 pending_bh;
293 int bh_requested;
294 int bh_running;
295
296 int isr_overflow;
297 int irq_requested; /* nonzero if IRQ requested */
298 int irq_occurred; /* for diagnostics use */
299
300 /* device configuration */
301
302 unsigned int bus_type;
303 unsigned int irq_level;
304 unsigned long irq_flags;
305
306 unsigned char __iomem * reg_addr; /* memory mapped registers address */
307 u32 phys_reg_addr;
308 int reg_addr_requested;
309
310 MGSL_PARAMS params; /* communications parameters */
311 u32 idle_mode;
312 u32 max_frame_size; /* as set by device config */
313
314 unsigned int raw_rx_size;
315 unsigned int if_mode;
316
317 /* device status */
318
319 int rx_enabled;
320 int rx_restart;
321
322 int tx_enabled;
323 int tx_active;
324
325 unsigned char signals; /* serial signal states */
326 int init_error; /* initialization error */
327
328 unsigned char *tx_buf;
329 int tx_count;
330
331 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
332 char char_buf[MAX_ASYNC_BUFFER_SIZE];
333 BOOLEAN drop_rts_on_tx_done;
334 struct _input_signal_events input_signal_events;
335
336 int dcd_chkcount; /* check counts to prevent */
337 int cts_chkcount; /* too many IRQs if a signal */
338 int dsr_chkcount; /* is floating */
339 int ri_chkcount;
340
341 char *bufs; /* virtual address of DMA buffer lists */
342 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
343
344 unsigned int rbuf_count;
345 struct slgt_desc *rbufs;
346 unsigned int rbuf_current;
347 unsigned int rbuf_index;
348
349 unsigned int tbuf_count;
350 struct slgt_desc *tbufs;
351 unsigned int tbuf_current;
352 unsigned int tbuf_start;
353
354 unsigned char *tmp_rbuf;
355 unsigned int tmp_rbuf_count;
356
357 /* SPPP/Cisco HDLC device parts */
358
359 int netcount;
360 int dosyncppp;
361 spinlock_t netlock;
362 #if SYNCLINK_GENERIC_HDLC
363 struct net_device *netdev;
364 #endif
365
366 };
367
368 static MGSL_PARAMS default_params = {
369 .mode = MGSL_MODE_HDLC,
370 .loopback = 0,
371 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
372 .encoding = HDLC_ENCODING_NRZI_SPACE,
373 .clock_speed = 0,
374 .addr_filter = 0xff,
375 .crc_type = HDLC_CRC_16_CCITT,
376 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
377 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
378 .data_rate = 9600,
379 .data_bits = 8,
380 .stop_bits = 1,
381 .parity = ASYNC_PARITY_NONE
382 };
383
384
385 #define BH_RECEIVE 1
386 #define BH_TRANSMIT 2
387 #define BH_STATUS 4
388 #define IO_PIN_SHUTDOWN_LIMIT 100
389
390 #define DMABUFSIZE 256
391 #define DESC_LIST_SIZE 4096
392
393 #define MASK_PARITY BIT1
394 #define MASK_FRAMING BIT0
395 #define MASK_BREAK BIT14
396 #define MASK_OVERRUN BIT4
397
398 #define GSR 0x00 /* global status */
399 #define JCR 0x04 /* JTAG control */
400 #define IODR 0x08 /* GPIO direction */
401 #define IOER 0x0c /* GPIO interrupt enable */
402 #define IOVR 0x10 /* GPIO value */
403 #define IOSR 0x14 /* GPIO interrupt status */
404 #define TDR 0x80 /* tx data */
405 #define RDR 0x80 /* rx data */
406 #define TCR 0x82 /* tx control */
407 #define TIR 0x84 /* tx idle */
408 #define TPR 0x85 /* tx preamble */
409 #define RCR 0x86 /* rx control */
410 #define VCR 0x88 /* V.24 control */
411 #define CCR 0x89 /* clock control */
412 #define BDR 0x8a /* baud divisor */
413 #define SCR 0x8c /* serial control */
414 #define SSR 0x8e /* serial status */
415 #define RDCSR 0x90 /* rx DMA control/status */
416 #define TDCSR 0x94 /* tx DMA control/status */
417 #define RDDAR 0x98 /* rx DMA descriptor address */
418 #define TDDAR 0x9c /* tx DMA descriptor address */
419
420 #define RXIDLE BIT14
421 #define RXBREAK BIT14
422 #define IRQ_TXDATA BIT13
423 #define IRQ_TXIDLE BIT12
424 #define IRQ_TXUNDER BIT11 /* HDLC */
425 #define IRQ_RXDATA BIT10
426 #define IRQ_RXIDLE BIT9 /* HDLC */
427 #define IRQ_RXBREAK BIT9 /* async */
428 #define IRQ_RXOVER BIT8
429 #define IRQ_DSR BIT7
430 #define IRQ_CTS BIT6
431 #define IRQ_DCD BIT5
432 #define IRQ_RI BIT4
433 #define IRQ_ALL 0x3ff0
434 #define IRQ_MASTER BIT0
435
436 #define slgt_irq_on(info, mask) \
437 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
438 #define slgt_irq_off(info, mask) \
439 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
440
441 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
442 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
443 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
444 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
445 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
446 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
447
448 static void msc_set_vcr(struct slgt_info *info);
449
450 static int startup(struct slgt_info *info);
451 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
452 static void shutdown(struct slgt_info *info);
453 static void program_hw(struct slgt_info *info);
454 static void change_params(struct slgt_info *info);
455
456 static int register_test(struct slgt_info *info);
457 static int irq_test(struct slgt_info *info);
458 static int loopback_test(struct slgt_info *info);
459 static int adapter_test(struct slgt_info *info);
460
461 static void reset_adapter(struct slgt_info *info);
462 static void reset_port(struct slgt_info *info);
463 static void async_mode(struct slgt_info *info);
464 static void sync_mode(struct slgt_info *info);
465
466 static void rx_stop(struct slgt_info *info);
467 static void rx_start(struct slgt_info *info);
468 static void reset_rbufs(struct slgt_info *info);
469 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
470 static void rdma_reset(struct slgt_info *info);
471 static int rx_get_frame(struct slgt_info *info);
472 static int rx_get_buf(struct slgt_info *info);
473
474 static void tx_start(struct slgt_info *info);
475 static void tx_stop(struct slgt_info *info);
476 static void tx_set_idle(struct slgt_info *info);
477 static unsigned int free_tbuf_count(struct slgt_info *info);
478 static void reset_tbufs(struct slgt_info *info);
479 static void tdma_reset(struct slgt_info *info);
480 static void tdma_start(struct slgt_info *info);
481 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
482
483 static void get_signals(struct slgt_info *info);
484 static void set_signals(struct slgt_info *info);
485 static void enable_loopback(struct slgt_info *info);
486 static void set_rate(struct slgt_info *info, u32 data_rate);
487
488 static int bh_action(struct slgt_info *info);
489 static void bh_handler(struct work_struct *work);
490 static void bh_transmit(struct slgt_info *info);
491 static void isr_serial(struct slgt_info *info);
492 static void isr_rdma(struct slgt_info *info);
493 static void isr_txeom(struct slgt_info *info, unsigned short status);
494 static void isr_tdma(struct slgt_info *info);
495 static irqreturn_t slgt_interrupt(int irq, void *dev_id);
496
497 static int alloc_dma_bufs(struct slgt_info *info);
498 static void free_dma_bufs(struct slgt_info *info);
499 static int alloc_desc(struct slgt_info *info);
500 static void free_desc(struct slgt_info *info);
501 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
502 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
503
504 static int alloc_tmp_rbuf(struct slgt_info *info);
505 static void free_tmp_rbuf(struct slgt_info *info);
506
507 static void tx_timeout(unsigned long context);
508 static void rx_timeout(unsigned long context);
509
510 /*
511 * ioctl handlers
512 */
513 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
514 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
515 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
516 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
517 static int set_txidle(struct slgt_info *info, int idle_mode);
518 static int tx_enable(struct slgt_info *info, int enable);
519 static int tx_abort(struct slgt_info *info);
520 static int rx_enable(struct slgt_info *info, int enable);
521 static int modem_input_wait(struct slgt_info *info,int arg);
522 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
523 static int tiocmget(struct tty_struct *tty, struct file *file);
524 static int tiocmset(struct tty_struct *tty, struct file *file,
525 unsigned int set, unsigned int clear);
526 static void set_break(struct tty_struct *tty, int break_state);
527 static int get_interface(struct slgt_info *info, int __user *if_mode);
528 static int set_interface(struct slgt_info *info, int if_mode);
529 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
530 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
531 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
532
533 /*
534 * driver functions
535 */
536 static void add_device(struct slgt_info *info);
537 static void device_init(int adapter_num, struct pci_dev *pdev);
538 static int claim_resources(struct slgt_info *info);
539 static void release_resources(struct slgt_info *info);
540
541 /*
542 * DEBUG OUTPUT CODE
543 */
544 #ifndef DBGINFO
545 #define DBGINFO(fmt)
546 #endif
547 #ifndef DBGERR
548 #define DBGERR(fmt)
549 #endif
550 #ifndef DBGBH
551 #define DBGBH(fmt)
552 #endif
553 #ifndef DBGISR
554 #define DBGISR(fmt)
555 #endif
556
557 #ifdef DBGDATA
558 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
559 {
560 int i;
561 int linecount;
562 printk("%s %s data:\n",info->device_name, label);
563 while(count) {
564 linecount = (count > 16) ? 16 : count;
565 for(i=0; i < linecount; i++)
566 printk("%02X ",(unsigned char)data[i]);
567 for(;i<17;i++)
568 printk(" ");
569 for(i=0;i<linecount;i++) {
570 if (data[i]>=040 && data[i]<=0176)
571 printk("%c",data[i]);
572 else
573 printk(".");
574 }
575 printk("\n");
576 data += linecount;
577 count -= linecount;
578 }
579 }
580 #else
581 #define DBGDATA(info, buf, size, label)
582 #endif
583
584 #ifdef DBGTBUF
585 static void dump_tbufs(struct slgt_info *info)
586 {
587 int i;
588 printk("tbuf_current=%d\n", info->tbuf_current);
589 for (i=0 ; i < info->tbuf_count ; i++) {
590 printk("%d: count=%04X status=%04X\n",
591 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
592 }
593 }
594 #else
595 #define DBGTBUF(info)
596 #endif
597
598 #ifdef DBGRBUF
599 static void dump_rbufs(struct slgt_info *info)
600 {
601 int i;
602 printk("rbuf_current=%d\n", info->rbuf_current);
603 for (i=0 ; i < info->rbuf_count ; i++) {
604 printk("%d: count=%04X status=%04X\n",
605 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
606 }
607 }
608 #else
609 #define DBGRBUF(info)
610 #endif
611
612 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
613 {
614 #ifdef SANITY_CHECK
615 if (!info) {
616 printk("null struct slgt_info for (%s) in %s\n", devname, name);
617 return 1;
618 }
619 if (info->magic != MGSL_MAGIC) {
620 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
621 return 1;
622 }
623 #else
624 if (!info)
625 return 1;
626 #endif
627 return 0;
628 }
629
630 /**
631 * line discipline callback wrappers
632 *
633 * The wrappers maintain line discipline references
634 * while calling into the line discipline.
635 *
636 * ldisc_receive_buf - pass receive data to line discipline
637 */
638 static void ldisc_receive_buf(struct tty_struct *tty,
639 const __u8 *data, char *flags, int count)
640 {
641 struct tty_ldisc *ld;
642 if (!tty)
643 return;
644 ld = tty_ldisc_ref(tty);
645 if (ld) {
646 if (ld->receive_buf)
647 ld->receive_buf(tty, data, flags, count);
648 tty_ldisc_deref(ld);
649 }
650 }
651
652 /* tty callbacks */
653
654 static int open(struct tty_struct *tty, struct file *filp)
655 {
656 struct slgt_info *info;
657 int retval, line;
658 unsigned long flags;
659
660 line = tty->index;
661 if ((line < 0) || (line >= slgt_device_count)) {
662 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
663 return -ENODEV;
664 }
665
666 info = slgt_device_list;
667 while(info && info->line != line)
668 info = info->next_device;
669 if (sanity_check(info, tty->name, "open"))
670 return -ENODEV;
671 if (info->init_error) {
672 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
673 return -ENODEV;
674 }
675
676 tty->driver_data = info;
677 info->tty = tty;
678
679 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
680
681 /* If port is closing, signal caller to try again */
682 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
683 if (info->flags & ASYNC_CLOSING)
684 interruptible_sleep_on(&info->close_wait);
685 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
686 -EAGAIN : -ERESTARTSYS);
687 goto cleanup;
688 }
689
690 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
691
692 spin_lock_irqsave(&info->netlock, flags);
693 if (info->netcount) {
694 retval = -EBUSY;
695 spin_unlock_irqrestore(&info->netlock, flags);
696 goto cleanup;
697 }
698 info->count++;
699 spin_unlock_irqrestore(&info->netlock, flags);
700
701 if (info->count == 1) {
702 /* 1st open on this device, init hardware */
703 retval = startup(info);
704 if (retval < 0)
705 goto cleanup;
706 }
707
708 retval = block_til_ready(tty, filp, info);
709 if (retval) {
710 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
711 goto cleanup;
712 }
713
714 retval = 0;
715
716 cleanup:
717 if (retval) {
718 if (tty->count == 1)
719 info->tty = NULL; /* tty layer will release tty struct */
720 if(info->count)
721 info->count--;
722 }
723
724 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
725 return retval;
726 }
727
728 static void close(struct tty_struct *tty, struct file *filp)
729 {
730 struct slgt_info *info = tty->driver_data;
731
732 if (sanity_check(info, tty->name, "close"))
733 return;
734 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
735
736 if (!info->count)
737 return;
738
739 if (tty_hung_up_p(filp))
740 goto cleanup;
741
742 if ((tty->count == 1) && (info->count != 1)) {
743 /*
744 * tty->count is 1 and the tty structure will be freed.
745 * info->count should be one in this case.
746 * if it's not, correct it so that the port is shutdown.
747 */
748 DBGERR(("%s close: bad refcount; tty->count=1, "
749 "info->count=%d\n", info->device_name, info->count));
750 info->count = 1;
751 }
752
753 info->count--;
754
755 /* if at least one open remaining, leave hardware active */
756 if (info->count)
757 goto cleanup;
758
759 info->flags |= ASYNC_CLOSING;
760
761 /* set tty->closing to notify line discipline to
762 * only process XON/XOFF characters. Only the N_TTY
763 * discipline appears to use this (ppp does not).
764 */
765 tty->closing = 1;
766
767 /* wait for transmit data to clear all layers */
768
769 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
770 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
771 tty_wait_until_sent(tty, info->closing_wait);
772 }
773
774 if (info->flags & ASYNC_INITIALIZED)
775 wait_until_sent(tty, info->timeout);
776 if (tty->driver->flush_buffer)
777 tty->driver->flush_buffer(tty);
778 tty_ldisc_flush(tty);
779
780 shutdown(info);
781
782 tty->closing = 0;
783 info->tty = NULL;
784
785 if (info->blocked_open) {
786 if (info->close_delay) {
787 msleep_interruptible(jiffies_to_msecs(info->close_delay));
788 }
789 wake_up_interruptible(&info->open_wait);
790 }
791
792 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
793
794 wake_up_interruptible(&info->close_wait);
795
796 cleanup:
797 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
798 }
799
800 static void hangup(struct tty_struct *tty)
801 {
802 struct slgt_info *info = tty->driver_data;
803
804 if (sanity_check(info, tty->name, "hangup"))
805 return;
806 DBGINFO(("%s hangup\n", info->device_name));
807
808 flush_buffer(tty);
809 shutdown(info);
810
811 info->count = 0;
812 info->flags &= ~ASYNC_NORMAL_ACTIVE;
813 info->tty = NULL;
814
815 wake_up_interruptible(&info->open_wait);
816 }
817
818 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
819 {
820 struct slgt_info *info = tty->driver_data;
821 unsigned long flags;
822
823 DBGINFO(("%s set_termios\n", tty->driver->name));
824
825 change_params(info);
826
827 /* Handle transition to B0 status */
828 if (old_termios->c_cflag & CBAUD &&
829 !(tty->termios->c_cflag & CBAUD)) {
830 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
831 spin_lock_irqsave(&info->lock,flags);
832 set_signals(info);
833 spin_unlock_irqrestore(&info->lock,flags);
834 }
835
836 /* Handle transition away from B0 status */
837 if (!(old_termios->c_cflag & CBAUD) &&
838 tty->termios->c_cflag & CBAUD) {
839 info->signals |= SerialSignal_DTR;
840 if (!(tty->termios->c_cflag & CRTSCTS) ||
841 !test_bit(TTY_THROTTLED, &tty->flags)) {
842 info->signals |= SerialSignal_RTS;
843 }
844 spin_lock_irqsave(&info->lock,flags);
845 set_signals(info);
846 spin_unlock_irqrestore(&info->lock,flags);
847 }
848
849 /* Handle turning off CRTSCTS */
850 if (old_termios->c_cflag & CRTSCTS &&
851 !(tty->termios->c_cflag & CRTSCTS)) {
852 tty->hw_stopped = 0;
853 tx_release(tty);
854 }
855 }
856
857 static int write(struct tty_struct *tty,
858 const unsigned char *buf, int count)
859 {
860 int ret = 0;
861 struct slgt_info *info = tty->driver_data;
862 unsigned long flags;
863
864 if (sanity_check(info, tty->name, "write"))
865 goto cleanup;
866 DBGINFO(("%s write count=%d\n", info->device_name, count));
867
868 if (!info->tx_buf)
869 goto cleanup;
870
871 if (count > info->max_frame_size) {
872 ret = -EIO;
873 goto cleanup;
874 }
875
876 if (!count)
877 goto cleanup;
878
879 if (info->params.mode == MGSL_MODE_RAW ||
880 info->params.mode == MGSL_MODE_MONOSYNC ||
881 info->params.mode == MGSL_MODE_BISYNC) {
882 unsigned int bufs_needed = (count/DMABUFSIZE);
883 unsigned int bufs_free = free_tbuf_count(info);
884 if (count % DMABUFSIZE)
885 ++bufs_needed;
886 if (bufs_needed > bufs_free)
887 goto cleanup;
888 } else {
889 if (info->tx_active)
890 goto cleanup;
891 if (info->tx_count) {
892 /* send accumulated data from send_char() calls */
893 /* as frame and wait before accepting more data. */
894 tx_load(info, info->tx_buf, info->tx_count);
895 goto start;
896 }
897 }
898
899 ret = info->tx_count = count;
900 tx_load(info, buf, count);
901 goto start;
902
903 start:
904 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
905 spin_lock_irqsave(&info->lock,flags);
906 if (!info->tx_active)
907 tx_start(info);
908 else
909 tdma_start(info);
910 spin_unlock_irqrestore(&info->lock,flags);
911 }
912
913 cleanup:
914 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
915 return ret;
916 }
917
918 static void put_char(struct tty_struct *tty, unsigned char ch)
919 {
920 struct slgt_info *info = tty->driver_data;
921 unsigned long flags;
922
923 if (sanity_check(info, tty->name, "put_char"))
924 return;
925 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
926 if (!info->tx_buf)
927 return;
928 spin_lock_irqsave(&info->lock,flags);
929 if (!info->tx_active && (info->tx_count < info->max_frame_size))
930 info->tx_buf[info->tx_count++] = ch;
931 spin_unlock_irqrestore(&info->lock,flags);
932 }
933
934 static void send_xchar(struct tty_struct *tty, char ch)
935 {
936 struct slgt_info *info = tty->driver_data;
937 unsigned long flags;
938
939 if (sanity_check(info, tty->name, "send_xchar"))
940 return;
941 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
942 info->x_char = ch;
943 if (ch) {
944 spin_lock_irqsave(&info->lock,flags);
945 if (!info->tx_enabled)
946 tx_start(info);
947 spin_unlock_irqrestore(&info->lock,flags);
948 }
949 }
950
951 static void wait_until_sent(struct tty_struct *tty, int timeout)
952 {
953 struct slgt_info *info = tty->driver_data;
954 unsigned long orig_jiffies, char_time;
955
956 if (!info )
957 return;
958 if (sanity_check(info, tty->name, "wait_until_sent"))
959 return;
960 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
961 if (!(info->flags & ASYNC_INITIALIZED))
962 goto exit;
963
964 orig_jiffies = jiffies;
965
966 /* Set check interval to 1/5 of estimated time to
967 * send a character, and make it at least 1. The check
968 * interval should also be less than the timeout.
969 * Note: use tight timings here to satisfy the NIST-PCTS.
970 */
971
972 if (info->params.data_rate) {
973 char_time = info->timeout/(32 * 5);
974 if (!char_time)
975 char_time++;
976 } else
977 char_time = 1;
978
979 if (timeout)
980 char_time = min_t(unsigned long, char_time, timeout);
981
982 while (info->tx_active) {
983 msleep_interruptible(jiffies_to_msecs(char_time));
984 if (signal_pending(current))
985 break;
986 if (timeout && time_after(jiffies, orig_jiffies + timeout))
987 break;
988 }
989
990 exit:
991 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
992 }
993
994 static int write_room(struct tty_struct *tty)
995 {
996 struct slgt_info *info = tty->driver_data;
997 int ret;
998
999 if (sanity_check(info, tty->name, "write_room"))
1000 return 0;
1001 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1002 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
1003 return ret;
1004 }
1005
1006 static void flush_chars(struct tty_struct *tty)
1007 {
1008 struct slgt_info *info = tty->driver_data;
1009 unsigned long flags;
1010
1011 if (sanity_check(info, tty->name, "flush_chars"))
1012 return;
1013 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1014
1015 if (info->tx_count <= 0 || tty->stopped ||
1016 tty->hw_stopped || !info->tx_buf)
1017 return;
1018
1019 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1020
1021 spin_lock_irqsave(&info->lock,flags);
1022 if (!info->tx_active && info->tx_count) {
1023 tx_load(info, info->tx_buf,info->tx_count);
1024 tx_start(info);
1025 }
1026 spin_unlock_irqrestore(&info->lock,flags);
1027 }
1028
1029 static void flush_buffer(struct tty_struct *tty)
1030 {
1031 struct slgt_info *info = tty->driver_data;
1032 unsigned long flags;
1033
1034 if (sanity_check(info, tty->name, "flush_buffer"))
1035 return;
1036 DBGINFO(("%s flush_buffer\n", info->device_name));
1037
1038 spin_lock_irqsave(&info->lock,flags);
1039 if (!info->tx_active)
1040 info->tx_count = 0;
1041 spin_unlock_irqrestore(&info->lock,flags);
1042
1043 tty_wakeup(tty);
1044 }
1045
1046 /*
1047 * throttle (stop) transmitter
1048 */
1049 static void tx_hold(struct tty_struct *tty)
1050 {
1051 struct slgt_info *info = tty->driver_data;
1052 unsigned long flags;
1053
1054 if (sanity_check(info, tty->name, "tx_hold"))
1055 return;
1056 DBGINFO(("%s tx_hold\n", info->device_name));
1057 spin_lock_irqsave(&info->lock,flags);
1058 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1059 tx_stop(info);
1060 spin_unlock_irqrestore(&info->lock,flags);
1061 }
1062
1063 /*
1064 * release (start) transmitter
1065 */
1066 static void tx_release(struct tty_struct *tty)
1067 {
1068 struct slgt_info *info = tty->driver_data;
1069 unsigned long flags;
1070
1071 if (sanity_check(info, tty->name, "tx_release"))
1072 return;
1073 DBGINFO(("%s tx_release\n", info->device_name));
1074 spin_lock_irqsave(&info->lock,flags);
1075 if (!info->tx_active && info->tx_count) {
1076 tx_load(info, info->tx_buf, info->tx_count);
1077 tx_start(info);
1078 }
1079 spin_unlock_irqrestore(&info->lock,flags);
1080 }
1081
1082 /*
1083 * Service an IOCTL request
1084 *
1085 * Arguments
1086 *
1087 * tty pointer to tty instance data
1088 * file pointer to associated file object for device
1089 * cmd IOCTL command code
1090 * arg command argument/context
1091 *
1092 * Return 0 if success, otherwise error code
1093 */
1094 static int ioctl(struct tty_struct *tty, struct file *file,
1095 unsigned int cmd, unsigned long arg)
1096 {
1097 struct slgt_info *info = tty->driver_data;
1098 struct mgsl_icount cnow; /* kernel counter temps */
1099 struct serial_icounter_struct __user *p_cuser; /* user space */
1100 unsigned long flags;
1101 void __user *argp = (void __user *)arg;
1102
1103 if (sanity_check(info, tty->name, "ioctl"))
1104 return -ENODEV;
1105 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1106
1107 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1108 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1109 if (tty->flags & (1 << TTY_IO_ERROR))
1110 return -EIO;
1111 }
1112
1113 switch (cmd) {
1114 case MGSL_IOCGPARAMS:
1115 return get_params(info, argp);
1116 case MGSL_IOCSPARAMS:
1117 return set_params(info, argp);
1118 case MGSL_IOCGTXIDLE:
1119 return get_txidle(info, argp);
1120 case MGSL_IOCSTXIDLE:
1121 return set_txidle(info, (int)arg);
1122 case MGSL_IOCTXENABLE:
1123 return tx_enable(info, (int)arg);
1124 case MGSL_IOCRXENABLE:
1125 return rx_enable(info, (int)arg);
1126 case MGSL_IOCTXABORT:
1127 return tx_abort(info);
1128 case MGSL_IOCGSTATS:
1129 return get_stats(info, argp);
1130 case MGSL_IOCWAITEVENT:
1131 return wait_mgsl_event(info, argp);
1132 case TIOCMIWAIT:
1133 return modem_input_wait(info,(int)arg);
1134 case MGSL_IOCGIF:
1135 return get_interface(info, argp);
1136 case MGSL_IOCSIF:
1137 return set_interface(info,(int)arg);
1138 case MGSL_IOCSGPIO:
1139 return set_gpio(info, argp);
1140 case MGSL_IOCGGPIO:
1141 return get_gpio(info, argp);
1142 case MGSL_IOCWAITGPIO:
1143 return wait_gpio(info, argp);
1144 case TIOCGICOUNT:
1145 spin_lock_irqsave(&info->lock,flags);
1146 cnow = info->icount;
1147 spin_unlock_irqrestore(&info->lock,flags);
1148 p_cuser = argp;
1149 if (put_user(cnow.cts, &p_cuser->cts) ||
1150 put_user(cnow.dsr, &p_cuser->dsr) ||
1151 put_user(cnow.rng, &p_cuser->rng) ||
1152 put_user(cnow.dcd, &p_cuser->dcd) ||
1153 put_user(cnow.rx, &p_cuser->rx) ||
1154 put_user(cnow.tx, &p_cuser->tx) ||
1155 put_user(cnow.frame, &p_cuser->frame) ||
1156 put_user(cnow.overrun, &p_cuser->overrun) ||
1157 put_user(cnow.parity, &p_cuser->parity) ||
1158 put_user(cnow.brk, &p_cuser->brk) ||
1159 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1160 return -EFAULT;
1161 return 0;
1162 default:
1163 return -ENOIOCTLCMD;
1164 }
1165 return 0;
1166 }
1167
1168 /*
1169 * support for 32 bit ioctl calls on 64 bit systems
1170 */
1171 #ifdef CONFIG_COMPAT
1172 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1173 {
1174 struct MGSL_PARAMS32 tmp_params;
1175
1176 DBGINFO(("%s get_params32\n", info->device_name));
1177 tmp_params.mode = (compat_ulong_t)info->params.mode;
1178 tmp_params.loopback = info->params.loopback;
1179 tmp_params.flags = info->params.flags;
1180 tmp_params.encoding = info->params.encoding;
1181 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1182 tmp_params.addr_filter = info->params.addr_filter;
1183 tmp_params.crc_type = info->params.crc_type;
1184 tmp_params.preamble_length = info->params.preamble_length;
1185 tmp_params.preamble = info->params.preamble;
1186 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1187 tmp_params.data_bits = info->params.data_bits;
1188 tmp_params.stop_bits = info->params.stop_bits;
1189 tmp_params.parity = info->params.parity;
1190 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1191 return -EFAULT;
1192 return 0;
1193 }
1194
1195 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1196 {
1197 struct MGSL_PARAMS32 tmp_params;
1198
1199 DBGINFO(("%s set_params32\n", info->device_name));
1200 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1201 return -EFAULT;
1202
1203 spin_lock(&info->lock);
1204 info->params.mode = tmp_params.mode;
1205 info->params.loopback = tmp_params.loopback;
1206 info->params.flags = tmp_params.flags;
1207 info->params.encoding = tmp_params.encoding;
1208 info->params.clock_speed = tmp_params.clock_speed;
1209 info->params.addr_filter = tmp_params.addr_filter;
1210 info->params.crc_type = tmp_params.crc_type;
1211 info->params.preamble_length = tmp_params.preamble_length;
1212 info->params.preamble = tmp_params.preamble;
1213 info->params.data_rate = tmp_params.data_rate;
1214 info->params.data_bits = tmp_params.data_bits;
1215 info->params.stop_bits = tmp_params.stop_bits;
1216 info->params.parity = tmp_params.parity;
1217 spin_unlock(&info->lock);
1218
1219 change_params(info);
1220
1221 return 0;
1222 }
1223
1224 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1225 unsigned int cmd, unsigned long arg)
1226 {
1227 struct slgt_info *info = tty->driver_data;
1228 int rc = -ENOIOCTLCMD;
1229
1230 if (sanity_check(info, tty->name, "compat_ioctl"))
1231 return -ENODEV;
1232 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1233
1234 switch (cmd) {
1235
1236 case MGSL_IOCSPARAMS32:
1237 rc = set_params32(info, compat_ptr(arg));
1238 break;
1239
1240 case MGSL_IOCGPARAMS32:
1241 rc = get_params32(info, compat_ptr(arg));
1242 break;
1243
1244 case MGSL_IOCGPARAMS:
1245 case MGSL_IOCSPARAMS:
1246 case MGSL_IOCGTXIDLE:
1247 case MGSL_IOCGSTATS:
1248 case MGSL_IOCWAITEVENT:
1249 case MGSL_IOCGIF:
1250 case MGSL_IOCSGPIO:
1251 case MGSL_IOCGGPIO:
1252 case MGSL_IOCWAITGPIO:
1253 case TIOCGICOUNT:
1254 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1255 break;
1256
1257 case MGSL_IOCSTXIDLE:
1258 case MGSL_IOCTXENABLE:
1259 case MGSL_IOCRXENABLE:
1260 case MGSL_IOCTXABORT:
1261 case TIOCMIWAIT:
1262 case MGSL_IOCSIF:
1263 rc = ioctl(tty, file, cmd, arg);
1264 break;
1265 }
1266
1267 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1268 return rc;
1269 }
1270 #else
1271 #define slgt_compat_ioctl NULL
1272 #endif /* ifdef CONFIG_COMPAT */
1273
1274 /*
1275 * proc fs support
1276 */
1277 static inline int line_info(char *buf, struct slgt_info *info)
1278 {
1279 char stat_buf[30];
1280 int ret;
1281 unsigned long flags;
1282
1283 ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1284 info->device_name, info->phys_reg_addr,
1285 info->irq_level, info->max_frame_size);
1286
1287 /* output current serial signal states */
1288 spin_lock_irqsave(&info->lock,flags);
1289 get_signals(info);
1290 spin_unlock_irqrestore(&info->lock,flags);
1291
1292 stat_buf[0] = 0;
1293 stat_buf[1] = 0;
1294 if (info->signals & SerialSignal_RTS)
1295 strcat(stat_buf, "|RTS");
1296 if (info->signals & SerialSignal_CTS)
1297 strcat(stat_buf, "|CTS");
1298 if (info->signals & SerialSignal_DTR)
1299 strcat(stat_buf, "|DTR");
1300 if (info->signals & SerialSignal_DSR)
1301 strcat(stat_buf, "|DSR");
1302 if (info->signals & SerialSignal_DCD)
1303 strcat(stat_buf, "|CD");
1304 if (info->signals & SerialSignal_RI)
1305 strcat(stat_buf, "|RI");
1306
1307 if (info->params.mode != MGSL_MODE_ASYNC) {
1308 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1309 info->icount.txok, info->icount.rxok);
1310 if (info->icount.txunder)
1311 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1312 if (info->icount.txabort)
1313 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1314 if (info->icount.rxshort)
1315 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1316 if (info->icount.rxlong)
1317 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1318 if (info->icount.rxover)
1319 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1320 if (info->icount.rxcrc)
1321 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1322 } else {
1323 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1324 info->icount.tx, info->icount.rx);
1325 if (info->icount.frame)
1326 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1327 if (info->icount.parity)
1328 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1329 if (info->icount.brk)
1330 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1331 if (info->icount.overrun)
1332 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1333 }
1334
1335 /* Append serial signal status to end */
1336 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1337
1338 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1339 info->tx_active,info->bh_requested,info->bh_running,
1340 info->pending_bh);
1341
1342 return ret;
1343 }
1344
1345 /* Called to print information about devices
1346 */
1347 static int read_proc(char *page, char **start, off_t off, int count,
1348 int *eof, void *data)
1349 {
1350 int len = 0, l;
1351 off_t begin = 0;
1352 struct slgt_info *info;
1353
1354 len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1355
1356 info = slgt_device_list;
1357 while( info ) {
1358 l = line_info(page + len, info);
1359 len += l;
1360 if (len+begin > off+count)
1361 goto done;
1362 if (len+begin < off) {
1363 begin += len;
1364 len = 0;
1365 }
1366 info = info->next_device;
1367 }
1368
1369 *eof = 1;
1370 done:
1371 if (off >= len+begin)
1372 return 0;
1373 *start = page + (off-begin);
1374 return ((count < begin+len-off) ? count : begin+len-off);
1375 }
1376
1377 /*
1378 * return count of bytes in transmit buffer
1379 */
1380 static int chars_in_buffer(struct tty_struct *tty)
1381 {
1382 struct slgt_info *info = tty->driver_data;
1383 if (sanity_check(info, tty->name, "chars_in_buffer"))
1384 return 0;
1385 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1386 return info->tx_count;
1387 }
1388
1389 /*
1390 * signal remote device to throttle send data (our receive data)
1391 */
1392 static void throttle(struct tty_struct * tty)
1393 {
1394 struct slgt_info *info = tty->driver_data;
1395 unsigned long flags;
1396
1397 if (sanity_check(info, tty->name, "throttle"))
1398 return;
1399 DBGINFO(("%s throttle\n", info->device_name));
1400 if (I_IXOFF(tty))
1401 send_xchar(tty, STOP_CHAR(tty));
1402 if (tty->termios->c_cflag & CRTSCTS) {
1403 spin_lock_irqsave(&info->lock,flags);
1404 info->signals &= ~SerialSignal_RTS;
1405 set_signals(info);
1406 spin_unlock_irqrestore(&info->lock,flags);
1407 }
1408 }
1409
1410 /*
1411 * signal remote device to stop throttling send data (our receive data)
1412 */
1413 static void unthrottle(struct tty_struct * tty)
1414 {
1415 struct slgt_info *info = tty->driver_data;
1416 unsigned long flags;
1417
1418 if (sanity_check(info, tty->name, "unthrottle"))
1419 return;
1420 DBGINFO(("%s unthrottle\n", info->device_name));
1421 if (I_IXOFF(tty)) {
1422 if (info->x_char)
1423 info->x_char = 0;
1424 else
1425 send_xchar(tty, START_CHAR(tty));
1426 }
1427 if (tty->termios->c_cflag & CRTSCTS) {
1428 spin_lock_irqsave(&info->lock,flags);
1429 info->signals |= SerialSignal_RTS;
1430 set_signals(info);
1431 spin_unlock_irqrestore(&info->lock,flags);
1432 }
1433 }
1434
1435 /*
1436 * set or clear transmit break condition
1437 * break_state -1=set break condition, 0=clear
1438 */
1439 static void set_break(struct tty_struct *tty, int break_state)
1440 {
1441 struct slgt_info *info = tty->driver_data;
1442 unsigned short value;
1443 unsigned long flags;
1444
1445 if (sanity_check(info, tty->name, "set_break"))
1446 return;
1447 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1448
1449 spin_lock_irqsave(&info->lock,flags);
1450 value = rd_reg16(info, TCR);
1451 if (break_state == -1)
1452 value |= BIT6;
1453 else
1454 value &= ~BIT6;
1455 wr_reg16(info, TCR, value);
1456 spin_unlock_irqrestore(&info->lock,flags);
1457 }
1458
1459 #if SYNCLINK_GENERIC_HDLC
1460
1461 /**
1462 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1463 * set encoding and frame check sequence (FCS) options
1464 *
1465 * dev pointer to network device structure
1466 * encoding serial encoding setting
1467 * parity FCS setting
1468 *
1469 * returns 0 if success, otherwise error code
1470 */
1471 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1472 unsigned short parity)
1473 {
1474 struct slgt_info *info = dev_to_port(dev);
1475 unsigned char new_encoding;
1476 unsigned short new_crctype;
1477
1478 /* return error if TTY interface open */
1479 if (info->count)
1480 return -EBUSY;
1481
1482 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1483
1484 switch (encoding)
1485 {
1486 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1487 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1488 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1489 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1490 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1491 default: return -EINVAL;
1492 }
1493
1494 switch (parity)
1495 {
1496 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1497 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1498 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1499 default: return -EINVAL;
1500 }
1501
1502 info->params.encoding = new_encoding;
1503 info->params.crc_type = new_crctype;
1504
1505 /* if network interface up, reprogram hardware */
1506 if (info->netcount)
1507 program_hw(info);
1508
1509 return 0;
1510 }
1511
1512 /**
1513 * called by generic HDLC layer to send frame
1514 *
1515 * skb socket buffer containing HDLC frame
1516 * dev pointer to network device structure
1517 *
1518 * returns 0 if success, otherwise error code
1519 */
1520 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1521 {
1522 struct slgt_info *info = dev_to_port(dev);
1523 struct net_device_stats *stats = hdlc_stats(dev);
1524 unsigned long flags;
1525
1526 DBGINFO(("%s hdlc_xmit\n", dev->name));
1527
1528 /* stop sending until this frame completes */
1529 netif_stop_queue(dev);
1530
1531 /* copy data to device buffers */
1532 info->tx_count = skb->len;
1533 tx_load(info, skb->data, skb->len);
1534
1535 /* update network statistics */
1536 stats->tx_packets++;
1537 stats->tx_bytes += skb->len;
1538
1539 /* done with socket buffer, so free it */
1540 dev_kfree_skb(skb);
1541
1542 /* save start time for transmit timeout detection */
1543 dev->trans_start = jiffies;
1544
1545 /* start hardware transmitter if necessary */
1546 spin_lock_irqsave(&info->lock,flags);
1547 if (!info->tx_active)
1548 tx_start(info);
1549 spin_unlock_irqrestore(&info->lock,flags);
1550
1551 return 0;
1552 }
1553
1554 /**
1555 * called by network layer when interface enabled
1556 * claim resources and initialize hardware
1557 *
1558 * dev pointer to network device structure
1559 *
1560 * returns 0 if success, otherwise error code
1561 */
1562 static int hdlcdev_open(struct net_device *dev)
1563 {
1564 struct slgt_info *info = dev_to_port(dev);
1565 int rc;
1566 unsigned long flags;
1567
1568 DBGINFO(("%s hdlcdev_open\n", dev->name));
1569
1570 /* generic HDLC layer open processing */
1571 if ((rc = hdlc_open(dev)))
1572 return rc;
1573
1574 /* arbitrate between network and tty opens */
1575 spin_lock_irqsave(&info->netlock, flags);
1576 if (info->count != 0 || info->netcount != 0) {
1577 DBGINFO(("%s hdlc_open busy\n", dev->name));
1578 spin_unlock_irqrestore(&info->netlock, flags);
1579 return -EBUSY;
1580 }
1581 info->netcount=1;
1582 spin_unlock_irqrestore(&info->netlock, flags);
1583
1584 /* claim resources and init adapter */
1585 if ((rc = startup(info)) != 0) {
1586 spin_lock_irqsave(&info->netlock, flags);
1587 info->netcount=0;
1588 spin_unlock_irqrestore(&info->netlock, flags);
1589 return rc;
1590 }
1591
1592 /* assert DTR and RTS, apply hardware settings */
1593 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1594 program_hw(info);
1595
1596 /* enable network layer transmit */
1597 dev->trans_start = jiffies;
1598 netif_start_queue(dev);
1599
1600 /* inform generic HDLC layer of current DCD status */
1601 spin_lock_irqsave(&info->lock, flags);
1602 get_signals(info);
1603 spin_unlock_irqrestore(&info->lock, flags);
1604 if (info->signals & SerialSignal_DCD)
1605 netif_carrier_on(dev);
1606 else
1607 netif_carrier_off(dev);
1608 return 0;
1609 }
1610
1611 /**
1612 * called by network layer when interface is disabled
1613 * shutdown hardware and release resources
1614 *
1615 * dev pointer to network device structure
1616 *
1617 * returns 0 if success, otherwise error code
1618 */
1619 static int hdlcdev_close(struct net_device *dev)
1620 {
1621 struct slgt_info *info = dev_to_port(dev);
1622 unsigned long flags;
1623
1624 DBGINFO(("%s hdlcdev_close\n", dev->name));
1625
1626 netif_stop_queue(dev);
1627
1628 /* shutdown adapter and release resources */
1629 shutdown(info);
1630
1631 hdlc_close(dev);
1632
1633 spin_lock_irqsave(&info->netlock, flags);
1634 info->netcount=0;
1635 spin_unlock_irqrestore(&info->netlock, flags);
1636
1637 return 0;
1638 }
1639
1640 /**
1641 * called by network layer to process IOCTL call to network device
1642 *
1643 * dev pointer to network device structure
1644 * ifr pointer to network interface request structure
1645 * cmd IOCTL command code
1646 *
1647 * returns 0 if success, otherwise error code
1648 */
1649 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1650 {
1651 const size_t size = sizeof(sync_serial_settings);
1652 sync_serial_settings new_line;
1653 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1654 struct slgt_info *info = dev_to_port(dev);
1655 unsigned int flags;
1656
1657 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1658
1659 /* return error if TTY interface open */
1660 if (info->count)
1661 return -EBUSY;
1662
1663 if (cmd != SIOCWANDEV)
1664 return hdlc_ioctl(dev, ifr, cmd);
1665
1666 switch(ifr->ifr_settings.type) {
1667 case IF_GET_IFACE: /* return current sync_serial_settings */
1668
1669 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1670 if (ifr->ifr_settings.size < size) {
1671 ifr->ifr_settings.size = size; /* data size wanted */
1672 return -ENOBUFS;
1673 }
1674
1675 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1676 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1677 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1678 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1679
1680 switch (flags){
1681 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1682 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1683 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1684 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1685 default: new_line.clock_type = CLOCK_DEFAULT;
1686 }
1687
1688 new_line.clock_rate = info->params.clock_speed;
1689 new_line.loopback = info->params.loopback ? 1:0;
1690
1691 if (copy_to_user(line, &new_line, size))
1692 return -EFAULT;
1693 return 0;
1694
1695 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1696
1697 if(!capable(CAP_NET_ADMIN))
1698 return -EPERM;
1699 if (copy_from_user(&new_line, line, size))
1700 return -EFAULT;
1701
1702 switch (new_line.clock_type)
1703 {
1704 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1705 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1706 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1707 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1708 case CLOCK_DEFAULT: flags = info->params.flags &
1709 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1710 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1711 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1712 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1713 default: return -EINVAL;
1714 }
1715
1716 if (new_line.loopback != 0 && new_line.loopback != 1)
1717 return -EINVAL;
1718
1719 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1720 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1721 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1722 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1723 info->params.flags |= flags;
1724
1725 info->params.loopback = new_line.loopback;
1726
1727 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1728 info->params.clock_speed = new_line.clock_rate;
1729 else
1730 info->params.clock_speed = 0;
1731
1732 /* if network interface up, reprogram hardware */
1733 if (info->netcount)
1734 program_hw(info);
1735 return 0;
1736
1737 default:
1738 return hdlc_ioctl(dev, ifr, cmd);
1739 }
1740 }
1741
1742 /**
1743 * called by network layer when transmit timeout is detected
1744 *
1745 * dev pointer to network device structure
1746 */
1747 static void hdlcdev_tx_timeout(struct net_device *dev)
1748 {
1749 struct slgt_info *info = dev_to_port(dev);
1750 struct net_device_stats *stats = hdlc_stats(dev);
1751 unsigned long flags;
1752
1753 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1754
1755 stats->tx_errors++;
1756 stats->tx_aborted_errors++;
1757
1758 spin_lock_irqsave(&info->lock,flags);
1759 tx_stop(info);
1760 spin_unlock_irqrestore(&info->lock,flags);
1761
1762 netif_wake_queue(dev);
1763 }
1764
1765 /**
1766 * called by device driver when transmit completes
1767 * reenable network layer transmit if stopped
1768 *
1769 * info pointer to device instance information
1770 */
1771 static void hdlcdev_tx_done(struct slgt_info *info)
1772 {
1773 if (netif_queue_stopped(info->netdev))
1774 netif_wake_queue(info->netdev);
1775 }
1776
1777 /**
1778 * called by device driver when frame received
1779 * pass frame to network layer
1780 *
1781 * info pointer to device instance information
1782 * buf pointer to buffer contianing frame data
1783 * size count of data bytes in buf
1784 */
1785 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1786 {
1787 struct sk_buff *skb = dev_alloc_skb(size);
1788 struct net_device *dev = info->netdev;
1789 struct net_device_stats *stats = hdlc_stats(dev);
1790
1791 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1792
1793 if (skb == NULL) {
1794 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1795 stats->rx_dropped++;
1796 return;
1797 }
1798
1799 memcpy(skb_put(skb, size),buf,size);
1800
1801 skb->protocol = hdlc_type_trans(skb, info->netdev);
1802
1803 stats->rx_packets++;
1804 stats->rx_bytes += size;
1805
1806 netif_rx(skb);
1807
1808 info->netdev->last_rx = jiffies;
1809 }
1810
1811 /**
1812 * called by device driver when adding device instance
1813 * do generic HDLC initialization
1814 *
1815 * info pointer to device instance information
1816 *
1817 * returns 0 if success, otherwise error code
1818 */
1819 static int hdlcdev_init(struct slgt_info *info)
1820 {
1821 int rc;
1822 struct net_device *dev;
1823 hdlc_device *hdlc;
1824
1825 /* allocate and initialize network and HDLC layer objects */
1826
1827 if (!(dev = alloc_hdlcdev(info))) {
1828 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1829 return -ENOMEM;
1830 }
1831
1832 /* for network layer reporting purposes only */
1833 dev->mem_start = info->phys_reg_addr;
1834 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1835 dev->irq = info->irq_level;
1836
1837 /* network layer callbacks and settings */
1838 dev->do_ioctl = hdlcdev_ioctl;
1839 dev->open = hdlcdev_open;
1840 dev->stop = hdlcdev_close;
1841 dev->tx_timeout = hdlcdev_tx_timeout;
1842 dev->watchdog_timeo = 10*HZ;
1843 dev->tx_queue_len = 50;
1844
1845 /* generic HDLC layer callbacks and settings */
1846 hdlc = dev_to_hdlc(dev);
1847 hdlc->attach = hdlcdev_attach;
1848 hdlc->xmit = hdlcdev_xmit;
1849
1850 /* register objects with HDLC layer */
1851 if ((rc = register_hdlc_device(dev))) {
1852 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1853 free_netdev(dev);
1854 return rc;
1855 }
1856
1857 info->netdev = dev;
1858 return 0;
1859 }
1860
1861 /**
1862 * called by device driver when removing device instance
1863 * do generic HDLC cleanup
1864 *
1865 * info pointer to device instance information
1866 */
1867 static void hdlcdev_exit(struct slgt_info *info)
1868 {
1869 unregister_hdlc_device(info->netdev);
1870 free_netdev(info->netdev);
1871 info->netdev = NULL;
1872 }
1873
1874 #endif /* ifdef CONFIG_HDLC */
1875
1876 /*
1877 * get async data from rx DMA buffers
1878 */
1879 static void rx_async(struct slgt_info *info)
1880 {
1881 struct tty_struct *tty = info->tty;
1882 struct mgsl_icount *icount = &info->icount;
1883 unsigned int start, end;
1884 unsigned char *p;
1885 unsigned char status;
1886 struct slgt_desc *bufs = info->rbufs;
1887 int i, count;
1888 int chars = 0;
1889 int stat;
1890 unsigned char ch;
1891
1892 start = end = info->rbuf_current;
1893
1894 while(desc_complete(bufs[end])) {
1895 count = desc_count(bufs[end]) - info->rbuf_index;
1896 p = bufs[end].buf + info->rbuf_index;
1897
1898 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1899 DBGDATA(info, p, count, "rx");
1900
1901 for(i=0 ; i < count; i+=2, p+=2) {
1902 ch = *p;
1903 icount->rx++;
1904
1905 stat = 0;
1906
1907 if ((status = *(p+1) & (BIT1 + BIT0))) {
1908 if (status & BIT1)
1909 icount->parity++;
1910 else if (status & BIT0)
1911 icount->frame++;
1912 /* discard char if tty control flags say so */
1913 if (status & info->ignore_status_mask)
1914 continue;
1915 if (status & BIT1)
1916 stat = TTY_PARITY;
1917 else if (status & BIT0)
1918 stat = TTY_FRAME;
1919 }
1920 if (tty) {
1921 tty_insert_flip_char(tty, ch, stat);
1922 chars++;
1923 }
1924 }
1925
1926 if (i < count) {
1927 /* receive buffer not completed */
1928 info->rbuf_index += i;
1929 mod_timer(&info->rx_timer, jiffies + 1);
1930 break;
1931 }
1932
1933 info->rbuf_index = 0;
1934 free_rbufs(info, end, end);
1935
1936 if (++end == info->rbuf_count)
1937 end = 0;
1938
1939 /* if entire list searched then no frame available */
1940 if (end == start)
1941 break;
1942 }
1943
1944 if (tty && chars)
1945 tty_flip_buffer_push(tty);
1946 }
1947
1948 /*
1949 * return next bottom half action to perform
1950 */
1951 static int bh_action(struct slgt_info *info)
1952 {
1953 unsigned long flags;
1954 int rc;
1955
1956 spin_lock_irqsave(&info->lock,flags);
1957
1958 if (info->pending_bh & BH_RECEIVE) {
1959 info->pending_bh &= ~BH_RECEIVE;
1960 rc = BH_RECEIVE;
1961 } else if (info->pending_bh & BH_TRANSMIT) {
1962 info->pending_bh &= ~BH_TRANSMIT;
1963 rc = BH_TRANSMIT;
1964 } else if (info->pending_bh & BH_STATUS) {
1965 info->pending_bh &= ~BH_STATUS;
1966 rc = BH_STATUS;
1967 } else {
1968 /* Mark BH routine as complete */
1969 info->bh_running = 0;
1970 info->bh_requested = 0;
1971 rc = 0;
1972 }
1973
1974 spin_unlock_irqrestore(&info->lock,flags);
1975
1976 return rc;
1977 }
1978
1979 /*
1980 * perform bottom half processing
1981 */
1982 static void bh_handler(struct work_struct *work)
1983 {
1984 struct slgt_info *info = container_of(work, struct slgt_info, task);
1985 int action;
1986
1987 if (!info)
1988 return;
1989 info->bh_running = 1;
1990
1991 while((action = bh_action(info))) {
1992 switch (action) {
1993 case BH_RECEIVE:
1994 DBGBH(("%s bh receive\n", info->device_name));
1995 switch(info->params.mode) {
1996 case MGSL_MODE_ASYNC:
1997 rx_async(info);
1998 break;
1999 case MGSL_MODE_HDLC:
2000 while(rx_get_frame(info));
2001 break;
2002 case MGSL_MODE_RAW:
2003 case MGSL_MODE_MONOSYNC:
2004 case MGSL_MODE_BISYNC:
2005 while(rx_get_buf(info));
2006 break;
2007 }
2008 /* restart receiver if rx DMA buffers exhausted */
2009 if (info->rx_restart)
2010 rx_start(info);
2011 break;
2012 case BH_TRANSMIT:
2013 bh_transmit(info);
2014 break;
2015 case BH_STATUS:
2016 DBGBH(("%s bh status\n", info->device_name));
2017 info->ri_chkcount = 0;
2018 info->dsr_chkcount = 0;
2019 info->dcd_chkcount = 0;
2020 info->cts_chkcount = 0;
2021 break;
2022 default:
2023 DBGBH(("%s unknown action\n", info->device_name));
2024 break;
2025 }
2026 }
2027 DBGBH(("%s bh_handler exit\n", info->device_name));
2028 }
2029
2030 static void bh_transmit(struct slgt_info *info)
2031 {
2032 struct tty_struct *tty = info->tty;
2033
2034 DBGBH(("%s bh_transmit\n", info->device_name));
2035 if (tty)
2036 tty_wakeup(tty);
2037 }
2038
2039 static void dsr_change(struct slgt_info *info)
2040 {
2041 get_signals(info);
2042 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2043 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2044 slgt_irq_off(info, IRQ_DSR);
2045 return;
2046 }
2047 info->icount.dsr++;
2048 if (info->signals & SerialSignal_DSR)
2049 info->input_signal_events.dsr_up++;
2050 else
2051 info->input_signal_events.dsr_down++;
2052 wake_up_interruptible(&info->status_event_wait_q);
2053 wake_up_interruptible(&info->event_wait_q);
2054 info->pending_bh |= BH_STATUS;
2055 }
2056
2057 static void cts_change(struct slgt_info *info)
2058 {
2059 get_signals(info);
2060 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2061 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2062 slgt_irq_off(info, IRQ_CTS);
2063 return;
2064 }
2065 info->icount.cts++;
2066 if (info->signals & SerialSignal_CTS)
2067 info->input_signal_events.cts_up++;
2068 else
2069 info->input_signal_events.cts_down++;
2070 wake_up_interruptible(&info->status_event_wait_q);
2071 wake_up_interruptible(&info->event_wait_q);
2072 info->pending_bh |= BH_STATUS;
2073
2074 if (info->flags & ASYNC_CTS_FLOW) {
2075 if (info->tty) {
2076 if (info->tty->hw_stopped) {
2077 if (info->signals & SerialSignal_CTS) {
2078 info->tty->hw_stopped = 0;
2079 info->pending_bh |= BH_TRANSMIT;
2080 return;
2081 }
2082 } else {
2083 if (!(info->signals & SerialSignal_CTS))
2084 info->tty->hw_stopped = 1;
2085 }
2086 }
2087 }
2088 }
2089
2090 static void dcd_change(struct slgt_info *info)
2091 {
2092 get_signals(info);
2093 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2094 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2095 slgt_irq_off(info, IRQ_DCD);
2096 return;
2097 }
2098 info->icount.dcd++;
2099 if (info->signals & SerialSignal_DCD) {
2100 info->input_signal_events.dcd_up++;
2101 } else {
2102 info->input_signal_events.dcd_down++;
2103 }
2104 #if SYNCLINK_GENERIC_HDLC
2105 if (info->netcount) {
2106 if (info->signals & SerialSignal_DCD)
2107 netif_carrier_on(info->netdev);
2108 else
2109 netif_carrier_off(info->netdev);
2110 }
2111 #endif
2112 wake_up_interruptible(&info->status_event_wait_q);
2113 wake_up_interruptible(&info->event_wait_q);
2114 info->pending_bh |= BH_STATUS;
2115
2116 if (info->flags & ASYNC_CHECK_CD) {
2117 if (info->signals & SerialSignal_DCD)
2118 wake_up_interruptible(&info->open_wait);
2119 else {
2120 if (info->tty)
2121 tty_hangup(info->tty);
2122 }
2123 }
2124 }
2125
2126 static void ri_change(struct slgt_info *info)
2127 {
2128 get_signals(info);
2129 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2130 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2131 slgt_irq_off(info, IRQ_RI);
2132 return;
2133 }
2134 info->icount.dcd++;
2135 if (info->signals & SerialSignal_RI) {
2136 info->input_signal_events.ri_up++;
2137 } else {
2138 info->input_signal_events.ri_down++;
2139 }
2140 wake_up_interruptible(&info->status_event_wait_q);
2141 wake_up_interruptible(&info->event_wait_q);
2142 info->pending_bh |= BH_STATUS;
2143 }
2144
2145 static void isr_serial(struct slgt_info *info)
2146 {
2147 unsigned short status = rd_reg16(info, SSR);
2148
2149 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2150
2151 wr_reg16(info, SSR, status); /* clear pending */
2152
2153 info->irq_occurred = 1;
2154
2155 if (info->params.mode == MGSL_MODE_ASYNC) {
2156 if (status & IRQ_TXIDLE) {
2157 if (info->tx_count)
2158 isr_txeom(info, status);
2159 }
2160 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2161 info->icount.brk++;
2162 /* process break detection if tty control allows */
2163 if (info->tty) {
2164 if (!(status & info->ignore_status_mask)) {
2165 if (info->read_status_mask & MASK_BREAK) {
2166 tty_insert_flip_char(info->tty, 0, TTY_BREAK);
2167 if (info->flags & ASYNC_SAK)
2168 do_SAK(info->tty);
2169 }
2170 }
2171 }
2172 }
2173 } else {
2174 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2175 isr_txeom(info, status);
2176
2177 if (status & IRQ_RXIDLE) {
2178 if (status & RXIDLE)
2179 info->icount.rxidle++;
2180 else
2181 info->icount.exithunt++;
2182 wake_up_interruptible(&info->event_wait_q);
2183 }
2184
2185 if (status & IRQ_RXOVER)
2186 rx_start(info);
2187 }
2188
2189 if (status & IRQ_DSR)
2190 dsr_change(info);
2191 if (status & IRQ_CTS)
2192 cts_change(info);
2193 if (status & IRQ_DCD)
2194 dcd_change(info);
2195 if (status & IRQ_RI)
2196 ri_change(info);
2197 }
2198
2199 static void isr_rdma(struct slgt_info *info)
2200 {
2201 unsigned int status = rd_reg32(info, RDCSR);
2202
2203 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2204
2205 /* RDCSR (rx DMA control/status)
2206 *
2207 * 31..07 reserved
2208 * 06 save status byte to DMA buffer
2209 * 05 error
2210 * 04 eol (end of list)
2211 * 03 eob (end of buffer)
2212 * 02 IRQ enable
2213 * 01 reset
2214 * 00 enable
2215 */
2216 wr_reg32(info, RDCSR, status); /* clear pending */
2217
2218 if (status & (BIT5 + BIT4)) {
2219 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2220 info->rx_restart = 1;
2221 }
2222 info->pending_bh |= BH_RECEIVE;
2223 }
2224
2225 static void isr_tdma(struct slgt_info *info)
2226 {
2227 unsigned int status = rd_reg32(info, TDCSR);
2228
2229 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2230
2231 /* TDCSR (tx DMA control/status)
2232 *
2233 * 31..06 reserved
2234 * 05 error
2235 * 04 eol (end of list)
2236 * 03 eob (end of buffer)
2237 * 02 IRQ enable
2238 * 01 reset
2239 * 00 enable
2240 */
2241 wr_reg32(info, TDCSR, status); /* clear pending */
2242
2243 if (status & (BIT5 + BIT4 + BIT3)) {
2244 // another transmit buffer has completed
2245 // run bottom half to get more send data from user
2246 info->pending_bh |= BH_TRANSMIT;
2247 }
2248 }
2249
2250 static void isr_txeom(struct slgt_info *info, unsigned short status)
2251 {
2252 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2253
2254 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2255 tdma_reset(info);
2256 reset_tbufs(info);
2257 if (status & IRQ_TXUNDER) {
2258 unsigned short val = rd_reg16(info, TCR);
2259 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2260 wr_reg16(info, TCR, val); /* clear reset bit */
2261 }
2262
2263 if (info->tx_active) {
2264 if (info->params.mode != MGSL_MODE_ASYNC) {
2265 if (status & IRQ_TXUNDER)
2266 info->icount.txunder++;
2267 else if (status & IRQ_TXIDLE)
2268 info->icount.txok++;
2269 }
2270
2271 info->tx_active = 0;
2272 info->tx_count = 0;
2273
2274 del_timer(&info->tx_timer);
2275
2276 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2277 info->signals &= ~SerialSignal_RTS;
2278 info->drop_rts_on_tx_done = 0;
2279 set_signals(info);
2280 }
2281
2282 #if SYNCLINK_GENERIC_HDLC
2283 if (info->netcount)
2284 hdlcdev_tx_done(info);
2285 else
2286 #endif
2287 {
2288 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2289 tx_stop(info);
2290 return;
2291 }
2292 info->pending_bh |= BH_TRANSMIT;
2293 }
2294 }
2295 }
2296
2297 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2298 {
2299 struct cond_wait *w, *prev;
2300
2301 /* wake processes waiting for specific transitions */
2302 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2303 if (w->data & changed) {
2304 w->data = state;
2305 wake_up_interruptible(&w->q);
2306 if (prev != NULL)
2307 prev->next = w->next;
2308 else
2309 info->gpio_wait_q = w->next;
2310 } else
2311 prev = w;
2312 }
2313 }
2314
2315 /* interrupt service routine
2316 *
2317 * irq interrupt number
2318 * dev_id device ID supplied during interrupt registration
2319 */
2320 static irqreturn_t slgt_interrupt(int irq, void *dev_id)
2321 {
2322 struct slgt_info *info;
2323 unsigned int gsr;
2324 unsigned int i;
2325
2326 DBGISR(("slgt_interrupt irq=%d entry\n", irq));
2327
2328 info = dev_id;
2329 if (!info)
2330 return IRQ_NONE;
2331
2332 spin_lock(&info->lock);
2333
2334 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2335 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2336 info->irq_occurred = 1;
2337 for(i=0; i < info->port_count ; i++) {
2338 if (info->port_array[i] == NULL)
2339 continue;
2340 if (gsr & (BIT8 << i))
2341 isr_serial(info->port_array[i]);
2342 if (gsr & (BIT16 << (i*2)))
2343 isr_rdma(info->port_array[i]);
2344 if (gsr & (BIT17 << (i*2)))
2345 isr_tdma(info->port_array[i]);
2346 }
2347 }
2348
2349 if (info->gpio_present) {
2350 unsigned int state;
2351 unsigned int changed;
2352 while ((changed = rd_reg32(info, IOSR)) != 0) {
2353 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2354 /* read latched state of GPIO signals */
2355 state = rd_reg32(info, IOVR);
2356 /* clear pending GPIO interrupt bits */
2357 wr_reg32(info, IOSR, changed);
2358 for (i=0 ; i < info->port_count ; i++) {
2359 if (info->port_array[i] != NULL)
2360 isr_gpio(info->port_array[i], changed, state);
2361 }
2362 }
2363 }
2364
2365 for(i=0; i < info->port_count ; i++) {
2366 struct slgt_info *port = info->port_array[i];
2367
2368 if (port && (port->count || port->netcount) &&
2369 port->pending_bh && !port->bh_running &&
2370 !port->bh_requested) {
2371 DBGISR(("%s bh queued\n", port->device_name));
2372 schedule_work(&port->task);
2373 port->bh_requested = 1;
2374 }
2375 }
2376
2377 spin_unlock(&info->lock);
2378
2379 DBGISR(("slgt_interrupt irq=%d exit\n", irq));
2380 return IRQ_HANDLED;
2381 }
2382
2383 static int startup(struct slgt_info *info)
2384 {
2385 DBGINFO(("%s startup\n", info->device_name));
2386
2387 if (info->flags & ASYNC_INITIALIZED)
2388 return 0;
2389
2390 if (!info->tx_buf) {
2391 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2392 if (!info->tx_buf) {
2393 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2394 return -ENOMEM;
2395 }
2396 }
2397
2398 info->pending_bh = 0;
2399
2400 memset(&info->icount, 0, sizeof(info->icount));
2401
2402 /* program hardware for current parameters */
2403 change_params(info);
2404
2405 if (info->tty)
2406 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2407
2408 info->flags |= ASYNC_INITIALIZED;
2409
2410 return 0;
2411 }
2412
2413 /*
2414 * called by close() and hangup() to shutdown hardware
2415 */
2416 static void shutdown(struct slgt_info *info)
2417 {
2418 unsigned long flags;
2419
2420 if (!(info->flags & ASYNC_INITIALIZED))
2421 return;
2422
2423 DBGINFO(("%s shutdown\n", info->device_name));
2424
2425 /* clear status wait queue because status changes */
2426 /* can't happen after shutting down the hardware */
2427 wake_up_interruptible(&info->status_event_wait_q);
2428 wake_up_interruptible(&info->event_wait_q);
2429
2430 del_timer_sync(&info->tx_timer);
2431 del_timer_sync(&info->rx_timer);
2432
2433 kfree(info->tx_buf);
2434 info->tx_buf = NULL;
2435
2436 spin_lock_irqsave(&info->lock,flags);
2437
2438 tx_stop(info);
2439 rx_stop(info);
2440
2441 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2442
2443 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2444 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2445 set_signals(info);
2446 }
2447
2448 flush_cond_wait(&info->gpio_wait_q);
2449
2450 spin_unlock_irqrestore(&info->lock,flags);
2451
2452 if (info->tty)
2453 set_bit(TTY_IO_ERROR, &info->tty->flags);
2454
2455 info->flags &= ~ASYNC_INITIALIZED;
2456 }
2457
2458 static void program_hw(struct slgt_info *info)
2459 {
2460 unsigned long flags;
2461
2462 spin_lock_irqsave(&info->lock,flags);
2463
2464 rx_stop(info);
2465 tx_stop(info);
2466
2467 if (info->params.mode != MGSL_MODE_ASYNC ||
2468 info->netcount)
2469 sync_mode(info);
2470 else
2471 async_mode(info);
2472
2473 set_signals(info);
2474
2475 info->dcd_chkcount = 0;
2476 info->cts_chkcount = 0;
2477 info->ri_chkcount = 0;
2478 info->dsr_chkcount = 0;
2479
2480 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2481 get_signals(info);
2482
2483 if (info->netcount ||
2484 (info->tty && info->tty->termios->c_cflag & CREAD))
2485 rx_start(info);
2486
2487 spin_unlock_irqrestore(&info->lock,flags);
2488 }
2489
2490 /*
2491 * reconfigure adapter based on new parameters
2492 */
2493 static void change_params(struct slgt_info *info)
2494 {
2495 unsigned cflag;
2496 int bits_per_char;
2497
2498 if (!info->tty || !info->tty->termios)
2499 return;
2500 DBGINFO(("%s change_params\n", info->device_name));
2501
2502 cflag = info->tty->termios->c_cflag;
2503
2504 /* if B0 rate (hangup) specified then negate DTR and RTS */
2505 /* otherwise assert DTR and RTS */
2506 if (cflag & CBAUD)
2507 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2508 else
2509 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2510
2511 /* byte size and parity */
2512
2513 switch (cflag & CSIZE) {
2514 case CS5: info->params.data_bits = 5; break;
2515 case CS6: info->params.data_bits = 6; break;
2516 case CS7: info->params.data_bits = 7; break;
2517 case CS8: info->params.data_bits = 8; break;
2518 default: info->params.data_bits = 7; break;
2519 }
2520
2521 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2522
2523 if (cflag & PARENB)
2524 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2525 else
2526 info->params.parity = ASYNC_PARITY_NONE;
2527
2528 /* calculate number of jiffies to transmit a full
2529 * FIFO (32 bytes) at specified data rate
2530 */
2531 bits_per_char = info->params.data_bits +
2532 info->params.stop_bits + 1;
2533
2534 info->params.data_rate = tty_get_baud_rate(info->tty);
2535
2536 if (info->params.data_rate) {
2537 info->timeout = (32*HZ*bits_per_char) /
2538 info->params.data_rate;
2539 }
2540 info->timeout += HZ/50; /* Add .02 seconds of slop */
2541
2542 if (cflag & CRTSCTS)
2543 info->flags |= ASYNC_CTS_FLOW;
2544 else
2545 info->flags &= ~ASYNC_CTS_FLOW;
2546
2547 if (cflag & CLOCAL)
2548 info->flags &= ~ASYNC_CHECK_CD;
2549 else
2550 info->flags |= ASYNC_CHECK_CD;
2551
2552 /* process tty input control flags */
2553
2554 info->read_status_mask = IRQ_RXOVER;
2555 if (I_INPCK(info->tty))
2556 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2557 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2558 info->read_status_mask |= MASK_BREAK;
2559 if (I_IGNPAR(info->tty))
2560 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2561 if (I_IGNBRK(info->tty)) {
2562 info->ignore_status_mask |= MASK_BREAK;
2563 /* If ignoring parity and break indicators, ignore
2564 * overruns too. (For real raw support).
2565 */
2566 if (I_IGNPAR(info->tty))
2567 info->ignore_status_mask |= MASK_OVERRUN;
2568 }
2569
2570 program_hw(info);
2571 }
2572
2573 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2574 {
2575 DBGINFO(("%s get_stats\n", info->device_name));
2576 if (!user_icount) {
2577 memset(&info->icount, 0, sizeof(info->icount));
2578 } else {
2579 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2580 return -EFAULT;
2581 }
2582 return 0;
2583 }
2584
2585 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2586 {
2587 DBGINFO(("%s get_params\n", info->device_name));
2588 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2589 return -EFAULT;
2590 return 0;
2591 }
2592
2593 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2594 {
2595 unsigned long flags;
2596 MGSL_PARAMS tmp_params;
2597
2598 DBGINFO(("%s set_params\n", info->device_name));
2599 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2600 return -EFAULT;
2601
2602 spin_lock_irqsave(&info->lock, flags);
2603 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2604 spin_unlock_irqrestore(&info->lock, flags);
2605
2606 change_params(info);
2607
2608 return 0;
2609 }
2610
2611 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2612 {
2613 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2614 if (put_user(info->idle_mode, idle_mode))
2615 return -EFAULT;
2616 return 0;
2617 }
2618
2619 static int set_txidle(struct slgt_info *info, int idle_mode)
2620 {
2621 unsigned long flags;
2622 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2623 spin_lock_irqsave(&info->lock,flags);
2624 info->idle_mode = idle_mode;
2625 if (info->params.mode != MGSL_MODE_ASYNC)
2626 tx_set_idle(info);
2627 spin_unlock_irqrestore(&info->lock,flags);
2628 return 0;
2629 }
2630
2631 static int tx_enable(struct slgt_info *info, int enable)
2632 {
2633 unsigned long flags;
2634 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2635 spin_lock_irqsave(&info->lock,flags);
2636 if (enable) {
2637 if (!info->tx_enabled)
2638 tx_start(info);
2639 } else {
2640 if (info->tx_enabled)
2641 tx_stop(info);
2642 }
2643 spin_unlock_irqrestore(&info->lock,flags);
2644 return 0;
2645 }
2646
2647 /*
2648 * abort transmit HDLC frame
2649 */
2650 static int tx_abort(struct slgt_info *info)
2651 {
2652 unsigned long flags;
2653 DBGINFO(("%s tx_abort\n", info->device_name));
2654 spin_lock_irqsave(&info->lock,flags);
2655 tdma_reset(info);
2656 spin_unlock_irqrestore(&info->lock,flags);
2657 return 0;
2658 }
2659
2660 static int rx_enable(struct slgt_info *info, int enable)
2661 {
2662 unsigned long flags;
2663 DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2664 spin_lock_irqsave(&info->lock,flags);
2665 if (enable) {
2666 if (!info->rx_enabled)
2667 rx_start(info);
2668 else if (enable == 2) {
2669 /* force hunt mode (write 1 to RCR[3]) */
2670 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2671 }
2672 } else {
2673 if (info->rx_enabled)
2674 rx_stop(info);
2675 }
2676 spin_unlock_irqrestore(&info->lock,flags);
2677 return 0;
2678 }
2679
2680 /*
2681 * wait for specified event to occur
2682 */
2683 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2684 {
2685 unsigned long flags;
2686 int s;
2687 int rc=0;
2688 struct mgsl_icount cprev, cnow;
2689 int events;
2690 int mask;
2691 struct _input_signal_events oldsigs, newsigs;
2692 DECLARE_WAITQUEUE(wait, current);
2693
2694 if (get_user(mask, mask_ptr))
2695 return -EFAULT;
2696
2697 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2698
2699 spin_lock_irqsave(&info->lock,flags);
2700
2701 /* return immediately if state matches requested events */
2702 get_signals(info);
2703 s = info->signals;
2704
2705 events = mask &
2706 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2707 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2708 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2709 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2710 if (events) {
2711 spin_unlock_irqrestore(&info->lock,flags);
2712 goto exit;
2713 }
2714
2715 /* save current irq counts */
2716 cprev = info->icount;
2717 oldsigs = info->input_signal_events;
2718
2719 /* enable hunt and idle irqs if needed */
2720 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2721 unsigned short val = rd_reg16(info, SCR);
2722 if (!(val & IRQ_RXIDLE))
2723 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2724 }
2725
2726 set_current_state(TASK_INTERRUPTIBLE);
2727 add_wait_queue(&info->event_wait_q, &wait);
2728
2729 spin_unlock_irqrestore(&info->lock,flags);
2730
2731 for(;;) {
2732 schedule();
2733 if (signal_pending(current)) {
2734 rc = -ERESTARTSYS;
2735 break;
2736 }
2737
2738 /* get current irq counts */
2739 spin_lock_irqsave(&info->lock,flags);
2740 cnow = info->icount;
2741 newsigs = info->input_signal_events;
2742 set_current_state(TASK_INTERRUPTIBLE);
2743 spin_unlock_irqrestore(&info->lock,flags);
2744
2745 /* if no change, wait aborted for some reason */
2746 if (newsigs.dsr_up == oldsigs.dsr_up &&
2747 newsigs.dsr_down == oldsigs.dsr_down &&
2748 newsigs.dcd_up == oldsigs.dcd_up &&
2749 newsigs.dcd_down == oldsigs.dcd_down &&
2750 newsigs.cts_up == oldsigs.cts_up &&
2751 newsigs.cts_down == oldsigs.cts_down &&
2752 newsigs.ri_up == oldsigs.ri_up &&
2753 newsigs.ri_down == oldsigs.ri_down &&
2754 cnow.exithunt == cprev.exithunt &&
2755 cnow.rxidle == cprev.rxidle) {
2756 rc = -EIO;
2757 break;
2758 }
2759
2760 events = mask &
2761 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2762 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2763 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2764 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2765 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2766 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2767 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2768 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2769 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2770 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2771 if (events)
2772 break;
2773
2774 cprev = cnow;
2775 oldsigs = newsigs;
2776 }
2777
2778 remove_wait_queue(&info->event_wait_q, &wait);
2779 set_current_state(TASK_RUNNING);
2780
2781
2782 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2783 spin_lock_irqsave(&info->lock,flags);
2784 if (!waitqueue_active(&info->event_wait_q)) {
2785 /* disable enable exit hunt mode/idle rcvd IRQs */
2786 wr_reg16(info, SCR,
2787 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2788 }
2789 spin_unlock_irqrestore(&info->lock,flags);
2790 }
2791 exit:
2792 if (rc == 0)
2793 rc = put_user(events, mask_ptr);
2794 return rc;
2795 }
2796
2797 static int get_interface(struct slgt_info *info, int __user *if_mode)
2798 {
2799 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2800 if (put_user(info->if_mode, if_mode))
2801 return -EFAULT;
2802 return 0;
2803 }
2804
2805 static int set_interface(struct slgt_info *info, int if_mode)
2806 {
2807 unsigned long flags;
2808 unsigned short val;
2809
2810 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2811 spin_lock_irqsave(&info->lock,flags);
2812 info->if_mode = if_mode;
2813
2814 msc_set_vcr(info);
2815
2816 /* TCR (tx control) 07 1=RTS driver control */
2817 val = rd_reg16(info, TCR);
2818 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2819 val |= BIT7;
2820 else
2821 val &= ~BIT7;
2822 wr_reg16(info, TCR, val);
2823
2824 spin_unlock_irqrestore(&info->lock,flags);
2825 return 0;
2826 }
2827
2828 /*
2829 * set general purpose IO pin state and direction
2830 *
2831 * user_gpio fields:
2832 * state each bit indicates a pin state
2833 * smask set bit indicates pin state to set
2834 * dir each bit indicates a pin direction (0=input, 1=output)
2835 * dmask set bit indicates pin direction to set
2836 */
2837 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2838 {
2839 unsigned long flags;
2840 struct gpio_desc gpio;
2841 __u32 data;
2842
2843 if (!info->gpio_present)
2844 return -EINVAL;
2845 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2846 return -EFAULT;
2847 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2848 info->device_name, gpio.state, gpio.smask,
2849 gpio.dir, gpio.dmask));
2850
2851 spin_lock_irqsave(&info->lock,flags);
2852 if (gpio.dmask) {
2853 data = rd_reg32(info, IODR);
2854 data |= gpio.dmask & gpio.dir;
2855 data &= ~(gpio.dmask & ~gpio.dir);
2856 wr_reg32(info, IODR, data);
2857 }
2858 if (gpio.smask) {
2859 data = rd_reg32(info, IOVR);
2860 data |= gpio.smask & gpio.state;
2861 data &= ~(gpio.smask & ~gpio.state);
2862 wr_reg32(info, IOVR, data);
2863 }
2864 spin_unlock_irqrestore(&info->lock,flags);
2865
2866 return 0;
2867 }
2868
2869 /*
2870 * get general purpose IO pin state and direction
2871 */
2872 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2873 {
2874 struct gpio_desc gpio;
2875 if (!info->gpio_present)
2876 return -EINVAL;
2877 gpio.state = rd_reg32(info, IOVR);
2878 gpio.smask = 0xffffffff;
2879 gpio.dir = rd_reg32(info, IODR);
2880 gpio.dmask = 0xffffffff;
2881 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2882 return -EFAULT;
2883 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2884 info->device_name, gpio.state, gpio.dir));
2885 return 0;
2886 }
2887
2888 /*
2889 * conditional wait facility
2890 */
2891 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2892 {
2893 init_waitqueue_head(&w->q);
2894 init_waitqueue_entry(&w->wait, current);
2895 w->data = data;
2896 }
2897
2898 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2899 {
2900 set_current_state(TASK_INTERRUPTIBLE);
2901 add_wait_queue(&w->q, &w->wait);
2902 w->next = *head;
2903 *head = w;
2904 }
2905
2906 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2907 {
2908 struct cond_wait *w, *prev;
2909 remove_wait_queue(&cw->q, &cw->wait);
2910 set_current_state(TASK_RUNNING);
2911 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2912 if (w == cw) {
2913 if (prev != NULL)
2914 prev->next = w->next;
2915 else
2916 *head = w->next;
2917 break;
2918 }
2919 }
2920 }
2921
2922 static void flush_cond_wait(struct cond_wait **head)
2923 {
2924 while (*head != NULL) {
2925 wake_up_interruptible(&(*head)->q);
2926 *head = (*head)->next;
2927 }
2928 }
2929
2930 /*
2931 * wait for general purpose I/O pin(s) to enter specified state
2932 *
2933 * user_gpio fields:
2934 * state - bit indicates target pin state
2935 * smask - set bit indicates watched pin
2936 *
2937 * The wait ends when at least one watched pin enters the specified
2938 * state. When 0 (no error) is returned, user_gpio->state is set to the
2939 * state of all GPIO pins when the wait ends.
2940 *
2941 * Note: Each pin may be a dedicated input, dedicated output, or
2942 * configurable input/output. The number and configuration of pins
2943 * varies with the specific adapter model. Only input pins (dedicated
2944 * or configured) can be monitored with this function.
2945 */
2946 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2947 {
2948 unsigned long flags;
2949 int rc = 0;
2950 struct gpio_desc gpio;
2951 struct cond_wait wait;
2952 u32 state;
2953
2954 if (!info->gpio_present)
2955 return -EINVAL;
2956 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2957 return -EFAULT;
2958 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2959 info->device_name, gpio.state, gpio.smask));
2960 /* ignore output pins identified by set IODR bit */
2961 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2962 return -EINVAL;
2963 init_cond_wait(&wait, gpio.smask);
2964
2965 spin_lock_irqsave(&info->lock, flags);
2966 /* enable interrupts for watched pins */
2967 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2968 /* get current pin states */
2969 state = rd_reg32(info, IOVR);
2970
2971 if (gpio.smask & ~(state ^ gpio.state)) {
2972 /* already in target state */
2973 gpio.state = state;
2974 } else {
2975 /* wait for target state */
2976 add_cond_wait(&info->gpio_wait_q, &wait);
2977 spin_unlock_irqrestore(&info->lock, flags);
2978 schedule();
2979 if (signal_pending(current))
2980 rc = -ERESTARTSYS;
2981 else
2982 gpio.state = wait.data;
2983 spin_lock_irqsave(&info->lock, flags);
2984 remove_cond_wait(&info->gpio_wait_q, &wait);
2985 }
2986
2987 /* disable all GPIO interrupts if no waiting processes */
2988 if (info->gpio_wait_q == NULL)
2989 wr_reg32(info, IOER, 0);
2990 spin_unlock_irqrestore(&info->lock,flags);
2991
2992 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2993 rc = -EFAULT;
2994 return rc;
2995 }
2996
2997 static int modem_input_wait(struct slgt_info *info,int arg)
2998 {
2999 unsigned long flags;
3000 int rc;
3001 struct mgsl_icount cprev, cnow;
3002 DECLARE_WAITQUEUE(wait, current);
3003
3004 /* save current irq counts */
3005 spin_lock_irqsave(&info->lock,flags);
3006 cprev = info->icount;
3007 add_wait_queue(&info->status_event_wait_q, &wait);
3008 set_current_state(TASK_INTERRUPTIBLE);
3009 spin_unlock_irqrestore(&info->lock,flags);
3010
3011 for(;;) {
3012 schedule();
3013 if (signal_pending(current)) {
3014 rc = -ERESTARTSYS;
3015 break;
3016 }
3017
3018 /* get new irq counts */
3019 spin_lock_irqsave(&info->lock,flags);
3020 cnow = info->icount;
3021 set_current_state(TASK_INTERRUPTIBLE);
3022 spin_unlock_irqrestore(&info->lock,flags);
3023
3024 /* if no change, wait aborted for some reason */
3025 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3026 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3027 rc = -EIO;
3028 break;
3029 }
3030
3031 /* check for change in caller specified modem input */
3032 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3033 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3034 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3035 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3036 rc = 0;
3037 break;
3038 }
3039
3040 cprev = cnow;
3041 }
3042 remove_wait_queue(&info->status_event_wait_q, &wait);
3043 set_current_state(TASK_RUNNING);
3044 return rc;
3045 }
3046
3047 /*
3048 * return state of serial control and status signals
3049 */
3050 static int tiocmget(struct tty_struct *tty, struct file *file)
3051 {
3052 struct slgt_info *info = tty->driver_data;
3053 unsigned int result;
3054 unsigned long flags;
3055
3056 spin_lock_irqsave(&info->lock,flags);
3057 get_signals(info);
3058 spin_unlock_irqrestore(&info->lock,flags);
3059
3060 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3061 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3062 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3063 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3064 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3065 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3066
3067 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3068 return result;
3069 }
3070
3071 /*
3072 * set modem control signals (DTR/RTS)
3073 *
3074 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3075 * TIOCMSET = set/clear signal values
3076 * value bit mask for command
3077 */
3078 static int tiocmset(struct tty_struct *tty, struct file *file,
3079 unsigned int set, unsigned int clear)
3080 {
3081 struct slgt_info *info = tty->driver_data;
3082 unsigned long flags;
3083
3084 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3085
3086 if (set & TIOCM_RTS)
3087 info->signals |= SerialSignal_RTS;
3088 if (set & TIOCM_DTR)
3089 info->signals |= SerialSignal_DTR;
3090 if (clear & TIOCM_RTS)
3091 info->signals &= ~SerialSignal_RTS;
3092 if (clear & TIOCM_DTR)
3093 info->signals &= ~SerialSignal_DTR;
3094
3095 spin_lock_irqsave(&info->lock,flags);
3096 set_signals(info);
3097 spin_unlock_irqrestore(&info->lock,flags);
3098 return 0;
3099 }
3100
3101 /*
3102 * block current process until the device is ready to open
3103 */
3104 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3105 struct slgt_info *info)
3106 {
3107 DECLARE_WAITQUEUE(wait, current);
3108 int retval;
3109 int do_clocal = 0, extra_count = 0;
3110 unsigned long flags;
3111
3112 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3113
3114 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3115 /* nonblock mode is set or port is not enabled */
3116 info->flags |= ASYNC_NORMAL_ACTIVE;
3117 return 0;
3118 }
3119
3120 if (tty->termios->c_cflag & CLOCAL)
3121 do_clocal = 1;
3122
3123 /* Wait for carrier detect and the line to become
3124 * free (i.e., not in use by the callout). While we are in
3125 * this loop, info->count is dropped by one, so that
3126 * close() knows when to free things. We restore it upon
3127 * exit, either normal or abnormal.
3128 */
3129
3130 retval = 0;
3131 add_wait_queue(&info->open_wait, &wait);
3132
3133 spin_lock_irqsave(&info->lock, flags);
3134 if (!tty_hung_up_p(filp)) {
3135 extra_count = 1;
3136 info->count--;
3137 }
3138 spin_unlock_irqrestore(&info->lock, flags);
3139 info->blocked_open++;
3140
3141 while (1) {
3142 if ((tty->termios->c_cflag & CBAUD)) {
3143 spin_lock_irqsave(&info->lock,flags);
3144 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3145 set_signals(info);
3146 spin_unlock_irqrestore(&info->lock,flags);
3147 }
3148
3149 set_current_state(TASK_INTERRUPTIBLE);
3150
3151 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3152 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3153 -EAGAIN : -ERESTARTSYS;
3154 break;
3155 }
3156
3157 spin_lock_irqsave(&info->lock,flags);
3158 get_signals(info);
3159 spin_unlock_irqrestore(&info->lock,flags);
3160
3161 if (!(info->flags & ASYNC_CLOSING) &&
3162 (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3163 break;
3164 }
3165
3166 if (signal_pending(current)) {
3167 retval = -ERESTARTSYS;
3168 break;
3169 }
3170
3171 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3172 schedule();
3173 }
3174
3175 set_current_state(TASK_RUNNING);
3176 remove_wait_queue(&info->open_wait, &wait);
3177
3178 if (extra_count)
3179 info->count++;
3180 info->blocked_open--;
3181
3182 if (!retval)
3183 info->flags |= ASYNC_NORMAL_ACTIVE;
3184
3185 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3186 return retval;
3187 }
3188
3189 static int alloc_tmp_rbuf(struct slgt_info *info)
3190 {
3191 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3192 if (info->tmp_rbuf == NULL)
3193 return -ENOMEM;
3194 return 0;
3195 }
3196
3197 static void free_tmp_rbuf(struct slgt_info *info)
3198 {
3199 kfree(info->tmp_rbuf);
3200 info->tmp_rbuf = NULL;
3201 }
3202
3203 /*
3204 * allocate DMA descriptor lists.
3205 */
3206 static int alloc_desc(struct slgt_info *info)
3207 {
3208 unsigned int i;
3209 unsigned int pbufs;
3210
3211 /* allocate memory to hold descriptor lists */
3212 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3213 if (info->bufs == NULL)
3214 return -ENOMEM;
3215
3216 memset(info->bufs, 0, DESC_LIST_SIZE);
3217
3218 info->rbufs = (struct slgt_desc*)info->bufs;
3219 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3220
3221 pbufs = (unsigned int)info->bufs_dma_addr;
3222
3223 /*
3224 * Build circular lists of descriptors
3225 */
3226
3227 for (i=0; i < info->rbuf_count; i++) {
3228 /* physical address of this descriptor */
3229 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3230
3231 /* physical address of next descriptor */
3232 if (i == info->rbuf_count - 1)
3233 info->rbufs[i].next = cpu_to_le32(pbufs);
3234 else
3235 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3236 set_desc_count(info->rbufs[i], DMABUFSIZE);
3237 }
3238
3239 for (i=0; i < info->tbuf_count; i++) {
3240 /* physical address of this descriptor */
3241 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3242
3243 /* physical address of next descriptor */
3244 if (i == info->tbuf_count - 1)
3245 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3246 else
3247 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3248 }
3249
3250 return 0;
3251 }
3252
3253 static void free_desc(struct slgt_info *info)
3254 {
3255 if (info->bufs != NULL) {
3256 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3257 info->bufs = NULL;
3258 info->rbufs = NULL;
3259 info->tbufs = NULL;
3260 }
3261 }
3262
3263 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3264 {
3265 int i;
3266 for (i=0; i < count; i++) {
3267 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3268 return -ENOMEM;
3269 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3270 }
3271 return 0;
3272 }
3273
3274 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3275 {
3276 int i;
3277 for (i=0; i < count; i++) {
3278 if (bufs[i].buf == NULL)
3279 continue;
3280 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3281 bufs[i].buf = NULL;
3282 }
3283 }
3284
3285 static int alloc_dma_bufs(struct slgt_info *info)
3286 {
3287 info->rbuf_count = 32;
3288 info->tbuf_count = 32;
3289
3290 if (alloc_desc(info) < 0 ||
3291 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3292 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3293 alloc_tmp_rbuf(info) < 0) {
3294 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3295 return -ENOMEM;
3296 }
3297 reset_rbufs(info);
3298 return 0;
3299 }
3300
3301 static void free_dma_bufs(struct slgt_info *info)
3302 {
3303 if (info->bufs) {
3304 free_bufs(info, info->rbufs, info->rbuf_count);
3305 free_bufs(info, info->tbufs, info->tbuf_count);
3306 free_desc(info);
3307 }
3308 free_tmp_rbuf(info);
3309 }
3310
3311 static int claim_resources(struct slgt_info *info)
3312 {
3313 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3314 DBGERR(("%s reg addr conflict, addr=%08X\n",
3315 info->device_name, info->phys_reg_addr));
3316 info->init_error = DiagStatus_AddressConflict;
3317 goto errout;
3318 }
3319 else
3320 info->reg_addr_requested = 1;
3321
3322 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3323 if (!info->reg_addr) {
3324 DBGERR(("%s cant map device registers, addr=%08X\n",
3325 info->device_name, info->phys_reg_addr));
3326 info->init_error = DiagStatus_CantAssignPciResources;
3327 goto errout;
3328 }
3329 return 0;
3330
3331 errout:
3332 release_resources(info);
3333 return -ENODEV;
3334 }
3335
3336 static void release_resources(struct slgt_info *info)
3337 {
3338 if (info->irq_requested) {
3339 free_irq(info->irq_level, info);
3340 info->irq_requested = 0;
3341 }
3342
3343 if (info->reg_addr_requested) {
3344 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3345 info->reg_addr_requested = 0;
3346 }
3347
3348 if (info->reg_addr) {
3349 iounmap(info->reg_addr);
3350 info->reg_addr = NULL;
3351 }
3352 }
3353
3354 /* Add the specified device instance data structure to the
3355 * global linked list of devices and increment the device count.
3356 */
3357 static void add_device(struct slgt_info *info)
3358 {
3359 char *devstr;
3360
3361 info->next_device = NULL;
3362 info->line = slgt_device_count;
3363 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3364
3365 if (info->line < MAX_DEVICES) {
3366 if (maxframe[info->line])
3367 info->max_frame_size = maxframe[info->line];
3368 info->dosyncppp = dosyncppp[info->line];
3369 }
3370
3371 slgt_device_count++;
3372
3373 if (!slgt_device_list)
3374 slgt_device_list = info;
3375 else {
3376 struct slgt_info *current_dev = slgt_device_list;
3377 while(current_dev->next_device)
3378 current_dev = current_dev->next_device;
3379 current_dev->next_device = info;
3380 }
3381
3382 if (info->max_frame_size < 4096)
3383 info->max_frame_size = 4096;
3384 else if (info->max_frame_size > 65535)
3385 info->max_frame_size = 65535;
3386
3387 switch(info->pdev->device) {
3388 case SYNCLINK_GT_DEVICE_ID:
3389 devstr = "GT";
3390 break;
3391 case SYNCLINK_GT2_DEVICE_ID:
3392 devstr = "GT2";
3393 break;
3394 case SYNCLINK_GT4_DEVICE_ID:
3395 devstr = "GT4";
3396 break;
3397 case SYNCLINK_AC_DEVICE_ID:
3398 devstr = "AC";
3399 info->params.mode = MGSL_MODE_ASYNC;
3400 break;
3401 default:
3402 devstr = "(unknown model)";
3403 }
3404 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3405 devstr, info->device_name, info->phys_reg_addr,
3406 info->irq_level, info->max_frame_size);
3407
3408 #if SYNCLINK_GENERIC_HDLC
3409 hdlcdev_init(info);
3410 #endif
3411 }
3412
3413 /*
3414 * allocate device instance structure, return NULL on failure
3415 */
3416 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3417 {
3418 struct slgt_info *info;
3419
3420 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3421
3422 if (!info) {
3423 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3424 driver_name, adapter_num, port_num));
3425 } else {
3426 info->magic = MGSL_MAGIC;
3427 INIT_WORK(&info->task, bh_handler);
3428 info->max_frame_size = 4096;
3429 info->raw_rx_size = DMABUFSIZE;
3430 info->close_delay = 5*HZ/10;
3431 info->closing_wait = 30*HZ;
3432 init_waitqueue_head(&info->open_wait);
3433 init_waitqueue_head(&info->close_wait);
3434 init_waitqueue_head(&info->status_event_wait_q);
3435 init_waitqueue_head(&info->event_wait_q);
3436 spin_lock_init(&info->netlock);
3437 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3438 info->idle_mode = HDLC_TXIDLE_FLAGS;
3439 info->adapter_num = adapter_num;
3440 info->port_num = port_num;
3441
3442 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3443 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3444
3445 /* Copy configuration info to device instance data */
3446 info->pdev = pdev;
3447 info->irq_level = pdev->irq;
3448 info->phys_reg_addr = pci_resource_start(pdev,0);
3449
3450 info->bus_type = MGSL_BUS_TYPE_PCI;
3451 info->irq_flags = IRQF_SHARED;
3452
3453 info->init_error = -1; /* assume error, set to 0 on successful init */
3454 }
3455
3456 return info;
3457 }
3458
3459 static void device_init(int adapter_num, struct pci_dev *pdev)
3460 {
3461 struct slgt_info *port_array[SLGT_MAX_PORTS];
3462 int i;
3463 int port_count = 1;
3464
3465 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3466 port_count = 2;
3467 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3468 port_count = 4;
3469
3470 /* allocate device instances for all ports */
3471 for (i=0; i < port_count; ++i) {
3472 port_array[i] = alloc_dev(adapter_num, i, pdev);
3473 if (port_array[i] == NULL) {
3474 for (--i; i >= 0; --i)
3475 kfree(port_array[i]);
3476 return;
3477 }
3478 }
3479
3480 /* give copy of port_array to all ports and add to device list */
3481 for (i=0; i < port_count; ++i) {
3482 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3483 add_device(port_array[i]);
3484 port_array[i]->port_count = port_count;
3485 spin_lock_init(&port_array[i]->lock);
3486 }
3487
3488 /* Allocate and claim adapter resources */
3489 if (!claim_resources(port_array[0])) {
3490
3491 alloc_dma_bufs(port_array[0]);
3492
3493 /* copy resource information from first port to others */
3494 for (i = 1; i < port_count; ++i) {
3495 port_array[i]->lock = port_array[0]->lock;
3496 port_array[i]->irq_level = port_array[0]->irq_level;
3497 port_array[i]->reg_addr = port_array[0]->reg_addr;
3498 alloc_dma_bufs(port_array[i]);
3499 }
3500
3501 if (request_irq(port_array[0]->irq_level,
3502 slgt_interrupt,
3503 port_array[0]->irq_flags,
3504 port_array[0]->device_name,
3505 port_array[0]) < 0) {
3506 DBGERR(("%s request_irq failed IRQ=%d\n",
3507 port_array[0]->device_name,
3508 port_array[0]->irq_level));
3509 } else {
3510 port_array[0]->irq_requested = 1;
3511 adapter_test(port_array[0]);
3512 for (i=1 ; i < port_count ; i++) {
3513 port_array[i]->init_error = port_array[0]->init_error;
3514 port_array[i]->gpio_present = port_array[0]->gpio_present;
3515 }
3516 }
3517 }
3518
3519 for (i=0; i < port_count; ++i)
3520 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3521 }
3522
3523 static int __devinit init_one(struct pci_dev *dev,
3524 const struct pci_device_id *ent)
3525 {
3526 if (pci_enable_device(dev)) {
3527 printk("error enabling pci device %p\n", dev);
3528 return -EIO;
3529 }
3530 pci_set_master(dev);
3531 device_init(slgt_device_count, dev);
3532 return 0;
3533 }
3534
3535 static void __devexit remove_one(struct pci_dev *dev)
3536 {
3537 }
3538
3539 static const struct tty_operations ops = {
3540 .open = open,
3541 .close = close,
3542 .write = write,
3543 .put_char = put_char,
3544 .flush_chars = flush_chars,
3545 .write_room = write_room,
3546 .chars_in_buffer = chars_in_buffer,
3547 .flush_buffer = flush_buffer,
3548 .ioctl = ioctl,
3549 .compat_ioctl = slgt_compat_ioctl,
3550 .throttle = throttle,
3551 .unthrottle = unthrottle,
3552 .send_xchar = send_xchar,
3553 .break_ctl = set_break,
3554 .wait_until_sent = wait_until_sent,
3555 .read_proc = read_proc,
3556 .set_termios = set_termios,
3557 .stop = tx_hold,
3558 .start = tx_release,
3559 .hangup = hangup,
3560 .tiocmget = tiocmget,
3561 .tiocmset = tiocmset,
3562 };
3563
3564 static void slgt_cleanup(void)
3565 {
3566 int rc;
3567 struct slgt_info *info;
3568 struct slgt_info *tmp;
3569
3570 printk("unload %s %s\n", driver_name, driver_version);
3571
3572 if (serial_driver) {
3573 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3574 tty_unregister_device(serial_driver, info->line);
3575 if ((rc = tty_unregister_driver(serial_driver)))
3576 DBGERR(("tty_unregister_driver error=%d\n", rc));
3577 put_tty_driver(serial_driver);
3578 }
3579
3580 /* reset devices */
3581 info = slgt_device_list;
3582 while(info) {
3583 reset_port(info);
3584 info = info->next_device;
3585 }
3586
3587 /* release devices */
3588 info = slgt_device_list;
3589 while(info) {
3590 #if SYNCLINK_GENERIC_HDLC
3591 hdlcdev_exit(info);
3592 #endif
3593 free_dma_bufs(info);
3594 free_tmp_rbuf(info);
3595 if (info->port_num == 0)
3596 release_resources(info);
3597 tmp = info;
3598 info = info->next_device;
3599 kfree(tmp);
3600 }
3601
3602 if (pci_registered)
3603 pci_unregister_driver(&pci_driver);
3604 }
3605
3606 /*
3607 * Driver initialization entry point.
3608 */
3609 static int __init slgt_init(void)
3610 {
3611 int rc;
3612
3613 printk("%s %s\n", driver_name, driver_version);
3614
3615 serial_driver = alloc_tty_driver(MAX_DEVICES);
3616 if (!serial_driver) {
3617 printk("%s can't allocate tty driver\n", driver_name);
3618 return -ENOMEM;
3619 }
3620
3621 /* Initialize the tty_driver structure */
3622
3623 serial_driver->owner = THIS_MODULE;
3624 serial_driver->driver_name = tty_driver_name;
3625 serial_driver->name = tty_dev_prefix;
3626 serial_driver->major = ttymajor;
3627 serial_driver->minor_start = 64;
3628 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3629 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3630 serial_driver->init_termios = tty_std_termios;
3631 serial_driver->init_termios.c_cflag =
3632 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3633 serial_driver->init_termios.c_ispeed = 9600;
3634 serial_driver->init_termios.c_ospeed = 9600;
3635 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3636 tty_set_operations(serial_driver, &ops);
3637 if ((rc = tty_register_driver(serial_driver)) < 0) {
3638 DBGERR(("%s can't register serial driver\n", driver_name));
3639 put_tty_driver(serial_driver);
3640 serial_driver = NULL;
3641 goto error;
3642 }
3643
3644 printk("%s %s, tty major#%d\n",
3645 driver_name, driver_version,
3646 serial_driver->major);
3647
3648 slgt_device_count = 0;
3649 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3650 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3651 goto error;
3652 }
3653 pci_registered = 1;
3654
3655 if (!slgt_device_list)
3656 printk("%s no devices found\n",driver_name);
3657
3658 return 0;
3659
3660 error:
3661 slgt_cleanup();
3662 return rc;
3663 }
3664
3665 static void __exit slgt_exit(void)
3666 {
3667 slgt_cleanup();
3668 }
3669
3670 module_init(slgt_init);
3671 module_exit(slgt_exit);
3672
3673 /*
3674 * register access routines
3675 */
3676
3677 #define CALC_REGADDR() \
3678 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3679 if (addr >= 0x80) \
3680 reg_addr += (info->port_num) * 32;
3681
3682 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3683 {
3684 CALC_REGADDR();
3685 return readb((void __iomem *)reg_addr);
3686 }
3687
3688 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3689 {
3690 CALC_REGADDR();
3691 writeb(value, (void __iomem *)reg_addr);
3692 }
3693
3694 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3695 {
3696 CALC_REGADDR();
3697 return readw((void __iomem *)reg_addr);
3698 }
3699
3700 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3701 {
3702 CALC_REGADDR();
3703 writew(value, (void __iomem *)reg_addr);
3704 }
3705
3706 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3707 {
3708 CALC_REGADDR();
3709 return readl((void __iomem *)reg_addr);
3710 }
3711
3712 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3713 {
3714 CALC_REGADDR();
3715 writel(value, (void __iomem *)reg_addr);
3716 }
3717
3718 static void rdma_reset(struct slgt_info *info)
3719 {
3720 unsigned int i;
3721
3722 /* set reset bit */
3723 wr_reg32(info, RDCSR, BIT1);
3724
3725 /* wait for enable bit cleared */
3726 for(i=0 ; i < 1000 ; i++)
3727 if (!(rd_reg32(info, RDCSR) & BIT0))
3728 break;
3729 }
3730
3731 static void tdma_reset(struct slgt_info *info)
3732 {
3733 unsigned int i;
3734
3735 /* set reset bit */
3736 wr_reg32(info, TDCSR, BIT1);
3737
3738 /* wait for enable bit cleared */
3739 for(i=0 ; i < 1000 ; i++)
3740 if (!(rd_reg32(info, TDCSR) & BIT0))
3741 break;
3742 }
3743
3744 /*
3745 * enable internal loopback
3746 * TxCLK and RxCLK are generated from BRG
3747 * and TxD is looped back to RxD internally.
3748 */
3749 static void enable_loopback(struct slgt_info *info)
3750 {
3751 /* SCR (serial control) BIT2=looopback enable */
3752 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3753
3754 if (info->params.mode != MGSL_MODE_ASYNC) {
3755 /* CCR (clock control)
3756 * 07..05 tx clock source (010 = BRG)
3757 * 04..02 rx clock source (010 = BRG)
3758 * 01 auxclk enable (0 = disable)
3759 * 00 BRG enable (1 = enable)
3760 *
3761 * 0100 1001
3762 */
3763 wr_reg8(info, CCR, 0x49);
3764
3765 /* set speed if available, otherwise use default */
3766 if (info->params.clock_speed)
3767 set_rate(info, info->params.clock_speed);
3768 else
3769 set_rate(info, 3686400);
3770 }
3771 }
3772
3773 /*
3774 * set baud rate generator to specified rate
3775 */
3776 static void set_rate(struct slgt_info *info, u32 rate)
3777 {
3778 unsigned int div;
3779 static unsigned int osc = 14745600;
3780
3781 /* div = osc/rate - 1
3782 *
3783 * Round div up if osc/rate is not integer to
3784 * force to next slowest rate.
3785 */
3786
3787 if (rate) {
3788 div = osc/rate;
3789 if (!(osc % rate) && div)
3790 div--;
3791 wr_reg16(info, BDR, (unsigned short)div);
3792 }
3793 }
3794
3795 static void rx_stop(struct slgt_info *info)
3796 {
3797 unsigned short val;
3798
3799 /* disable and reset receiver */
3800 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3801 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3802 wr_reg16(info, RCR, val); /* clear reset bit */
3803
3804 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3805
3806 /* clear pending rx interrupts */
3807 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3808
3809 rdma_reset(info);
3810
3811 info->rx_enabled = 0;
3812 info->rx_restart = 0;
3813 }
3814
3815 static void rx_start(struct slgt_info *info)
3816 {
3817 unsigned short val;
3818
3819 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3820
3821 /* clear pending rx overrun IRQ */
3822 wr_reg16(info, SSR, IRQ_RXOVER);
3823
3824 /* reset and disable receiver */
3825 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3826 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3827 wr_reg16(info, RCR, val); /* clear reset bit */
3828
3829 rdma_reset(info);
3830 reset_rbufs(info);
3831
3832 /* set 1st descriptor address */
3833 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3834
3835 if (info->params.mode != MGSL_MODE_ASYNC) {
3836 /* enable rx DMA and DMA interrupt */
3837 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3838 } else {
3839 /* enable saving of rx status, rx DMA and DMA interrupt */
3840 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3841 }
3842
3843 slgt_irq_on(info, IRQ_RXOVER);
3844
3845 /* enable receiver */
3846 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3847
3848 info->rx_restart = 0;
3849 info->rx_enabled = 1;
3850 }
3851
3852 static void tx_start(struct slgt_info *info)
3853 {
3854 if (!info->tx_enabled) {
3855 wr_reg16(info, TCR,
3856 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3857 info->tx_enabled = TRUE;
3858 }
3859
3860 if (info->tx_count) {
3861 info->drop_rts_on_tx_done = 0;
3862
3863 if (info->params.mode != MGSL_MODE_ASYNC) {
3864 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3865 get_signals(info);
3866 if (!(info->signals & SerialSignal_RTS)) {
3867 info->signals |= SerialSignal_RTS;
3868 set_signals(info);
3869 info->drop_rts_on_tx_done = 1;
3870 }
3871 }
3872
3873 slgt_irq_off(info, IRQ_TXDATA);
3874 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3875 /* clear tx idle and underrun status bits */
3876 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3877 if (info->params.mode == MGSL_MODE_HDLC)
3878 mod_timer(&info->tx_timer, jiffies +
3879 msecs_to_jiffies(5000));
3880 } else {
3881 slgt_irq_off(info, IRQ_TXDATA);
3882 slgt_irq_on(info, IRQ_TXIDLE);
3883 /* clear tx idle status bit */
3884 wr_reg16(info, SSR, IRQ_TXIDLE);
3885 }
3886 tdma_start(info);
3887 info->tx_active = 1;
3888 }
3889 }
3890
3891 /*
3892 * start transmit DMA if inactive and there are unsent buffers
3893 */
3894 static void tdma_start(struct slgt_info *info)
3895 {
3896 unsigned int i;
3897
3898 if (rd_reg32(info, TDCSR) & BIT0)
3899 return;
3900
3901 /* transmit DMA inactive, check for unsent buffers */
3902 i = info->tbuf_start;
3903 while (!desc_count(info->tbufs[i])) {
3904 if (++i == info->tbuf_count)
3905 i = 0;
3906 if (i == info->tbuf_current)
3907 return;
3908 }
3909 info->tbuf_start = i;
3910
3911 /* there are unsent buffers, start transmit DMA */
3912
3913 /* reset needed if previous error condition */
3914 tdma_reset(info);
3915
3916 /* set 1st descriptor address */
3917 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3918 switch(info->params.mode) {
3919 case MGSL_MODE_RAW:
3920 case MGSL_MODE_MONOSYNC:
3921 case MGSL_MODE_BISYNC:
3922 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3923 break;
3924 default:
3925 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3926 }
3927 }
3928
3929 static void tx_stop(struct slgt_info *info)
3930 {
3931 unsigned short val;
3932
3933 del_timer(&info->tx_timer);
3934
3935 tdma_reset(info);
3936
3937 /* reset and disable transmitter */
3938 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3939 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3940
3941 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3942
3943 /* clear tx idle and underrun status bit */
3944 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3945
3946 reset_tbufs(info);
3947
3948 info->tx_enabled = 0;
3949 info->tx_active = 0;
3950 }
3951
3952 static void reset_port(struct slgt_info *info)
3953 {
3954 if (!info->reg_addr)
3955 return;
3956
3957 tx_stop(info);
3958 rx_stop(info);
3959
3960 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3961 set_signals(info);
3962
3963 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3964 }
3965
3966 static void reset_adapter(struct slgt_info *info)
3967 {
3968 int i;
3969 for (i=0; i < info->port_count; ++i) {
3970 if (info->port_array[i])
3971 reset_port(info->port_array[i]);
3972 }
3973 }
3974
3975 static void async_mode(struct slgt_info *info)
3976 {
3977 unsigned short val;
3978
3979 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3980 tx_stop(info);
3981 rx_stop(info);
3982
3983 /* TCR (tx control)
3984 *
3985 * 15..13 mode, 010=async
3986 * 12..10 encoding, 000=NRZ
3987 * 09 parity enable
3988 * 08 1=odd parity, 0=even parity
3989 * 07 1=RTS driver control
3990 * 06 1=break enable
3991 * 05..04 character length
3992 * 00=5 bits
3993 * 01=6 bits
3994 * 10=7 bits
3995 * 11=8 bits
3996 * 03 0=1 stop bit, 1=2 stop bits
3997 * 02 reset
3998 * 01 enable
3999 * 00 auto-CTS enable
4000 */
4001 val = 0x4000;
4002
4003 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4004 val |= BIT7;
4005
4006 if (info->params.parity != ASYNC_PARITY_NONE) {
4007 val |= BIT9;
4008 if (info->params.parity == ASYNC_PARITY_ODD)
4009 val |= BIT8;
4010 }
4011
4012 switch (info->params.data_bits)
4013 {
4014 case 6: val |= BIT4; break;
4015 case 7: val |= BIT5; break;
4016 case 8: val |= BIT5 + BIT4; break;
4017 }
4018
4019 if (info->params.stop_bits != 1)
4020 val |= BIT3;
4021
4022 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4023 val |= BIT0;
4024
4025 wr_reg16(info, TCR, val);
4026
4027 /* RCR (rx control)
4028 *
4029 * 15..13 mode, 010=async
4030 * 12..10 encoding, 000=NRZ
4031 * 09 parity enable
4032 * 08 1=odd parity, 0=even parity
4033 * 07..06 reserved, must be 0
4034 * 05..04 character length
4035 * 00=5 bits
4036 * 01=6 bits
4037 * 10=7 bits
4038 * 11=8 bits
4039 * 03 reserved, must be zero
4040 * 02 reset
4041 * 01 enable
4042 * 00 auto-DCD enable
4043 */
4044 val = 0x4000;
4045
4046 if (info->params.parity != ASYNC_PARITY_NONE) {
4047 val |= BIT9;
4048 if (info->params.parity == ASYNC_PARITY_ODD)
4049 val |= BIT8;
4050 }
4051
4052 switch (info->params.data_bits)
4053 {
4054 case 6: val |= BIT4; break;
4055 case 7: val |= BIT5; break;
4056 case 8: val |= BIT5 + BIT4; break;
4057 }
4058
4059 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4060 val |= BIT0;
4061
4062 wr_reg16(info, RCR, val);
4063
4064 /* CCR (clock control)
4065 *
4066 * 07..05 011 = tx clock source is BRG/16
4067 * 04..02 010 = rx clock source is BRG
4068 * 01 0 = auxclk disabled
4069 * 00 1 = BRG enabled
4070 *
4071 * 0110 1001
4072 */
4073 wr_reg8(info, CCR, 0x69);
4074
4075 msc_set_vcr(info);
4076
4077 /* SCR (serial control)
4078 *
4079 * 15 1=tx req on FIFO half empty
4080 * 14 1=rx req on FIFO half full
4081 * 13 tx data IRQ enable
4082 * 12 tx idle IRQ enable
4083 * 11 rx break on IRQ enable
4084 * 10 rx data IRQ enable
4085 * 09 rx break off IRQ enable
4086 * 08 overrun IRQ enable
4087 * 07 DSR IRQ enable
4088 * 06 CTS IRQ enable
4089 * 05 DCD IRQ enable
4090 * 04 RI IRQ enable
4091 * 03 reserved, must be zero
4092 * 02 1=txd->rxd internal loopback enable
4093 * 01 reserved, must be zero
4094 * 00 1=master IRQ enable
4095 */
4096 val = BIT15 + BIT14 + BIT0;
4097 wr_reg16(info, SCR, val);
4098
4099 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4100
4101 set_rate(info, info->params.data_rate * 16);
4102
4103 if (info->params.loopback)
4104 enable_loopback(info);
4105 }
4106
4107 static void sync_mode(struct slgt_info *info)
4108 {
4109 unsigned short val;
4110
4111 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4112 tx_stop(info);
4113 rx_stop(info);
4114
4115 /* TCR (tx control)
4116 *
4117 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4118 * 12..10 encoding
4119 * 09 CRC enable
4120 * 08 CRC32
4121 * 07 1=RTS driver control
4122 * 06 preamble enable
4123 * 05..04 preamble length
4124 * 03 share open/close flag
4125 * 02 reset
4126 * 01 enable
4127 * 00 auto-CTS enable
4128 */
4129 val = 0;
4130
4131 switch(info->params.mode) {
4132 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4133 case MGSL_MODE_BISYNC: val |= BIT15; break;
4134 case MGSL_MODE_RAW: val |= BIT13; break;
4135 }
4136 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4137 val |= BIT7;
4138
4139 switch(info->params.encoding)
4140 {
4141 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4142 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4143 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4144 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4145 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4146 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4147 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4148 }
4149
4150 switch (info->params.crc_type & HDLC_CRC_MASK)
4151 {
4152 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4153 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4154 }
4155
4156 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4157 val |= BIT6;
4158
4159 switch (info->params.preamble_length)
4160 {
4161 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4162 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4163 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4164 }
4165
4166 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4167 val |= BIT0;
4168
4169 wr_reg16(info, TCR, val);
4170
4171 /* TPR (transmit preamble) */
4172
4173 switch (info->params.preamble)
4174 {
4175 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4176 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4177 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4178 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4179 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4180 default: val = 0x7e; break;
4181 }
4182 wr_reg8(info, TPR, (unsigned char)val);
4183
4184 /* RCR (rx control)
4185 *
4186 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4187 * 12..10 encoding
4188 * 09 CRC enable
4189 * 08 CRC32
4190 * 07..03 reserved, must be 0
4191 * 02 reset
4192 * 01 enable
4193 * 00 auto-DCD enable
4194 */
4195 val = 0;
4196
4197 switch(info->params.mode) {
4198 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4199 case MGSL_MODE_BISYNC: val |= BIT15; break;
4200 case MGSL_MODE_RAW: val |= BIT13; break;
4201 }
4202
4203 switch(info->params.encoding)
4204 {
4205 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4206 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4207 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4208 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4209 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4210 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4211 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4212 }
4213
4214 switch (info->params.crc_type & HDLC_CRC_MASK)
4215 {
4216 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4217 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4218 }
4219
4220 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4221 val |= BIT0;
4222
4223 wr_reg16(info, RCR, val);
4224
4225 /* CCR (clock control)
4226 *
4227 * 07..05 tx clock source
4228 * 04..02 rx clock source
4229 * 01 auxclk enable
4230 * 00 BRG enable
4231 */
4232 val = 0;
4233
4234 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4235 {
4236 // when RxC source is DPLL, BRG generates 16X DPLL
4237 // reference clock, so take TxC from BRG/16 to get
4238 // transmit clock at actual data rate
4239 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4240 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4241 else
4242 val |= BIT6; /* 010, txclk = BRG */
4243 }
4244 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4245 val |= BIT7; /* 100, txclk = DPLL Input */
4246 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4247 val |= BIT5; /* 001, txclk = RXC Input */
4248
4249 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4250 val |= BIT3; /* 010, rxclk = BRG */
4251 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4252 val |= BIT4; /* 100, rxclk = DPLL */
4253 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4254 val |= BIT2; /* 001, rxclk = TXC Input */
4255
4256 if (info->params.clock_speed)
4257 val |= BIT1 + BIT0;
4258
4259 wr_reg8(info, CCR, (unsigned char)val);
4260
4261 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4262 {
4263 // program DPLL mode
4264 switch(info->params.encoding)
4265 {
4266 case HDLC_ENCODING_BIPHASE_MARK:
4267 case HDLC_ENCODING_BIPHASE_SPACE:
4268 val = BIT7; break;
4269 case HDLC_ENCODING_BIPHASE_LEVEL:
4270 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4271 val = BIT7 + BIT6; break;
4272 default: val = BIT6; // NRZ encodings
4273 }
4274 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4275
4276 // DPLL requires a 16X reference clock from BRG
4277 set_rate(info, info->params.clock_speed * 16);
4278 }
4279 else
4280 set_rate(info, info->params.clock_speed);
4281
4282 tx_set_idle(info);
4283
4284 msc_set_vcr(info);
4285
4286 /* SCR (serial control)
4287 *
4288 * 15 1=tx req on FIFO half empty
4289 * 14 1=rx req on FIFO half full
4290 * 13 tx data IRQ enable
4291 * 12 tx idle IRQ enable
4292 * 11 underrun IRQ enable
4293 * 10 rx data IRQ enable
4294 * 09 rx idle IRQ enable
4295 * 08 overrun IRQ enable
4296 * 07 DSR IRQ enable
4297 * 06 CTS IRQ enable
4298 * 05 DCD IRQ enable
4299 * 04 RI IRQ enable
4300 * 03 reserved, must be zero
4301 * 02 1=txd->rxd internal loopback enable
4302 * 01 reserved, must be zero
4303 * 00 1=master IRQ enable
4304 */
4305 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4306
4307 if (info->params.loopback)
4308 enable_loopback(info);
4309 }
4310
4311 /*
4312 * set transmit idle mode
4313 */
4314 static void tx_set_idle(struct slgt_info *info)
4315 {
4316 unsigned char val;
4317 unsigned short tcr;
4318
4319 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4320 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4321 */
4322 tcr = rd_reg16(info, TCR);
4323 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4324 /* disable preamble, set idle size to 16 bits */
4325 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4326 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4327 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4328 } else if (!(tcr & BIT6)) {
4329 /* preamble is disabled, set idle size to 8 bits */
4330 tcr &= ~(BIT5 + BIT4);
4331 }
4332 wr_reg16(info, TCR, tcr);
4333
4334 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4335 /* LSB of custom tx idle specified in tx idle register */
4336 val = (unsigned char)(info->idle_mode & 0xff);
4337 } else {
4338 /* standard 8 bit idle patterns */
4339 switch(info->idle_mode)
4340 {
4341 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4342 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4343 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4344 case HDLC_TXIDLE_ZEROS:
4345 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4346 default: val = 0xff;
4347 }
4348 }
4349
4350 wr_reg8(info, TIR, val);
4351 }
4352
4353 /*
4354 * get state of V24 status (input) signals
4355 */
4356 static void get_signals(struct slgt_info *info)
4357 {
4358 unsigned short status = rd_reg16(info, SSR);
4359
4360 /* clear all serial signals except DTR and RTS */
4361 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4362
4363 if (status & BIT3)
4364 info->signals |= SerialSignal_DSR;
4365 if (status & BIT2)
4366 info->signals |= SerialSignal_CTS;
4367 if (status & BIT1)
4368 info->signals |= SerialSignal_DCD;
4369 if (status & BIT0)
4370 info->signals |= SerialSignal_RI;
4371 }
4372
4373 /*
4374 * set V.24 Control Register based on current configuration
4375 */
4376 static void msc_set_vcr(struct slgt_info *info)
4377 {
4378 unsigned char val = 0;
4379
4380 /* VCR (V.24 control)
4381 *
4382 * 07..04 serial IF select
4383 * 03 DTR
4384 * 02 RTS
4385 * 01 LL
4386 * 00 RL
4387 */
4388
4389 switch(info->if_mode & MGSL_INTERFACE_MASK)
4390 {
4391 case MGSL_INTERFACE_RS232:
4392 val |= BIT5; /* 0010 */
4393 break;
4394 case MGSL_INTERFACE_V35:
4395 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4396 break;
4397 case MGSL_INTERFACE_RS422:
4398 val |= BIT6; /* 0100 */
4399 break;
4400 }
4401
4402 if (info->signals & SerialSignal_DTR)
4403 val |= BIT3;
4404 if (info->signals & SerialSignal_RTS)
4405 val |= BIT2;
4406 if (info->if_mode & MGSL_INTERFACE_LL)
4407 val |= BIT1;
4408 if (info->if_mode & MGSL_INTERFACE_RL)
4409 val |= BIT0;
4410 wr_reg8(info, VCR, val);
4411 }
4412
4413 /*
4414 * set state of V24 control (output) signals
4415 */
4416 static void set_signals(struct slgt_info *info)
4417 {
4418 unsigned char val = rd_reg8(info, VCR);
4419 if (info->signals & SerialSignal_DTR)
4420 val |= BIT3;
4421 else
4422 val &= ~BIT3;
4423 if (info->signals & SerialSignal_RTS)
4424 val |= BIT2;
4425 else
4426 val &= ~BIT2;
4427 wr_reg8(info, VCR, val);
4428 }
4429
4430 /*
4431 * free range of receive DMA buffers (i to last)
4432 */
4433 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4434 {
4435 int done = 0;
4436
4437 while(!done) {
4438 /* reset current buffer for reuse */
4439 info->rbufs[i].status = 0;
4440 switch(info->params.mode) {
4441 case MGSL_MODE_RAW:
4442 case MGSL_MODE_MONOSYNC:
4443 case MGSL_MODE_BISYNC:
4444 set_desc_count(info->rbufs[i], info->raw_rx_size);
4445 break;
4446 default:
4447 set_desc_count(info->rbufs[i], DMABUFSIZE);
4448 }
4449
4450 if (i == last)
4451 done = 1;
4452 if (++i == info->rbuf_count)
4453 i = 0;
4454 }
4455 info->rbuf_current = i;
4456 }
4457
4458 /*
4459 * mark all receive DMA buffers as free
4460 */
4461 static void reset_rbufs(struct slgt_info *info)
4462 {
4463 free_rbufs(info, 0, info->rbuf_count - 1);
4464 }
4465
4466 /*
4467 * pass receive HDLC frame to upper layer
4468 *
4469 * return 1 if frame available, otherwise 0
4470 */
4471 static int rx_get_frame(struct slgt_info *info)
4472 {
4473 unsigned int start, end;
4474 unsigned short status;
4475 unsigned int framesize = 0;
4476 int rc = 0;
4477 unsigned long flags;
4478 struct tty_struct *tty = info->tty;
4479 unsigned char addr_field = 0xff;
4480 unsigned int crc_size = 0;
4481
4482 switch (info->params.crc_type & HDLC_CRC_MASK) {
4483 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4484 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4485 }
4486
4487 check_again:
4488
4489 framesize = 0;
4490 addr_field = 0xff;
4491 start = end = info->rbuf_current;
4492
4493 for (;;) {
4494 if (!desc_complete(info->rbufs[end]))
4495 goto cleanup;
4496
4497 if (framesize == 0 && info->params.addr_filter != 0xff)
4498 addr_field = info->rbufs[end].buf[0];
4499
4500 framesize += desc_count(info->rbufs[end]);
4501
4502 if (desc_eof(info->rbufs[end]))
4503 break;
4504
4505 if (++end == info->rbuf_count)
4506 end = 0;
4507
4508 if (end == info->rbuf_current) {
4509 if (info->rx_enabled){
4510 spin_lock_irqsave(&info->lock,flags);
4511 rx_start(info);
4512 spin_unlock_irqrestore(&info->lock,flags);
4513 }
4514 goto cleanup;
4515 }
4516 }
4517
4518 /* status
4519 *
4520 * 15 buffer complete
4521 * 14..06 reserved
4522 * 05..04 residue
4523 * 02 eof (end of frame)
4524 * 01 CRC error
4525 * 00 abort
4526 */
4527 status = desc_status(info->rbufs[end]);
4528
4529 /* ignore CRC bit if not using CRC (bit is undefined) */
4530 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4531 status &= ~BIT1;
4532
4533 if (framesize == 0 ||
4534 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4535 free_rbufs(info, start, end);
4536 goto check_again;
4537 }
4538
4539 if (framesize < (2 + crc_size) || status & BIT0) {
4540 info->icount.rxshort++;
4541 framesize = 0;
4542 } else if (status & BIT1) {
4543 info->icount.rxcrc++;
4544 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4545 framesize = 0;
4546 }
4547
4548 #if SYNCLINK_GENERIC_HDLC
4549 if (framesize == 0) {
4550 struct net_device_stats *stats = hdlc_stats(info->netdev);
4551 stats->rx_errors++;
4552 stats->rx_frame_errors++;
4553 }
4554 #endif
4555
4556 DBGBH(("%s rx frame status=%04X size=%d\n",
4557 info->device_name, status, framesize));
4558 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4559
4560 if (framesize) {
4561 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4562 framesize -= crc_size;
4563 crc_size = 0;
4564 }
4565
4566 if (framesize > info->max_frame_size + crc_size)
4567 info->icount.rxlong++;
4568 else {
4569 /* copy dma buffer(s) to contiguous temp buffer */
4570 int copy_count = framesize;
4571 int i = start;
4572 unsigned char *p = info->tmp_rbuf;
4573 info->tmp_rbuf_count = framesize;
4574
4575 info->icount.rxok++;
4576
4577 while(copy_count) {
4578 int partial_count = min(copy_count, DMABUFSIZE);
4579 memcpy(p, info->rbufs[i].buf, partial_count);
4580 p += partial_count;
4581 copy_count -= partial_count;
4582 if (++i == info->rbuf_count)
4583 i = 0;
4584 }
4585
4586 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4587 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4588 framesize++;
4589 }
4590
4591 #if SYNCLINK_GENERIC_HDLC
4592 if (info->netcount)
4593 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4594 else
4595 #endif
4596 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4597 }
4598 }
4599 free_rbufs(info, start, end);
4600 rc = 1;
4601
4602 cleanup:
4603 return rc;
4604 }
4605
4606 /*
4607 * pass receive buffer (RAW synchronous mode) to tty layer
4608 * return 1 if buffer available, otherwise 0
4609 */
4610 static int rx_get_buf(struct slgt_info *info)
4611 {
4612 unsigned int i = info->rbuf_current;
4613 unsigned int count;
4614
4615 if (!desc_complete(info->rbufs[i]))
4616 return 0;
4617 count = desc_count(info->rbufs[i]);
4618 switch(info->params.mode) {
4619 case MGSL_MODE_MONOSYNC:
4620 case MGSL_MODE_BISYNC:
4621 /* ignore residue in byte synchronous modes */
4622 if (desc_residue(info->rbufs[i]))
4623 count--;
4624 break;
4625 }
4626 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4627 DBGINFO(("rx_get_buf size=%d\n", count));
4628 if (count)
4629 ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4630 info->flag_buf, count);
4631 free_rbufs(info, i, i);
4632 return 1;
4633 }
4634
4635 static void reset_tbufs(struct slgt_info *info)
4636 {
4637 unsigned int i;
4638 info->tbuf_current = 0;
4639 for (i=0 ; i < info->tbuf_count ; i++) {
4640 info->tbufs[i].status = 0;
4641 info->tbufs[i].count = 0;
4642 }
4643 }
4644
4645 /*
4646 * return number of free transmit DMA buffers
4647 */
4648 static unsigned int free_tbuf_count(struct slgt_info *info)
4649 {
4650 unsigned int count = 0;
4651 unsigned int i = info->tbuf_current;
4652
4653 do
4654 {
4655 if (desc_count(info->tbufs[i]))
4656 break; /* buffer in use */
4657 ++count;
4658 if (++i == info->tbuf_count)
4659 i=0;
4660 } while (i != info->tbuf_current);
4661
4662 /* if tx DMA active, last zero count buffer is in use */
4663 if (count && (rd_reg32(info, TDCSR) & BIT0))
4664 --count;
4665
4666 return count;
4667 }
4668
4669 /*
4670 * load transmit DMA buffer(s) with data
4671 */
4672 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4673 {
4674 unsigned short count;
4675 unsigned int i;
4676 struct slgt_desc *d;
4677
4678 if (size == 0)
4679 return;
4680
4681 DBGDATA(info, buf, size, "tx");
4682
4683 info->tbuf_start = i = info->tbuf_current;
4684
4685 while (size) {
4686 d = &info->tbufs[i];
4687 if (++i == info->tbuf_count)
4688 i = 0;
4689
4690 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4691 memcpy(d->buf, buf, count);
4692
4693 size -= count;
4694 buf += count;
4695
4696 /*
4697 * set EOF bit for last buffer of HDLC frame or
4698 * for every buffer in raw mode
4699 */
4700 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4701 info->params.mode == MGSL_MODE_RAW)
4702 set_desc_eof(*d, 1);
4703 else
4704 set_desc_eof(*d, 0);
4705
4706 set_desc_count(*d, count);
4707 }
4708
4709 info->tbuf_current = i;
4710 }
4711
4712 static int register_test(struct slgt_info *info)
4713 {
4714 static unsigned short patterns[] =
4715 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4716 static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4717 unsigned int i;
4718 int rc = 0;
4719
4720 for (i=0 ; i < count ; i++) {
4721 wr_reg16(info, TIR, patterns[i]);
4722 wr_reg16(info, BDR, patterns[(i+1)%count]);
4723 if ((rd_reg16(info, TIR) != patterns[i]) ||
4724 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4725 rc = -ENODEV;
4726 break;
4727 }
4728 }
4729 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4730 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4731 return rc;
4732 }
4733
4734 static int irq_test(struct slgt_info *info)
4735 {
4736 unsigned long timeout;
4737 unsigned long flags;
4738 struct tty_struct *oldtty = info->tty;
4739 u32 speed = info->params.data_rate;
4740
4741 info->params.data_rate = 921600;
4742 info->tty = NULL;
4743
4744 spin_lock_irqsave(&info->lock, flags);
4745 async_mode(info);
4746 slgt_irq_on(info, IRQ_TXIDLE);
4747
4748 /* enable transmitter */
4749 wr_reg16(info, TCR,
4750 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4751
4752 /* write one byte and wait for tx idle */
4753 wr_reg16(info, TDR, 0);
4754
4755 /* assume failure */
4756 info->init_error = DiagStatus_IrqFailure;
4757 info->irq_occurred = FALSE;
4758
4759 spin_unlock_irqrestore(&info->lock, flags);
4760
4761 timeout=100;
4762 while(timeout-- && !info->irq_occurred)
4763 msleep_interruptible(10);
4764
4765 spin_lock_irqsave(&info->lock,flags);
4766 reset_port(info);
4767 spin_unlock_irqrestore(&info->lock,flags);
4768
4769 info->params.data_rate = speed;
4770 info->tty = oldtty;
4771
4772 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4773 return info->irq_occurred ? 0 : -ENODEV;
4774 }
4775
4776 static int loopback_test_rx(struct slgt_info *info)
4777 {
4778 unsigned char *src, *dest;
4779 int count;
4780
4781 if (desc_complete(info->rbufs[0])) {
4782 count = desc_count(info->rbufs[0]);
4783 src = info->rbufs[0].buf;
4784 dest = info->tmp_rbuf;
4785
4786 for( ; count ; count-=2, src+=2) {
4787 /* src=data byte (src+1)=status byte */
4788 if (!(*(src+1) & (BIT9 + BIT8))) {
4789 *dest = *src;
4790 dest++;
4791 info->tmp_rbuf_count++;
4792 }
4793 }
4794 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4795 return 1;
4796 }
4797 return 0;
4798 }
4799
4800 static int loopback_test(struct slgt_info *info)
4801 {
4802 #define TESTFRAMESIZE 20
4803
4804 unsigned long timeout;
4805 u16 count = TESTFRAMESIZE;
4806 unsigned char buf[TESTFRAMESIZE];
4807 int rc = -ENODEV;
4808 unsigned long flags;
4809
4810 struct tty_struct *oldtty = info->tty;
4811 MGSL_PARAMS params;
4812
4813 memcpy(&params, &info->params, sizeof(params));
4814
4815 info->params.mode = MGSL_MODE_ASYNC;
4816 info->params.data_rate = 921600;
4817 info->params.loopback = 1;
4818 info->tty = NULL;
4819
4820 /* build and send transmit frame */
4821 for (count = 0; count < TESTFRAMESIZE; ++count)
4822 buf[count] = (unsigned char)count;
4823
4824 info->tmp_rbuf_count = 0;
4825 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4826
4827 /* program hardware for HDLC and enabled receiver */
4828 spin_lock_irqsave(&info->lock,flags);
4829 async_mode(info);
4830 rx_start(info);
4831 info->tx_count = count;
4832 tx_load(info, buf, count);
4833 tx_start(info);
4834 spin_unlock_irqrestore(&info->lock, flags);
4835
4836 /* wait for receive complete */
4837 for (timeout = 100; timeout; --timeout) {
4838 msleep_interruptible(10);
4839 if (loopback_test_rx(info)) {
4840 rc = 0;
4841 break;
4842 }
4843 }
4844
4845 /* verify received frame length and contents */
4846 if (!rc && (info->tmp_rbuf_count != count ||
4847 memcmp(buf, info->tmp_rbuf, count))) {
4848 rc = -ENODEV;
4849 }
4850
4851 spin_lock_irqsave(&info->lock,flags);
4852 reset_adapter(info);
4853 spin_unlock_irqrestore(&info->lock,flags);
4854
4855 memcpy(&info->params, &params, sizeof(info->params));
4856 info->tty = oldtty;
4857
4858 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4859 return rc;
4860 }
4861
4862 static int adapter_test(struct slgt_info *info)
4863 {
4864 DBGINFO(("testing %s\n", info->device_name));
4865 if (register_test(info) < 0) {
4866 printk("register test failure %s addr=%08X\n",
4867 info->device_name, info->phys_reg_addr);
4868 } else if (irq_test(info) < 0) {
4869 printk("IRQ test failure %s IRQ=%d\n",
4870 info->device_name, info->irq_level);
4871 } else if (loopback_test(info) < 0) {
4872 printk("loopback test failure %s\n", info->device_name);
4873 }
4874 return info->init_error;
4875 }
4876
4877 /*
4878 * transmit timeout handler
4879 */
4880 static void tx_timeout(unsigned long context)
4881 {
4882 struct slgt_info *info = (struct slgt_info*)context;
4883 unsigned long flags;
4884
4885 DBGINFO(("%s tx_timeout\n", info->device_name));
4886 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4887 info->icount.txtimeout++;
4888 }
4889 spin_lock_irqsave(&info->lock,flags);
4890 info->tx_active = 0;
4891 info->tx_count = 0;
4892 spin_unlock_irqrestore(&info->lock,flags);
4893
4894 #if SYNCLINK_GENERIC_HDLC
4895 if (info->netcount)
4896 hdlcdev_tx_done(info);
4897 else
4898 #endif
4899 bh_transmit(info);
4900 }
4901
4902 /*
4903 * receive buffer polling timer
4904 */
4905 static void rx_timeout(unsigned long context)
4906 {
4907 struct slgt_info *info = (struct slgt_info*)context;
4908 unsigned long flags;
4909
4910 DBGINFO(("%s rx_timeout\n", info->device_name));
4911 spin_lock_irqsave(&info->lock, flags);
4912 info->pending_bh |= BH_RECEIVE;
4913 spin_unlock_irqrestore(&info->lock, flags);
4914 bh_handler(&info->task);
4915 }
4916
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