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knfsd: Validate filehandle type in fsid_source
[linux-2.6/mini2440.git] / drivers / ata / sata_sx4.c
blob97aefdd87be4d28ee62556c54c2522eb11f51393
1 /*
2 * sata_sx4.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
30 *
31 */
32
33 /*
34 Theory of operation
35 -------------------
36
37 The SX4 (PDC20621) chip features a single Host DMA (HDMA) copy
38 engine, DIMM memory, and four ATA engines (one per SATA port).
39 Data is copied to/from DIMM memory by the HDMA engine, before
40 handing off to one (or more) of the ATA engines. The ATA
41 engines operate solely on DIMM memory.
42
43 The SX4 behaves like a PATA chip, with no SATA controls or
44 knowledge whatsoever, leading to the presumption that
45 PATA<->SATA bridges exist on SX4 boards, external to the
46 PDC20621 chip itself.
47
48 The chip is quite capable, supporting an XOR engine and linked
49 hardware commands (permits a string to transactions to be
50 submitted and waited-on as a single unit), and an optional
51 microprocessor.
52
53 The limiting factor is largely software. This Linux driver was
54 written to multiplex the single HDMA engine to copy disk
55 transactions into a fixed DIMM memory space, from where an ATA
56 engine takes over. As a result, each WRITE looks like this:
57
58 submit HDMA packet to hardware
59 hardware copies data from system memory to DIMM
60 hardware raises interrupt
61
62 submit ATA packet to hardware
63 hardware executes ATA WRITE command, w/ data in DIMM
64 hardware raises interrupt
65
66 and each READ looks like this:
67
68 submit ATA packet to hardware
69 hardware executes ATA READ command, w/ data in DIMM
70 hardware raises interrupt
71
72 submit HDMA packet to hardware
73 hardware copies data from DIMM to system memory
74 hardware raises interrupt
75
76 This is a very slow, lock-step way of doing things that can
77 certainly be improved by motivated kernel hackers.
78
79 */
80
81 #include <linux/kernel.h>
82 #include <linux/module.h>
83 #include <linux/pci.h>
84 #include <linux/init.h>
85 #include <linux/blkdev.h>
86 #include <linux/delay.h>
87 #include <linux/interrupt.h>
88 #include <linux/device.h>
89 #include <scsi/scsi_host.h>
90 #include <scsi/scsi_cmnd.h>
91 #include <linux/libata.h>
92 #include "sata_promise.h"
93
94 #define DRV_NAME "sata_sx4"
95 #define DRV_VERSION "0.12"
96
97
98 enum {
99 PDC_MMIO_BAR = 3,
100 PDC_DIMM_BAR = 4,
101
102 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
103
104 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
105 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
106 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
107 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
108
109 PDC_CTLSTAT = 0x60, /* IDEn control / status */
110
111 PDC_20621_SEQCTL = 0x400,
112 PDC_20621_SEQMASK = 0x480,
113 PDC_20621_GENERAL_CTL = 0x484,
114 PDC_20621_PAGE_SIZE = (32 * 1024),
115
116 /* chosen, not constant, values; we design our own DIMM mem map */
117 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
118 PDC_20621_DIMM_BASE = 0x00200000,
119 PDC_20621_DIMM_DATA = (64 * 1024),
120 PDC_DIMM_DATA_STEP = (256 * 1024),
121 PDC_DIMM_WINDOW_STEP = (8 * 1024),
122 PDC_DIMM_HOST_PRD = (6 * 1024),
123 PDC_DIMM_HOST_PKT = (128 * 0),
124 PDC_DIMM_HPKT_PRD = (128 * 1),
125 PDC_DIMM_ATA_PKT = (128 * 2),
126 PDC_DIMM_APKT_PRD = (128 * 3),
127 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
128 PDC_PAGE_WINDOW = 0x40,
129 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
130 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
131 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
132
133 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
134
135 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
136 (1<<23),
137
138 board_20621 = 0, /* FastTrak S150 SX4 */
139
140 PDC_MASK_INT = (1 << 10), /* HDMA/ATA mask int */
141 PDC_RESET = (1 << 11), /* HDMA/ATA reset */
142 PDC_DMA_ENABLE = (1 << 7), /* DMA start/stop */
143
144 PDC_MAX_HDMA = 32,
145 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
146
147 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
148 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
149 PDC_I2C_CONTROL = 0x48,
150 PDC_I2C_ADDR_DATA = 0x4C,
151 PDC_DIMM0_CONTROL = 0x80,
152 PDC_DIMM1_CONTROL = 0x84,
153 PDC_SDRAM_CONTROL = 0x88,
154 PDC_I2C_WRITE = 0, /* master -> slave */
155 PDC_I2C_READ = (1 << 6), /* master <- slave */
156 PDC_I2C_START = (1 << 7), /* start I2C proto */
157 PDC_I2C_MASK_INT = (1 << 5), /* mask I2C interrupt */
158 PDC_I2C_COMPLETE = (1 << 16), /* I2C normal compl. */
159 PDC_I2C_NO_ACK = (1 << 20), /* slave no-ack addr */
160 PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
161 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
162 PDC_DIMM_SPD_ROW_NUM = 3,
163 PDC_DIMM_SPD_COLUMN_NUM = 4,
164 PDC_DIMM_SPD_MODULE_ROW = 5,
165 PDC_DIMM_SPD_TYPE = 11,
166 PDC_DIMM_SPD_FRESH_RATE = 12,
167 PDC_DIMM_SPD_BANK_NUM = 17,
168 PDC_DIMM_SPD_CAS_LATENCY = 18,
169 PDC_DIMM_SPD_ATTRIBUTE = 21,
170 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
171 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
172 PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
173 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
174 PDC_DIMM_SPD_SYSTEM_FREQ = 126,
175 PDC_CTL_STATUS = 0x08,
176 PDC_DIMM_WINDOW_CTLR = 0x0C,
177 PDC_TIME_CONTROL = 0x3C,
178 PDC_TIME_PERIOD = 0x40,
179 PDC_TIME_COUNTER = 0x44,
180 PDC_GENERAL_CTLR = 0x484,
181 PCI_PLL_INIT = 0x8A531824,
182 PCI_X_TCOUNT = 0xEE1E5CFF,
183
184 /* PDC_TIME_CONTROL bits */
185 PDC_TIMER_BUZZER = (1 << 10),
186 PDC_TIMER_MODE_PERIODIC = 0, /* bits 9:8 == 00 */
187 PDC_TIMER_MODE_ONCE = (1 << 8), /* bits 9:8 == 01 */
188 PDC_TIMER_ENABLE = (1 << 7),
189 PDC_TIMER_MASK_INT = (1 << 5),
190 PDC_TIMER_SEQ_MASK = 0x1f, /* SEQ ID for timer */
191 PDC_TIMER_DEFAULT = PDC_TIMER_MODE_ONCE |
192 PDC_TIMER_ENABLE |
193 PDC_TIMER_MASK_INT,
194 };
195
196
197 struct pdc_port_priv {
198 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
199 u8 *pkt;
200 dma_addr_t pkt_dma;
201 };
202
203 struct pdc_host_priv {
204 unsigned int doing_hdma;
205 unsigned int hdma_prod;
206 unsigned int hdma_cons;
207 struct {
208 struct ata_queued_cmd *qc;
209 unsigned int seq;
210 unsigned long pkt_ofs;
211 } hdma[32];
212 };
213
214
215 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
216 static void pdc_eng_timeout(struct ata_port *ap);
217 static void pdc_20621_phy_reset (struct ata_port *ap);
218 static int pdc_port_start(struct ata_port *ap);
219 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
220 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
221 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
222 static unsigned int pdc20621_dimm_init(struct ata_host *host);
223 static int pdc20621_detect_dimm(struct ata_host *host);
224 static unsigned int pdc20621_i2c_read(struct ata_host *host,
225 u32 device, u32 subaddr, u32 *pdata);
226 static int pdc20621_prog_dimm0(struct ata_host *host);
227 static unsigned int pdc20621_prog_dimm_global(struct ata_host *host);
228 #ifdef ATA_VERBOSE_DEBUG
229 static void pdc20621_get_from_dimm(struct ata_host *host,
230 void *psource, u32 offset, u32 size);
231 #endif
232 static void pdc20621_put_to_dimm(struct ata_host *host,
233 void *psource, u32 offset, u32 size);
234 static void pdc20621_irq_clear(struct ata_port *ap);
235 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
236
237
238 static struct scsi_host_template pdc_sata_sht = {
239 .module = THIS_MODULE,
240 .name = DRV_NAME,
241 .ioctl = ata_scsi_ioctl,
242 .queuecommand = ata_scsi_queuecmd,
243 .can_queue = ATA_DEF_QUEUE,
244 .this_id = ATA_SHT_THIS_ID,
245 .sg_tablesize = LIBATA_MAX_PRD,
246 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
247 .emulated = ATA_SHT_EMULATED,
248 .use_clustering = ATA_SHT_USE_CLUSTERING,
249 .proc_name = DRV_NAME,
250 .dma_boundary = ATA_DMA_BOUNDARY,
251 .slave_configure = ata_scsi_slave_config,
252 .slave_destroy = ata_scsi_slave_destroy,
253 .bios_param = ata_std_bios_param,
254 };
255
256 static const struct ata_port_operations pdc_20621_ops = {
257 .port_disable = ata_port_disable,
258 .tf_load = pdc_tf_load_mmio,
259 .tf_read = ata_tf_read,
260 .check_status = ata_check_status,
261 .exec_command = pdc_exec_command_mmio,
262 .dev_select = ata_std_dev_select,
263 .phy_reset = pdc_20621_phy_reset,
264 .qc_prep = pdc20621_qc_prep,
265 .qc_issue = pdc20621_qc_issue_prot,
266 .data_xfer = ata_data_xfer,
267 .eng_timeout = pdc_eng_timeout,
268 .irq_clear = pdc20621_irq_clear,
269 .irq_on = ata_irq_on,
270 .irq_ack = ata_irq_ack,
271 .port_start = pdc_port_start,
272 };
273
274 static const struct ata_port_info pdc_port_info[] = {
275 /* board_20621 */
276 {
277 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
278 ATA_FLAG_SRST | ATA_FLAG_MMIO |
279 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING,
280 .pio_mask = 0x1f, /* pio0-4 */
281 .mwdma_mask = 0x07, /* mwdma0-2 */
282 .udma_mask = ATA_UDMA6,
283 .port_ops = &pdc_20621_ops,
284 },
285
286 };
287
288 static const struct pci_device_id pdc_sata_pci_tbl[] = {
289 { PCI_VDEVICE(PROMISE, 0x6622), board_20621 },
290
291 { } /* terminate list */
292 };
293
294 static struct pci_driver pdc_sata_pci_driver = {
295 .name = DRV_NAME,
296 .id_table = pdc_sata_pci_tbl,
297 .probe = pdc_sata_init_one,
298 .remove = ata_pci_remove_one,
299 };
300
301
302 static int pdc_port_start(struct ata_port *ap)
303 {
304 struct device *dev = ap->host->dev;
305 struct pdc_port_priv *pp;
306 int rc;
307
308 rc = ata_port_start(ap);
309 if (rc)
310 return rc;
311
312 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
313 if (!pp)
314 return -ENOMEM;
315
316 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
317 if (!pp->pkt)
318 return -ENOMEM;
319
320 ap->private_data = pp;
321
322 return 0;
323 }
324
325 static void pdc_20621_phy_reset (struct ata_port *ap)
326 {
327 VPRINTK("ENTER\n");
328 ap->cbl = ATA_CBL_SATA;
329 ata_port_probe(ap);
330 ata_bus_reset(ap);
331 }
332
333 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
334 unsigned int portno,
335 unsigned int total_len)
336 {
337 u32 addr;
338 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
339 u32 *buf32 = (u32 *) buf;
340
341 /* output ATA packet S/G table */
342 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
343 (PDC_DIMM_DATA_STEP * portno);
344 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
345 buf32[dw] = cpu_to_le32(addr);
346 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
347
348 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
349 PDC_20621_DIMM_BASE +
350 (PDC_DIMM_WINDOW_STEP * portno) +
351 PDC_DIMM_APKT_PRD,
352 buf32[dw], buf32[dw + 1]);
353 }
354
355 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
356 unsigned int portno,
357 unsigned int total_len)
358 {
359 u32 addr;
360 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
361 u32 *buf32 = (u32 *) buf;
362
363 /* output Host DMA packet S/G table */
364 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
365 (PDC_DIMM_DATA_STEP * portno);
366
367 buf32[dw] = cpu_to_le32(addr);
368 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
369
370 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
371 PDC_20621_DIMM_BASE +
372 (PDC_DIMM_WINDOW_STEP * portno) +
373 PDC_DIMM_HPKT_PRD,
374 buf32[dw], buf32[dw + 1]);
375 }
376
377 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
378 unsigned int devno, u8 *buf,
379 unsigned int portno)
380 {
381 unsigned int i, dw;
382 u32 *buf32 = (u32 *) buf;
383 u8 dev_reg;
384
385 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
386 (PDC_DIMM_WINDOW_STEP * portno) +
387 PDC_DIMM_APKT_PRD;
388 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
389
390 i = PDC_DIMM_ATA_PKT;
391
392 /*
393 * Set up ATA packet
394 */
395 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
396 buf[i++] = PDC_PKT_READ;
397 else if (tf->protocol == ATA_PROT_NODATA)
398 buf[i++] = PDC_PKT_NODATA;
399 else
400 buf[i++] = 0;
401 buf[i++] = 0; /* reserved */
402 buf[i++] = portno + 1; /* seq. id */
403 buf[i++] = 0xff; /* delay seq. id */
404
405 /* dimm dma S/G, and next-pkt */
406 dw = i >> 2;
407 if (tf->protocol == ATA_PROT_NODATA)
408 buf32[dw] = 0;
409 else
410 buf32[dw] = cpu_to_le32(dimm_sg);
411 buf32[dw + 1] = 0;
412 i += 8;
413
414 if (devno == 0)
415 dev_reg = ATA_DEVICE_OBS;
416 else
417 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
418
419 /* select device */
420 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
421 buf[i++] = dev_reg;
422
423 /* device control register */
424 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
425 buf[i++] = tf->ctl;
426
427 return i;
428 }
429
430 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
431 unsigned int portno)
432 {
433 unsigned int dw;
434 u32 tmp, *buf32 = (u32 *) buf;
435
436 unsigned int host_sg = PDC_20621_DIMM_BASE +
437 (PDC_DIMM_WINDOW_STEP * portno) +
438 PDC_DIMM_HOST_PRD;
439 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
440 (PDC_DIMM_WINDOW_STEP * portno) +
441 PDC_DIMM_HPKT_PRD;
442 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
443 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
444
445 dw = PDC_DIMM_HOST_PKT >> 2;
446
447 /*
448 * Set up Host DMA packet
449 */
450 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
451 tmp = PDC_PKT_READ;
452 else
453 tmp = 0;
454 tmp |= ((portno + 1 + 4) << 16); /* seq. id */
455 tmp |= (0xff << 24); /* delay seq. id */
456 buf32[dw + 0] = cpu_to_le32(tmp);
457 buf32[dw + 1] = cpu_to_le32(host_sg);
458 buf32[dw + 2] = cpu_to_le32(dimm_sg);
459 buf32[dw + 3] = 0;
460
461 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
462 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
463 PDC_DIMM_HOST_PKT,
464 buf32[dw + 0],
465 buf32[dw + 1],
466 buf32[dw + 2],
467 buf32[dw + 3]);
468 }
469
470 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
471 {
472 struct scatterlist *sg;
473 struct ata_port *ap = qc->ap;
474 struct pdc_port_priv *pp = ap->private_data;
475 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
476 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
477 unsigned int portno = ap->port_no;
478 unsigned int i, idx, total_len = 0, sgt_len;
479 u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
480
481 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
482
483 VPRINTK("ata%u: ENTER\n", ap->print_id);
484
485 /* hard-code chip #0 */
486 mmio += PDC_CHIP0_OFS;
487
488 /*
489 * Build S/G table
490 */
491 idx = 0;
492 ata_for_each_sg(sg, qc) {
493 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
494 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
495 total_len += sg_dma_len(sg);
496 }
497 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
498 sgt_len = idx * 4;
499
500 /*
501 * Build ATA, host DMA packets
502 */
503 pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
504 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
505
506 pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
507 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
508
509 if (qc->tf.flags & ATA_TFLAG_LBA48)
510 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
511 else
512 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
513
514 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
515
516 /* copy three S/G tables and two packets to DIMM MMIO window */
517 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
518 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
519 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
520 PDC_DIMM_HOST_PRD,
521 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
522
523 /* force host FIFO dump */
524 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
525
526 readl(dimm_mmio); /* MMIO PCI posting flush */
527
528 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
529 }
530
531 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
532 {
533 struct ata_port *ap = qc->ap;
534 struct pdc_port_priv *pp = ap->private_data;
535 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
536 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
537 unsigned int portno = ap->port_no;
538 unsigned int i;
539
540 VPRINTK("ata%u: ENTER\n", ap->print_id);
541
542 /* hard-code chip #0 */
543 mmio += PDC_CHIP0_OFS;
544
545 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
546
547 if (qc->tf.flags & ATA_TFLAG_LBA48)
548 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
549 else
550 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
551
552 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
553
554 /* copy three S/G tables and two packets to DIMM MMIO window */
555 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
556 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
557
558 /* force host FIFO dump */
559 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
560
561 readl(dimm_mmio); /* MMIO PCI posting flush */
562
563 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
564 }
565
566 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
567 {
568 switch (qc->tf.protocol) {
569 case ATA_PROT_DMA:
570 pdc20621_dma_prep(qc);
571 break;
572 case ATA_PROT_NODATA:
573 pdc20621_nodata_prep(qc);
574 break;
575 default:
576 break;
577 }
578 }
579
580 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
581 unsigned int seq,
582 u32 pkt_ofs)
583 {
584 struct ata_port *ap = qc->ap;
585 struct ata_host *host = ap->host;
586 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
587
588 /* hard-code chip #0 */
589 mmio += PDC_CHIP0_OFS;
590
591 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
592 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
593
594 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
595 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
596 }
597
598 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
599 unsigned int seq,
600 u32 pkt_ofs)
601 {
602 struct ata_port *ap = qc->ap;
603 struct pdc_host_priv *pp = ap->host->private_data;
604 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
605
606 if (!pp->doing_hdma) {
607 __pdc20621_push_hdma(qc, seq, pkt_ofs);
608 pp->doing_hdma = 1;
609 return;
610 }
611
612 pp->hdma[idx].qc = qc;
613 pp->hdma[idx].seq = seq;
614 pp->hdma[idx].pkt_ofs = pkt_ofs;
615 pp->hdma_prod++;
616 }
617
618 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
619 {
620 struct ata_port *ap = qc->ap;
621 struct pdc_host_priv *pp = ap->host->private_data;
622 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
623
624 /* if nothing on queue, we're done */
625 if (pp->hdma_prod == pp->hdma_cons) {
626 pp->doing_hdma = 0;
627 return;
628 }
629
630 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
631 pp->hdma[idx].pkt_ofs);
632 pp->hdma_cons++;
633 }
634
635 #ifdef ATA_VERBOSE_DEBUG
636 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
637 {
638 struct ata_port *ap = qc->ap;
639 unsigned int port_no = ap->port_no;
640 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
641
642 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
643 dimm_mmio += PDC_DIMM_HOST_PKT;
644
645 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
646 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
647 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
648 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
649 }
650 #else
651 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
652 #endif /* ATA_VERBOSE_DEBUG */
653
654 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
655 {
656 struct ata_port *ap = qc->ap;
657 struct ata_host *host = ap->host;
658 unsigned int port_no = ap->port_no;
659 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
660 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
661 u8 seq = (u8) (port_no + 1);
662 unsigned int port_ofs;
663
664 /* hard-code chip #0 */
665 mmio += PDC_CHIP0_OFS;
666
667 VPRINTK("ata%u: ENTER\n", ap->print_id);
668
669 wmb(); /* flush PRD, pkt writes */
670
671 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
672
673 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
674 if (rw && qc->tf.protocol == ATA_PROT_DMA) {
675 seq += 4;
676
677 pdc20621_dump_hdma(qc);
678 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
679 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
680 port_ofs + PDC_DIMM_HOST_PKT,
681 port_ofs + PDC_DIMM_HOST_PKT,
682 seq);
683 } else {
684 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
685 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
686
687 writel(port_ofs + PDC_DIMM_ATA_PKT,
688 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
689 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
690 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
691 port_ofs + PDC_DIMM_ATA_PKT,
692 port_ofs + PDC_DIMM_ATA_PKT,
693 seq);
694 }
695 }
696
697 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
698 {
699 switch (qc->tf.protocol) {
700 case ATA_PROT_DMA:
701 case ATA_PROT_NODATA:
702 pdc20621_packet_start(qc);
703 return 0;
704
705 case ATA_PROT_ATAPI_DMA:
706 BUG();
707 break;
708
709 default:
710 break;
711 }
712
713 return ata_qc_issue_prot(qc);
714 }
715
716 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
717 struct ata_queued_cmd *qc,
718 unsigned int doing_hdma,
719 void __iomem *mmio)
720 {
721 unsigned int port_no = ap->port_no;
722 unsigned int port_ofs =
723 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
724 u8 status;
725 unsigned int handled = 0;
726
727 VPRINTK("ENTER\n");
728
729 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
730 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
731
732 /* step two - DMA from DIMM to host */
733 if (doing_hdma) {
734 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->print_id,
735 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
736 /* get drive status; clear intr; complete txn */
737 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
738 ata_qc_complete(qc);
739 pdc20621_pop_hdma(qc);
740 }
741
742 /* step one - exec ATA command */
743 else {
744 u8 seq = (u8) (port_no + 1 + 4);
745 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->print_id,
746 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
747
748 /* submit hdma pkt */
749 pdc20621_dump_hdma(qc);
750 pdc20621_push_hdma(qc, seq,
751 port_ofs + PDC_DIMM_HOST_PKT);
752 }
753 handled = 1;
754
755 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
756
757 /* step one - DMA from host to DIMM */
758 if (doing_hdma) {
759 u8 seq = (u8) (port_no + 1);
760 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->print_id,
761 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
762
763 /* submit ata pkt */
764 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
765 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
766 writel(port_ofs + PDC_DIMM_ATA_PKT,
767 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
768 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
769 }
770
771 /* step two - execute ATA command */
772 else {
773 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->print_id,
774 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
775 /* get drive status; clear intr; complete txn */
776 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
777 ata_qc_complete(qc);
778 pdc20621_pop_hdma(qc);
779 }
780 handled = 1;
781
782 /* command completion, but no data xfer */
783 } else if (qc->tf.protocol == ATA_PROT_NODATA) {
784
785 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
786 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
787 qc->err_mask |= ac_err_mask(status);
788 ata_qc_complete(qc);
789 handled = 1;
790
791 } else {
792 ap->stats.idle_irq++;
793 }
794
795 return handled;
796 }
797
798 static void pdc20621_irq_clear(struct ata_port *ap)
799 {
800 struct ata_host *host = ap->host;
801 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
802
803 mmio += PDC_CHIP0_OFS;
804
805 readl(mmio + PDC_20621_SEQMASK);
806 }
807
808 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance)
809 {
810 struct ata_host *host = dev_instance;
811 struct ata_port *ap;
812 u32 mask = 0;
813 unsigned int i, tmp, port_no;
814 unsigned int handled = 0;
815 void __iomem *mmio_base;
816
817 VPRINTK("ENTER\n");
818
819 if (!host || !host->iomap[PDC_MMIO_BAR]) {
820 VPRINTK("QUICK EXIT\n");
821 return IRQ_NONE;
822 }
823
824 mmio_base = host->iomap[PDC_MMIO_BAR];
825
826 /* reading should also clear interrupts */
827 mmio_base += PDC_CHIP0_OFS;
828 mask = readl(mmio_base + PDC_20621_SEQMASK);
829 VPRINTK("mask == 0x%x\n", mask);
830
831 if (mask == 0xffffffff) {
832 VPRINTK("QUICK EXIT 2\n");
833 return IRQ_NONE;
834 }
835 mask &= 0xffff; /* only 16 tags possible */
836 if (!mask) {
837 VPRINTK("QUICK EXIT 3\n");
838 return IRQ_NONE;
839 }
840
841 spin_lock(&host->lock);
842
843 for (i = 1; i < 9; i++) {
844 port_no = i - 1;
845 if (port_no > 3)
846 port_no -= 4;
847 if (port_no >= host->n_ports)
848 ap = NULL;
849 else
850 ap = host->ports[port_no];
851 tmp = mask & (1 << i);
852 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
853 if (tmp && ap &&
854 !(ap->flags & ATA_FLAG_DISABLED)) {
855 struct ata_queued_cmd *qc;
856
857 qc = ata_qc_from_tag(ap, ap->active_tag);
858 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
859 handled += pdc20621_host_intr(ap, qc, (i > 4),
860 mmio_base);
861 }
862 }
863
864 spin_unlock(&host->lock);
865
866 VPRINTK("mask == 0x%x\n", mask);
867
868 VPRINTK("EXIT\n");
869
870 return IRQ_RETVAL(handled);
871 }
872
873 static void pdc_eng_timeout(struct ata_port *ap)
874 {
875 u8 drv_stat;
876 struct ata_host *host = ap->host;
877 struct ata_queued_cmd *qc;
878 unsigned long flags;
879
880 DPRINTK("ENTER\n");
881
882 spin_lock_irqsave(&host->lock, flags);
883
884 qc = ata_qc_from_tag(ap, ap->active_tag);
885
886 switch (qc->tf.protocol) {
887 case ATA_PROT_DMA:
888 case ATA_PROT_NODATA:
889 ata_port_printk(ap, KERN_ERR, "command timeout\n");
890 qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
891 break;
892
893 default:
894 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
895
896 ata_port_printk(ap, KERN_ERR,
897 "unknown timeout, cmd 0x%x stat 0x%x\n",
898 qc->tf.command, drv_stat);
899
900 qc->err_mask |= ac_err_mask(drv_stat);
901 break;
902 }
903
904 spin_unlock_irqrestore(&host->lock, flags);
905 ata_eh_qc_complete(qc);
906 DPRINTK("EXIT\n");
907 }
908
909 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
910 {
911 WARN_ON (tf->protocol == ATA_PROT_DMA ||
912 tf->protocol == ATA_PROT_NODATA);
913 ata_tf_load(ap, tf);
914 }
915
916
917 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
918 {
919 WARN_ON (tf->protocol == ATA_PROT_DMA ||
920 tf->protocol == ATA_PROT_NODATA);
921 ata_exec_command(ap, tf);
922 }
923
924
925 static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
926 {
927 port->cmd_addr = base;
928 port->data_addr = base;
929 port->feature_addr =
930 port->error_addr = base + 0x4;
931 port->nsect_addr = base + 0x8;
932 port->lbal_addr = base + 0xc;
933 port->lbam_addr = base + 0x10;
934 port->lbah_addr = base + 0x14;
935 port->device_addr = base + 0x18;
936 port->command_addr =
937 port->status_addr = base + 0x1c;
938 port->altstatus_addr =
939 port->ctl_addr = base + 0x38;
940 }
941
942
943 #ifdef ATA_VERBOSE_DEBUG
944 static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
945 u32 offset, u32 size)
946 {
947 u32 window_size;
948 u16 idx;
949 u8 page_mask;
950 long dist;
951 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
952 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
953
954 /* hard-code chip #0 */
955 mmio += PDC_CHIP0_OFS;
956
957 page_mask = 0x00;
958 window_size = 0x2000 * 4; /* 32K byte uchar size */
959 idx = (u16) (offset / window_size);
960
961 writel(0x01, mmio + PDC_GENERAL_CTLR);
962 readl(mmio + PDC_GENERAL_CTLR);
963 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
964 readl(mmio + PDC_DIMM_WINDOW_CTLR);
965
966 offset -= (idx * window_size);
967 idx++;
968 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
969 (long) (window_size - offset);
970 memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
971 dist);
972
973 psource += dist;
974 size -= dist;
975 for (; (long) size >= (long) window_size ;) {
976 writel(0x01, mmio + PDC_GENERAL_CTLR);
977 readl(mmio + PDC_GENERAL_CTLR);
978 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
979 readl(mmio + PDC_DIMM_WINDOW_CTLR);
980 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
981 window_size / 4);
982 psource += window_size;
983 size -= window_size;
984 idx ++;
985 }
986
987 if (size) {
988 writel(0x01, mmio + PDC_GENERAL_CTLR);
989 readl(mmio + PDC_GENERAL_CTLR);
990 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
991 readl(mmio + PDC_DIMM_WINDOW_CTLR);
992 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
993 size / 4);
994 }
995 }
996 #endif
997
998
999 static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
1000 u32 offset, u32 size)
1001 {
1002 u32 window_size;
1003 u16 idx;
1004 u8 page_mask;
1005 long dist;
1006 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1007 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
1008
1009 /* hard-code chip #0 */
1010 mmio += PDC_CHIP0_OFS;
1011
1012 page_mask = 0x00;
1013 window_size = 0x2000 * 4; /* 32K byte uchar size */
1014 idx = (u16) (offset / window_size);
1015
1016 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1017 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1018 offset -= (idx * window_size);
1019 idx++;
1020 dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1021 (long) (window_size - offset);
1022 memcpy_toio(dimm_mmio + offset / 4, psource, dist);
1023 writel(0x01, mmio + PDC_GENERAL_CTLR);
1024 readl(mmio + PDC_GENERAL_CTLR);
1025
1026 psource += dist;
1027 size -= dist;
1028 for (; (long) size >= (long) window_size ;) {
1029 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1030 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1031 memcpy_toio(dimm_mmio, psource, window_size / 4);
1032 writel(0x01, mmio + PDC_GENERAL_CTLR);
1033 readl(mmio + PDC_GENERAL_CTLR);
1034 psource += window_size;
1035 size -= window_size;
1036 idx ++;
1037 }
1038
1039 if (size) {
1040 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1041 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1042 memcpy_toio(dimm_mmio, psource, size / 4);
1043 writel(0x01, mmio + PDC_GENERAL_CTLR);
1044 readl(mmio + PDC_GENERAL_CTLR);
1045 }
1046 }
1047
1048
1049 static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
1050 u32 subaddr, u32 *pdata)
1051 {
1052 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1053 u32 i2creg = 0;
1054 u32 status;
1055 u32 count =0;
1056
1057 /* hard-code chip #0 */
1058 mmio += PDC_CHIP0_OFS;
1059
1060 i2creg |= device << 24;
1061 i2creg |= subaddr << 16;
1062
1063 /* Set the device and subaddress */
1064 writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
1065 readl(mmio + PDC_I2C_ADDR_DATA);
1066
1067 /* Write Control to perform read operation, mask int */
1068 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1069 mmio + PDC_I2C_CONTROL);
1070
1071 for (count = 0; count <= 1000; count ++) {
1072 status = readl(mmio + PDC_I2C_CONTROL);
1073 if (status & PDC_I2C_COMPLETE) {
1074 status = readl(mmio + PDC_I2C_ADDR_DATA);
1075 break;
1076 } else if (count == 1000)
1077 return 0;
1078 }
1079
1080 *pdata = (status >> 8) & 0x000000ff;
1081 return 1;
1082 }
1083
1084
1085 static int pdc20621_detect_dimm(struct ata_host *host)
1086 {
1087 u32 data=0 ;
1088 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1089 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1090 if (data == 100)
1091 return 100;
1092 } else
1093 return 0;
1094
1095 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1096 if(data <= 0x75)
1097 return 133;
1098 } else
1099 return 0;
1100
1101 return 0;
1102 }
1103
1104
1105 static int pdc20621_prog_dimm0(struct ata_host *host)
1106 {
1107 u32 spd0[50];
1108 u32 data = 0;
1109 int size, i;
1110 u8 bdimmsize;
1111 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1112 static const struct {
1113 unsigned int reg;
1114 unsigned int ofs;
1115 } pdc_i2c_read_data [] = {
1116 { PDC_DIMM_SPD_TYPE, 11 },
1117 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1118 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1119 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1120 { PDC_DIMM_SPD_ROW_NUM, 3 },
1121 { PDC_DIMM_SPD_BANK_NUM, 17 },
1122 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1123 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1124 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1125 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1126 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1127 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1128 };
1129
1130 /* hard-code chip #0 */
1131 mmio += PDC_CHIP0_OFS;
1132
1133 for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1134 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1135 pdc_i2c_read_data[i].reg,
1136 &spd0[pdc_i2c_read_data[i].ofs]);
1137
1138 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1139 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1140 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1141 data |= (((((spd0[29] > spd0[28])
1142 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1143 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1144
1145 if (spd0[18] & 0x08)
1146 data |= ((0x03) << 14);
1147 else if (spd0[18] & 0x04)
1148 data |= ((0x02) << 14);
1149 else if (spd0[18] & 0x01)
1150 data |= ((0x01) << 14);
1151 else
1152 data |= (0 << 14);
1153
1154 /*
1155 Calculate the size of bDIMMSize (power of 2) and
1156 merge the DIMM size by program start/end address.
1157 */
1158
1159 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1160 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
1161 data |= (((size / 16) - 1) << 16);
1162 data |= (0 << 23);
1163 data |= 8;
1164 writel(data, mmio + PDC_DIMM0_CONTROL);
1165 readl(mmio + PDC_DIMM0_CONTROL);
1166 return size;
1167 }
1168
1169
1170 static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
1171 {
1172 u32 data, spd0;
1173 int error, i;
1174 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1175
1176 /* hard-code chip #0 */
1177 mmio += PDC_CHIP0_OFS;
1178
1179 /*
1180 Set To Default : DIMM Module Global Control Register (0x022259F1)
1181 DIMM Arbitration Disable (bit 20)
1182 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1183 Refresh Enable (bit 17)
1184 */
1185
1186 data = 0x022259F1;
1187 writel(data, mmio + PDC_SDRAM_CONTROL);
1188 readl(mmio + PDC_SDRAM_CONTROL);
1189
1190 /* Turn on for ECC */
1191 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1192 PDC_DIMM_SPD_TYPE, &spd0);
1193 if (spd0 == 0x02) {
1194 data |= (0x01 << 16);
1195 writel(data, mmio + PDC_SDRAM_CONTROL);
1196 readl(mmio + PDC_SDRAM_CONTROL);
1197 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1198 }
1199
1200 /* DIMM Initialization Select/Enable (bit 18/19) */
1201 data &= (~(1<<18));
1202 data |= (1<<19);
1203 writel(data, mmio + PDC_SDRAM_CONTROL);
1204
1205 error = 1;
1206 for (i = 1; i <= 10; i++) { /* polling ~5 secs */
1207 data = readl(mmio + PDC_SDRAM_CONTROL);
1208 if (!(data & (1<<19))) {
1209 error = 0;
1210 break;
1211 }
1212 msleep(i*100);
1213 }
1214 return error;
1215 }
1216
1217
1218 static unsigned int pdc20621_dimm_init(struct ata_host *host)
1219 {
1220 int speed, size, length;
1221 u32 addr,spd0,pci_status;
1222 u32 tmp=0;
1223 u32 time_period=0;
1224 u32 tcount=0;
1225 u32 ticks=0;
1226 u32 clock=0;
1227 u32 fparam=0;
1228 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1229
1230 /* hard-code chip #0 */
1231 mmio += PDC_CHIP0_OFS;
1232
1233 /* Initialize PLL based upon PCI Bus Frequency */
1234
1235 /* Initialize Time Period Register */
1236 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1237 time_period = readl(mmio + PDC_TIME_PERIOD);
1238 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1239
1240 /* Enable timer */
1241 writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
1242 readl(mmio + PDC_TIME_CONTROL);
1243
1244 /* Wait 3 seconds */
1245 msleep(3000);
1246
1247 /*
1248 When timer is enabled, counter is decreased every internal
1249 clock cycle.
1250 */
1251
1252 tcount = readl(mmio + PDC_TIME_COUNTER);
1253 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1254
1255 /*
1256 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1257 register should be >= (0xffffffff - 3x10^8).
1258 */
1259 if(tcount >= PCI_X_TCOUNT) {
1260 ticks = (time_period - tcount);
1261 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1262
1263 clock = (ticks / 300000);
1264 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1265
1266 clock = (clock * 33);
1267 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1268
1269 /* PLL F Param (bit 22:16) */
1270 fparam = (1400000 / clock) - 2;
1271 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1272
1273 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1274 pci_status = (0x8a001824 | (fparam << 16));
1275 } else
1276 pci_status = PCI_PLL_INIT;
1277
1278 /* Initialize PLL. */
1279 VPRINTK("pci_status: 0x%x\n", pci_status);
1280 writel(pci_status, mmio + PDC_CTL_STATUS);
1281 readl(mmio + PDC_CTL_STATUS);
1282
1283 /*
1284 Read SPD of DIMM by I2C interface,
1285 and program the DIMM Module Controller.
1286 */
1287 if (!(speed = pdc20621_detect_dimm(host))) {
1288 printk(KERN_ERR "Detect Local DIMM Fail\n");
1289 return 1; /* DIMM error */
1290 }
1291 VPRINTK("Local DIMM Speed = %d\n", speed);
1292
1293 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1294 size = pdc20621_prog_dimm0(host);
1295 VPRINTK("Local DIMM Size = %dMB\n",size);
1296
1297 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1298 if (pdc20621_prog_dimm_global(host)) {
1299 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1300 return 1;
1301 }
1302
1303 #ifdef ATA_VERBOSE_DEBUG
1304 {
1305 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1306 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1307 '1','.','1','0',
1308 '9','8','0','3','1','6','1','2',0,0};
1309 u8 test_parttern2[40] = {0};
1310
1311 pdc20621_put_to_dimm(host, (void *) test_parttern2, 0x10040, 40);
1312 pdc20621_put_to_dimm(host, (void *) test_parttern2, 0x40, 40);
1313
1314 pdc20621_put_to_dimm(host, (void *) test_parttern1, 0x10040, 40);
1315 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x40, 40);
1316 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1317 test_parttern2[1], &(test_parttern2[2]));
1318 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x10040,
1319 40);
1320 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1321 test_parttern2[1], &(test_parttern2[2]));
1322
1323 pdc20621_put_to_dimm(host, (void *) test_parttern1, 0x40, 40);
1324 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x40, 40);
1325 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1326 test_parttern2[1], &(test_parttern2[2]));
1327 }
1328 #endif
1329
1330 /* ECC initiliazation. */
1331
1332 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1333 PDC_DIMM_SPD_TYPE, &spd0);
1334 if (spd0 == 0x02) {
1335 VPRINTK("Start ECC initialization\n");
1336 addr = 0;
1337 length = size * 1024 * 1024;
1338 while (addr < length) {
1339 pdc20621_put_to_dimm(host, (void *) &tmp, addr,
1340 sizeof(u32));
1341 addr += sizeof(u32);
1342 }
1343 VPRINTK("Finish ECC initialization\n");
1344 }
1345 return 0;
1346 }
1347
1348
1349 static void pdc_20621_init(struct ata_host *host)
1350 {
1351 u32 tmp;
1352 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1353
1354 /* hard-code chip #0 */
1355 mmio += PDC_CHIP0_OFS;
1356
1357 /*
1358 * Select page 0x40 for our 32k DIMM window
1359 */
1360 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1361 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1362 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1363
1364 /*
1365 * Reset Host DMA
1366 */
1367 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1368 tmp |= PDC_RESET;
1369 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1370 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1371
1372 udelay(10);
1373
1374 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1375 tmp &= ~PDC_RESET;
1376 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1377 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1378 }
1379
1380 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1381 {
1382 static int printed_version;
1383 const struct ata_port_info *ppi[] =
1384 { &pdc_port_info[ent->driver_data], NULL };
1385 struct ata_host *host;
1386 void __iomem *base;
1387 struct pdc_host_priv *hpriv;
1388 int rc;
1389
1390 if (!printed_version++)
1391 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1392
1393 /* allocate host */
1394 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
1395 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1396 if (!host || !hpriv)
1397 return -ENOMEM;
1398
1399 host->private_data = hpriv;
1400
1401 /* acquire resources and fill host */
1402 rc = pcim_enable_device(pdev);
1403 if (rc)
1404 return rc;
1405
1406 rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR),
1407 DRV_NAME);
1408 if (rc == -EBUSY)
1409 pcim_pin_device(pdev);
1410 if (rc)
1411 return rc;
1412 host->iomap = pcim_iomap_table(pdev);
1413
1414 base = host->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
1415 pdc_sata_setup_port(&host->ports[0]->ioaddr, base + 0x200);
1416 pdc_sata_setup_port(&host->ports[1]->ioaddr, base + 0x280);
1417 pdc_sata_setup_port(&host->ports[2]->ioaddr, base + 0x300);
1418 pdc_sata_setup_port(&host->ports[3]->ioaddr, base + 0x380);
1419
1420 /* configure and activate */
1421 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1422 if (rc)
1423 return rc;
1424 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1425 if (rc)
1426 return rc;
1427
1428 if (pdc20621_dimm_init(host))
1429 return -ENOMEM;
1430 pdc_20621_init(host);
1431
1432 pci_set_master(pdev);
1433 return ata_host_activate(host, pdev->irq, pdc20621_interrupt,
1434 IRQF_SHARED, &pdc_sata_sht);
1435 }
1436
1437
1438 static int __init pdc_sata_init(void)
1439 {
1440 return pci_register_driver(&pdc_sata_pci_driver);
1441 }
1442
1443
1444 static void __exit pdc_sata_exit(void)
1445 {
1446 pci_unregister_driver(&pdc_sata_pci_driver);
1447 }
1448
1449
1450 MODULE_AUTHOR("Jeff Garzik");
1451 MODULE_DESCRIPTION("Promise SATA low-level driver");
1452 MODULE_LICENSE("GPL");
1453 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1454 MODULE_VERSION(DRV_VERSION);
1455
1456 module_init(pdc_sata_init);
1457 module_exit(pdc_sata_exit);
Support for the Chinese Samsung S3C2440 based development boards