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KVM: VMX: Handle vmx instruction vmexits
[linux-2.6/mini2440.git] / arch / x86 / kvm / vmx.c
blobfa0adcd8a36f12b4e526f7ac1989f4b9e8847f69
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include "kvm_cache_regs.h"
29 #include "x86.h"
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33 #include <asm/vmx.h>
34 #include <asm/virtext.h>
35 #include <asm/mce.h>
36
37 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38
39 MODULE_AUTHOR("Qumranet");
40 MODULE_LICENSE("GPL");
41
42 static int bypass_guest_pf = 1;
43 module_param(bypass_guest_pf, bool, 0);
44
45 static int enable_vpid = 1;
46 module_param(enable_vpid, bool, 0);
47
48 static int flexpriority_enabled = 1;
49 module_param(flexpriority_enabled, bool, 0);
50
51 static int enable_ept = 1;
52 module_param(enable_ept, bool, 0);
53
54 static int emulate_invalid_guest_state = 0;
55 module_param(emulate_invalid_guest_state, bool, 0);
56
57 struct vmcs {
58 u32 revision_id;
59 u32 abort;
60 char data[0];
61 };
62
63 struct vcpu_vmx {
64 struct kvm_vcpu vcpu;
65 struct list_head local_vcpus_link;
66 unsigned long host_rsp;
67 int launched;
68 u8 fail;
69 u32 idt_vectoring_info;
70 struct kvm_msr_entry *guest_msrs;
71 struct kvm_msr_entry *host_msrs;
72 int nmsrs;
73 int save_nmsrs;
74 int msr_offset_efer;
75 #ifdef CONFIG_X86_64
76 int msr_offset_kernel_gs_base;
77 #endif
78 struct vmcs *vmcs;
79 struct {
80 int loaded;
81 u16 fs_sel, gs_sel, ldt_sel;
82 int gs_ldt_reload_needed;
83 int fs_reload_needed;
84 int guest_efer_loaded;
85 } host_state;
86 struct {
87 struct {
88 bool pending;
89 u8 vector;
90 unsigned rip;
91 } irq;
92 } rmode;
93 int vpid;
94 bool emulation_required;
95 enum emulation_result invalid_state_emulation_result;
96
97 /* Support for vnmi-less CPUs */
98 int soft_vnmi_blocked;
99 ktime_t entry_time;
100 s64 vnmi_blocked_time;
101
102 u32 exit_reason;
103 };
104
105 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
106 {
107 return container_of(vcpu, struct vcpu_vmx, vcpu);
108 }
109
110 static int init_rmode(struct kvm *kvm);
111 static u64 construct_eptp(unsigned long root_hpa);
112
113 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
114 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
115 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
116
117 static struct page *vmx_io_bitmap_a;
118 static struct page *vmx_io_bitmap_b;
119 static struct page *vmx_msr_bitmap;
120
121 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
122 static DEFINE_SPINLOCK(vmx_vpid_lock);
123
124 static struct vmcs_config {
125 int size;
126 int order;
127 u32 revision_id;
128 u32 pin_based_exec_ctrl;
129 u32 cpu_based_exec_ctrl;
130 u32 cpu_based_2nd_exec_ctrl;
131 u32 vmexit_ctrl;
132 u32 vmentry_ctrl;
133 } vmcs_config;
134
135 static struct vmx_capability {
136 u32 ept;
137 u32 vpid;
138 } vmx_capability;
139
140 #define VMX_SEGMENT_FIELD(seg) \
141 [VCPU_SREG_##seg] = { \
142 .selector = GUEST_##seg##_SELECTOR, \
143 .base = GUEST_##seg##_BASE, \
144 .limit = GUEST_##seg##_LIMIT, \
145 .ar_bytes = GUEST_##seg##_AR_BYTES, \
146 }
147
148 static struct kvm_vmx_segment_field {
149 unsigned selector;
150 unsigned base;
151 unsigned limit;
152 unsigned ar_bytes;
153 } kvm_vmx_segment_fields[] = {
154 VMX_SEGMENT_FIELD(CS),
155 VMX_SEGMENT_FIELD(DS),
156 VMX_SEGMENT_FIELD(ES),
157 VMX_SEGMENT_FIELD(FS),
158 VMX_SEGMENT_FIELD(GS),
159 VMX_SEGMENT_FIELD(SS),
160 VMX_SEGMENT_FIELD(TR),
161 VMX_SEGMENT_FIELD(LDTR),
162 };
163
164 /*
165 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
166 * away by decrementing the array size.
167 */
168 static const u32 vmx_msr_index[] = {
169 #ifdef CONFIG_X86_64
170 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
171 #endif
172 MSR_EFER, MSR_K6_STAR,
173 };
174 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
175
176 static void load_msrs(struct kvm_msr_entry *e, int n)
177 {
178 int i;
179
180 for (i = 0; i < n; ++i)
181 wrmsrl(e[i].index, e[i].data);
182 }
183
184 static void save_msrs(struct kvm_msr_entry *e, int n)
185 {
186 int i;
187
188 for (i = 0; i < n; ++i)
189 rdmsrl(e[i].index, e[i].data);
190 }
191
192 static inline int is_page_fault(u32 intr_info)
193 {
194 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
195 INTR_INFO_VALID_MASK)) ==
196 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
197 }
198
199 static inline int is_no_device(u32 intr_info)
200 {
201 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
202 INTR_INFO_VALID_MASK)) ==
203 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
204 }
205
206 static inline int is_invalid_opcode(u32 intr_info)
207 {
208 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
209 INTR_INFO_VALID_MASK)) ==
210 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
211 }
212
213 static inline int is_external_interrupt(u32 intr_info)
214 {
215 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
216 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
217 }
218
219 static inline int cpu_has_vmx_msr_bitmap(void)
220 {
221 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
222 }
223
224 static inline int cpu_has_vmx_tpr_shadow(void)
225 {
226 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
227 }
228
229 static inline int vm_need_tpr_shadow(struct kvm *kvm)
230 {
231 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
232 }
233
234 static inline int cpu_has_secondary_exec_ctrls(void)
235 {
236 return (vmcs_config.cpu_based_exec_ctrl &
237 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
238 }
239
240 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
241 {
242 return flexpriority_enabled
243 && (vmcs_config.cpu_based_2nd_exec_ctrl &
244 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
245 }
246
247 static inline int cpu_has_vmx_invept_individual_addr(void)
248 {
249 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
250 }
251
252 static inline int cpu_has_vmx_invept_context(void)
253 {
254 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
255 }
256
257 static inline int cpu_has_vmx_invept_global(void)
258 {
259 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
260 }
261
262 static inline int cpu_has_vmx_ept(void)
263 {
264 return (vmcs_config.cpu_based_2nd_exec_ctrl &
265 SECONDARY_EXEC_ENABLE_EPT);
266 }
267
268 static inline int vm_need_ept(void)
269 {
270 return (cpu_has_vmx_ept() && enable_ept);
271 }
272
273 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
274 {
275 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
276 (irqchip_in_kernel(kvm)));
277 }
278
279 static inline int cpu_has_vmx_vpid(void)
280 {
281 return (vmcs_config.cpu_based_2nd_exec_ctrl &
282 SECONDARY_EXEC_ENABLE_VPID);
283 }
284
285 static inline int cpu_has_virtual_nmis(void)
286 {
287 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
288 }
289
290 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
291 {
292 int i;
293
294 for (i = 0; i < vmx->nmsrs; ++i)
295 if (vmx->guest_msrs[i].index == msr)
296 return i;
297 return -1;
298 }
299
300 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
301 {
302 struct {
303 u64 vpid : 16;
304 u64 rsvd : 48;
305 u64 gva;
306 } operand = { vpid, 0, gva };
307
308 asm volatile (__ex(ASM_VMX_INVVPID)
309 /* CF==1 or ZF==1 --> rc = -1 */
310 "; ja 1f ; ud2 ; 1:"
311 : : "a"(&operand), "c"(ext) : "cc", "memory");
312 }
313
314 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
315 {
316 struct {
317 u64 eptp, gpa;
318 } operand = {eptp, gpa};
319
320 asm volatile (__ex(ASM_VMX_INVEPT)
321 /* CF==1 or ZF==1 --> rc = -1 */
322 "; ja 1f ; ud2 ; 1:\n"
323 : : "a" (&operand), "c" (ext) : "cc", "memory");
324 }
325
326 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
327 {
328 int i;
329
330 i = __find_msr_index(vmx, msr);
331 if (i >= 0)
332 return &vmx->guest_msrs[i];
333 return NULL;
334 }
335
336 static void vmcs_clear(struct vmcs *vmcs)
337 {
338 u64 phys_addr = __pa(vmcs);
339 u8 error;
340
341 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
342 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
343 : "cc", "memory");
344 if (error)
345 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
346 vmcs, phys_addr);
347 }
348
349 static void __vcpu_clear(void *arg)
350 {
351 struct vcpu_vmx *vmx = arg;
352 int cpu = raw_smp_processor_id();
353
354 if (vmx->vcpu.cpu == cpu)
355 vmcs_clear(vmx->vmcs);
356 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
357 per_cpu(current_vmcs, cpu) = NULL;
358 rdtscll(vmx->vcpu.arch.host_tsc);
359 list_del(&vmx->local_vcpus_link);
360 vmx->vcpu.cpu = -1;
361 vmx->launched = 0;
362 }
363
364 static void vcpu_clear(struct vcpu_vmx *vmx)
365 {
366 if (vmx->vcpu.cpu == -1)
367 return;
368 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
369 }
370
371 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
372 {
373 if (vmx->vpid == 0)
374 return;
375
376 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
377 }
378
379 static inline void ept_sync_global(void)
380 {
381 if (cpu_has_vmx_invept_global())
382 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
383 }
384
385 static inline void ept_sync_context(u64 eptp)
386 {
387 if (vm_need_ept()) {
388 if (cpu_has_vmx_invept_context())
389 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
390 else
391 ept_sync_global();
392 }
393 }
394
395 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
396 {
397 if (vm_need_ept()) {
398 if (cpu_has_vmx_invept_individual_addr())
399 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
400 eptp, gpa);
401 else
402 ept_sync_context(eptp);
403 }
404 }
405
406 static unsigned long vmcs_readl(unsigned long field)
407 {
408 unsigned long value;
409
410 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
411 : "=a"(value) : "d"(field) : "cc");
412 return value;
413 }
414
415 static u16 vmcs_read16(unsigned long field)
416 {
417 return vmcs_readl(field);
418 }
419
420 static u32 vmcs_read32(unsigned long field)
421 {
422 return vmcs_readl(field);
423 }
424
425 static u64 vmcs_read64(unsigned long field)
426 {
427 #ifdef CONFIG_X86_64
428 return vmcs_readl(field);
429 #else
430 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
431 #endif
432 }
433
434 static noinline void vmwrite_error(unsigned long field, unsigned long value)
435 {
436 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
437 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
438 dump_stack();
439 }
440
441 static void vmcs_writel(unsigned long field, unsigned long value)
442 {
443 u8 error;
444
445 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
446 : "=q"(error) : "a"(value), "d"(field) : "cc");
447 if (unlikely(error))
448 vmwrite_error(field, value);
449 }
450
451 static void vmcs_write16(unsigned long field, u16 value)
452 {
453 vmcs_writel(field, value);
454 }
455
456 static void vmcs_write32(unsigned long field, u32 value)
457 {
458 vmcs_writel(field, value);
459 }
460
461 static void vmcs_write64(unsigned long field, u64 value)
462 {
463 vmcs_writel(field, value);
464 #ifndef CONFIG_X86_64
465 asm volatile ("");
466 vmcs_writel(field+1, value >> 32);
467 #endif
468 }
469
470 static void vmcs_clear_bits(unsigned long field, u32 mask)
471 {
472 vmcs_writel(field, vmcs_readl(field) & ~mask);
473 }
474
475 static void vmcs_set_bits(unsigned long field, u32 mask)
476 {
477 vmcs_writel(field, vmcs_readl(field) | mask);
478 }
479
480 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
481 {
482 u32 eb;
483
484 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
485 if (!vcpu->fpu_active)
486 eb |= 1u << NM_VECTOR;
487 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
488 if (vcpu->guest_debug &
489 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
490 eb |= 1u << DB_VECTOR;
491 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
492 eb |= 1u << BP_VECTOR;
493 }
494 if (vcpu->arch.rmode.active)
495 eb = ~0;
496 if (vm_need_ept())
497 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
498 vmcs_write32(EXCEPTION_BITMAP, eb);
499 }
500
501 static void reload_tss(void)
502 {
503 /*
504 * VT restores TR but not its size. Useless.
505 */
506 struct descriptor_table gdt;
507 struct desc_struct *descs;
508
509 kvm_get_gdt(&gdt);
510 descs = (void *)gdt.base;
511 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
512 load_TR_desc();
513 }
514
515 static void load_transition_efer(struct vcpu_vmx *vmx)
516 {
517 int efer_offset = vmx->msr_offset_efer;
518 u64 host_efer = vmx->host_msrs[efer_offset].data;
519 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
520 u64 ignore_bits;
521
522 if (efer_offset < 0)
523 return;
524 /*
525 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
526 * outside long mode
527 */
528 ignore_bits = EFER_NX | EFER_SCE;
529 #ifdef CONFIG_X86_64
530 ignore_bits |= EFER_LMA | EFER_LME;
531 /* SCE is meaningful only in long mode on Intel */
532 if (guest_efer & EFER_LMA)
533 ignore_bits &= ~(u64)EFER_SCE;
534 #endif
535 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
536 return;
537
538 vmx->host_state.guest_efer_loaded = 1;
539 guest_efer &= ~ignore_bits;
540 guest_efer |= host_efer & ignore_bits;
541 wrmsrl(MSR_EFER, guest_efer);
542 vmx->vcpu.stat.efer_reload++;
543 }
544
545 static void reload_host_efer(struct vcpu_vmx *vmx)
546 {
547 if (vmx->host_state.guest_efer_loaded) {
548 vmx->host_state.guest_efer_loaded = 0;
549 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
550 }
551 }
552
553 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
554 {
555 struct vcpu_vmx *vmx = to_vmx(vcpu);
556
557 if (vmx->host_state.loaded)
558 return;
559
560 vmx->host_state.loaded = 1;
561 /*
562 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
563 * allow segment selectors with cpl > 0 or ti == 1.
564 */
565 vmx->host_state.ldt_sel = kvm_read_ldt();
566 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
567 vmx->host_state.fs_sel = kvm_read_fs();
568 if (!(vmx->host_state.fs_sel & 7)) {
569 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
570 vmx->host_state.fs_reload_needed = 0;
571 } else {
572 vmcs_write16(HOST_FS_SELECTOR, 0);
573 vmx->host_state.fs_reload_needed = 1;
574 }
575 vmx->host_state.gs_sel = kvm_read_gs();
576 if (!(vmx->host_state.gs_sel & 7))
577 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
578 else {
579 vmcs_write16(HOST_GS_SELECTOR, 0);
580 vmx->host_state.gs_ldt_reload_needed = 1;
581 }
582
583 #ifdef CONFIG_X86_64
584 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
585 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
586 #else
587 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
588 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
589 #endif
590
591 #ifdef CONFIG_X86_64
592 if (is_long_mode(&vmx->vcpu))
593 save_msrs(vmx->host_msrs +
594 vmx->msr_offset_kernel_gs_base, 1);
595
596 #endif
597 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
598 load_transition_efer(vmx);
599 }
600
601 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
602 {
603 unsigned long flags;
604
605 if (!vmx->host_state.loaded)
606 return;
607
608 ++vmx->vcpu.stat.host_state_reload;
609 vmx->host_state.loaded = 0;
610 if (vmx->host_state.fs_reload_needed)
611 kvm_load_fs(vmx->host_state.fs_sel);
612 if (vmx->host_state.gs_ldt_reload_needed) {
613 kvm_load_ldt(vmx->host_state.ldt_sel);
614 /*
615 * If we have to reload gs, we must take care to
616 * preserve our gs base.
617 */
618 local_irq_save(flags);
619 kvm_load_gs(vmx->host_state.gs_sel);
620 #ifdef CONFIG_X86_64
621 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
622 #endif
623 local_irq_restore(flags);
624 }
625 reload_tss();
626 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
627 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
628 reload_host_efer(vmx);
629 }
630
631 static void vmx_load_host_state(struct vcpu_vmx *vmx)
632 {
633 preempt_disable();
634 __vmx_load_host_state(vmx);
635 preempt_enable();
636 }
637
638 /*
639 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
640 * vcpu mutex is already taken.
641 */
642 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
643 {
644 struct vcpu_vmx *vmx = to_vmx(vcpu);
645 u64 phys_addr = __pa(vmx->vmcs);
646 u64 tsc_this, delta, new_offset;
647
648 if (vcpu->cpu != cpu) {
649 vcpu_clear(vmx);
650 kvm_migrate_timers(vcpu);
651 vpid_sync_vcpu_all(vmx);
652 local_irq_disable();
653 list_add(&vmx->local_vcpus_link,
654 &per_cpu(vcpus_on_cpu, cpu));
655 local_irq_enable();
656 }
657
658 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
659 u8 error;
660
661 per_cpu(current_vmcs, cpu) = vmx->vmcs;
662 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
663 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
664 : "cc");
665 if (error)
666 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
667 vmx->vmcs, phys_addr);
668 }
669
670 if (vcpu->cpu != cpu) {
671 struct descriptor_table dt;
672 unsigned long sysenter_esp;
673
674 vcpu->cpu = cpu;
675 /*
676 * Linux uses per-cpu TSS and GDT, so set these when switching
677 * processors.
678 */
679 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
680 kvm_get_gdt(&dt);
681 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
682
683 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
684 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
685
686 /*
687 * Make sure the time stamp counter is monotonous.
688 */
689 rdtscll(tsc_this);
690 if (tsc_this < vcpu->arch.host_tsc) {
691 delta = vcpu->arch.host_tsc - tsc_this;
692 new_offset = vmcs_read64(TSC_OFFSET) + delta;
693 vmcs_write64(TSC_OFFSET, new_offset);
694 }
695 }
696 }
697
698 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
699 {
700 __vmx_load_host_state(to_vmx(vcpu));
701 }
702
703 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
704 {
705 if (vcpu->fpu_active)
706 return;
707 vcpu->fpu_active = 1;
708 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
709 if (vcpu->arch.cr0 & X86_CR0_TS)
710 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
711 update_exception_bitmap(vcpu);
712 }
713
714 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
715 {
716 if (!vcpu->fpu_active)
717 return;
718 vcpu->fpu_active = 0;
719 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
720 update_exception_bitmap(vcpu);
721 }
722
723 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
724 {
725 return vmcs_readl(GUEST_RFLAGS);
726 }
727
728 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
729 {
730 if (vcpu->arch.rmode.active)
731 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
732 vmcs_writel(GUEST_RFLAGS, rflags);
733 }
734
735 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
736 {
737 unsigned long rip;
738 u32 interruptibility;
739
740 rip = kvm_rip_read(vcpu);
741 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
742 kvm_rip_write(vcpu, rip);
743
744 /*
745 * We emulated an instruction, so temporary interrupt blocking
746 * should be removed, if set.
747 */
748 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
749 if (interruptibility & 3)
750 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
751 interruptibility & ~3);
752 vcpu->arch.interrupt_window_open = 1;
753 }
754
755 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
756 bool has_error_code, u32 error_code)
757 {
758 struct vcpu_vmx *vmx = to_vmx(vcpu);
759 u32 intr_info = nr | INTR_INFO_VALID_MASK;
760
761 if (has_error_code) {
762 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
763 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
764 }
765
766 if (vcpu->arch.rmode.active) {
767 vmx->rmode.irq.pending = true;
768 vmx->rmode.irq.vector = nr;
769 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
770 if (nr == BP_VECTOR || nr == OF_VECTOR)
771 vmx->rmode.irq.rip++;
772 intr_info |= INTR_TYPE_SOFT_INTR;
773 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
774 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
775 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
776 return;
777 }
778
779 if (nr == BP_VECTOR || nr == OF_VECTOR) {
780 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
781 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
782 } else
783 intr_info |= INTR_TYPE_HARD_EXCEPTION;
784
785 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
786 }
787
788 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
789 {
790 return false;
791 }
792
793 /*
794 * Swap MSR entry in host/guest MSR entry array.
795 */
796 #ifdef CONFIG_X86_64
797 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
798 {
799 struct kvm_msr_entry tmp;
800
801 tmp = vmx->guest_msrs[to];
802 vmx->guest_msrs[to] = vmx->guest_msrs[from];
803 vmx->guest_msrs[from] = tmp;
804 tmp = vmx->host_msrs[to];
805 vmx->host_msrs[to] = vmx->host_msrs[from];
806 vmx->host_msrs[from] = tmp;
807 }
808 #endif
809
810 /*
811 * Set up the vmcs to automatically save and restore system
812 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
813 * mode, as fiddling with msrs is very expensive.
814 */
815 static void setup_msrs(struct vcpu_vmx *vmx)
816 {
817 int save_nmsrs;
818
819 vmx_load_host_state(vmx);
820 save_nmsrs = 0;
821 #ifdef CONFIG_X86_64
822 if (is_long_mode(&vmx->vcpu)) {
823 int index;
824
825 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
826 if (index >= 0)
827 move_msr_up(vmx, index, save_nmsrs++);
828 index = __find_msr_index(vmx, MSR_LSTAR);
829 if (index >= 0)
830 move_msr_up(vmx, index, save_nmsrs++);
831 index = __find_msr_index(vmx, MSR_CSTAR);
832 if (index >= 0)
833 move_msr_up(vmx, index, save_nmsrs++);
834 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
835 if (index >= 0)
836 move_msr_up(vmx, index, save_nmsrs++);
837 /*
838 * MSR_K6_STAR is only needed on long mode guests, and only
839 * if efer.sce is enabled.
840 */
841 index = __find_msr_index(vmx, MSR_K6_STAR);
842 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
843 move_msr_up(vmx, index, save_nmsrs++);
844 }
845 #endif
846 vmx->save_nmsrs = save_nmsrs;
847
848 #ifdef CONFIG_X86_64
849 vmx->msr_offset_kernel_gs_base =
850 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
851 #endif
852 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
853 }
854
855 /*
856 * reads and returns guest's timestamp counter "register"
857 * guest_tsc = host_tsc + tsc_offset -- 21.3
858 */
859 static u64 guest_read_tsc(void)
860 {
861 u64 host_tsc, tsc_offset;
862
863 rdtscll(host_tsc);
864 tsc_offset = vmcs_read64(TSC_OFFSET);
865 return host_tsc + tsc_offset;
866 }
867
868 /*
869 * writes 'guest_tsc' into guest's timestamp counter "register"
870 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
871 */
872 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
873 {
874 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
875 }
876
877 /*
878 * Reads an msr value (of 'msr_index') into 'pdata'.
879 * Returns 0 on success, non-0 otherwise.
880 * Assumes vcpu_load() was already called.
881 */
882 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
883 {
884 u64 data;
885 struct kvm_msr_entry *msr;
886
887 if (!pdata) {
888 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
889 return -EINVAL;
890 }
891
892 switch (msr_index) {
893 #ifdef CONFIG_X86_64
894 case MSR_FS_BASE:
895 data = vmcs_readl(GUEST_FS_BASE);
896 break;
897 case MSR_GS_BASE:
898 data = vmcs_readl(GUEST_GS_BASE);
899 break;
900 case MSR_EFER:
901 return kvm_get_msr_common(vcpu, msr_index, pdata);
902 #endif
903 case MSR_IA32_TIME_STAMP_COUNTER:
904 data = guest_read_tsc();
905 break;
906 case MSR_IA32_SYSENTER_CS:
907 data = vmcs_read32(GUEST_SYSENTER_CS);
908 break;
909 case MSR_IA32_SYSENTER_EIP:
910 data = vmcs_readl(GUEST_SYSENTER_EIP);
911 break;
912 case MSR_IA32_SYSENTER_ESP:
913 data = vmcs_readl(GUEST_SYSENTER_ESP);
914 break;
915 default:
916 vmx_load_host_state(to_vmx(vcpu));
917 msr = find_msr_entry(to_vmx(vcpu), msr_index);
918 if (msr) {
919 data = msr->data;
920 break;
921 }
922 return kvm_get_msr_common(vcpu, msr_index, pdata);
923 }
924
925 *pdata = data;
926 return 0;
927 }
928
929 /*
930 * Writes msr value into into the appropriate "register".
931 * Returns 0 on success, non-0 otherwise.
932 * Assumes vcpu_load() was already called.
933 */
934 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
935 {
936 struct vcpu_vmx *vmx = to_vmx(vcpu);
937 struct kvm_msr_entry *msr;
938 u64 host_tsc;
939 int ret = 0;
940
941 switch (msr_index) {
942 case MSR_EFER:
943 vmx_load_host_state(vmx);
944 ret = kvm_set_msr_common(vcpu, msr_index, data);
945 break;
946 #ifdef CONFIG_X86_64
947 case MSR_FS_BASE:
948 vmcs_writel(GUEST_FS_BASE, data);
949 break;
950 case MSR_GS_BASE:
951 vmcs_writel(GUEST_GS_BASE, data);
952 break;
953 #endif
954 case MSR_IA32_SYSENTER_CS:
955 vmcs_write32(GUEST_SYSENTER_CS, data);
956 break;
957 case MSR_IA32_SYSENTER_EIP:
958 vmcs_writel(GUEST_SYSENTER_EIP, data);
959 break;
960 case MSR_IA32_SYSENTER_ESP:
961 vmcs_writel(GUEST_SYSENTER_ESP, data);
962 break;
963 case MSR_IA32_TIME_STAMP_COUNTER:
964 rdtscll(host_tsc);
965 guest_write_tsc(data, host_tsc);
966 break;
967 case MSR_P6_PERFCTR0:
968 case MSR_P6_PERFCTR1:
969 case MSR_P6_EVNTSEL0:
970 case MSR_P6_EVNTSEL1:
971 /*
972 * Just discard all writes to the performance counters; this
973 * should keep both older linux and windows 64-bit guests
974 * happy
975 */
976 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
977
978 break;
979 case MSR_IA32_CR_PAT:
980 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
981 vmcs_write64(GUEST_IA32_PAT, data);
982 vcpu->arch.pat = data;
983 break;
984 }
985 /* Otherwise falls through to kvm_set_msr_common */
986 default:
987 vmx_load_host_state(vmx);
988 msr = find_msr_entry(vmx, msr_index);
989 if (msr) {
990 msr->data = data;
991 break;
992 }
993 ret = kvm_set_msr_common(vcpu, msr_index, data);
994 }
995
996 return ret;
997 }
998
999 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1000 {
1001 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1002 switch (reg) {
1003 case VCPU_REGS_RSP:
1004 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1005 break;
1006 case VCPU_REGS_RIP:
1007 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1008 break;
1009 default:
1010 break;
1011 }
1012 }
1013
1014 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1015 {
1016 int old_debug = vcpu->guest_debug;
1017 unsigned long flags;
1018
1019 vcpu->guest_debug = dbg->control;
1020 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1021 vcpu->guest_debug = 0;
1022
1023 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1024 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1025 else
1026 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1027
1028 flags = vmcs_readl(GUEST_RFLAGS);
1029 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1030 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1031 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1032 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1033 vmcs_writel(GUEST_RFLAGS, flags);
1034
1035 update_exception_bitmap(vcpu);
1036
1037 return 0;
1038 }
1039
1040 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1041 {
1042 if (!vcpu->arch.interrupt.pending)
1043 return -1;
1044 return vcpu->arch.interrupt.nr;
1045 }
1046
1047 static __init int cpu_has_kvm_support(void)
1048 {
1049 return cpu_has_vmx();
1050 }
1051
1052 static __init int vmx_disabled_by_bios(void)
1053 {
1054 u64 msr;
1055
1056 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1057 return (msr & (FEATURE_CONTROL_LOCKED |
1058 FEATURE_CONTROL_VMXON_ENABLED))
1059 == FEATURE_CONTROL_LOCKED;
1060 /* locked but not enabled */
1061 }
1062
1063 static void hardware_enable(void *garbage)
1064 {
1065 int cpu = raw_smp_processor_id();
1066 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1067 u64 old;
1068
1069 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1070 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1071 if ((old & (FEATURE_CONTROL_LOCKED |
1072 FEATURE_CONTROL_VMXON_ENABLED))
1073 != (FEATURE_CONTROL_LOCKED |
1074 FEATURE_CONTROL_VMXON_ENABLED))
1075 /* enable and lock */
1076 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1077 FEATURE_CONTROL_LOCKED |
1078 FEATURE_CONTROL_VMXON_ENABLED);
1079 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1080 asm volatile (ASM_VMX_VMXON_RAX
1081 : : "a"(&phys_addr), "m"(phys_addr)
1082 : "memory", "cc");
1083 }
1084
1085 static void vmclear_local_vcpus(void)
1086 {
1087 int cpu = raw_smp_processor_id();
1088 struct vcpu_vmx *vmx, *n;
1089
1090 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1091 local_vcpus_link)
1092 __vcpu_clear(vmx);
1093 }
1094
1095
1096 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1097 * tricks.
1098 */
1099 static void kvm_cpu_vmxoff(void)
1100 {
1101 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1102 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1103 }
1104
1105 static void hardware_disable(void *garbage)
1106 {
1107 vmclear_local_vcpus();
1108 kvm_cpu_vmxoff();
1109 }
1110
1111 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1112 u32 msr, u32 *result)
1113 {
1114 u32 vmx_msr_low, vmx_msr_high;
1115 u32 ctl = ctl_min | ctl_opt;
1116
1117 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1118
1119 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1120 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1121
1122 /* Ensure minimum (required) set of control bits are supported. */
1123 if (ctl_min & ~ctl)
1124 return -EIO;
1125
1126 *result = ctl;
1127 return 0;
1128 }
1129
1130 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1131 {
1132 u32 vmx_msr_low, vmx_msr_high;
1133 u32 min, opt, min2, opt2;
1134 u32 _pin_based_exec_control = 0;
1135 u32 _cpu_based_exec_control = 0;
1136 u32 _cpu_based_2nd_exec_control = 0;
1137 u32 _vmexit_control = 0;
1138 u32 _vmentry_control = 0;
1139
1140 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1141 opt = PIN_BASED_VIRTUAL_NMIS;
1142 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1143 &_pin_based_exec_control) < 0)
1144 return -EIO;
1145
1146 min = CPU_BASED_HLT_EXITING |
1147 #ifdef CONFIG_X86_64
1148 CPU_BASED_CR8_LOAD_EXITING |
1149 CPU_BASED_CR8_STORE_EXITING |
1150 #endif
1151 CPU_BASED_CR3_LOAD_EXITING |
1152 CPU_BASED_CR3_STORE_EXITING |
1153 CPU_BASED_USE_IO_BITMAPS |
1154 CPU_BASED_MOV_DR_EXITING |
1155 CPU_BASED_USE_TSC_OFFSETING |
1156 CPU_BASED_INVLPG_EXITING;
1157 opt = CPU_BASED_TPR_SHADOW |
1158 CPU_BASED_USE_MSR_BITMAPS |
1159 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1160 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1161 &_cpu_based_exec_control) < 0)
1162 return -EIO;
1163 #ifdef CONFIG_X86_64
1164 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1165 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1166 ~CPU_BASED_CR8_STORE_EXITING;
1167 #endif
1168 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1169 min2 = 0;
1170 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1171 SECONDARY_EXEC_WBINVD_EXITING |
1172 SECONDARY_EXEC_ENABLE_VPID |
1173 SECONDARY_EXEC_ENABLE_EPT;
1174 if (adjust_vmx_controls(min2, opt2,
1175 MSR_IA32_VMX_PROCBASED_CTLS2,
1176 &_cpu_based_2nd_exec_control) < 0)
1177 return -EIO;
1178 }
1179 #ifndef CONFIG_X86_64
1180 if (!(_cpu_based_2nd_exec_control &
1181 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1182 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1183 #endif
1184 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1185 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1186 enabled */
1187 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1188 CPU_BASED_CR3_STORE_EXITING |
1189 CPU_BASED_INVLPG_EXITING);
1190 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1191 &_cpu_based_exec_control) < 0)
1192 return -EIO;
1193 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1194 vmx_capability.ept, vmx_capability.vpid);
1195 }
1196
1197 min = 0;
1198 #ifdef CONFIG_X86_64
1199 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1200 #endif
1201 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1202 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1203 &_vmexit_control) < 0)
1204 return -EIO;
1205
1206 min = 0;
1207 opt = VM_ENTRY_LOAD_IA32_PAT;
1208 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1209 &_vmentry_control) < 0)
1210 return -EIO;
1211
1212 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1213
1214 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1215 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1216 return -EIO;
1217
1218 #ifdef CONFIG_X86_64
1219 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1220 if (vmx_msr_high & (1u<<16))
1221 return -EIO;
1222 #endif
1223
1224 /* Require Write-Back (WB) memory type for VMCS accesses. */
1225 if (((vmx_msr_high >> 18) & 15) != 6)
1226 return -EIO;
1227
1228 vmcs_conf->size = vmx_msr_high & 0x1fff;
1229 vmcs_conf->order = get_order(vmcs_config.size);
1230 vmcs_conf->revision_id = vmx_msr_low;
1231
1232 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1233 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1234 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1235 vmcs_conf->vmexit_ctrl = _vmexit_control;
1236 vmcs_conf->vmentry_ctrl = _vmentry_control;
1237
1238 return 0;
1239 }
1240
1241 static struct vmcs *alloc_vmcs_cpu(int cpu)
1242 {
1243 int node = cpu_to_node(cpu);
1244 struct page *pages;
1245 struct vmcs *vmcs;
1246
1247 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1248 if (!pages)
1249 return NULL;
1250 vmcs = page_address(pages);
1251 memset(vmcs, 0, vmcs_config.size);
1252 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1253 return vmcs;
1254 }
1255
1256 static struct vmcs *alloc_vmcs(void)
1257 {
1258 return alloc_vmcs_cpu(raw_smp_processor_id());
1259 }
1260
1261 static void free_vmcs(struct vmcs *vmcs)
1262 {
1263 free_pages((unsigned long)vmcs, vmcs_config.order);
1264 }
1265
1266 static void free_kvm_area(void)
1267 {
1268 int cpu;
1269
1270 for_each_online_cpu(cpu)
1271 free_vmcs(per_cpu(vmxarea, cpu));
1272 }
1273
1274 static __init int alloc_kvm_area(void)
1275 {
1276 int cpu;
1277
1278 for_each_online_cpu(cpu) {
1279 struct vmcs *vmcs;
1280
1281 vmcs = alloc_vmcs_cpu(cpu);
1282 if (!vmcs) {
1283 free_kvm_area();
1284 return -ENOMEM;
1285 }
1286
1287 per_cpu(vmxarea, cpu) = vmcs;
1288 }
1289 return 0;
1290 }
1291
1292 static __init int hardware_setup(void)
1293 {
1294 if (setup_vmcs_config(&vmcs_config) < 0)
1295 return -EIO;
1296
1297 if (boot_cpu_has(X86_FEATURE_NX))
1298 kvm_enable_efer_bits(EFER_NX);
1299
1300 return alloc_kvm_area();
1301 }
1302
1303 static __exit void hardware_unsetup(void)
1304 {
1305 free_kvm_area();
1306 }
1307
1308 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1309 {
1310 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1311
1312 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1313 vmcs_write16(sf->selector, save->selector);
1314 vmcs_writel(sf->base, save->base);
1315 vmcs_write32(sf->limit, save->limit);
1316 vmcs_write32(sf->ar_bytes, save->ar);
1317 } else {
1318 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1319 << AR_DPL_SHIFT;
1320 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1321 }
1322 }
1323
1324 static void enter_pmode(struct kvm_vcpu *vcpu)
1325 {
1326 unsigned long flags;
1327 struct vcpu_vmx *vmx = to_vmx(vcpu);
1328
1329 vmx->emulation_required = 1;
1330 vcpu->arch.rmode.active = 0;
1331
1332 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1333 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1334 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1335
1336 flags = vmcs_readl(GUEST_RFLAGS);
1337 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1338 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1339 vmcs_writel(GUEST_RFLAGS, flags);
1340
1341 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1342 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1343
1344 update_exception_bitmap(vcpu);
1345
1346 if (emulate_invalid_guest_state)
1347 return;
1348
1349 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1350 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1351 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1352 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1353
1354 vmcs_write16(GUEST_SS_SELECTOR, 0);
1355 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1356
1357 vmcs_write16(GUEST_CS_SELECTOR,
1358 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1359 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1360 }
1361
1362 static gva_t rmode_tss_base(struct kvm *kvm)
1363 {
1364 if (!kvm->arch.tss_addr) {
1365 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1366 kvm->memslots[0].npages - 3;
1367 return base_gfn << PAGE_SHIFT;
1368 }
1369 return kvm->arch.tss_addr;
1370 }
1371
1372 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1373 {
1374 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1375
1376 save->selector = vmcs_read16(sf->selector);
1377 save->base = vmcs_readl(sf->base);
1378 save->limit = vmcs_read32(sf->limit);
1379 save->ar = vmcs_read32(sf->ar_bytes);
1380 vmcs_write16(sf->selector, save->base >> 4);
1381 vmcs_write32(sf->base, save->base & 0xfffff);
1382 vmcs_write32(sf->limit, 0xffff);
1383 vmcs_write32(sf->ar_bytes, 0xf3);
1384 }
1385
1386 static void enter_rmode(struct kvm_vcpu *vcpu)
1387 {
1388 unsigned long flags;
1389 struct vcpu_vmx *vmx = to_vmx(vcpu);
1390
1391 vmx->emulation_required = 1;
1392 vcpu->arch.rmode.active = 1;
1393
1394 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1395 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1396
1397 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1398 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1399
1400 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1401 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1402
1403 flags = vmcs_readl(GUEST_RFLAGS);
1404 vcpu->arch.rmode.save_iopl
1405 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1406
1407 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1408
1409 vmcs_writel(GUEST_RFLAGS, flags);
1410 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1411 update_exception_bitmap(vcpu);
1412
1413 if (emulate_invalid_guest_state)
1414 goto continue_rmode;
1415
1416 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1417 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1418 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1419
1420 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1421 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1422 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1423 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1424 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1425
1426 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1427 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1428 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1429 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1430
1431 continue_rmode:
1432 kvm_mmu_reset_context(vcpu);
1433 init_rmode(vcpu->kvm);
1434 }
1435
1436 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1437 {
1438 struct vcpu_vmx *vmx = to_vmx(vcpu);
1439 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1440
1441 vcpu->arch.shadow_efer = efer;
1442 if (!msr)
1443 return;
1444 if (efer & EFER_LMA) {
1445 vmcs_write32(VM_ENTRY_CONTROLS,
1446 vmcs_read32(VM_ENTRY_CONTROLS) |
1447 VM_ENTRY_IA32E_MODE);
1448 msr->data = efer;
1449 } else {
1450 vmcs_write32(VM_ENTRY_CONTROLS,
1451 vmcs_read32(VM_ENTRY_CONTROLS) &
1452 ~VM_ENTRY_IA32E_MODE);
1453
1454 msr->data = efer & ~EFER_LME;
1455 }
1456 setup_msrs(vmx);
1457 }
1458
1459 #ifdef CONFIG_X86_64
1460
1461 static void enter_lmode(struct kvm_vcpu *vcpu)
1462 {
1463 u32 guest_tr_ar;
1464
1465 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1466 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1467 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1468 __func__);
1469 vmcs_write32(GUEST_TR_AR_BYTES,
1470 (guest_tr_ar & ~AR_TYPE_MASK)
1471 | AR_TYPE_BUSY_64_TSS);
1472 }
1473 vcpu->arch.shadow_efer |= EFER_LMA;
1474 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1475 }
1476
1477 static void exit_lmode(struct kvm_vcpu *vcpu)
1478 {
1479 vcpu->arch.shadow_efer &= ~EFER_LMA;
1480
1481 vmcs_write32(VM_ENTRY_CONTROLS,
1482 vmcs_read32(VM_ENTRY_CONTROLS)
1483 & ~VM_ENTRY_IA32E_MODE);
1484 }
1485
1486 #endif
1487
1488 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1489 {
1490 vpid_sync_vcpu_all(to_vmx(vcpu));
1491 if (vm_need_ept())
1492 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1493 }
1494
1495 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1496 {
1497 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1498 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1499 }
1500
1501 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1502 {
1503 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1504 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1505 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1506 return;
1507 }
1508 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1509 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1510 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1511 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1512 }
1513 }
1514
1515 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1516
1517 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1518 unsigned long cr0,
1519 struct kvm_vcpu *vcpu)
1520 {
1521 if (!(cr0 & X86_CR0_PG)) {
1522 /* From paging/starting to nonpaging */
1523 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1524 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1525 (CPU_BASED_CR3_LOAD_EXITING |
1526 CPU_BASED_CR3_STORE_EXITING));
1527 vcpu->arch.cr0 = cr0;
1528 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1529 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1530 *hw_cr0 &= ~X86_CR0_WP;
1531 } else if (!is_paging(vcpu)) {
1532 /* From nonpaging to paging */
1533 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1534 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1535 ~(CPU_BASED_CR3_LOAD_EXITING |
1536 CPU_BASED_CR3_STORE_EXITING));
1537 vcpu->arch.cr0 = cr0;
1538 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1539 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1540 *hw_cr0 &= ~X86_CR0_WP;
1541 }
1542 }
1543
1544 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1545 struct kvm_vcpu *vcpu)
1546 {
1547 if (!is_paging(vcpu)) {
1548 *hw_cr4 &= ~X86_CR4_PAE;
1549 *hw_cr4 |= X86_CR4_PSE;
1550 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1551 *hw_cr4 &= ~X86_CR4_PAE;
1552 }
1553
1554 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1555 {
1556 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1557 KVM_VM_CR0_ALWAYS_ON;
1558
1559 vmx_fpu_deactivate(vcpu);
1560
1561 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1562 enter_pmode(vcpu);
1563
1564 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1565 enter_rmode(vcpu);
1566
1567 #ifdef CONFIG_X86_64
1568 if (vcpu->arch.shadow_efer & EFER_LME) {
1569 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1570 enter_lmode(vcpu);
1571 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1572 exit_lmode(vcpu);
1573 }
1574 #endif
1575
1576 if (vm_need_ept())
1577 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1578
1579 vmcs_writel(CR0_READ_SHADOW, cr0);
1580 vmcs_writel(GUEST_CR0, hw_cr0);
1581 vcpu->arch.cr0 = cr0;
1582
1583 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1584 vmx_fpu_activate(vcpu);
1585 }
1586
1587 static u64 construct_eptp(unsigned long root_hpa)
1588 {
1589 u64 eptp;
1590
1591 /* TODO write the value reading from MSR */
1592 eptp = VMX_EPT_DEFAULT_MT |
1593 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1594 eptp |= (root_hpa & PAGE_MASK);
1595
1596 return eptp;
1597 }
1598
1599 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1600 {
1601 unsigned long guest_cr3;
1602 u64 eptp;
1603
1604 guest_cr3 = cr3;
1605 if (vm_need_ept()) {
1606 eptp = construct_eptp(cr3);
1607 vmcs_write64(EPT_POINTER, eptp);
1608 ept_sync_context(eptp);
1609 ept_load_pdptrs(vcpu);
1610 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1611 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1612 }
1613
1614 vmx_flush_tlb(vcpu);
1615 vmcs_writel(GUEST_CR3, guest_cr3);
1616 if (vcpu->arch.cr0 & X86_CR0_PE)
1617 vmx_fpu_deactivate(vcpu);
1618 }
1619
1620 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1621 {
1622 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1623 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1624
1625 vcpu->arch.cr4 = cr4;
1626 if (vm_need_ept())
1627 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1628
1629 vmcs_writel(CR4_READ_SHADOW, cr4);
1630 vmcs_writel(GUEST_CR4, hw_cr4);
1631 }
1632
1633 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1634 {
1635 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1636
1637 return vmcs_readl(sf->base);
1638 }
1639
1640 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1641 struct kvm_segment *var, int seg)
1642 {
1643 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1644 u32 ar;
1645
1646 var->base = vmcs_readl(sf->base);
1647 var->limit = vmcs_read32(sf->limit);
1648 var->selector = vmcs_read16(sf->selector);
1649 ar = vmcs_read32(sf->ar_bytes);
1650 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1651 ar = 0;
1652 var->type = ar & 15;
1653 var->s = (ar >> 4) & 1;
1654 var->dpl = (ar >> 5) & 3;
1655 var->present = (ar >> 7) & 1;
1656 var->avl = (ar >> 12) & 1;
1657 var->l = (ar >> 13) & 1;
1658 var->db = (ar >> 14) & 1;
1659 var->g = (ar >> 15) & 1;
1660 var->unusable = (ar >> 16) & 1;
1661 }
1662
1663 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1664 {
1665 struct kvm_segment kvm_seg;
1666
1667 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1668 return 0;
1669
1670 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1671 return 3;
1672
1673 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1674 return kvm_seg.selector & 3;
1675 }
1676
1677 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1678 {
1679 u32 ar;
1680
1681 if (var->unusable)
1682 ar = 1 << 16;
1683 else {
1684 ar = var->type & 15;
1685 ar |= (var->s & 1) << 4;
1686 ar |= (var->dpl & 3) << 5;
1687 ar |= (var->present & 1) << 7;
1688 ar |= (var->avl & 1) << 12;
1689 ar |= (var->l & 1) << 13;
1690 ar |= (var->db & 1) << 14;
1691 ar |= (var->g & 1) << 15;
1692 }
1693 if (ar == 0) /* a 0 value means unusable */
1694 ar = AR_UNUSABLE_MASK;
1695
1696 return ar;
1697 }
1698
1699 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1700 struct kvm_segment *var, int seg)
1701 {
1702 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1703 u32 ar;
1704
1705 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1706 vcpu->arch.rmode.tr.selector = var->selector;
1707 vcpu->arch.rmode.tr.base = var->base;
1708 vcpu->arch.rmode.tr.limit = var->limit;
1709 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1710 return;
1711 }
1712 vmcs_writel(sf->base, var->base);
1713 vmcs_write32(sf->limit, var->limit);
1714 vmcs_write16(sf->selector, var->selector);
1715 if (vcpu->arch.rmode.active && var->s) {
1716 /*
1717 * Hack real-mode segments into vm86 compatibility.
1718 */
1719 if (var->base == 0xffff0000 && var->selector == 0xf000)
1720 vmcs_writel(sf->base, 0xf0000);
1721 ar = 0xf3;
1722 } else
1723 ar = vmx_segment_access_rights(var);
1724 vmcs_write32(sf->ar_bytes, ar);
1725 }
1726
1727 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1728 {
1729 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1730
1731 *db = (ar >> 14) & 1;
1732 *l = (ar >> 13) & 1;
1733 }
1734
1735 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1736 {
1737 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1738 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1739 }
1740
1741 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1742 {
1743 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1744 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1745 }
1746
1747 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1748 {
1749 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1750 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1751 }
1752
1753 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1754 {
1755 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1756 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1757 }
1758
1759 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1760 {
1761 struct kvm_segment var;
1762 u32 ar;
1763
1764 vmx_get_segment(vcpu, &var, seg);
1765 ar = vmx_segment_access_rights(&var);
1766
1767 if (var.base != (var.selector << 4))
1768 return false;
1769 if (var.limit != 0xffff)
1770 return false;
1771 if (ar != 0xf3)
1772 return false;
1773
1774 return true;
1775 }
1776
1777 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1778 {
1779 struct kvm_segment cs;
1780 unsigned int cs_rpl;
1781
1782 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1783 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1784
1785 if (cs.unusable)
1786 return false;
1787 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1788 return false;
1789 if (!cs.s)
1790 return false;
1791 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1792 if (cs.dpl > cs_rpl)
1793 return false;
1794 } else {
1795 if (cs.dpl != cs_rpl)
1796 return false;
1797 }
1798 if (!cs.present)
1799 return false;
1800
1801 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1802 return true;
1803 }
1804
1805 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1806 {
1807 struct kvm_segment ss;
1808 unsigned int ss_rpl;
1809
1810 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1811 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1812
1813 if (ss.unusable)
1814 return true;
1815 if (ss.type != 3 && ss.type != 7)
1816 return false;
1817 if (!ss.s)
1818 return false;
1819 if (ss.dpl != ss_rpl) /* DPL != RPL */
1820 return false;
1821 if (!ss.present)
1822 return false;
1823
1824 return true;
1825 }
1826
1827 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1828 {
1829 struct kvm_segment var;
1830 unsigned int rpl;
1831
1832 vmx_get_segment(vcpu, &var, seg);
1833 rpl = var.selector & SELECTOR_RPL_MASK;
1834
1835 if (var.unusable)
1836 return true;
1837 if (!var.s)
1838 return false;
1839 if (!var.present)
1840 return false;
1841 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1842 if (var.dpl < rpl) /* DPL < RPL */
1843 return false;
1844 }
1845
1846 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1847 * rights flags
1848 */
1849 return true;
1850 }
1851
1852 static bool tr_valid(struct kvm_vcpu *vcpu)
1853 {
1854 struct kvm_segment tr;
1855
1856 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1857
1858 if (tr.unusable)
1859 return false;
1860 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1861 return false;
1862 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1863 return false;
1864 if (!tr.present)
1865 return false;
1866
1867 return true;
1868 }
1869
1870 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1871 {
1872 struct kvm_segment ldtr;
1873
1874 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1875
1876 if (ldtr.unusable)
1877 return true;
1878 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1879 return false;
1880 if (ldtr.type != 2)
1881 return false;
1882 if (!ldtr.present)
1883 return false;
1884
1885 return true;
1886 }
1887
1888 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1889 {
1890 struct kvm_segment cs, ss;
1891
1892 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1893 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1894
1895 return ((cs.selector & SELECTOR_RPL_MASK) ==
1896 (ss.selector & SELECTOR_RPL_MASK));
1897 }
1898
1899 /*
1900 * Check if guest state is valid. Returns true if valid, false if
1901 * not.
1902 * We assume that registers are always usable
1903 */
1904 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1905 {
1906 /* real mode guest state checks */
1907 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1908 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1909 return false;
1910 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1911 return false;
1912 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1913 return false;
1914 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1915 return false;
1916 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1917 return false;
1918 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1919 return false;
1920 } else {
1921 /* protected mode guest state checks */
1922 if (!cs_ss_rpl_check(vcpu))
1923 return false;
1924 if (!code_segment_valid(vcpu))
1925 return false;
1926 if (!stack_segment_valid(vcpu))
1927 return false;
1928 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1929 return false;
1930 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1931 return false;
1932 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1933 return false;
1934 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1935 return false;
1936 if (!tr_valid(vcpu))
1937 return false;
1938 if (!ldtr_valid(vcpu))
1939 return false;
1940 }
1941 /* TODO:
1942 * - Add checks on RIP
1943 * - Add checks on RFLAGS
1944 */
1945
1946 return true;
1947 }
1948
1949 static int init_rmode_tss(struct kvm *kvm)
1950 {
1951 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1952 u16 data = 0;
1953 int ret = 0;
1954 int r;
1955
1956 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1957 if (r < 0)
1958 goto out;
1959 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1960 r = kvm_write_guest_page(kvm, fn++, &data,
1961 TSS_IOPB_BASE_OFFSET, sizeof(u16));
1962 if (r < 0)
1963 goto out;
1964 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1965 if (r < 0)
1966 goto out;
1967 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1968 if (r < 0)
1969 goto out;
1970 data = ~0;
1971 r = kvm_write_guest_page(kvm, fn, &data,
1972 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1973 sizeof(u8));
1974 if (r < 0)
1975 goto out;
1976
1977 ret = 1;
1978 out:
1979 return ret;
1980 }
1981
1982 static int init_rmode_identity_map(struct kvm *kvm)
1983 {
1984 int i, r, ret;
1985 pfn_t identity_map_pfn;
1986 u32 tmp;
1987
1988 if (!vm_need_ept())
1989 return 1;
1990 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1991 printk(KERN_ERR "EPT: identity-mapping pagetable "
1992 "haven't been allocated!\n");
1993 return 0;
1994 }
1995 if (likely(kvm->arch.ept_identity_pagetable_done))
1996 return 1;
1997 ret = 0;
1998 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1999 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2000 if (r < 0)
2001 goto out;
2002 /* Set up identity-mapping pagetable for EPT in real mode */
2003 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2004 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2005 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2006 r = kvm_write_guest_page(kvm, identity_map_pfn,
2007 &tmp, i * sizeof(tmp), sizeof(tmp));
2008 if (r < 0)
2009 goto out;
2010 }
2011 kvm->arch.ept_identity_pagetable_done = true;
2012 ret = 1;
2013 out:
2014 return ret;
2015 }
2016
2017 static void seg_setup(int seg)
2018 {
2019 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2020
2021 vmcs_write16(sf->selector, 0);
2022 vmcs_writel(sf->base, 0);
2023 vmcs_write32(sf->limit, 0xffff);
2024 vmcs_write32(sf->ar_bytes, 0xf3);
2025 }
2026
2027 static int alloc_apic_access_page(struct kvm *kvm)
2028 {
2029 struct kvm_userspace_memory_region kvm_userspace_mem;
2030 int r = 0;
2031
2032 down_write(&kvm->slots_lock);
2033 if (kvm->arch.apic_access_page)
2034 goto out;
2035 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2036 kvm_userspace_mem.flags = 0;
2037 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2038 kvm_userspace_mem.memory_size = PAGE_SIZE;
2039 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2040 if (r)
2041 goto out;
2042
2043 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2044 out:
2045 up_write(&kvm->slots_lock);
2046 return r;
2047 }
2048
2049 static int alloc_identity_pagetable(struct kvm *kvm)
2050 {
2051 struct kvm_userspace_memory_region kvm_userspace_mem;
2052 int r = 0;
2053
2054 down_write(&kvm->slots_lock);
2055 if (kvm->arch.ept_identity_pagetable)
2056 goto out;
2057 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2058 kvm_userspace_mem.flags = 0;
2059 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2060 kvm_userspace_mem.memory_size = PAGE_SIZE;
2061 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2062 if (r)
2063 goto out;
2064
2065 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2066 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2067 out:
2068 up_write(&kvm->slots_lock);
2069 return r;
2070 }
2071
2072 static void allocate_vpid(struct vcpu_vmx *vmx)
2073 {
2074 int vpid;
2075
2076 vmx->vpid = 0;
2077 if (!enable_vpid || !cpu_has_vmx_vpid())
2078 return;
2079 spin_lock(&vmx_vpid_lock);
2080 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2081 if (vpid < VMX_NR_VPIDS) {
2082 vmx->vpid = vpid;
2083 __set_bit(vpid, vmx_vpid_bitmap);
2084 }
2085 spin_unlock(&vmx_vpid_lock);
2086 }
2087
2088 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
2089 {
2090 void *va;
2091
2092 if (!cpu_has_vmx_msr_bitmap())
2093 return;
2094
2095 /*
2096 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2097 * have the write-low and read-high bitmap offsets the wrong way round.
2098 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2099 */
2100 va = kmap(msr_bitmap);
2101 if (msr <= 0x1fff) {
2102 __clear_bit(msr, va + 0x000); /* read-low */
2103 __clear_bit(msr, va + 0x800); /* write-low */
2104 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2105 msr &= 0x1fff;
2106 __clear_bit(msr, va + 0x400); /* read-high */
2107 __clear_bit(msr, va + 0xc00); /* write-high */
2108 }
2109 kunmap(msr_bitmap);
2110 }
2111
2112 /*
2113 * Sets up the vmcs for emulated real mode.
2114 */
2115 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2116 {
2117 u32 host_sysenter_cs, msr_low, msr_high;
2118 u32 junk;
2119 u64 host_pat, tsc_this, tsc_base;
2120 unsigned long a;
2121 struct descriptor_table dt;
2122 int i;
2123 unsigned long kvm_vmx_return;
2124 u32 exec_control;
2125
2126 /* I/O */
2127 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2128 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
2129
2130 if (cpu_has_vmx_msr_bitmap())
2131 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2132
2133 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2134
2135 /* Control */
2136 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2137 vmcs_config.pin_based_exec_ctrl);
2138
2139 exec_control = vmcs_config.cpu_based_exec_ctrl;
2140 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2141 exec_control &= ~CPU_BASED_TPR_SHADOW;
2142 #ifdef CONFIG_X86_64
2143 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2144 CPU_BASED_CR8_LOAD_EXITING;
2145 #endif
2146 }
2147 if (!vm_need_ept())
2148 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2149 CPU_BASED_CR3_LOAD_EXITING |
2150 CPU_BASED_INVLPG_EXITING;
2151 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2152
2153 if (cpu_has_secondary_exec_ctrls()) {
2154 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2155 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2156 exec_control &=
2157 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2158 if (vmx->vpid == 0)
2159 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2160 if (!vm_need_ept())
2161 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2162 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2163 }
2164
2165 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2166 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2167 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2168
2169 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2170 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2171 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2172
2173 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2174 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2175 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2176 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2177 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2178 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2179 #ifdef CONFIG_X86_64
2180 rdmsrl(MSR_FS_BASE, a);
2181 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2182 rdmsrl(MSR_GS_BASE, a);
2183 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2184 #else
2185 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2186 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2187 #endif
2188
2189 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2190
2191 kvm_get_idt(&dt);
2192 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2193
2194 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2195 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2196 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2197 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2198 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2199
2200 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2201 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2202 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2203 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2204 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2205 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2206
2207 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2208 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2209 host_pat = msr_low | ((u64) msr_high << 32);
2210 vmcs_write64(HOST_IA32_PAT, host_pat);
2211 }
2212 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2213 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2214 host_pat = msr_low | ((u64) msr_high << 32);
2215 /* Write the default value follow host pat */
2216 vmcs_write64(GUEST_IA32_PAT, host_pat);
2217 /* Keep arch.pat sync with GUEST_IA32_PAT */
2218 vmx->vcpu.arch.pat = host_pat;
2219 }
2220
2221 for (i = 0; i < NR_VMX_MSR; ++i) {
2222 u32 index = vmx_msr_index[i];
2223 u32 data_low, data_high;
2224 u64 data;
2225 int j = vmx->nmsrs;
2226
2227 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2228 continue;
2229 if (wrmsr_safe(index, data_low, data_high) < 0)
2230 continue;
2231 data = data_low | ((u64)data_high << 32);
2232 vmx->host_msrs[j].index = index;
2233 vmx->host_msrs[j].reserved = 0;
2234 vmx->host_msrs[j].data = data;
2235 vmx->guest_msrs[j] = vmx->host_msrs[j];
2236 ++vmx->nmsrs;
2237 }
2238
2239 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2240
2241 /* 22.2.1, 20.8.1 */
2242 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2243
2244 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2245 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2246
2247 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2248 rdtscll(tsc_this);
2249 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2250 tsc_base = tsc_this;
2251
2252 guest_write_tsc(0, tsc_base);
2253
2254 return 0;
2255 }
2256
2257 static int init_rmode(struct kvm *kvm)
2258 {
2259 if (!init_rmode_tss(kvm))
2260 return 0;
2261 if (!init_rmode_identity_map(kvm))
2262 return 0;
2263 return 1;
2264 }
2265
2266 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2267 {
2268 struct vcpu_vmx *vmx = to_vmx(vcpu);
2269 u64 msr;
2270 int ret;
2271
2272 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2273 down_read(&vcpu->kvm->slots_lock);
2274 if (!init_rmode(vmx->vcpu.kvm)) {
2275 ret = -ENOMEM;
2276 goto out;
2277 }
2278
2279 vmx->vcpu.arch.rmode.active = 0;
2280
2281 vmx->soft_vnmi_blocked = 0;
2282
2283 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2284 kvm_set_cr8(&vmx->vcpu, 0);
2285 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2286 if (vmx->vcpu.vcpu_id == 0)
2287 msr |= MSR_IA32_APICBASE_BSP;
2288 kvm_set_apic_base(&vmx->vcpu, msr);
2289
2290 fx_init(&vmx->vcpu);
2291
2292 seg_setup(VCPU_SREG_CS);
2293 /*
2294 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2295 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2296 */
2297 if (vmx->vcpu.vcpu_id == 0) {
2298 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2299 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2300 } else {
2301 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2302 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2303 }
2304
2305 seg_setup(VCPU_SREG_DS);
2306 seg_setup(VCPU_SREG_ES);
2307 seg_setup(VCPU_SREG_FS);
2308 seg_setup(VCPU_SREG_GS);
2309 seg_setup(VCPU_SREG_SS);
2310
2311 vmcs_write16(GUEST_TR_SELECTOR, 0);
2312 vmcs_writel(GUEST_TR_BASE, 0);
2313 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2314 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2315
2316 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2317 vmcs_writel(GUEST_LDTR_BASE, 0);
2318 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2319 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2320
2321 vmcs_write32(GUEST_SYSENTER_CS, 0);
2322 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2323 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2324
2325 vmcs_writel(GUEST_RFLAGS, 0x02);
2326 if (vmx->vcpu.vcpu_id == 0)
2327 kvm_rip_write(vcpu, 0xfff0);
2328 else
2329 kvm_rip_write(vcpu, 0);
2330 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2331
2332 vmcs_writel(GUEST_DR7, 0x400);
2333
2334 vmcs_writel(GUEST_GDTR_BASE, 0);
2335 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2336
2337 vmcs_writel(GUEST_IDTR_BASE, 0);
2338 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2339
2340 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2341 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2342 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2343
2344 /* Special registers */
2345 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2346
2347 setup_msrs(vmx);
2348
2349 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2350
2351 if (cpu_has_vmx_tpr_shadow()) {
2352 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2353 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2354 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2355 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2356 vmcs_write32(TPR_THRESHOLD, 0);
2357 }
2358
2359 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2360 vmcs_write64(APIC_ACCESS_ADDR,
2361 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2362
2363 if (vmx->vpid != 0)
2364 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2365
2366 vmx->vcpu.arch.cr0 = 0x60000010;
2367 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2368 vmx_set_cr4(&vmx->vcpu, 0);
2369 vmx_set_efer(&vmx->vcpu, 0);
2370 vmx_fpu_activate(&vmx->vcpu);
2371 update_exception_bitmap(&vmx->vcpu);
2372
2373 vpid_sync_vcpu_all(vmx);
2374
2375 ret = 0;
2376
2377 /* HACK: Don't enable emulation on guest boot/reset */
2378 vmx->emulation_required = 0;
2379
2380 out:
2381 up_read(&vcpu->kvm->slots_lock);
2382 return ret;
2383 }
2384
2385 static void enable_irq_window(struct kvm_vcpu *vcpu)
2386 {
2387 u32 cpu_based_vm_exec_control;
2388
2389 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2390 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2391 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2392 }
2393
2394 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2395 {
2396 u32 cpu_based_vm_exec_control;
2397
2398 if (!cpu_has_virtual_nmis()) {
2399 enable_irq_window(vcpu);
2400 return;
2401 }
2402
2403 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2404 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2405 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2406 }
2407
2408 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2409 {
2410 struct vcpu_vmx *vmx = to_vmx(vcpu);
2411
2412 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2413
2414 ++vcpu->stat.irq_injections;
2415 if (vcpu->arch.rmode.active) {
2416 vmx->rmode.irq.pending = true;
2417 vmx->rmode.irq.vector = irq;
2418 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2419 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2420 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2421 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2422 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2423 return;
2424 }
2425 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2426 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2427 }
2428
2429 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2430 {
2431 struct vcpu_vmx *vmx = to_vmx(vcpu);
2432
2433 if (!cpu_has_virtual_nmis()) {
2434 /*
2435 * Tracking the NMI-blocked state in software is built upon
2436 * finding the next open IRQ window. This, in turn, depends on
2437 * well-behaving guests: They have to keep IRQs disabled at
2438 * least as long as the NMI handler runs. Otherwise we may
2439 * cause NMI nesting, maybe breaking the guest. But as this is
2440 * highly unlikely, we can live with the residual risk.
2441 */
2442 vmx->soft_vnmi_blocked = 1;
2443 vmx->vnmi_blocked_time = 0;
2444 }
2445
2446 ++vcpu->stat.nmi_injections;
2447 if (vcpu->arch.rmode.active) {
2448 vmx->rmode.irq.pending = true;
2449 vmx->rmode.irq.vector = NMI_VECTOR;
2450 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2451 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2452 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2453 INTR_INFO_VALID_MASK);
2454 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2455 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2456 return;
2457 }
2458 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2459 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2460 }
2461
2462 static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2463 {
2464 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2465
2466 vcpu->arch.nmi_window_open =
2467 !(guest_intr & (GUEST_INTR_STATE_STI |
2468 GUEST_INTR_STATE_MOV_SS |
2469 GUEST_INTR_STATE_NMI));
2470 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2471 vcpu->arch.nmi_window_open = 0;
2472
2473 vcpu->arch.interrupt_window_open =
2474 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2475 !(guest_intr & (GUEST_INTR_STATE_STI |
2476 GUEST_INTR_STATE_MOV_SS)));
2477 }
2478
2479 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2480 {
2481 int word_index = __ffs(vcpu->arch.irq_summary);
2482 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2483 int irq = word_index * BITS_PER_LONG + bit_index;
2484
2485 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2486 if (!vcpu->arch.irq_pending[word_index])
2487 clear_bit(word_index, &vcpu->arch.irq_summary);
2488 kvm_queue_interrupt(vcpu, irq);
2489 }
2490
2491 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2492 struct kvm_run *kvm_run)
2493 {
2494 vmx_update_window_states(vcpu);
2495
2496 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
2497 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2498 GUEST_INTR_STATE_STI |
2499 GUEST_INTR_STATE_MOV_SS);
2500
2501 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2502 if (vcpu->arch.interrupt.pending) {
2503 enable_nmi_window(vcpu);
2504 } else if (vcpu->arch.nmi_window_open) {
2505 vcpu->arch.nmi_pending = false;
2506 vcpu->arch.nmi_injected = true;
2507 } else {
2508 enable_nmi_window(vcpu);
2509 return;
2510 }
2511 }
2512 if (vcpu->arch.nmi_injected) {
2513 vmx_inject_nmi(vcpu);
2514 if (vcpu->arch.nmi_pending)
2515 enable_nmi_window(vcpu);
2516 else if (vcpu->arch.irq_summary
2517 || kvm_run->request_interrupt_window)
2518 enable_irq_window(vcpu);
2519 return;
2520 }
2521
2522 if (vcpu->arch.interrupt_window_open) {
2523 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2524 kvm_do_inject_irq(vcpu);
2525
2526 if (vcpu->arch.interrupt.pending)
2527 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2528 }
2529 if (!vcpu->arch.interrupt_window_open &&
2530 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2531 enable_irq_window(vcpu);
2532 }
2533
2534 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2535 {
2536 int ret;
2537 struct kvm_userspace_memory_region tss_mem = {
2538 .slot = TSS_PRIVATE_MEMSLOT,
2539 .guest_phys_addr = addr,
2540 .memory_size = PAGE_SIZE * 3,
2541 .flags = 0,
2542 };
2543
2544 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2545 if (ret)
2546 return ret;
2547 kvm->arch.tss_addr = addr;
2548 return 0;
2549 }
2550
2551 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2552 int vec, u32 err_code)
2553 {
2554 /*
2555 * Instruction with address size override prefix opcode 0x67
2556 * Cause the #SS fault with 0 error code in VM86 mode.
2557 */
2558 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2559 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2560 return 1;
2561 /*
2562 * Forward all other exceptions that are valid in real mode.
2563 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2564 * the required debugging infrastructure rework.
2565 */
2566 switch (vec) {
2567 case DB_VECTOR:
2568 if (vcpu->guest_debug &
2569 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2570 return 0;
2571 kvm_queue_exception(vcpu, vec);
2572 return 1;
2573 case BP_VECTOR:
2574 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2575 return 0;
2576 /* fall through */
2577 case DE_VECTOR:
2578 case OF_VECTOR:
2579 case BR_VECTOR:
2580 case UD_VECTOR:
2581 case DF_VECTOR:
2582 case SS_VECTOR:
2583 case GP_VECTOR:
2584 case MF_VECTOR:
2585 kvm_queue_exception(vcpu, vec);
2586 return 1;
2587 }
2588 return 0;
2589 }
2590
2591 /*
2592 * Trigger machine check on the host. We assume all the MSRs are already set up
2593 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2594 * We pass a fake environment to the machine check handler because we want
2595 * the guest to be always treated like user space, no matter what context
2596 * it used internally.
2597 */
2598 static void kvm_machine_check(void)
2599 {
2600 #ifdef CONFIG_X86_MCE
2601 struct pt_regs regs = {
2602 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2603 .flags = X86_EFLAGS_IF,
2604 };
2605
2606 #ifdef CONFIG_X86_64
2607 do_machine_check(&regs, 0);
2608 #else
2609 machine_check_vector(&regs, 0);
2610 #endif
2611 #endif
2612 }
2613
2614 static int handle_machine_check(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2615 {
2616 /* already handled by vcpu_run */
2617 return 1;
2618 }
2619
2620 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2621 {
2622 struct vcpu_vmx *vmx = to_vmx(vcpu);
2623 u32 intr_info, ex_no, error_code;
2624 unsigned long cr2, rip, dr6;
2625 u32 vect_info;
2626 enum emulation_result er;
2627
2628 vect_info = vmx->idt_vectoring_info;
2629 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2630
2631 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2632 if (ex_no == MC_VECTOR)
2633 return handle_machine_check(vcpu, kvm_run);
2634
2635 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2636 !is_page_fault(intr_info))
2637 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2638 "intr info 0x%x\n", __func__, vect_info, intr_info);
2639
2640 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2641 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2642 set_bit(irq, vcpu->arch.irq_pending);
2643 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2644 }
2645
2646 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2647 return 1; /* already handled by vmx_vcpu_run() */
2648
2649 if (is_no_device(intr_info)) {
2650 vmx_fpu_activate(vcpu);
2651 return 1;
2652 }
2653
2654 if (is_invalid_opcode(intr_info)) {
2655 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2656 if (er != EMULATE_DONE)
2657 kvm_queue_exception(vcpu, UD_VECTOR);
2658 return 1;
2659 }
2660
2661 error_code = 0;
2662 rip = kvm_rip_read(vcpu);
2663 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2664 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2665 if (is_page_fault(intr_info)) {
2666 /* EPT won't cause page fault directly */
2667 if (vm_need_ept())
2668 BUG();
2669 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2670 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2671 (u32)((u64)cr2 >> 32), handler);
2672 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2673 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2674 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2675 }
2676
2677 if (vcpu->arch.rmode.active &&
2678 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2679 error_code)) {
2680 if (vcpu->arch.halt_request) {
2681 vcpu->arch.halt_request = 0;
2682 return kvm_emulate_halt(vcpu);
2683 }
2684 return 1;
2685 }
2686
2687 switch (ex_no) {
2688 case DB_VECTOR:
2689 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2690 if (!(vcpu->guest_debug &
2691 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2692 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2693 kvm_queue_exception(vcpu, DB_VECTOR);
2694 return 1;
2695 }
2696 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2697 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2698 /* fall through */
2699 case BP_VECTOR:
2700 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2701 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2702 kvm_run->debug.arch.exception = ex_no;
2703 break;
2704 default:
2705 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2706 kvm_run->ex.exception = ex_no;
2707 kvm_run->ex.error_code = error_code;
2708 break;
2709 }
2710 return 0;
2711 }
2712
2713 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2714 struct kvm_run *kvm_run)
2715 {
2716 ++vcpu->stat.irq_exits;
2717 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2718 return 1;
2719 }
2720
2721 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2722 {
2723 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2724 return 0;
2725 }
2726
2727 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2728 {
2729 unsigned long exit_qualification;
2730 int size, in, string;
2731 unsigned port;
2732
2733 ++vcpu->stat.io_exits;
2734 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2735 string = (exit_qualification & 16) != 0;
2736
2737 if (string) {
2738 if (emulate_instruction(vcpu,
2739 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2740 return 0;
2741 return 1;
2742 }
2743
2744 size = (exit_qualification & 7) + 1;
2745 in = (exit_qualification & 8) != 0;
2746 port = exit_qualification >> 16;
2747
2748 skip_emulated_instruction(vcpu);
2749 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2750 }
2751
2752 static void
2753 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2754 {
2755 /*
2756 * Patch in the VMCALL instruction:
2757 */
2758 hypercall[0] = 0x0f;
2759 hypercall[1] = 0x01;
2760 hypercall[2] = 0xc1;
2761 }
2762
2763 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2764 {
2765 unsigned long exit_qualification;
2766 int cr;
2767 int reg;
2768
2769 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2770 cr = exit_qualification & 15;
2771 reg = (exit_qualification >> 8) & 15;
2772 switch ((exit_qualification >> 4) & 3) {
2773 case 0: /* mov to cr */
2774 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2775 (u32)kvm_register_read(vcpu, reg),
2776 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2777 handler);
2778 switch (cr) {
2779 case 0:
2780 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2781 skip_emulated_instruction(vcpu);
2782 return 1;
2783 case 3:
2784 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2785 skip_emulated_instruction(vcpu);
2786 return 1;
2787 case 4:
2788 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2789 skip_emulated_instruction(vcpu);
2790 return 1;
2791 case 8:
2792 kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2793 skip_emulated_instruction(vcpu);
2794 if (irqchip_in_kernel(vcpu->kvm))
2795 return 1;
2796 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2797 return 0;
2798 };
2799 break;
2800 case 2: /* clts */
2801 vmx_fpu_deactivate(vcpu);
2802 vcpu->arch.cr0 &= ~X86_CR0_TS;
2803 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2804 vmx_fpu_activate(vcpu);
2805 KVMTRACE_0D(CLTS, vcpu, handler);
2806 skip_emulated_instruction(vcpu);
2807 return 1;
2808 case 1: /*mov from cr*/
2809 switch (cr) {
2810 case 3:
2811 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2812 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2813 (u32)kvm_register_read(vcpu, reg),
2814 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2815 handler);
2816 skip_emulated_instruction(vcpu);
2817 return 1;
2818 case 8:
2819 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2820 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2821 (u32)kvm_register_read(vcpu, reg), handler);
2822 skip_emulated_instruction(vcpu);
2823 return 1;
2824 }
2825 break;
2826 case 3: /* lmsw */
2827 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2828
2829 skip_emulated_instruction(vcpu);
2830 return 1;
2831 default:
2832 break;
2833 }
2834 kvm_run->exit_reason = 0;
2835 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2836 (int)(exit_qualification >> 4) & 3, cr);
2837 return 0;
2838 }
2839
2840 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2841 {
2842 unsigned long exit_qualification;
2843 unsigned long val;
2844 int dr, reg;
2845
2846 dr = vmcs_readl(GUEST_DR7);
2847 if (dr & DR7_GD) {
2848 /*
2849 * As the vm-exit takes precedence over the debug trap, we
2850 * need to emulate the latter, either for the host or the
2851 * guest debugging itself.
2852 */
2853 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2854 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2855 kvm_run->debug.arch.dr7 = dr;
2856 kvm_run->debug.arch.pc =
2857 vmcs_readl(GUEST_CS_BASE) +
2858 vmcs_readl(GUEST_RIP);
2859 kvm_run->debug.arch.exception = DB_VECTOR;
2860 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2861 return 0;
2862 } else {
2863 vcpu->arch.dr7 &= ~DR7_GD;
2864 vcpu->arch.dr6 |= DR6_BD;
2865 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2866 kvm_queue_exception(vcpu, DB_VECTOR);
2867 return 1;
2868 }
2869 }
2870
2871 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2872 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2873 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2874 if (exit_qualification & TYPE_MOV_FROM_DR) {
2875 switch (dr) {
2876 case 0 ... 3:
2877 val = vcpu->arch.db[dr];
2878 break;
2879 case 6:
2880 val = vcpu->arch.dr6;
2881 break;
2882 case 7:
2883 val = vcpu->arch.dr7;
2884 break;
2885 default:
2886 val = 0;
2887 }
2888 kvm_register_write(vcpu, reg, val);
2889 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2890 } else {
2891 val = vcpu->arch.regs[reg];
2892 switch (dr) {
2893 case 0 ... 3:
2894 vcpu->arch.db[dr] = val;
2895 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2896 vcpu->arch.eff_db[dr] = val;
2897 break;
2898 case 4 ... 5:
2899 if (vcpu->arch.cr4 & X86_CR4_DE)
2900 kvm_queue_exception(vcpu, UD_VECTOR);
2901 break;
2902 case 6:
2903 if (val & 0xffffffff00000000ULL) {
2904 kvm_queue_exception(vcpu, GP_VECTOR);
2905 break;
2906 }
2907 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2908 break;
2909 case 7:
2910 if (val & 0xffffffff00000000ULL) {
2911 kvm_queue_exception(vcpu, GP_VECTOR);
2912 break;
2913 }
2914 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2915 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2916 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2917 vcpu->arch.switch_db_regs =
2918 (val & DR7_BP_EN_MASK);
2919 }
2920 break;
2921 }
2922 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
2923 }
2924 skip_emulated_instruction(vcpu);
2925 return 1;
2926 }
2927
2928 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2929 {
2930 kvm_emulate_cpuid(vcpu);
2931 return 1;
2932 }
2933
2934 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2935 {
2936 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2937 u64 data;
2938
2939 if (vmx_get_msr(vcpu, ecx, &data)) {
2940 kvm_inject_gp(vcpu, 0);
2941 return 1;
2942 }
2943
2944 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2945 handler);
2946
2947 /* FIXME: handling of bits 32:63 of rax, rdx */
2948 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2949 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2950 skip_emulated_instruction(vcpu);
2951 return 1;
2952 }
2953
2954 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2955 {
2956 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2957 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2958 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2959
2960 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2961 handler);
2962
2963 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2964 kvm_inject_gp(vcpu, 0);
2965 return 1;
2966 }
2967
2968 skip_emulated_instruction(vcpu);
2969 return 1;
2970 }
2971
2972 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2973 struct kvm_run *kvm_run)
2974 {
2975 return 1;
2976 }
2977
2978 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2979 struct kvm_run *kvm_run)
2980 {
2981 u32 cpu_based_vm_exec_control;
2982
2983 /* clear pending irq */
2984 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2985 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2986 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2987
2988 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2989 ++vcpu->stat.irq_window_exits;
2990
2991 /*
2992 * If the user space waits to inject interrupts, exit as soon as
2993 * possible
2994 */
2995 if (kvm_run->request_interrupt_window &&
2996 !vcpu->arch.irq_summary) {
2997 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2998 return 0;
2999 }
3000 return 1;
3001 }
3002
3003 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3004 {
3005 skip_emulated_instruction(vcpu);
3006 return kvm_emulate_halt(vcpu);
3007 }
3008
3009 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3010 {
3011 skip_emulated_instruction(vcpu);
3012 kvm_emulate_hypercall(vcpu);
3013 return 1;
3014 }
3015
3016 static int handle_vmx_insn(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3017 {
3018 kvm_queue_exception(vcpu, UD_VECTOR);
3019 return 1;
3020 }
3021
3022 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3023 {
3024 u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3025
3026 kvm_mmu_invlpg(vcpu, exit_qualification);
3027 skip_emulated_instruction(vcpu);
3028 return 1;
3029 }
3030
3031 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3032 {
3033 skip_emulated_instruction(vcpu);
3034 /* TODO: Add support for VT-d/pass-through device */
3035 return 1;
3036 }
3037
3038 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3039 {
3040 u64 exit_qualification;
3041 enum emulation_result er;
3042 unsigned long offset;
3043
3044 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3045 offset = exit_qualification & 0xffful;
3046
3047 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3048
3049 if (er != EMULATE_DONE) {
3050 printk(KERN_ERR
3051 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3052 offset);
3053 return -ENOTSUPP;
3054 }
3055 return 1;
3056 }
3057
3058 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3059 {
3060 struct vcpu_vmx *vmx = to_vmx(vcpu);
3061 unsigned long exit_qualification;
3062 u16 tss_selector;
3063 int reason;
3064
3065 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3066
3067 reason = (u32)exit_qualification >> 30;
3068 if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
3069 (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
3070 (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
3071 == INTR_TYPE_NMI_INTR) {
3072 vcpu->arch.nmi_injected = false;
3073 if (cpu_has_virtual_nmis())
3074 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3075 GUEST_INTR_STATE_NMI);
3076 }
3077 tss_selector = exit_qualification;
3078
3079 if (!kvm_task_switch(vcpu, tss_selector, reason))
3080 return 0;
3081
3082 /* clear all local breakpoint enable flags */
3083 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3084
3085 /*
3086 * TODO: What about debug traps on tss switch?
3087 * Are we supposed to inject them and update dr6?
3088 */
3089
3090 return 1;
3091 }
3092
3093 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3094 {
3095 u64 exit_qualification;
3096 gpa_t gpa;
3097 int gla_validity;
3098
3099 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3100
3101 if (exit_qualification & (1 << 6)) {
3102 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3103 return -ENOTSUPP;
3104 }
3105
3106 gla_validity = (exit_qualification >> 7) & 0x3;
3107 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3108 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3109 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3110 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3111 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3112 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3113 (long unsigned int)exit_qualification);
3114 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3115 kvm_run->hw.hardware_exit_reason = 0;
3116 return -ENOTSUPP;
3117 }
3118
3119 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3120 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3121 }
3122
3123 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3124 {
3125 u32 cpu_based_vm_exec_control;
3126
3127 /* clear pending NMI */
3128 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3129 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3130 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3131 ++vcpu->stat.nmi_window_exits;
3132
3133 return 1;
3134 }
3135
3136 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3137 struct kvm_run *kvm_run)
3138 {
3139 struct vcpu_vmx *vmx = to_vmx(vcpu);
3140 enum emulation_result err = EMULATE_DONE;
3141
3142 preempt_enable();
3143 local_irq_enable();
3144
3145 while (!guest_state_valid(vcpu)) {
3146 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3147
3148 if (err == EMULATE_DO_MMIO)
3149 break;
3150
3151 if (err != EMULATE_DONE) {
3152 kvm_report_emulation_failure(vcpu, "emulation failure");
3153 return;
3154 }
3155
3156 if (signal_pending(current))
3157 break;
3158 if (need_resched())
3159 schedule();
3160 }
3161
3162 local_irq_disable();
3163 preempt_disable();
3164
3165 vmx->invalid_state_emulation_result = err;
3166 }
3167
3168 /*
3169 * The exit handlers return 1 if the exit was handled fully and guest execution
3170 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3171 * to be done to userspace and return 0.
3172 */
3173 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3174 struct kvm_run *kvm_run) = {
3175 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3176 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3177 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3178 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3179 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3180 [EXIT_REASON_CR_ACCESS] = handle_cr,
3181 [EXIT_REASON_DR_ACCESS] = handle_dr,
3182 [EXIT_REASON_CPUID] = handle_cpuid,
3183 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3184 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3185 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3186 [EXIT_REASON_HLT] = handle_halt,
3187 [EXIT_REASON_INVLPG] = handle_invlpg,
3188 [EXIT_REASON_VMCALL] = handle_vmcall,
3189 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3190 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3191 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3192 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3193 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3194 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3195 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3196 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3197 [EXIT_REASON_VMON] = handle_vmx_insn,
3198 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3199 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3200 [EXIT_REASON_WBINVD] = handle_wbinvd,
3201 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3202 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3203 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3204 };
3205
3206 static const int kvm_vmx_max_exit_handlers =
3207 ARRAY_SIZE(kvm_vmx_exit_handlers);
3208
3209 /*
3210 * The guest has exited. See if we can fix it or if we need userspace
3211 * assistance.
3212 */
3213 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3214 {
3215 struct vcpu_vmx *vmx = to_vmx(vcpu);
3216 u32 exit_reason = vmx->exit_reason;
3217 u32 vectoring_info = vmx->idt_vectoring_info;
3218
3219 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3220 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3221
3222 /* If we need to emulate an MMIO from handle_invalid_guest_state
3223 * we just return 0 */
3224 if (vmx->emulation_required && emulate_invalid_guest_state) {
3225 if (guest_state_valid(vcpu))
3226 vmx->emulation_required = 0;
3227 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
3228 }
3229
3230 /* Access CR3 don't cause VMExit in paging mode, so we need
3231 * to sync with guest real CR3. */
3232 if (vm_need_ept() && is_paging(vcpu)) {
3233 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3234 ept_load_pdptrs(vcpu);
3235 }
3236
3237 if (unlikely(vmx->fail)) {
3238 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3239 kvm_run->fail_entry.hardware_entry_failure_reason
3240 = vmcs_read32(VM_INSTRUCTION_ERROR);
3241 return 0;
3242 }
3243
3244 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3245 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3246 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3247 exit_reason != EXIT_REASON_TASK_SWITCH))
3248 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3249 "(0x%x) and exit reason is 0x%x\n",
3250 __func__, vectoring_info, exit_reason);
3251
3252 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3253 if (vcpu->arch.interrupt_window_open) {
3254 vmx->soft_vnmi_blocked = 0;
3255 vcpu->arch.nmi_window_open = 1;
3256 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3257 vcpu->arch.nmi_pending) {
3258 /*
3259 * This CPU don't support us in finding the end of an
3260 * NMI-blocked window if the guest runs with IRQs
3261 * disabled. So we pull the trigger after 1 s of
3262 * futile waiting, but inform the user about this.
3263 */
3264 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3265 "state on VCPU %d after 1 s timeout\n",
3266 __func__, vcpu->vcpu_id);
3267 vmx->soft_vnmi_blocked = 0;
3268 vmx->vcpu.arch.nmi_window_open = 1;
3269 }
3270 }
3271
3272 if (exit_reason < kvm_vmx_max_exit_handlers
3273 && kvm_vmx_exit_handlers[exit_reason])
3274 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3275 else {
3276 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3277 kvm_run->hw.hardware_exit_reason = exit_reason;
3278 }
3279 return 0;
3280 }
3281
3282 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3283 {
3284 int max_irr, tpr;
3285
3286 if (!vm_need_tpr_shadow(vcpu->kvm))
3287 return;
3288
3289 if (!kvm_lapic_enabled(vcpu) ||
3290 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3291 vmcs_write32(TPR_THRESHOLD, 0);
3292 return;
3293 }
3294
3295 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3296 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3297 }
3298
3299 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3300 {
3301 u32 exit_intr_info;
3302 u32 idt_vectoring_info;
3303 bool unblock_nmi;
3304 u8 vector;
3305 int type;
3306 bool idtv_info_valid;
3307 u32 error;
3308
3309 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3310 if (cpu_has_virtual_nmis()) {
3311 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3312 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3313 /*
3314 * SDM 3: 25.7.1.2
3315 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3316 * a guest IRET fault.
3317 */
3318 if (unblock_nmi && vector != DF_VECTOR)
3319 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3320 GUEST_INTR_STATE_NMI);
3321 } else if (unlikely(vmx->soft_vnmi_blocked))
3322 vmx->vnmi_blocked_time +=
3323 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3324
3325 idt_vectoring_info = vmx->idt_vectoring_info;
3326 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3327 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3328 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3329 if (vmx->vcpu.arch.nmi_injected) {
3330 /*
3331 * SDM 3: 25.7.1.2
3332 * Clear bit "block by NMI" before VM entry if a NMI delivery
3333 * faulted.
3334 */
3335 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3336 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3337 GUEST_INTR_STATE_NMI);
3338 else
3339 vmx->vcpu.arch.nmi_injected = false;
3340 }
3341 kvm_clear_exception_queue(&vmx->vcpu);
3342 if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION ||
3343 type == INTR_TYPE_SOFT_EXCEPTION)) {
3344 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3345 error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3346 kvm_queue_exception_e(&vmx->vcpu, vector, error);
3347 } else
3348 kvm_queue_exception(&vmx->vcpu, vector);
3349 vmx->idt_vectoring_info = 0;
3350 }
3351 kvm_clear_interrupt_queue(&vmx->vcpu);
3352 if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3353 kvm_queue_interrupt(&vmx->vcpu, vector);
3354 vmx->idt_vectoring_info = 0;
3355 }
3356 }
3357
3358 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3359 {
3360 update_tpr_threshold(vcpu);
3361
3362 vmx_update_window_states(vcpu);
3363
3364 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3365 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3366 GUEST_INTR_STATE_STI |
3367 GUEST_INTR_STATE_MOV_SS);
3368
3369 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3370 if (vcpu->arch.interrupt.pending) {
3371 enable_nmi_window(vcpu);
3372 } else if (vcpu->arch.nmi_window_open) {
3373 vcpu->arch.nmi_pending = false;
3374 vcpu->arch.nmi_injected = true;
3375 } else {
3376 enable_nmi_window(vcpu);
3377 return;
3378 }
3379 }
3380 if (vcpu->arch.nmi_injected) {
3381 vmx_inject_nmi(vcpu);
3382 if (vcpu->arch.nmi_pending)
3383 enable_nmi_window(vcpu);
3384 else if (kvm_cpu_has_interrupt(vcpu))
3385 enable_irq_window(vcpu);
3386 return;
3387 }
3388 if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3389 if (vcpu->arch.interrupt_window_open)
3390 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3391 else
3392 enable_irq_window(vcpu);
3393 }
3394 if (vcpu->arch.interrupt.pending) {
3395 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3396 if (kvm_cpu_has_interrupt(vcpu))
3397 enable_irq_window(vcpu);
3398 }
3399 }
3400
3401 /*
3402 * Failure to inject an interrupt should give us the information
3403 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3404 * when fetching the interrupt redirection bitmap in the real-mode
3405 * tss, this doesn't happen. So we do it ourselves.
3406 */
3407 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3408 {
3409 vmx->rmode.irq.pending = 0;
3410 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3411 return;
3412 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3413 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3414 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3415 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3416 return;
3417 }
3418 vmx->idt_vectoring_info =
3419 VECTORING_INFO_VALID_MASK
3420 | INTR_TYPE_EXT_INTR
3421 | vmx->rmode.irq.vector;
3422 }
3423
3424 #ifdef CONFIG_X86_64
3425 #define R "r"
3426 #define Q "q"
3427 #else
3428 #define R "e"
3429 #define Q "l"
3430 #endif
3431
3432 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3433 {
3434 struct vcpu_vmx *vmx = to_vmx(vcpu);
3435 u32 intr_info;
3436
3437 /* Record the guest's net vcpu time for enforced NMI injections. */
3438 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3439 vmx->entry_time = ktime_get();
3440
3441 /* Handle invalid guest state instead of entering VMX */
3442 if (vmx->emulation_required && emulate_invalid_guest_state) {
3443 handle_invalid_guest_state(vcpu, kvm_run);
3444 return;
3445 }
3446
3447 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3448 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3449 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3450 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3451
3452 /*
3453 * Loading guest fpu may have cleared host cr0.ts
3454 */
3455 vmcs_writel(HOST_CR0, read_cr0());
3456
3457 set_debugreg(vcpu->arch.dr6, 6);
3458
3459 asm(
3460 /* Store host registers */
3461 "push %%"R"dx; push %%"R"bp;"
3462 "push %%"R"cx \n\t"
3463 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3464 "je 1f \n\t"
3465 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3466 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3467 "1: \n\t"
3468 /* Check if vmlaunch of vmresume is needed */
3469 "cmpl $0, %c[launched](%0) \n\t"
3470 /* Load guest registers. Don't clobber flags. */
3471 "mov %c[cr2](%0), %%"R"ax \n\t"
3472 "mov %%"R"ax, %%cr2 \n\t"
3473 "mov %c[rax](%0), %%"R"ax \n\t"
3474 "mov %c[rbx](%0), %%"R"bx \n\t"
3475 "mov %c[rdx](%0), %%"R"dx \n\t"
3476 "mov %c[rsi](%0), %%"R"si \n\t"
3477 "mov %c[rdi](%0), %%"R"di \n\t"
3478 "mov %c[rbp](%0), %%"R"bp \n\t"
3479 #ifdef CONFIG_X86_64
3480 "mov %c[r8](%0), %%r8 \n\t"
3481 "mov %c[r9](%0), %%r9 \n\t"
3482 "mov %c[r10](%0), %%r10 \n\t"
3483 "mov %c[r11](%0), %%r11 \n\t"
3484 "mov %c[r12](%0), %%r12 \n\t"
3485 "mov %c[r13](%0), %%r13 \n\t"
3486 "mov %c[r14](%0), %%r14 \n\t"
3487 "mov %c[r15](%0), %%r15 \n\t"
3488 #endif
3489 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3490
3491 /* Enter guest mode */
3492 "jne .Llaunched \n\t"
3493 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3494 "jmp .Lkvm_vmx_return \n\t"
3495 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3496 ".Lkvm_vmx_return: "
3497 /* Save guest registers, load host registers, keep flags */
3498 "xchg %0, (%%"R"sp) \n\t"
3499 "mov %%"R"ax, %c[rax](%0) \n\t"
3500 "mov %%"R"bx, %c[rbx](%0) \n\t"
3501 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3502 "mov %%"R"dx, %c[rdx](%0) \n\t"
3503 "mov %%"R"si, %c[rsi](%0) \n\t"
3504 "mov %%"R"di, %c[rdi](%0) \n\t"
3505 "mov %%"R"bp, %c[rbp](%0) \n\t"
3506 #ifdef CONFIG_X86_64
3507 "mov %%r8, %c[r8](%0) \n\t"
3508 "mov %%r9, %c[r9](%0) \n\t"
3509 "mov %%r10, %c[r10](%0) \n\t"
3510 "mov %%r11, %c[r11](%0) \n\t"
3511 "mov %%r12, %c[r12](%0) \n\t"
3512 "mov %%r13, %c[r13](%0) \n\t"
3513 "mov %%r14, %c[r14](%0) \n\t"
3514 "mov %%r15, %c[r15](%0) \n\t"
3515 #endif
3516 "mov %%cr2, %%"R"ax \n\t"
3517 "mov %%"R"ax, %c[cr2](%0) \n\t"
3518
3519 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3520 "setbe %c[fail](%0) \n\t"
3521 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3522 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3523 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3524 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3525 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3526 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3527 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3528 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3529 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3530 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3531 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3532 #ifdef CONFIG_X86_64
3533 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3534 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3535 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3536 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3537 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3538 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3539 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3540 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3541 #endif
3542 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3543 : "cc", "memory"
3544 , R"bx", R"di", R"si"
3545 #ifdef CONFIG_X86_64
3546 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3547 #endif
3548 );
3549
3550 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3551 vcpu->arch.regs_dirty = 0;
3552
3553 get_debugreg(vcpu->arch.dr6, 6);
3554
3555 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3556 if (vmx->rmode.irq.pending)
3557 fixup_rmode_irq(vmx);
3558
3559 vmx_update_window_states(vcpu);
3560
3561 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3562 vmx->launched = 1;
3563
3564 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3565
3566 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3567
3568 /* Handle machine checks before interrupts are enabled */
3569 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) ||
3570 (intr_info & INTR_INFO_VECTOR_MASK) == MC_VECTOR)
3571 kvm_machine_check();
3572
3573 /* We need to handle NMIs before interrupts are enabled */
3574 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3575 (intr_info & INTR_INFO_VALID_MASK)) {
3576 KVMTRACE_0D(NMI, vcpu, handler);
3577 asm("int $2");
3578 }
3579
3580 vmx_complete_interrupts(vmx);
3581 }
3582
3583 #undef R
3584 #undef Q
3585
3586 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3587 {
3588 struct vcpu_vmx *vmx = to_vmx(vcpu);
3589
3590 if (vmx->vmcs) {
3591 vcpu_clear(vmx);
3592 free_vmcs(vmx->vmcs);
3593 vmx->vmcs = NULL;
3594 }
3595 }
3596
3597 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3598 {
3599 struct vcpu_vmx *vmx = to_vmx(vcpu);
3600
3601 spin_lock(&vmx_vpid_lock);
3602 if (vmx->vpid != 0)
3603 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3604 spin_unlock(&vmx_vpid_lock);
3605 vmx_free_vmcs(vcpu);
3606 kfree(vmx->host_msrs);
3607 kfree(vmx->guest_msrs);
3608 kvm_vcpu_uninit(vcpu);
3609 kmem_cache_free(kvm_vcpu_cache, vmx);
3610 }
3611
3612 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3613 {
3614 int err;
3615 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3616 int cpu;
3617
3618 if (!vmx)
3619 return ERR_PTR(-ENOMEM);
3620
3621 allocate_vpid(vmx);
3622
3623 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3624 if (err)
3625 goto free_vcpu;
3626
3627 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3628 if (!vmx->guest_msrs) {
3629 err = -ENOMEM;
3630 goto uninit_vcpu;
3631 }
3632
3633 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3634 if (!vmx->host_msrs)
3635 goto free_guest_msrs;
3636
3637 vmx->vmcs = alloc_vmcs();
3638 if (!vmx->vmcs)
3639 goto free_msrs;
3640
3641 vmcs_clear(vmx->vmcs);
3642
3643 cpu = get_cpu();
3644 vmx_vcpu_load(&vmx->vcpu, cpu);
3645 err = vmx_vcpu_setup(vmx);
3646 vmx_vcpu_put(&vmx->vcpu);
3647 put_cpu();
3648 if (err)
3649 goto free_vmcs;
3650 if (vm_need_virtualize_apic_accesses(kvm))
3651 if (alloc_apic_access_page(kvm) != 0)
3652 goto free_vmcs;
3653
3654 if (vm_need_ept())
3655 if (alloc_identity_pagetable(kvm) != 0)
3656 goto free_vmcs;
3657
3658 return &vmx->vcpu;
3659
3660 free_vmcs:
3661 free_vmcs(vmx->vmcs);
3662 free_msrs:
3663 kfree(vmx->host_msrs);
3664 free_guest_msrs:
3665 kfree(vmx->guest_msrs);
3666 uninit_vcpu:
3667 kvm_vcpu_uninit(&vmx->vcpu);
3668 free_vcpu:
3669 kmem_cache_free(kvm_vcpu_cache, vmx);
3670 return ERR_PTR(err);
3671 }
3672
3673 static void __init vmx_check_processor_compat(void *rtn)
3674 {
3675 struct vmcs_config vmcs_conf;
3676
3677 *(int *)rtn = 0;
3678 if (setup_vmcs_config(&vmcs_conf) < 0)
3679 *(int *)rtn = -EIO;
3680 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3681 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3682 smp_processor_id());
3683 *(int *)rtn = -EIO;
3684 }
3685 }
3686
3687 static int get_ept_level(void)
3688 {
3689 return VMX_EPT_DEFAULT_GAW + 1;
3690 }
3691
3692 static int vmx_get_mt_mask_shift(void)
3693 {
3694 return VMX_EPT_MT_EPTE_SHIFT;
3695 }
3696
3697 static struct kvm_x86_ops vmx_x86_ops = {
3698 .cpu_has_kvm_support = cpu_has_kvm_support,
3699 .disabled_by_bios = vmx_disabled_by_bios,
3700 .hardware_setup = hardware_setup,
3701 .hardware_unsetup = hardware_unsetup,
3702 .check_processor_compatibility = vmx_check_processor_compat,
3703 .hardware_enable = hardware_enable,
3704 .hardware_disable = hardware_disable,
3705 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3706
3707 .vcpu_create = vmx_create_vcpu,
3708 .vcpu_free = vmx_free_vcpu,
3709 .vcpu_reset = vmx_vcpu_reset,
3710
3711 .prepare_guest_switch = vmx_save_host_state,
3712 .vcpu_load = vmx_vcpu_load,
3713 .vcpu_put = vmx_vcpu_put,
3714
3715 .set_guest_debug = set_guest_debug,
3716 .get_msr = vmx_get_msr,
3717 .set_msr = vmx_set_msr,
3718 .get_segment_base = vmx_get_segment_base,
3719 .get_segment = vmx_get_segment,
3720 .set_segment = vmx_set_segment,
3721 .get_cpl = vmx_get_cpl,
3722 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3723 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3724 .set_cr0 = vmx_set_cr0,
3725 .set_cr3 = vmx_set_cr3,
3726 .set_cr4 = vmx_set_cr4,
3727 .set_efer = vmx_set_efer,
3728 .get_idt = vmx_get_idt,
3729 .set_idt = vmx_set_idt,
3730 .get_gdt = vmx_get_gdt,
3731 .set_gdt = vmx_set_gdt,
3732 .cache_reg = vmx_cache_reg,
3733 .get_rflags = vmx_get_rflags,
3734 .set_rflags = vmx_set_rflags,
3735
3736 .tlb_flush = vmx_flush_tlb,
3737
3738 .run = vmx_vcpu_run,
3739 .handle_exit = kvm_handle_exit,
3740 .skip_emulated_instruction = skip_emulated_instruction,
3741 .patch_hypercall = vmx_patch_hypercall,
3742 .get_irq = vmx_get_irq,
3743 .set_irq = vmx_inject_irq,
3744 .queue_exception = vmx_queue_exception,
3745 .exception_injected = vmx_exception_injected,
3746 .inject_pending_irq = vmx_intr_assist,
3747 .inject_pending_vectors = do_interrupt_requests,
3748
3749 .set_tss_addr = vmx_set_tss_addr,
3750 .get_tdp_level = get_ept_level,
3751 .get_mt_mask_shift = vmx_get_mt_mask_shift,
3752 };
3753
3754 static int __init vmx_init(void)
3755 {
3756 void *va;
3757 int r;
3758
3759 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3760 if (!vmx_io_bitmap_a)
3761 return -ENOMEM;
3762
3763 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3764 if (!vmx_io_bitmap_b) {
3765 r = -ENOMEM;
3766 goto out;
3767 }
3768
3769 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3770 if (!vmx_msr_bitmap) {
3771 r = -ENOMEM;
3772 goto out1;
3773 }
3774
3775 /*
3776 * Allow direct access to the PC debug port (it is often used for I/O
3777 * delays, but the vmexits simply slow things down).
3778 */
3779 va = kmap(vmx_io_bitmap_a);
3780 memset(va, 0xff, PAGE_SIZE);
3781 clear_bit(0x80, va);
3782 kunmap(vmx_io_bitmap_a);
3783
3784 va = kmap(vmx_io_bitmap_b);
3785 memset(va, 0xff, PAGE_SIZE);
3786 kunmap(vmx_io_bitmap_b);
3787
3788 va = kmap(vmx_msr_bitmap);
3789 memset(va, 0xff, PAGE_SIZE);
3790 kunmap(vmx_msr_bitmap);
3791
3792 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3793
3794 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3795 if (r)
3796 goto out2;
3797
3798 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3799 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3800 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3801 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3802 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3803
3804 if (vm_need_ept()) {
3805 bypass_guest_pf = 0;
3806 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3807 VMX_EPT_WRITABLE_MASK);
3808 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3809 VMX_EPT_EXECUTABLE_MASK,
3810 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3811 kvm_enable_tdp();
3812 } else
3813 kvm_disable_tdp();
3814
3815 if (bypass_guest_pf)
3816 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3817
3818 ept_sync_global();
3819
3820 return 0;
3821
3822 out2:
3823 __free_page(vmx_msr_bitmap);
3824 out1:
3825 __free_page(vmx_io_bitmap_b);
3826 out:
3827 __free_page(vmx_io_bitmap_a);
3828 return r;
3829 }
3830
3831 static void __exit vmx_exit(void)
3832 {
3833 __free_page(vmx_msr_bitmap);
3834 __free_page(vmx_io_bitmap_b);
3835 __free_page(vmx_io_bitmap_a);
3836
3837 kvm_exit();
3838 }
3839
3840 module_init(vmx_init)
3841 module_exit(vmx_exit)
Support for the Chinese Samsung S3C2440 based development boards