2 * Performance counter x86 architecture code
4 * Copyright(C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright(C) 2008 Red Hat, Inc., Ingo Molnar
6 * Copyright(C) 2009 Jaswinder Singh Rajput
7 * Copyright(C) 2009 Advanced Micro Devices, Inc., Robert Richter
9 * For licencing details see kernel-base/COPYING
12 #include <linux/perf_counter.h>
13 #include <linux/capability.h>
14 #include <linux/notifier.h>
15 #include <linux/hardirq.h>
16 #include <linux/kprobes.h>
17 #include <linux/module.h>
18 #include <linux/kdebug.h>
19 #include <linux/sched.h>
20 #include <linux/uaccess.h>
23 #include <asm/stacktrace.h>
26 static bool perf_counters_initialized __read_mostly
;
29 * Number of (generic) HW counters:
31 static int nr_counters_generic __read_mostly
;
32 static u64 perf_counter_mask __read_mostly
;
33 static u64 counter_value_mask __read_mostly
;
34 static int counter_value_bits __read_mostly
;
36 static int nr_counters_fixed __read_mostly
;
38 struct cpu_hw_counters
{
39 struct perf_counter
*counters
[X86_PMC_IDX_MAX
];
40 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
41 unsigned long interrupts
;
43 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
48 * struct x86_pmu - generic x86 pmu
51 int (*handle_irq
)(struct pt_regs
*, int);
52 u64 (*save_disable_all
)(void);
53 void (*restore_all
)(u64
);
54 void (*ack_status
)(u64
);
55 void (*enable
)(int, u64
);
56 void (*disable
)(int, u64
);
59 u64 (*event_map
)(int);
60 u64 (*raw_event
)(u64
);
64 static struct x86_pmu
*x86_pmu __read_mostly
;
66 static DEFINE_PER_CPU(struct cpu_hw_counters
, cpu_hw_counters
) = {
70 static __read_mostly
int intel_perfmon_version
;
73 * Intel PerfMon v3. Used on Core2 and later.
75 static const u64 intel_perfmon_event_map
[] =
77 [PERF_COUNT_CPU_CYCLES
] = 0x003c,
78 [PERF_COUNT_INSTRUCTIONS
] = 0x00c0,
79 [PERF_COUNT_CACHE_REFERENCES
] = 0x4f2e,
80 [PERF_COUNT_CACHE_MISSES
] = 0x412e,
81 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x00c4,
82 [PERF_COUNT_BRANCH_MISSES
] = 0x00c5,
83 [PERF_COUNT_BUS_CYCLES
] = 0x013c,
86 static u64
intel_pmu_event_map(int event
)
88 return intel_perfmon_event_map
[event
];
91 static u64
intel_pmu_raw_event(u64 event
)
93 #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
94 #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
95 #define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
97 #define CORE_EVNTSEL_MASK \
98 (CORE_EVNTSEL_EVENT_MASK | \
99 CORE_EVNTSEL_UNIT_MASK | \
100 CORE_EVNTSEL_COUNTER_MASK)
102 return event
& CORE_EVNTSEL_MASK
;
106 * AMD Performance Monitor K7 and later.
108 static const u64 amd_perfmon_event_map
[] =
110 [PERF_COUNT_CPU_CYCLES
] = 0x0076,
111 [PERF_COUNT_INSTRUCTIONS
] = 0x00c0,
112 [PERF_COUNT_CACHE_REFERENCES
] = 0x0080,
113 [PERF_COUNT_CACHE_MISSES
] = 0x0081,
114 [PERF_COUNT_BRANCH_INSTRUCTIONS
] = 0x00c4,
115 [PERF_COUNT_BRANCH_MISSES
] = 0x00c5,
118 static u64
amd_pmu_event_map(int event
)
120 return amd_perfmon_event_map
[event
];
123 static u64
amd_pmu_raw_event(u64 event
)
125 #define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
126 #define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
127 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
129 #define K7_EVNTSEL_MASK \
130 (K7_EVNTSEL_EVENT_MASK | \
131 K7_EVNTSEL_UNIT_MASK | \
132 K7_EVNTSEL_COUNTER_MASK)
134 return event
& K7_EVNTSEL_MASK
;
138 * Propagate counter elapsed time into the generic counter.
139 * Can only be executed on the CPU where the counter is active.
140 * Returns the delta events processed.
143 x86_perf_counter_update(struct perf_counter
*counter
,
144 struct hw_perf_counter
*hwc
, int idx
)
146 u64 prev_raw_count
, new_raw_count
, delta
;
149 * Careful: an NMI might modify the previous counter value.
151 * Our tactic to handle this is to first atomically read and
152 * exchange a new raw count - then add that new-prev delta
153 * count to the generic counter atomically:
156 prev_raw_count
= atomic64_read(&hwc
->prev_count
);
157 rdmsrl(hwc
->counter_base
+ idx
, new_raw_count
);
159 if (atomic64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
160 new_raw_count
) != prev_raw_count
)
164 * Now we have the new raw value and have updated the prev
165 * timestamp already. We can now calculate the elapsed delta
166 * (counter-)time and add that to the generic counter.
168 * Careful, not all hw sign-extends above the physical width
169 * of the count, so we do that by clipping the delta to 32 bits:
171 delta
= (u64
)(u32
)((s32
)new_raw_count
- (s32
)prev_raw_count
);
173 atomic64_add(delta
, &counter
->count
);
174 atomic64_sub(delta
, &hwc
->period_left
);
177 static atomic_t num_counters
;
178 static DEFINE_MUTEX(pmc_reserve_mutex
);
180 static bool reserve_pmc_hardware(void)
184 if (nmi_watchdog
== NMI_LOCAL_APIC
)
185 disable_lapic_nmi_watchdog();
187 for (i
= 0; i
< nr_counters_generic
; i
++) {
188 if (!reserve_perfctr_nmi(x86_pmu
->perfctr
+ i
))
192 for (i
= 0; i
< nr_counters_generic
; i
++) {
193 if (!reserve_evntsel_nmi(x86_pmu
->eventsel
+ i
))
200 for (i
--; i
>= 0; i
--)
201 release_evntsel_nmi(x86_pmu
->eventsel
+ i
);
203 i
= nr_counters_generic
;
206 for (i
--; i
>= 0; i
--)
207 release_perfctr_nmi(x86_pmu
->perfctr
+ i
);
209 if (nmi_watchdog
== NMI_LOCAL_APIC
)
210 enable_lapic_nmi_watchdog();
215 static void release_pmc_hardware(void)
219 for (i
= 0; i
< nr_counters_generic
; i
++) {
220 release_perfctr_nmi(x86_pmu
->perfctr
+ i
);
221 release_evntsel_nmi(x86_pmu
->eventsel
+ i
);
224 if (nmi_watchdog
== NMI_LOCAL_APIC
)
225 enable_lapic_nmi_watchdog();
228 static void hw_perf_counter_destroy(struct perf_counter
*counter
)
230 if (atomic_dec_and_mutex_lock(&num_counters
, &pmc_reserve_mutex
)) {
231 release_pmc_hardware();
232 mutex_unlock(&pmc_reserve_mutex
);
237 * Setup the hardware configuration for a given hw_event_type
239 static int __hw_perf_counter_init(struct perf_counter
*counter
)
241 struct perf_counter_hw_event
*hw_event
= &counter
->hw_event
;
242 struct hw_perf_counter
*hwc
= &counter
->hw
;
245 /* disable temporarily */
246 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
249 if (unlikely(!perf_counters_initialized
))
253 if (atomic_inc_not_zero(&num_counters
)) {
254 mutex_lock(&pmc_reserve_mutex
);
255 if (atomic_read(&num_counters
) == 0 && !reserve_pmc_hardware())
258 atomic_inc(&num_counters
);
259 mutex_unlock(&pmc_reserve_mutex
);
266 * (keep 'enabled' bit clear for now)
268 hwc
->config
= ARCH_PERFMON_EVENTSEL_INT
;
271 * Count user and OS events unless requested not to.
273 if (!hw_event
->exclude_user
)
274 hwc
->config
|= ARCH_PERFMON_EVENTSEL_USR
;
275 if (!hw_event
->exclude_kernel
)
276 hwc
->config
|= ARCH_PERFMON_EVENTSEL_OS
;
279 * If privileged enough, allow NMI events:
282 if (capable(CAP_SYS_ADMIN
) && hw_event
->nmi
)
285 hwc
->irq_period
= hw_event
->irq_period
;
287 * Intel PMCs cannot be accessed sanely above 32 bit width,
288 * so we install an artificial 1<<31 period regardless of
289 * the generic counter period:
291 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
292 if ((s64
)hwc
->irq_period
<= 0 || hwc
->irq_period
> 0x7FFFFFFF)
293 hwc
->irq_period
= 0x7FFFFFFF;
295 atomic64_set(&hwc
->period_left
, hwc
->irq_period
);
298 * Raw event type provide the config in the event structure
300 if (perf_event_raw(hw_event
)) {
301 hwc
->config
|= x86_pmu
->raw_event(perf_event_config(hw_event
));
303 if (perf_event_id(hw_event
) >= x86_pmu
->max_events
)
308 hwc
->config
|= x86_pmu
->event_map(perf_event_id(hw_event
));
311 counter
->destroy
= hw_perf_counter_destroy
;
316 static u64
intel_pmu_save_disable_all(void)
320 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
321 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, 0);
326 static u64
amd_pmu_save_disable_all(void)
328 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
331 enabled
= cpuc
->enabled
;
334 * ensure we write the disable before we start disabling the
335 * counters proper, so that amd_pmu_enable_counter() does the
340 for (idx
= 0; idx
< nr_counters_generic
; idx
++) {
343 if (!test_bit(idx
, cpuc
->active_mask
))
345 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
346 if (!(val
& ARCH_PERFMON_EVENTSEL0_ENABLE
))
348 val
&= ~ARCH_PERFMON_EVENTSEL0_ENABLE
;
349 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
355 u64
hw_perf_save_disable(void)
357 if (unlikely(!perf_counters_initialized
))
360 return x86_pmu
->save_disable_all();
363 * Exported because of ACPI idle
365 EXPORT_SYMBOL_GPL(hw_perf_save_disable
);
367 static void intel_pmu_restore_all(u64 ctrl
)
369 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
372 static void amd_pmu_restore_all(u64 ctrl
)
374 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
377 cpuc
->enabled
= ctrl
;
382 for (idx
= 0; idx
< nr_counters_generic
; idx
++) {
385 if (!test_bit(idx
, cpuc
->active_mask
))
387 rdmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
388 if (val
& ARCH_PERFMON_EVENTSEL0_ENABLE
)
390 val
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
391 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, val
);
395 void hw_perf_restore(u64 ctrl
)
397 if (unlikely(!perf_counters_initialized
))
400 x86_pmu
->restore_all(ctrl
);
403 * Exported because of ACPI idle
405 EXPORT_SYMBOL_GPL(hw_perf_restore
);
407 static inline u64
intel_pmu_get_status(u64 mask
)
411 if (unlikely(!perf_counters_initialized
))
413 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
418 static void intel_pmu_ack_status(u64 ack
)
420 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, ack
);
423 static void amd_pmu_ack_status(u64 ack
)
427 static void hw_perf_ack_status(u64 ack
)
429 if (unlikely(!perf_counters_initialized
))
432 x86_pmu
->ack_status(ack
);
435 static void intel_pmu_enable_counter(int idx
, u64 config
)
437 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ idx
,
438 config
| ARCH_PERFMON_EVENTSEL0_ENABLE
);
441 static void amd_pmu_enable_counter(int idx
, u64 config
)
443 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
445 set_bit(idx
, cpuc
->active_mask
);
447 config
|= ARCH_PERFMON_EVENTSEL0_ENABLE
;
449 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, config
);
452 static void hw_perf_enable(int idx
, u64 config
)
454 if (unlikely(!perf_counters_initialized
))
457 x86_pmu
->enable(idx
, config
);
460 static void intel_pmu_disable_counter(int idx
, u64 config
)
462 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0
+ idx
, config
);
465 static void amd_pmu_disable_counter(int idx
, u64 config
)
467 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
469 clear_bit(idx
, cpuc
->active_mask
);
470 wrmsrl(MSR_K7_EVNTSEL0
+ idx
, config
);
474 static void hw_perf_disable(int idx
, u64 config
)
476 if (unlikely(!perf_counters_initialized
))
479 x86_pmu
->disable(idx
, config
);
483 __pmc_fixed_disable(struct perf_counter
*counter
,
484 struct hw_perf_counter
*hwc
, unsigned int __idx
)
486 int idx
= __idx
- X86_PMC_IDX_FIXED
;
490 mask
= 0xfULL
<< (idx
* 4);
492 rdmsrl(hwc
->config_base
, ctrl_val
);
494 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
498 __x86_pmu_disable(struct perf_counter
*counter
,
499 struct hw_perf_counter
*hwc
, unsigned int idx
)
501 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
))
502 __pmc_fixed_disable(counter
, hwc
, idx
);
504 hw_perf_disable(idx
, hwc
->config
);
507 static DEFINE_PER_CPU(u64
, prev_left
[X86_PMC_IDX_MAX
]);
510 * Set the next IRQ period, based on the hwc->period_left value.
511 * To be called with the counter disabled in hw:
514 __hw_perf_counter_set_period(struct perf_counter
*counter
,
515 struct hw_perf_counter
*hwc
, int idx
)
517 s64 left
= atomic64_read(&hwc
->period_left
);
518 s64 period
= hwc
->irq_period
;
522 * If we are way outside a reasoable range then just skip forward:
524 if (unlikely(left
<= -period
)) {
526 atomic64_set(&hwc
->period_left
, left
);
529 if (unlikely(left
<= 0)) {
531 atomic64_set(&hwc
->period_left
, left
);
534 per_cpu(prev_left
[idx
], smp_processor_id()) = left
;
537 * The hw counter starts counting from this counter offset,
538 * mark it to be able to extra future deltas:
540 atomic64_set(&hwc
->prev_count
, (u64
)-left
);
542 err
= checking_wrmsrl(hwc
->counter_base
+ idx
,
543 (u64
)(-left
) & counter_value_mask
);
547 __pmc_fixed_enable(struct perf_counter
*counter
,
548 struct hw_perf_counter
*hwc
, unsigned int __idx
)
550 int idx
= __idx
- X86_PMC_IDX_FIXED
;
551 u64 ctrl_val
, bits
, mask
;
555 * Enable IRQ generation (0x8),
556 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
560 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_USR
)
562 if (hwc
->config
& ARCH_PERFMON_EVENTSEL_OS
)
565 mask
= 0xfULL
<< (idx
* 4);
567 rdmsrl(hwc
->config_base
, ctrl_val
);
570 err
= checking_wrmsrl(hwc
->config_base
, ctrl_val
);
574 __x86_pmu_enable(struct perf_counter
*counter
,
575 struct hw_perf_counter
*hwc
, int idx
)
577 if (unlikely(hwc
->config_base
== MSR_ARCH_PERFMON_FIXED_CTR_CTRL
))
578 __pmc_fixed_enable(counter
, hwc
, idx
);
580 hw_perf_enable(idx
, hwc
->config
);
584 fixed_mode_idx(struct perf_counter
*counter
, struct hw_perf_counter
*hwc
)
588 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
591 if (unlikely(hwc
->nmi
))
594 event
= hwc
->config
& ARCH_PERFMON_EVENT_MASK
;
596 if (unlikely(event
== x86_pmu
->event_map(PERF_COUNT_INSTRUCTIONS
)))
597 return X86_PMC_IDX_FIXED_INSTRUCTIONS
;
598 if (unlikely(event
== x86_pmu
->event_map(PERF_COUNT_CPU_CYCLES
)))
599 return X86_PMC_IDX_FIXED_CPU_CYCLES
;
600 if (unlikely(event
== x86_pmu
->event_map(PERF_COUNT_BUS_CYCLES
)))
601 return X86_PMC_IDX_FIXED_BUS_CYCLES
;
607 * Find a PMC slot for the freshly enabled / scheduled in counter:
609 static int x86_pmu_enable(struct perf_counter
*counter
)
611 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
612 struct hw_perf_counter
*hwc
= &counter
->hw
;
615 idx
= fixed_mode_idx(counter
, hwc
);
618 * Try to get the fixed counter, if that is already taken
619 * then try to get a generic counter:
621 if (test_and_set_bit(idx
, cpuc
->used
))
624 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
626 * We set it so that counter_base + idx in wrmsr/rdmsr maps to
627 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
630 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
634 /* Try to get the previous generic counter again */
635 if (test_and_set_bit(idx
, cpuc
->used
)) {
637 idx
= find_first_zero_bit(cpuc
->used
, nr_counters_generic
);
638 if (idx
== nr_counters_generic
)
641 set_bit(idx
, cpuc
->used
);
644 hwc
->config_base
= x86_pmu
->eventsel
;
645 hwc
->counter_base
= x86_pmu
->perfctr
;
648 perf_counters_lapic_init(hwc
->nmi
);
650 __x86_pmu_disable(counter
, hwc
, idx
);
652 cpuc
->counters
[idx
] = counter
;
654 * Make it visible before enabling the hw:
658 __hw_perf_counter_set_period(counter
, hwc
, idx
);
659 __x86_pmu_enable(counter
, hwc
, idx
);
664 void perf_counter_print_debug(void)
666 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
667 struct cpu_hw_counters
*cpuc
;
670 if (!nr_counters_generic
)
675 cpu
= smp_processor_id();
676 cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
678 if (intel_perfmon_version
>= 2) {
679 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
680 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
681 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
682 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
685 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
686 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
687 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
688 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
690 pr_info("CPU#%d: used: %016llx\n", cpu
, *(u64
*)cpuc
->used
);
692 for (idx
= 0; idx
< nr_counters_generic
; idx
++) {
693 rdmsrl(x86_pmu
->eventsel
+ idx
, pmc_ctrl
);
694 rdmsrl(x86_pmu
->perfctr
+ idx
, pmc_count
);
696 prev_left
= per_cpu(prev_left
[idx
], cpu
);
698 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
700 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
701 cpu
, idx
, pmc_count
);
702 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
703 cpu
, idx
, prev_left
);
705 for (idx
= 0; idx
< nr_counters_fixed
; idx
++) {
706 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
708 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
709 cpu
, idx
, pmc_count
);
714 static void x86_pmu_disable(struct perf_counter
*counter
)
716 struct cpu_hw_counters
*cpuc
= &__get_cpu_var(cpu_hw_counters
);
717 struct hw_perf_counter
*hwc
= &counter
->hw
;
718 unsigned int idx
= hwc
->idx
;
720 __x86_pmu_disable(counter
, hwc
, idx
);
722 clear_bit(idx
, cpuc
->used
);
723 cpuc
->counters
[idx
] = NULL
;
725 * Make sure the cleared pointer becomes visible before we
726 * (potentially) free the counter:
731 * Drain the remaining delta count out of a counter
732 * that we are disabling:
734 x86_perf_counter_update(counter
, hwc
, idx
);
738 * Save and restart an expired counter. Called by NMI contexts,
739 * so it has to be careful about preempting normal counter ops:
741 static void perf_save_and_restart(struct perf_counter
*counter
)
743 struct hw_perf_counter
*hwc
= &counter
->hw
;
746 x86_perf_counter_update(counter
, hwc
, idx
);
747 __hw_perf_counter_set_period(counter
, hwc
, idx
);
749 if (counter
->state
== PERF_COUNTER_STATE_ACTIVE
)
750 __x86_pmu_enable(counter
, hwc
, idx
);
754 * Maximum interrupt frequency of 100KHz per CPU
756 #define PERFMON_MAX_INTERRUPTS (100000/HZ)
759 * This handler is triggered by the local APIC, so the APIC IRQ handling
762 static int intel_pmu_handle_irq(struct pt_regs
*regs
, int nmi
)
764 int bit
, cpu
= smp_processor_id();
766 struct cpu_hw_counters
*cpuc
= &per_cpu(cpu_hw_counters
, cpu
);
769 cpuc
->throttle_ctrl
= hw_perf_save_disable();
771 status
= intel_pmu_get_status(cpuc
->throttle_ctrl
);
777 inc_irq_stat(apic_perf_irqs
);
779 for_each_bit(bit
, (unsigned long *)&status
, X86_PMC_IDX_MAX
) {
780 struct perf_counter
*counter
= cpuc
->counters
[bit
];
782 clear_bit(bit
, (unsigned long *) &status
);
786 perf_save_and_restart(counter
);
787 if (perf_counter_overflow(counter
, nmi
, regs
, 0))
788 __x86_pmu_disable(counter
, &counter
->hw
, bit
);
791 hw_perf_ack_status(ack
);
794 * Repeat if there is more work to be done:
796 status
= intel_pmu_get_status(cpuc
->throttle_ctrl
);
801 * Restore - do not reenable when global enable is off or throttled:
803 if (++cpuc
->interrupts
< PERFMON_MAX_INTERRUPTS
)
804 hw_perf_restore(cpuc
->throttle_ctrl
);
809 static int amd_pmu_handle_irq(struct pt_regs
*regs
, int nmi
) { return 0; }
811 void perf_counter_unthrottle(void)
813 struct cpu_hw_counters
*cpuc
;
815 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
818 if (unlikely(!perf_counters_initialized
))
821 cpuc
= &__get_cpu_var(cpu_hw_counters
);
822 if (cpuc
->interrupts
>= PERFMON_MAX_INTERRUPTS
) {
823 if (printk_ratelimit())
824 printk(KERN_WARNING
"PERFMON: max interrupts exceeded!\n");
825 hw_perf_restore(cpuc
->throttle_ctrl
);
827 cpuc
->interrupts
= 0;
830 void smp_perf_counter_interrupt(struct pt_regs
*regs
)
833 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
835 x86_pmu
->handle_irq(regs
, 0);
839 void smp_perf_pending_interrupt(struct pt_regs
*regs
)
843 inc_irq_stat(apic_pending_irqs
);
844 perf_counter_do_pending();
848 void set_perf_counter_pending(void)
850 apic
->send_IPI_self(LOCAL_PENDING_VECTOR
);
853 void perf_counters_lapic_init(int nmi
)
857 if (!perf_counters_initialized
)
860 * Enable the performance counter vector in the APIC LVT:
862 apic_val
= apic_read(APIC_LVTERR
);
864 apic_write(APIC_LVTERR
, apic_val
| APIC_LVT_MASKED
);
866 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
868 apic_write(APIC_LVTPC
, LOCAL_PERF_VECTOR
);
869 apic_write(APIC_LVTERR
, apic_val
);
873 perf_counter_nmi_handler(struct notifier_block
*self
,
874 unsigned long cmd
, void *__args
)
876 struct die_args
*args
= __args
;
877 struct pt_regs
*regs
;
891 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
892 ret
= x86_pmu
->handle_irq(regs
, 1);
894 return ret
? NOTIFY_STOP
: NOTIFY_OK
;
897 static __read_mostly
struct notifier_block perf_counter_nmi_notifier
= {
898 .notifier_call
= perf_counter_nmi_handler
,
903 static struct x86_pmu intel_pmu
= {
904 .handle_irq
= intel_pmu_handle_irq
,
905 .save_disable_all
= intel_pmu_save_disable_all
,
906 .restore_all
= intel_pmu_restore_all
,
907 .ack_status
= intel_pmu_ack_status
,
908 .enable
= intel_pmu_enable_counter
,
909 .disable
= intel_pmu_disable_counter
,
910 .eventsel
= MSR_ARCH_PERFMON_EVENTSEL0
,
911 .perfctr
= MSR_ARCH_PERFMON_PERFCTR0
,
912 .event_map
= intel_pmu_event_map
,
913 .raw_event
= intel_pmu_raw_event
,
914 .max_events
= ARRAY_SIZE(intel_perfmon_event_map
),
917 static struct x86_pmu amd_pmu
= {
918 .handle_irq
= amd_pmu_handle_irq
,
919 .save_disable_all
= amd_pmu_save_disable_all
,
920 .restore_all
= amd_pmu_restore_all
,
921 .ack_status
= amd_pmu_ack_status
,
922 .enable
= amd_pmu_enable_counter
,
923 .disable
= amd_pmu_disable_counter
,
924 .eventsel
= MSR_K7_EVNTSEL0
,
925 .perfctr
= MSR_K7_PERFCTR0
,
926 .event_map
= amd_pmu_event_map
,
927 .raw_event
= amd_pmu_raw_event
,
928 .max_events
= ARRAY_SIZE(amd_perfmon_event_map
),
931 static struct x86_pmu
*intel_pmu_init(void)
933 union cpuid10_edx edx
;
934 union cpuid10_eax eax
;
938 if (!cpu_has(&boot_cpu_data
, X86_FEATURE_ARCH_PERFMON
))
942 * Check whether the Architectural PerfMon supports
943 * Branch Misses Retired Event or not.
945 cpuid(10, &eax
.full
, &ebx
, &unused
, &edx
.full
);
946 if (eax
.split
.mask_length
<= ARCH_PERFMON_BRANCH_MISSES_RETIRED
)
949 intel_perfmon_version
= eax
.split
.version_id
;
950 if (intel_perfmon_version
< 2)
953 pr_info("Intel Performance Monitoring support detected.\n");
954 pr_info("... version: %d\n", intel_perfmon_version
);
955 pr_info("... bit width: %d\n", eax
.split
.bit_width
);
956 pr_info("... mask length: %d\n", eax
.split
.mask_length
);
958 nr_counters_generic
= eax
.split
.num_counters
;
959 nr_counters_fixed
= edx
.split
.num_counters_fixed
;
960 counter_value_mask
= (1ULL << eax
.split
.bit_width
) - 1;
965 static struct x86_pmu
*amd_pmu_init(void)
967 nr_counters_generic
= 4;
968 nr_counters_fixed
= 0;
969 counter_value_mask
= 0x0000FFFFFFFFFFFFULL
;
970 counter_value_bits
= 48;
972 pr_info("AMD Performance Monitoring support detected.\n");
977 void __init
init_hw_perf_counters(void)
979 switch (boot_cpu_data
.x86_vendor
) {
980 case X86_VENDOR_INTEL
:
981 x86_pmu
= intel_pmu_init();
984 x86_pmu
= amd_pmu_init();
992 pr_info("... num counters: %d\n", nr_counters_generic
);
993 if (nr_counters_generic
> X86_PMC_MAX_GENERIC
) {
994 nr_counters_generic
= X86_PMC_MAX_GENERIC
;
995 WARN(1, KERN_ERR
"hw perf counters %d > max(%d), clipping!",
996 nr_counters_generic
, X86_PMC_MAX_GENERIC
);
998 perf_counter_mask
= (1 << nr_counters_generic
) - 1;
999 perf_max_counters
= nr_counters_generic
;
1001 pr_info("... value mask: %016Lx\n", counter_value_mask
);
1003 if (nr_counters_fixed
> X86_PMC_MAX_FIXED
) {
1004 nr_counters_fixed
= X86_PMC_MAX_FIXED
;
1005 WARN(1, KERN_ERR
"hw perf counters fixed %d > max(%d), clipping!",
1006 nr_counters_fixed
, X86_PMC_MAX_FIXED
);
1008 pr_info("... fixed counters: %d\n", nr_counters_fixed
);
1010 perf_counter_mask
|= ((1LL << nr_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
1012 pr_info("... counter mask: %016Lx\n", perf_counter_mask
);
1013 perf_counters_initialized
= true;
1015 perf_counters_lapic_init(0);
1016 register_die_notifier(&perf_counter_nmi_notifier
);
1019 static void x86_pmu_read(struct perf_counter
*counter
)
1021 x86_perf_counter_update(counter
, &counter
->hw
, counter
->hw
.idx
);
1024 static const struct pmu pmu
= {
1025 .enable
= x86_pmu_enable
,
1026 .disable
= x86_pmu_disable
,
1027 .read
= x86_pmu_read
,
1030 const struct pmu
*hw_perf_counter_init(struct perf_counter
*counter
)
1034 err
= __hw_perf_counter_init(counter
);
1036 return ERR_PTR(err
);
1046 void callchain_store(struct perf_callchain_entry
*entry
, unsigned long ip
)
1048 if (entry
->nr
< MAX_STACK_DEPTH
)
1049 entry
->ip
[entry
->nr
++] = ip
;
1052 static DEFINE_PER_CPU(struct perf_callchain_entry
, irq_entry
);
1053 static DEFINE_PER_CPU(struct perf_callchain_entry
, nmi_entry
);
1057 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1059 /* Ignore warnings */
1062 static void backtrace_warning(void *data
, char *msg
)
1064 /* Ignore warnings */
1067 static int backtrace_stack(void *data
, char *name
)
1069 /* Don't bother with IRQ stacks for now */
1073 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1075 struct perf_callchain_entry
*entry
= data
;
1078 callchain_store(entry
, addr
);
1081 static const struct stacktrace_ops backtrace_ops
= {
1082 .warning
= backtrace_warning
,
1083 .warning_symbol
= backtrace_warning_symbol
,
1084 .stack
= backtrace_stack
,
1085 .address
= backtrace_address
,
1089 perf_callchain_kernel(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1095 callchain_store(entry
, instruction_pointer(regs
));
1097 stack
= ((char *)regs
+ sizeof(struct pt_regs
));
1098 #ifdef CONFIG_FRAME_POINTER
1099 bp
= frame_pointer(regs
);
1104 dump_trace(NULL
, regs
, (void *)stack
, bp
, &backtrace_ops
, entry
);
1106 entry
->kernel
= entry
->nr
- nr
;
1110 struct stack_frame
{
1111 const void __user
*next_fp
;
1112 unsigned long return_address
;
1115 static int copy_stack_frame(const void __user
*fp
, struct stack_frame
*frame
)
1119 if (!access_ok(VERIFY_READ
, fp
, sizeof(*frame
)))
1123 pagefault_disable();
1124 if (__copy_from_user_inatomic(frame
, fp
, sizeof(*frame
)))
1132 perf_callchain_user(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1134 struct stack_frame frame
;
1135 const void __user
*fp
;
1138 regs
= (struct pt_regs
*)current
->thread
.sp0
- 1;
1139 fp
= (void __user
*)regs
->bp
;
1141 callchain_store(entry
, regs
->ip
);
1143 while (entry
->nr
< MAX_STACK_DEPTH
) {
1144 frame
.next_fp
= NULL
;
1145 frame
.return_address
= 0;
1147 if (!copy_stack_frame(fp
, &frame
))
1150 if ((unsigned long)fp
< user_stack_pointer(regs
))
1153 callchain_store(entry
, frame
.return_address
);
1157 entry
->user
= entry
->nr
- nr
;
1161 perf_do_callchain(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1168 is_user
= user_mode(regs
);
1170 if (!current
|| current
->pid
== 0)
1173 if (is_user
&& current
->state
!= TASK_RUNNING
)
1177 perf_callchain_kernel(regs
, entry
);
1180 perf_callchain_user(regs
, entry
);
1183 struct perf_callchain_entry
*perf_callchain(struct pt_regs
*regs
)
1185 struct perf_callchain_entry
*entry
;
1188 entry
= &__get_cpu_var(nmi_entry
);
1190 entry
= &__get_cpu_var(irq_entry
);
1197 perf_do_callchain(regs
, entry
);