drivers/net/chelsio/cpl5_cmd.h

   1 /*****************************************************************************
   2  *                                                                           *
   3  * File: cpl5_cmd.h                                                          *
   4  * $Revision: 1.6 $                                                          *
   5  * $Date: 2005/06/21 18:29:47 $                                              *
   6  * Description:                                                              *
   7  *  part of the Chelsio 10Gb Ethernet Driver.                                *
   8  *                                                                           *
   9  * This program is free software; you can redistribute it and/or modify      *
  10  * it under the terms of the GNU General Public License, version 2, as       *
  11  * published by the Free Software Foundation.                                *
  12  *                                                                           *
  13  * You should have received a copy of the GNU General Public License along   *
  14  * with this program; if not, write to the Free Software Foundation, Inc.,   *
  15  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
  16  *                                                                           *
  17  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
  18  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
  19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
  20  *                                                                           *
  21  * http://www.chelsio.com                                                    *
  22  *                                                                           *
  23  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
  24  * All rights reserved.                                                      *
  25  *                                                                           *
  26  * Maintainers: maintainers@chelsio.com                                      *
  27  *                                                                           *
  28  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
  29  *          Tina Yang               <tainay@chelsio.com>                     *
  30  *          Felix Marti             <felix@chelsio.com>                      *
  31  *          Scott Bardone           <sbardone@chelsio.com>                   *
  32  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
  33  *          Frank DiMambro          <frank@chelsio.com>                      *
  34  *                                                                           *
  35  * History:                                                                  *
  36  *                                                                           *
  37  ****************************************************************************/
  38
  39 #ifndef _CXGB_CPL5_CMD_H_
  40 #define _CXGB_CPL5_CMD_H_
  41
  42 #include <asm/byteorder.h>
  43
  44 #if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
  45 #error "Adjust your <asm/byteorder.h> defines"
  46 #endif
  47
  48 enum CPL_opcode {
  49         CPL_PASS_OPEN_REQ     = 0x1,
  50         CPL_PASS_OPEN_RPL     = 0x2,
  51         CPL_PASS_ESTABLISH    = 0x3,
  52         CPL_PASS_ACCEPT_REQ   = 0xE,
  53         CPL_PASS_ACCEPT_RPL   = 0x4,
  54         CPL_ACT_OPEN_REQ      = 0x5,
  55         CPL_ACT_OPEN_RPL      = 0x6,
  56         CPL_CLOSE_CON_REQ     = 0x7,
  57         CPL_CLOSE_CON_RPL     = 0x8,
  58         CPL_CLOSE_LISTSRV_REQ = 0x9,
  59         CPL_CLOSE_LISTSRV_RPL = 0xA,
  60         CPL_ABORT_REQ         = 0xB,
  61         CPL_ABORT_RPL         = 0xC,
  62         CPL_PEER_CLOSE        = 0xD,
  63         CPL_ACT_ESTABLISH     = 0x17,
  64
  65         CPL_GET_TCB           = 0x24,
  66         CPL_GET_TCB_RPL       = 0x25,
  67         CPL_SET_TCB           = 0x26,
  68         CPL_SET_TCB_FIELD     = 0x27,
  69         CPL_SET_TCB_RPL       = 0x28,
  70         CPL_PCMD              = 0x29,
  71
  72         CPL_PCMD_READ         = 0x31,
  73         CPL_PCMD_READ_RPL     = 0x32,
  74
  75
  76         CPL_RX_DATA           = 0xA0,
  77         CPL_RX_DATA_DDP       = 0xA1,
  78         CPL_RX_DATA_ACK       = 0xA3,
  79         CPL_RX_PKT            = 0xAD,
  80         CPL_RX_ISCSI_HDR      = 0xAF,
  81         CPL_TX_DATA_ACK       = 0xB0,
  82         CPL_TX_DATA           = 0xB1,
  83         CPL_TX_PKT            = 0xB2,
  84         CPL_TX_PKT_LSO        = 0xB6,
  85
  86         CPL_RTE_DELETE_REQ    = 0xC0,
  87         CPL_RTE_DELETE_RPL    = 0xC1,
  88         CPL_RTE_WRITE_REQ     = 0xC2,
  89         CPL_RTE_WRITE_RPL     = 0xD3,
  90         CPL_RTE_READ_REQ      = 0xC3,
  91         CPL_RTE_READ_RPL      = 0xC4,
  92         CPL_L2T_WRITE_REQ     = 0xC5,
  93         CPL_L2T_WRITE_RPL     = 0xD4,
  94         CPL_L2T_READ_REQ      = 0xC6,
  95         CPL_L2T_READ_RPL      = 0xC7,
  96         CPL_SMT_WRITE_REQ     = 0xC8,
  97         CPL_SMT_WRITE_RPL     = 0xD5,
  98         CPL_SMT_READ_REQ      = 0xC9,
  99         CPL_SMT_READ_RPL      = 0xCA,
 100         CPL_ARP_MISS_REQ      = 0xCD,
 101         CPL_ARP_MISS_RPL      = 0xCE,
 102         CPL_MIGRATE_C2T_REQ   = 0xDC,
 103         CPL_MIGRATE_C2T_RPL   = 0xDD,
 104         CPL_ERROR             = 0xD7,
 105
 106         /* internal: driver -> TOM */
 107         CPL_MSS_CHANGE        = 0xE1
 108 };
 109
 110 #define NUM_CPL_CMDS 256
 111
 112 enum CPL_error {
 113         CPL_ERR_NONE               = 0,
 114         CPL_ERR_TCAM_PARITY        = 1,
 115         CPL_ERR_TCAM_FULL          = 3,
 116         CPL_ERR_CONN_RESET         = 20,
 117         CPL_ERR_CONN_EXIST         = 22,
 118         CPL_ERR_ARP_MISS           = 23,
 119         CPL_ERR_BAD_SYN            = 24,
 120         CPL_ERR_CONN_TIMEDOUT      = 30,
 121         CPL_ERR_XMIT_TIMEDOUT      = 31,
 122         CPL_ERR_PERSIST_TIMEDOUT   = 32,
 123         CPL_ERR_FINWAIT2_TIMEDOUT  = 33,
 124         CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
 125         CPL_ERR_ABORT_FAILED       = 42,
 126         CPL_ERR_GENERAL            = 99
 127 };
 128
 129 enum {
 130         CPL_CONN_POLICY_AUTO = 0,
 131         CPL_CONN_POLICY_ASK  = 1,
 132         CPL_CONN_POLICY_DENY = 3
 133 };
 134
 135 enum {
 136         ULP_MODE_NONE   = 0,
 137         ULP_MODE_TCPDDP = 1,
 138         ULP_MODE_ISCSI  = 2,
 139         ULP_MODE_IWARP  = 3,
 140         ULP_MODE_SSL    = 4
 141 };
 142
 143 enum {
 144         CPL_PASS_OPEN_ACCEPT,
 145         CPL_PASS_OPEN_REJECT
 146 };
 147
 148 enum {
 149         CPL_ABORT_SEND_RST = 0,
 150         CPL_ABORT_NO_RST,
 151         CPL_ABORT_POST_CLOSE_REQ = 2
 152 };
 153
 154 enum {                // TX_PKT_LSO ethernet types
 155         CPL_ETH_II,
 156         CPL_ETH_II_VLAN,
 157         CPL_ETH_802_3,
 158         CPL_ETH_802_3_VLAN
 159 };
 160
 161 union opcode_tid {
 162         u32 opcode_tid;
 163         u8 opcode;
 164 };
 165
 166 #define S_OPCODE 24
 167 #define V_OPCODE(x) ((x) << S_OPCODE)
 168 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
 169 #define G_TID(x)    ((x) & 0xFFFFFF)
 170
 171 /* tid is assumed to be 24-bits */
 172 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
 173
 174 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
 175
 176 /* extract the TID from a CPL command */
 177 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
 178
 179 struct tcp_options {
 180         u16 mss;
 181         u8 wsf;
 182 #if defined(__LITTLE_ENDIAN_BITFIELD)
 183         u8 rsvd:4;
 184         u8 ecn:1;
 185         u8 sack:1;
 186         u8 tstamp:1;
 187 #else
 188         u8 tstamp:1;
 189         u8 sack:1;
 190         u8 ecn:1;
 191         u8 rsvd:4;
 192 #endif
 193 };
 194
 195 struct cpl_pass_open_req {
 196         union opcode_tid ot;
 197         u16 local_port;
 198         u16 peer_port;
 199         u32 local_ip;
 200         u32 peer_ip;
 201         u32 opt0h;
 202         u32 opt0l;
 203         u32 peer_netmask;
 204         u32 opt1;
 205 };
 206
 207 struct cpl_pass_open_rpl {
 208         union opcode_tid ot;
 209         u16 local_port;
 210         u16 peer_port;
 211         u32 local_ip;
 212         u32 peer_ip;
 213         u8 resvd[7];
 214         u8 status;
 215 };
 216
 217 struct cpl_pass_establish {
 218         union opcode_tid ot;
 219         u16 local_port;
 220         u16 peer_port;
 221         u32 local_ip;
 222         u32 peer_ip;
 223         u32 tos_tid;
 224         u8  l2t_idx;
 225         u8  rsvd[3];
 226         u32 snd_isn;
 227         u32 rcv_isn;
 228 };
 229
 230 struct cpl_pass_accept_req {
 231         union opcode_tid ot;
 232         u16 local_port;
 233         u16 peer_port;
 234         u32 local_ip;
 235         u32 peer_ip;
 236         u32 tos_tid;
 237         struct tcp_options tcp_options;
 238         u8  dst_mac[6];
 239         u16 vlan_tag;
 240         u8  src_mac[6];
 241         u8  rsvd[2];
 242         u32 rcv_isn;
 243         u32 unknown_tcp_options;
 244 };
 245
 246 struct cpl_pass_accept_rpl {
 247         union opcode_tid ot;
 248         u32 rsvd0;
 249         u32 rsvd1;
 250         u32 peer_ip;
 251         u32 opt0h;
 252         union {
 253                 u32 opt0l;
 254                 struct {
 255                     u8 rsvd[3];
 256                     u8 status;
 257                 };
 258         };
 259 };
 260
 261 struct cpl_act_open_req {
 262         union opcode_tid ot;
 263         u16 local_port;
 264         u16 peer_port;
 265         u32 local_ip;
 266         u32 peer_ip;
 267         u32 opt0h;
 268         u32 opt0l;
 269         u32 iff_vlantag;
 270         u32 rsvd;
 271 };
 272
 273 struct cpl_act_open_rpl {
 274         union opcode_tid ot;
 275         u16 local_port;
 276         u16 peer_port;
 277         u32 local_ip;
 278         u32 peer_ip;
 279         u32 new_tid;
 280         u8  rsvd[3];
 281         u8  status;
 282 };
 283
 284 struct cpl_act_establish {
 285         union opcode_tid ot;
 286         u16 local_port;
 287         u16 peer_port;
 288         u32 local_ip;
 289         u32 peer_ip;
 290         u32 tos_tid;
 291         u32 rsvd;
 292         u32 snd_isn;
 293         u32 rcv_isn;
 294 };
 295
 296 struct cpl_get_tcb {
 297         union opcode_tid ot;
 298         u32 rsvd;
 299 };
 300
 301 struct cpl_get_tcb_rpl {
 302         union opcode_tid ot;
 303         u16 len;
 304         u8 rsvd;
 305         u8 status;
 306 };
 307
 308 struct cpl_set_tcb {
 309         union opcode_tid ot;
 310         u16 len;
 311         u16 rsvd;
 312 };
 313
 314 struct cpl_set_tcb_field {
 315         union opcode_tid ot;
 316         u8 rsvd[3];
 317         u8 offset;
 318         u32 mask;
 319         u32 val;
 320 };
 321
 322 struct cpl_set_tcb_rpl {
 323         union opcode_tid ot;
 324         u8 rsvd[3];
 325         u8 status;
 326 };
 327
 328 struct cpl_pcmd {
 329         union opcode_tid ot;
 330         u16 dlen_in;
 331         u16 dlen_out;
 332         u32 pcmd_parm[2];
 333 };
 334
 335 struct cpl_pcmd_read {
 336         union opcode_tid ot;
 337         u32 rsvd1;
 338         u16 rsvd2;
 339         u32 addr;
 340         u16 len;
 341 };
 342
 343 struct cpl_pcmd_read_rpl {
 344         union opcode_tid ot;
 345         u16 len;
 346 };
 347
 348 struct cpl_close_con_req {
 349         union opcode_tid ot;
 350         u32 rsvd;
 351 };
 352
 353 struct cpl_close_con_rpl {
 354         union opcode_tid ot;
 355         u8 rsvd[3];
 356         u8 status;
 357         u32 snd_nxt;
 358         u32 rcv_nxt;
 359 };
 360
 361 struct cpl_close_listserv_req {
 362         union opcode_tid ot;
 363         u32 rsvd;
 364 };
 365
 366 struct cpl_close_listserv_rpl {
 367         union opcode_tid ot;
 368         u8 rsvd[3];
 369         u8 status;
 370 };
 371
 372 struct cpl_abort_req {
 373         union opcode_tid ot;
 374         u32 rsvd0;
 375         u8  rsvd1;
 376         u8  cmd;
 377         u8  rsvd2[6];
 378 };
 379
 380 struct cpl_abort_rpl {
 381         union opcode_tid ot;
 382         u32 rsvd0;
 383         u8  rsvd1;
 384         u8  status;
 385         u8  rsvd2[6];
 386 };
 387
 388 struct cpl_peer_close {
 389         union opcode_tid ot;
 390         u32 rsvd;
 391 };
 392
 393 struct cpl_tx_data {
 394         union opcode_tid ot;
 395         u32 len;
 396         u32 rsvd0;
 397         u16 urg;
 398         u16 flags;
 399 };
 400
 401 struct cpl_tx_data_ack {
 402         union opcode_tid ot;
 403         u32 ack_seq;
 404 };
 405
 406 struct cpl_rx_data {
 407         union opcode_tid ot;
 408         u32 len;
 409         u32 seq;
 410         u16 urg;
 411         u8  rsvd;
 412         u8  status;
 413 };
 414
 415 struct cpl_rx_data_ack {
 416         union opcode_tid ot;
 417         u32 credit;
 418 };
 419
 420 struct cpl_rx_data_ddp {
 421         union opcode_tid ot;
 422         u32 len;
 423         u32 seq;
 424         u32 nxt_seq;
 425         u32 ulp_crc;
 426         u16 ddp_status;
 427         u8  rsvd;
 428         u8  status;
 429 };
 430
 431 /*
 432  * We want this header's alignment to be no more stringent than 2-byte aligned.
 433  * All fields are u8 or u16 except for the length.  However that field is not
 434  * used so we break it into 2 16-bit parts to easily meet our alignment needs.
 435  */
 436 struct cpl_tx_pkt {
 437         u8 opcode;
 438 #if defined(__LITTLE_ENDIAN_BITFIELD)
 439         u8 iff:4;
 440         u8 ip_csum_dis:1;
 441         u8 l4_csum_dis:1;
 442         u8 vlan_valid:1;
 443         u8 rsvd:1;
 444 #else
 445         u8 rsvd:1;
 446         u8 vlan_valid:1;
 447         u8 l4_csum_dis:1;
 448         u8 ip_csum_dis:1;
 449         u8 iff:4;
 450 #endif
 451         u16 vlan;
 452         u16 len_hi;
 453         u16 len_lo;
 454 };
 455
 456 struct cpl_tx_pkt_lso {
 457         u8 opcode;
 458 #if defined(__LITTLE_ENDIAN_BITFIELD)
 459         u8 iff:4;
 460         u8 ip_csum_dis:1;
 461         u8 l4_csum_dis:1;
 462         u8 vlan_valid:1;
 463         u8 :1;
 464 #else
 465         u8 :1;
 466         u8 vlan_valid:1;
 467         u8 l4_csum_dis:1;
 468         u8 ip_csum_dis:1;
 469         u8 iff:4;
 470 #endif
 471         u16 vlan;
 472         __be32 len;
 473
 474         u8 rsvd[5];
 475 #if defined(__LITTLE_ENDIAN_BITFIELD)
 476         u8 tcp_hdr_words:4;
 477         u8 ip_hdr_words:4;
 478 #else
 479         u8 ip_hdr_words:4;
 480         u8 tcp_hdr_words:4;
 481 #endif
 482         __be16 eth_type_mss;
 483 };
 484
 485 struct cpl_rx_pkt {
 486         u8 opcode;
 487 #if defined(__LITTLE_ENDIAN_BITFIELD)
 488         u8 iff:4;
 489         u8 csum_valid:1;
 490         u8 bad_pkt:1;
 491         u8 vlan_valid:1;
 492         u8 rsvd:1;
 493 #else
 494         u8 rsvd:1;
 495         u8 vlan_valid:1;
 496         u8 bad_pkt:1;
 497         u8 csum_valid:1;
 498         u8 iff:4;
 499 #endif
 500         u16 csum;
 501         u16 vlan;
 502         u16 len;
 503 };
 504
 505 struct cpl_l2t_write_req {
 506         union opcode_tid ot;
 507         u32 params;
 508         u8 rsvd1[2];
 509         u8 dst_mac[6];
 510 };
 511
 512 struct cpl_l2t_write_rpl {
 513         union opcode_tid ot;
 514         u8 status;
 515         u8 rsvd[3];
 516 };
 517
 518 struct cpl_l2t_read_req {
 519         union opcode_tid ot;
 520         u8 rsvd[3];
 521         u8 l2t_idx;
 522 };
 523
 524 struct cpl_l2t_read_rpl {
 525         union opcode_tid ot;
 526         u32 params;
 527         u8 rsvd1[2];
 528         u8 dst_mac[6];
 529 };
 530
 531 struct cpl_smt_write_req {
 532         union opcode_tid ot;
 533         u8 rsvd0;
 534 #if defined(__LITTLE_ENDIAN_BITFIELD)
 535         u8 rsvd1:1;
 536         u8 mtu_idx:3;
 537         u8 iff:4;
 538 #else
 539         u8 iff:4;
 540         u8 mtu_idx:3;
 541         u8 rsvd1:1;
 542 #endif
 543         u16 rsvd2;
 544         u16 rsvd3;
 545         u8  src_mac1[6];
 546         u16 rsvd4;
 547         u8  src_mac0[6];
 548 };
 549
 550 struct cpl_smt_write_rpl {
 551         union opcode_tid ot;
 552         u8 status;
 553         u8 rsvd[3];
 554 };
 555
 556 struct cpl_smt_read_req {
 557         union opcode_tid ot;
 558         u8 rsvd0;
 559 #if defined(__LITTLE_ENDIAN_BITFIELD)
 560         u8 rsvd1:4;
 561         u8 iff:4;
 562 #else
 563         u8 iff:4;
 564         u8 rsvd1:4;
 565 #endif
 566         u16 rsvd2;
 567 };
 568
 569 struct cpl_smt_read_rpl {
 570         union opcode_tid ot;
 571         u8 status;
 572 #if defined(__LITTLE_ENDIAN_BITFIELD)
 573         u8 rsvd1:1;
 574         u8 mtu_idx:3;
 575         u8 rsvd0:4;
 576 #else
 577         u8 rsvd0:4;
 578         u8 mtu_idx:3;
 579         u8 rsvd1:1;
 580 #endif
 581         u16 rsvd2;
 582         u16 rsvd3;
 583         u8  src_mac1[6];
 584         u16 rsvd4;
 585         u8  src_mac0[6];
 586 };
 587
 588 struct cpl_rte_delete_req {
 589         union opcode_tid ot;
 590         u32 params;
 591 };
 592
 593 struct cpl_rte_delete_rpl {
 594         union opcode_tid ot;
 595         u8 status;
 596         u8 rsvd[3];
 597 };
 598
 599 struct cpl_rte_write_req {
 600         union opcode_tid ot;
 601         u32 params;
 602         u32 netmask;
 603         u32 faddr;
 604 };
 605
 606 struct cpl_rte_write_rpl {
 607         union opcode_tid ot;
 608         u8 status;
 609         u8 rsvd[3];
 610 };
 611
 612 struct cpl_rte_read_req {
 613         union opcode_tid ot;
 614         u32 params;
 615 };
 616
 617 struct cpl_rte_read_rpl {
 618         union opcode_tid ot;
 619         u8 status;
 620         u8 rsvd0[2];
 621         u8 l2t_idx;
 622 #if defined(__LITTLE_ENDIAN_BITFIELD)
 623         u8 rsvd1:7;
 624         u8 select:1;
 625 #else
 626         u8 select:1;
 627         u8 rsvd1:7;
 628 #endif
 629         u8 rsvd2[3];
 630         u32 addr;
 631 };
 632
 633 struct cpl_mss_change {
 634         union opcode_tid ot;
 635         u32 mss;
 636 };
 637
 638 #endif /* _CXGB_CPL5_CMD_H_ */
 639