2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
31 #include <linux/dmi.h>
32 #include <linux/dmar.h>
34 #include <asm/atomic.h>
37 #include <asm/mpspec.h>
39 #include <asm/arch_hooks.h>
41 #include <asm/pgalloc.h>
42 #include <asm/i8253.h>
45 #include <asm/proto.h>
46 #include <asm/timex.h>
48 #include <asm/i8259.h>
50 #include <mach_apic.h>
51 #include <mach_apicdef.h>
57 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
58 # error SPURIOUS_APIC_VECTOR definition error
63 * Knob to control our willingness to enable the local APIC.
67 static int force_enable_local_apic
;
69 * APIC command line parameters
71 static int __init
parse_lapic(char *arg
)
73 force_enable_local_apic
= 1;
76 early_param("lapic", parse_lapic
);
77 /* Local APIC was disabled by the BIOS and enabled by the kernel */
78 static int enabled_via_apicbase
;
83 static int apic_calibrate_pmtmr __initdata
;
84 static __init
int setup_apicpmtimer(char *s
)
86 apic_calibrate_pmtmr
= 1;
90 __setup("apicpmtimer", setup_apicpmtimer
);
99 /* x2apic enabled before OS handover */
100 int x2apic_preenabled
;
102 static __init
int setup_nox2apic(char *str
)
105 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
108 early_param("nox2apic", setup_nox2apic
);
111 unsigned long mp_lapic_addr
;
113 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
114 static int disable_apic_timer __cpuinitdata
;
115 /* Local APIC timer works in C2 */
116 int local_apic_timer_c2_ok
;
117 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
119 int first_system_vector
= 0xfe;
122 * Debug level, exported for io_apic.c
124 unsigned int apic_verbosity
;
128 /* Have we found an MP table */
129 int smp_found_config
;
131 static struct resource lapic_resource
= {
132 .name
= "Local APIC",
133 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
136 static unsigned int calibration_result
;
138 static int lapic_next_event(unsigned long delta
,
139 struct clock_event_device
*evt
);
140 static void lapic_timer_setup(enum clock_event_mode mode
,
141 struct clock_event_device
*evt
);
142 static void lapic_timer_broadcast(const cpumask_t
*mask
);
143 static void apic_pm_activate(void);
146 * The local apic timer can be used for any function which is CPU local.
148 static struct clock_event_device lapic_clockevent
= {
150 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
151 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
153 .set_mode
= lapic_timer_setup
,
154 .set_next_event
= lapic_next_event
,
155 .broadcast
= lapic_timer_broadcast
,
159 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
161 static unsigned long apic_phys
;
164 * Get the LAPIC version
166 static inline int lapic_get_version(void)
168 return GET_APIC_VERSION(apic_read(APIC_LVR
));
172 * Check, if the APIC is integrated or a separate chip
174 static inline int lapic_is_integrated(void)
179 return APIC_INTEGRATED(lapic_get_version());
184 * Check, whether this is a modern or a first generation APIC
186 static int modern_apic(void)
188 /* AMD systems use old APIC versions, so check the CPU */
189 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
190 boot_cpu_data
.x86
>= 0xf)
192 return lapic_get_version() >= 0x14;
196 * Paravirt kernels also might be using these below ops. So we still
197 * use generic apic_read()/apic_write(), which might be pointing to different
198 * ops in PARAVIRT case.
200 void xapic_wait_icr_idle(void)
202 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
206 u32
safe_xapic_wait_icr_idle(void)
213 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
217 } while (timeout
++ < 1000);
222 void xapic_icr_write(u32 low
, u32 id
)
224 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
225 apic_write(APIC_ICR
, low
);
228 u64
xapic_icr_read(void)
232 icr2
= apic_read(APIC_ICR2
);
233 icr1
= apic_read(APIC_ICR
);
235 return icr1
| ((u64
)icr2
<< 32);
238 static struct apic_ops xapic_ops
= {
239 .read
= native_apic_mem_read
,
240 .write
= native_apic_mem_write
,
241 .icr_read
= xapic_icr_read
,
242 .icr_write
= xapic_icr_write
,
243 .wait_icr_idle
= xapic_wait_icr_idle
,
244 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
247 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
248 EXPORT_SYMBOL_GPL(apic_ops
);
251 static void x2apic_wait_icr_idle(void)
253 /* no need to wait for icr idle in x2apic */
257 static u32
safe_x2apic_wait_icr_idle(void)
259 /* no need to wait for icr idle in x2apic */
263 void x2apic_icr_write(u32 low
, u32 id
)
265 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
268 u64
x2apic_icr_read(void)
272 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
276 static struct apic_ops x2apic_ops
= {
277 .read
= native_apic_msr_read
,
278 .write
= native_apic_msr_write
,
279 .icr_read
= x2apic_icr_read
,
280 .icr_write
= x2apic_icr_write
,
281 .wait_icr_idle
= x2apic_wait_icr_idle
,
282 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
287 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
289 void __cpuinit
enable_NMI_through_LVT0(void)
293 /* unmask and set to NMI */
296 /* Level triggered for 82489DX (32bit mode) */
297 if (!lapic_is_integrated())
298 v
|= APIC_LVT_LEVEL_TRIGGER
;
300 apic_write(APIC_LVT0
, v
);
305 * get_physical_broadcast - Get number of physical broadcast IDs
307 int get_physical_broadcast(void)
309 return modern_apic() ? 0xff : 0xf;
314 * lapic_get_maxlvt - get the maximum number of local vector table entries
316 int lapic_get_maxlvt(void)
320 v
= apic_read(APIC_LVR
);
322 * - we always have APIC integrated on 64bit mode
323 * - 82489DXs do not report # of LVT entries
325 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
333 #define APIC_DIVISOR 16
336 * This function sets up the local APIC timer, with a timeout of
337 * 'clocks' APIC bus clock. During calibration we actually call
338 * this function twice on the boot CPU, once with a bogus timeout
339 * value, second time for real. The other (noncalibrating) CPUs
340 * call this function only once, with the real, calibrated value.
342 * We do reads before writes even if unnecessary, to get around the
343 * P5 APIC double write bug.
345 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
347 unsigned int lvtt_value
, tmp_value
;
349 lvtt_value
= LOCAL_TIMER_VECTOR
;
351 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
352 if (!lapic_is_integrated())
353 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
356 lvtt_value
|= APIC_LVT_MASKED
;
358 apic_write(APIC_LVTT
, lvtt_value
);
363 tmp_value
= apic_read(APIC_TDCR
);
364 apic_write(APIC_TDCR
,
365 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
369 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
373 * Setup extended LVT, AMD specific (K8, family 10h)
375 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
376 * MCE interrupts are supported. Thus MCE offset must be set to 0.
378 * If mask=1, the LVT entry does not generate interrupts while mask=0
379 * enables the vector. See also the BKDGs.
382 #define APIC_EILVT_LVTOFF_MCE 0
383 #define APIC_EILVT_LVTOFF_IBS 1
385 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
387 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
388 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
393 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
395 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
396 return APIC_EILVT_LVTOFF_MCE
;
399 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
401 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
402 return APIC_EILVT_LVTOFF_IBS
;
404 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
407 * Program the next event, relative to now
409 static int lapic_next_event(unsigned long delta
,
410 struct clock_event_device
*evt
)
412 apic_write(APIC_TMICT
, delta
);
417 * Setup the lapic timer in periodic or oneshot mode
419 static void lapic_timer_setup(enum clock_event_mode mode
,
420 struct clock_event_device
*evt
)
425 /* Lapic used as dummy for broadcast ? */
426 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
429 local_irq_save(flags
);
432 case CLOCK_EVT_MODE_PERIODIC
:
433 case CLOCK_EVT_MODE_ONESHOT
:
434 __setup_APIC_LVTT(calibration_result
,
435 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
437 case CLOCK_EVT_MODE_UNUSED
:
438 case CLOCK_EVT_MODE_SHUTDOWN
:
439 v
= apic_read(APIC_LVTT
);
440 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
441 apic_write(APIC_LVTT
, v
);
442 apic_write(APIC_TMICT
, 0xffffffff);
444 case CLOCK_EVT_MODE_RESUME
:
445 /* Nothing to do here */
449 local_irq_restore(flags
);
453 * Local APIC timer broadcast function
455 static void lapic_timer_broadcast(const cpumask_t
*mask
)
458 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
463 * Setup the local APIC timer for this CPU. Copy the initilized values
464 * of the boot CPU and register the clock event in the framework.
466 static void __cpuinit
setup_APIC_timer(void)
468 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
470 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
471 levt
->cpumask
= cpumask_of(smp_processor_id());
473 clockevents_register_device(levt
);
477 * In this functions we calibrate APIC bus clocks to the external timer.
479 * We want to do the calibration only once since we want to have local timer
480 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
483 * This was previously done by reading the PIT/HPET and waiting for a wrap
484 * around to find out, that a tick has elapsed. I have a box, where the PIT
485 * readout is broken, so it never gets out of the wait loop again. This was
486 * also reported by others.
488 * Monitoring the jiffies value is inaccurate and the clockevents
489 * infrastructure allows us to do a simple substitution of the interrupt
492 * The calibration routine also uses the pm_timer when possible, as the PIT
493 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
494 * back to normal later in the boot process).
497 #define LAPIC_CAL_LOOPS (HZ/10)
499 static __initdata
int lapic_cal_loops
= -1;
500 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
501 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
502 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
503 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
506 * Temporary interrupt handler.
508 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
510 unsigned long long tsc
= 0;
511 long tapic
= apic_read(APIC_TMCCT
);
512 unsigned long pm
= acpi_pm_read_early();
517 switch (lapic_cal_loops
++) {
519 lapic_cal_t1
= tapic
;
520 lapic_cal_tsc1
= tsc
;
522 lapic_cal_j1
= jiffies
;
525 case LAPIC_CAL_LOOPS
:
526 lapic_cal_t2
= tapic
;
527 lapic_cal_tsc2
= tsc
;
528 if (pm
< lapic_cal_pm1
)
529 pm
+= ACPI_PM_OVRRUN
;
531 lapic_cal_j2
= jiffies
;
536 static int __init
calibrate_by_pmtimer(long deltapm
, long *delta
)
538 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
539 const long pm_thresh
= pm_100ms
/ 100;
543 #ifndef CONFIG_X86_PM_TIMER
547 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
549 /* Check, if the PM timer is available */
553 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
555 if (deltapm
> (pm_100ms
- pm_thresh
) &&
556 deltapm
< (pm_100ms
+ pm_thresh
)) {
557 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
559 res
= (((u64
)deltapm
) * mult
) >> 22;
560 do_div(res
, 1000000);
561 pr_warning("APIC calibration not consistent "
562 "with PM Timer: %ldms instead of 100ms\n",
564 /* Correct the lapic counter value */
565 res
= (((u64
)(*delta
)) * pm_100ms
);
566 do_div(res
, deltapm
);
567 pr_info("APIC delta adjusted to PM-Timer: "
568 "%lu (%ld)\n", (unsigned long)res
, *delta
);
575 static int __init
calibrate_APIC_clock(void)
577 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
578 void (*real_handler
)(struct clock_event_device
*dev
);
579 unsigned long deltaj
;
581 int pm_referenced
= 0;
585 /* Replace the global interrupt handler */
586 real_handler
= global_clock_event
->event_handler
;
587 global_clock_event
->event_handler
= lapic_cal_handler
;
590 * Setup the APIC counter to maximum. There is no way the lapic
591 * can underflow in the 100ms detection time frame
593 __setup_APIC_LVTT(0xffffffff, 0, 0);
595 /* Let the interrupts run */
598 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
603 /* Restore the real event handler */
604 global_clock_event
->event_handler
= real_handler
;
606 /* Build delta t1-t2 as apic timer counts down */
607 delta
= lapic_cal_t1
- lapic_cal_t2
;
608 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
610 /* we trust the PM based calibration if possible */
611 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
614 /* Calculate the scaled math multiplication factor */
615 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
616 lapic_clockevent
.shift
);
617 lapic_clockevent
.max_delta_ns
=
618 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
619 lapic_clockevent
.min_delta_ns
=
620 clockevent_delta2ns(0xF, &lapic_clockevent
);
622 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
624 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
625 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
626 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
630 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
631 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
633 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
634 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
637 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
639 calibration_result
/ (1000000 / HZ
),
640 calibration_result
% (1000000 / HZ
));
643 * Do a sanity check on the APIC calibration result
645 if (calibration_result
< (1000000 / HZ
)) {
647 pr_warning("APIC frequency too slow, disabling apic timer\n");
651 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
654 * PM timer calibration failed or not turned on
655 * so lets try APIC timer based calibration
657 if (!pm_referenced
) {
658 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
661 * Setup the apic timer manually
663 levt
->event_handler
= lapic_cal_handler
;
664 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
665 lapic_cal_loops
= -1;
667 /* Let the interrupts run */
670 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
673 /* Stop the lapic timer */
674 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
677 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
678 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
680 /* Check, if the jiffies result is consistent */
681 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
682 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
684 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
688 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
689 pr_warning("APIC timer disabled due to verification failure.\n");
697 * Setup the boot APIC
699 * Calibrate and verify the result.
701 void __init
setup_boot_APIC_clock(void)
704 * The local apic timer can be disabled via the kernel
705 * commandline or from the CPU detection code. Register the lapic
706 * timer as a dummy clock event source on SMP systems, so the
707 * broadcast mechanism is used. On UP systems simply ignore it.
709 if (disable_apic_timer
) {
710 pr_info("Disabling APIC timer\n");
711 /* No broadcast on UP ! */
712 if (num_possible_cpus() > 1) {
713 lapic_clockevent
.mult
= 1;
719 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
720 "calibrating APIC timer ...\n");
722 if (calibrate_APIC_clock()) {
723 /* No broadcast on UP ! */
724 if (num_possible_cpus() > 1)
730 * If nmi_watchdog is set to IO_APIC, we need the
731 * PIT/HPET going. Otherwise register lapic as a dummy
734 if (nmi_watchdog
!= NMI_IO_APIC
)
735 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
737 pr_warning("APIC timer registered as dummy,"
738 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
740 /* Setup the lapic or request the broadcast */
744 void __cpuinit
setup_secondary_APIC_clock(void)
750 * The guts of the apic timer interrupt
752 static void local_apic_timer_interrupt(void)
754 int cpu
= smp_processor_id();
755 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
758 * Normally we should not be here till LAPIC has been initialized but
759 * in some cases like kdump, its possible that there is a pending LAPIC
760 * timer interrupt from previous kernel's context and is delivered in
761 * new kernel the moment interrupts are enabled.
763 * Interrupts are enabled early and LAPIC is setup much later, hence
764 * its possible that when we get here evt->event_handler is NULL.
765 * Check for event_handler being NULL and discard the interrupt as
768 if (!evt
->event_handler
) {
769 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
771 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
776 * the NMI deadlock-detector uses this.
779 add_pda(apic_timer_irqs
, 1);
781 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
784 evt
->event_handler(evt
);
788 * Local APIC timer interrupt. This is the most natural way for doing
789 * local interrupts, but local timer interrupts can be emulated by
790 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
792 * [ if a single-CPU system runs an SMP kernel then we call the local
793 * interrupt as well. Thus we cannot inline the local irq ... ]
795 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
797 struct pt_regs
*old_regs
= set_irq_regs(regs
);
800 * NOTE! We'd better ACK the irq immediately,
801 * because timer handling can be slow.
805 * update_process_times() expects us to have done irq_enter().
806 * Besides, if we don't timer interrupts ignore the global
807 * interrupt lock, which is the WrongThing (tm) to do.
813 local_apic_timer_interrupt();
816 set_irq_regs(old_regs
);
819 int setup_profiling_timer(unsigned int multiplier
)
825 * Local APIC start and shutdown
829 * clear_local_APIC - shutdown the local APIC
831 * This is called, when a CPU is disabled and before rebooting, so the state of
832 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
833 * leftovers during boot.
835 void clear_local_APIC(void)
840 /* APIC hasn't been mapped yet */
844 maxlvt
= lapic_get_maxlvt();
846 * Masking an LVT entry can trigger a local APIC error
847 * if the vector is zero. Mask LVTERR first to prevent this.
850 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
851 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
854 * Careful: we have to set masks only first to deassert
855 * any level-triggered sources.
857 v
= apic_read(APIC_LVTT
);
858 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
859 v
= apic_read(APIC_LVT0
);
860 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
861 v
= apic_read(APIC_LVT1
);
862 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
864 v
= apic_read(APIC_LVTPC
);
865 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
868 /* lets not touch this if we didn't frob it */
869 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
871 v
= apic_read(APIC_LVTTHMR
);
872 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
876 * Clean APIC state for other OSs:
878 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
879 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
880 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
882 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
884 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
886 /* Integrated APIC (!82489DX) ? */
887 if (lapic_is_integrated()) {
889 /* Clear ESR due to Pentium errata 3AP and 11AP */
890 apic_write(APIC_ESR
, 0);
896 * disable_local_APIC - clear and disable the local APIC
898 void disable_local_APIC(void)
905 * Disable APIC (implies clearing of registers
908 value
= apic_read(APIC_SPIV
);
909 value
&= ~APIC_SPIV_APIC_ENABLED
;
910 apic_write(APIC_SPIV
, value
);
914 * When LAPIC was disabled by the BIOS and enabled by the kernel,
915 * restore the disabled state.
917 if (enabled_via_apicbase
) {
920 rdmsr(MSR_IA32_APICBASE
, l
, h
);
921 l
&= ~MSR_IA32_APICBASE_ENABLE
;
922 wrmsr(MSR_IA32_APICBASE
, l
, h
);
928 * If Linux enabled the LAPIC against the BIOS default disable it down before
929 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
930 * not power-off. Additionally clear all LVT entries before disable_local_APIC
931 * for the case where Linux didn't enable the LAPIC.
933 void lapic_shutdown(void)
940 local_irq_save(flags
);
943 if (!enabled_via_apicbase
)
947 disable_local_APIC();
950 local_irq_restore(flags
);
954 * This is to verify that we're looking at a real local APIC.
955 * Check these against your board if the CPUs aren't getting
956 * started for no apparent reason.
958 int __init
verify_local_APIC(void)
960 unsigned int reg0
, reg1
;
963 * The version register is read-only in a real APIC.
965 reg0
= apic_read(APIC_LVR
);
966 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
967 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
968 reg1
= apic_read(APIC_LVR
);
969 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
972 * The two version reads above should print the same
973 * numbers. If the second one is different, then we
974 * poke at a non-APIC.
980 * Check if the version looks reasonably.
982 reg1
= GET_APIC_VERSION(reg0
);
983 if (reg1
== 0x00 || reg1
== 0xff)
985 reg1
= lapic_get_maxlvt();
986 if (reg1
< 0x02 || reg1
== 0xff)
990 * The ID register is read/write in a real APIC.
992 reg0
= apic_read(APIC_ID
);
993 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
994 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
995 reg1
= apic_read(APIC_ID
);
996 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
997 apic_write(APIC_ID
, reg0
);
998 if (reg1
!= (reg0
^ APIC_ID_MASK
))
1002 * The next two are just to see if we have sane values.
1003 * They're only really relevant if we're in Virtual Wire
1004 * compatibility mode, but most boxes are anymore.
1006 reg0
= apic_read(APIC_LVT0
);
1007 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1008 reg1
= apic_read(APIC_LVT1
);
1009 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1015 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1017 void __init
sync_Arb_IDs(void)
1020 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1023 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1029 apic_wait_icr_idle();
1031 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1032 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1033 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1037 * An initial setup of the virtual wire mode.
1039 void __init
init_bsp_APIC(void)
1044 * Don't do the setup now if we have a SMP BIOS as the
1045 * through-I/O-APIC virtual wire mode might be active.
1047 if (smp_found_config
|| !cpu_has_apic
)
1051 * Do not trust the local APIC being empty at bootup.
1058 value
= apic_read(APIC_SPIV
);
1059 value
&= ~APIC_VECTOR_MASK
;
1060 value
|= APIC_SPIV_APIC_ENABLED
;
1062 #ifdef CONFIG_X86_32
1063 /* This bit is reserved on P4/Xeon and should be cleared */
1064 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1065 (boot_cpu_data
.x86
== 15))
1066 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1069 value
|= APIC_SPIV_FOCUS_DISABLED
;
1070 value
|= SPURIOUS_APIC_VECTOR
;
1071 apic_write(APIC_SPIV
, value
);
1074 * Set up the virtual wire mode.
1076 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1077 value
= APIC_DM_NMI
;
1078 if (!lapic_is_integrated()) /* 82489DX */
1079 value
|= APIC_LVT_LEVEL_TRIGGER
;
1080 apic_write(APIC_LVT1
, value
);
1083 static void __cpuinit
lapic_setup_esr(void)
1085 unsigned int oldvalue
, value
, maxlvt
;
1087 if (!lapic_is_integrated()) {
1088 pr_info("No ESR for 82489DX.\n");
1094 * Something untraceable is creating bad interrupts on
1095 * secondary quads ... for the moment, just leave the
1096 * ESR disabled - we can't do anything useful with the
1097 * errors anyway - mbligh
1099 pr_info("Leaving ESR disabled.\n");
1103 maxlvt
= lapic_get_maxlvt();
1104 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1105 apic_write(APIC_ESR
, 0);
1106 oldvalue
= apic_read(APIC_ESR
);
1108 /* enables sending errors */
1109 value
= ERROR_APIC_VECTOR
;
1110 apic_write(APIC_LVTERR
, value
);
1113 * spec says clear errors after enabling vector.
1116 apic_write(APIC_ESR
, 0);
1117 value
= apic_read(APIC_ESR
);
1118 if (value
!= oldvalue
)
1119 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1120 "vector: 0x%08x after: 0x%08x\n",
1126 * setup_local_APIC - setup the local APIC
1128 void __cpuinit
setup_local_APIC(void)
1133 #ifdef CONFIG_X86_32
1134 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1135 if (lapic_is_integrated() && esr_disable
) {
1136 apic_write(APIC_ESR
, 0);
1137 apic_write(APIC_ESR
, 0);
1138 apic_write(APIC_ESR
, 0);
1139 apic_write(APIC_ESR
, 0);
1146 * Double-check whether this APIC is really registered.
1147 * This is meaningless in clustered apic mode, so we skip it.
1149 if (!apic_id_registered())
1153 * Intel recommends to set DFR, LDR and TPR before enabling
1154 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1155 * document number 292116). So here it goes...
1160 * Set Task Priority to 'accept all'. We never change this
1163 value
= apic_read(APIC_TASKPRI
);
1164 value
&= ~APIC_TPRI_MASK
;
1165 apic_write(APIC_TASKPRI
, value
);
1168 * After a crash, we no longer service the interrupts and a pending
1169 * interrupt from previous kernel might still have ISR bit set.
1171 * Most probably by now CPU has serviced that pending interrupt and
1172 * it might not have done the ack_APIC_irq() because it thought,
1173 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1174 * does not clear the ISR bit and cpu thinks it has already serivced
1175 * the interrupt. Hence a vector might get locked. It was noticed
1176 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1178 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1179 value
= apic_read(APIC_ISR
+ i
*0x10);
1180 for (j
= 31; j
>= 0; j
--) {
1187 * Now that we are all set up, enable the APIC
1189 value
= apic_read(APIC_SPIV
);
1190 value
&= ~APIC_VECTOR_MASK
;
1194 value
|= APIC_SPIV_APIC_ENABLED
;
1196 #ifdef CONFIG_X86_32
1198 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1199 * certain networking cards. If high frequency interrupts are
1200 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1201 * entry is masked/unmasked at a high rate as well then sooner or
1202 * later IOAPIC line gets 'stuck', no more interrupts are received
1203 * from the device. If focus CPU is disabled then the hang goes
1206 * [ This bug can be reproduced easily with a level-triggered
1207 * PCI Ne2000 networking cards and PII/PIII processors, dual
1211 * Actually disabling the focus CPU check just makes the hang less
1212 * frequent as it makes the interrupt distributon model be more
1213 * like LRU than MRU (the short-term load is more even across CPUs).
1214 * See also the comment in end_level_ioapic_irq(). --macro
1218 * - enable focus processor (bit==0)
1219 * - 64bit mode always use processor focus
1220 * so no need to set it
1222 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1226 * Set spurious IRQ vector
1228 value
|= SPURIOUS_APIC_VECTOR
;
1229 apic_write(APIC_SPIV
, value
);
1232 * Set up LVT0, LVT1:
1234 * set up through-local-APIC on the BP's LINT0. This is not
1235 * strictly necessary in pure symmetric-IO mode, but sometimes
1236 * we delegate interrupts to the 8259A.
1239 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1241 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1242 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1243 value
= APIC_DM_EXTINT
;
1244 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1245 smp_processor_id());
1247 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1248 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1249 smp_processor_id());
1251 apic_write(APIC_LVT0
, value
);
1254 * only the BP should see the LINT1 NMI signal, obviously.
1256 if (!smp_processor_id())
1257 value
= APIC_DM_NMI
;
1259 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1260 if (!lapic_is_integrated()) /* 82489DX */
1261 value
|= APIC_LVT_LEVEL_TRIGGER
;
1262 apic_write(APIC_LVT1
, value
);
1267 void __cpuinit
end_local_APIC_setup(void)
1271 #ifdef CONFIG_X86_32
1274 /* Disable the local apic timer */
1275 value
= apic_read(APIC_LVTT
);
1276 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1277 apic_write(APIC_LVTT
, value
);
1281 setup_apic_nmi_watchdog(NULL
);
1286 void check_x2apic(void)
1290 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1292 if (msr
& X2APIC_ENABLE
) {
1293 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1294 x2apic_preenabled
= x2apic
= 1;
1295 apic_ops
= &x2apic_ops
;
1299 void enable_x2apic(void)
1303 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1304 if (!(msr
& X2APIC_ENABLE
)) {
1305 pr_info("Enabling x2apic\n");
1306 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1310 void __init
enable_IR_x2apic(void)
1312 #ifdef CONFIG_INTR_REMAP
1314 unsigned long flags
;
1316 if (!cpu_has_x2apic
)
1319 if (!x2apic_preenabled
&& disable_x2apic
) {
1320 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1321 "because of nox2apic\n");
1325 if (x2apic_preenabled
&& disable_x2apic
)
1326 panic("Bios already enabled x2apic, can't enforce nox2apic");
1328 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1329 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1330 "because of skipping io-apic setup\n");
1334 ret
= dmar_table_init();
1336 pr_info("dmar_table_init() failed with %d:\n", ret
);
1338 if (x2apic_preenabled
)
1339 panic("x2apic enabled by bios. But IR enabling failed");
1341 pr_info("Not enabling x2apic,Intr-remapping\n");
1345 local_irq_save(flags
);
1348 ret
= save_mask_IO_APIC_setup();
1350 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1354 ret
= enable_intr_remapping(1);
1356 if (ret
&& x2apic_preenabled
) {
1357 local_irq_restore(flags
);
1358 panic("x2apic enabled by bios. But IR enabling failed");
1366 apic_ops
= &x2apic_ops
;
1373 * IR enabling failed
1375 restore_IO_APIC_setup();
1377 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1381 local_irq_restore(flags
);
1384 if (!x2apic_preenabled
)
1385 pr_info("Enabled x2apic and interrupt-remapping\n");
1387 pr_info("Enabled Interrupt-remapping\n");
1389 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1391 if (!cpu_has_x2apic
)
1394 if (x2apic_preenabled
)
1395 panic("x2apic enabled prior OS handover,"
1396 " enable CONFIG_INTR_REMAP");
1398 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1404 #endif /* HAVE_X2APIC */
1406 #ifdef CONFIG_X86_64
1408 * Detect and enable local APICs on non-SMP boards.
1409 * Original code written by Keir Fraser.
1410 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1411 * not correctly set up (usually the APIC timer won't work etc.)
1413 static int __init
detect_init_APIC(void)
1415 if (!cpu_has_apic
) {
1416 pr_info("No local APIC present\n");
1420 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1421 boot_cpu_physical_apicid
= 0;
1426 * Detect and initialize APIC
1428 static int __init
detect_init_APIC(void)
1432 /* Disabled by kernel option? */
1436 switch (boot_cpu_data
.x86_vendor
) {
1437 case X86_VENDOR_AMD
:
1438 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1439 (boot_cpu_data
.x86
== 15))
1442 case X86_VENDOR_INTEL
:
1443 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1444 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1451 if (!cpu_has_apic
) {
1453 * Over-ride BIOS and try to enable the local APIC only if
1454 * "lapic" specified.
1456 if (!force_enable_local_apic
) {
1457 pr_info("Local APIC disabled by BIOS -- "
1458 "you can enable it with \"lapic\"\n");
1462 * Some BIOSes disable the local APIC in the APIC_BASE
1463 * MSR. This can only be done in software for Intel P6 or later
1464 * and AMD K7 (Model > 1) or later.
1466 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1467 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1468 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1469 l
&= ~MSR_IA32_APICBASE_BASE
;
1470 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1471 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1472 enabled_via_apicbase
= 1;
1476 * The APIC feature bit should now be enabled
1479 features
= cpuid_edx(1);
1480 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1481 pr_warning("Could not enable APIC!\n");
1484 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1485 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1487 /* The BIOS may have set up the APIC at some other address */
1488 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1489 if (l
& MSR_IA32_APICBASE_ENABLE
)
1490 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1492 pr_info("Found and enabled local APIC!\n");
1499 pr_info("No local APIC present or hardware disabled\n");
1504 #ifdef CONFIG_X86_64
1505 void __init
early_init_lapic_mapping(void)
1507 unsigned long phys_addr
;
1510 * If no local APIC can be found then go out
1511 * : it means there is no mpatable and MADT
1513 if (!smp_found_config
)
1516 phys_addr
= mp_lapic_addr
;
1518 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1519 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1520 APIC_BASE
, phys_addr
);
1523 * Fetch the APIC ID of the BSP in case we have a
1524 * default configuration (or the MP table is broken).
1526 boot_cpu_physical_apicid
= read_apic_id();
1531 * init_apic_mappings - initialize APIC mappings
1533 void __init
init_apic_mappings(void)
1537 boot_cpu_physical_apicid
= read_apic_id();
1543 * If no local APIC can be found then set up a fake all
1544 * zeroes page to simulate the local APIC and another
1545 * one for the IO-APIC.
1547 if (!smp_found_config
&& detect_init_APIC()) {
1548 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1549 apic_phys
= __pa(apic_phys
);
1551 apic_phys
= mp_lapic_addr
;
1553 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1554 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1555 APIC_BASE
, apic_phys
);
1558 * Fetch the APIC ID of the BSP in case we have a
1559 * default configuration (or the MP table is broken).
1561 if (boot_cpu_physical_apicid
== -1U)
1562 boot_cpu_physical_apicid
= read_apic_id();
1566 * This initializes the IO-APIC and APIC hardware if this is
1569 int apic_version
[MAX_APICS
];
1571 int __init
APIC_init_uniprocessor(void)
1573 #ifdef CONFIG_X86_64
1575 pr_info("Apic disabled\n");
1578 if (!cpu_has_apic
) {
1580 pr_info("Apic disabled by BIOS\n");
1584 if (!smp_found_config
&& !cpu_has_apic
)
1588 * Complain if the BIOS pretends there is one.
1590 if (!cpu_has_apic
&&
1591 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1592 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1593 boot_cpu_physical_apicid
);
1594 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1602 #ifdef CONFIG_X86_64
1603 setup_apic_routing();
1606 verify_local_APIC();
1609 #ifdef CONFIG_X86_64
1610 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1613 * Hack: In case of kdump, after a crash, kernel might be booting
1614 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1615 * might be zero if read from MP tables. Get it from LAPIC.
1617 # ifdef CONFIG_CRASH_DUMP
1618 boot_cpu_physical_apicid
= read_apic_id();
1621 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1624 #ifdef CONFIG_X86_64
1626 * Now enable IO-APICs, actually call clear_IO_APIC
1627 * We need clear_IO_APIC before enabling vector on BP
1629 if (!skip_ioapic_setup
&& nr_ioapics
)
1633 #ifdef CONFIG_X86_IO_APIC
1634 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1636 localise_nmi_watchdog();
1637 end_local_APIC_setup();
1639 #ifdef CONFIG_X86_IO_APIC
1640 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1642 # ifdef CONFIG_X86_64
1648 #ifdef CONFIG_X86_64
1649 setup_boot_APIC_clock();
1650 check_nmi_watchdog();
1659 * Local APIC interrupts
1663 * This interrupt should _never_ happen with our APIC/SMP architecture
1665 void smp_spurious_interrupt(struct pt_regs
*regs
)
1669 #ifdef CONFIG_X86_64
1674 * Check if this really is a spurious interrupt and ACK it
1675 * if it is a vectored one. Just in case...
1676 * Spurious interrupts should not be ACKed.
1678 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1679 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1682 #ifdef CONFIG_X86_64
1683 add_pda(irq_spurious_count
, 1);
1685 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1686 pr_info("spurious APIC interrupt on CPU#%d, "
1687 "should never happen.\n", smp_processor_id());
1688 __get_cpu_var(irq_stat
).irq_spurious_count
++;
1694 * This interrupt should never happen with our APIC/SMP architecture
1696 void smp_error_interrupt(struct pt_regs
*regs
)
1700 #ifdef CONFIG_X86_64
1704 /* First tickle the hardware, only then report what went on. -- REW */
1705 v
= apic_read(APIC_ESR
);
1706 apic_write(APIC_ESR
, 0);
1707 v1
= apic_read(APIC_ESR
);
1709 atomic_inc(&irq_err_count
);
1712 * Here is what the APIC error bits mean:
1714 * 1: Receive CS error
1715 * 2: Send accept error
1716 * 3: Receive accept error
1718 * 5: Send illegal vector
1719 * 6: Received illegal vector
1720 * 7: Illegal register address
1722 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1723 smp_processor_id(), v
, v1
);
1728 * connect_bsp_APIC - attach the APIC to the interrupt system
1730 void __init
connect_bsp_APIC(void)
1732 #ifdef CONFIG_X86_32
1735 * Do not trust the local APIC being empty at bootup.
1739 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1740 * local APIC to INT and NMI lines.
1742 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1743 "enabling APIC mode.\n");
1752 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1753 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1755 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1758 void disconnect_bsp_APIC(int virt_wire_setup
)
1762 #ifdef CONFIG_X86_32
1765 * Put the board back into PIC mode (has an effect only on
1766 * certain older boards). Note that APIC interrupts, including
1767 * IPIs, won't work beyond this point! The only exception are
1770 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1771 "entering PIC mode.\n");
1778 /* Go back to Virtual Wire compatibility mode */
1780 /* For the spurious interrupt use vector F, and enable it */
1781 value
= apic_read(APIC_SPIV
);
1782 value
&= ~APIC_VECTOR_MASK
;
1783 value
|= APIC_SPIV_APIC_ENABLED
;
1785 apic_write(APIC_SPIV
, value
);
1787 if (!virt_wire_setup
) {
1789 * For LVT0 make it edge triggered, active high,
1790 * external and enabled
1792 value
= apic_read(APIC_LVT0
);
1793 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1794 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1795 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1796 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1797 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1798 apic_write(APIC_LVT0
, value
);
1801 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1805 * For LVT1 make it edge triggered, active high,
1808 value
= apic_read(APIC_LVT1
);
1809 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1810 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1811 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1812 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1813 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1814 apic_write(APIC_LVT1
, value
);
1817 void __cpuinit
generic_processor_info(int apicid
, int version
)
1824 if (version
== 0x0) {
1825 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1826 "fixing up to 0x10. (tell your hw vendor)\n",
1830 apic_version
[apicid
] = version
;
1832 if (num_processors
>= nr_cpu_ids
) {
1833 int max
= nr_cpu_ids
;
1834 int thiscpu
= max
+ disabled_cpus
;
1837 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1838 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1845 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1847 physid_set(apicid
, phys_cpu_present_map
);
1848 if (apicid
== boot_cpu_physical_apicid
) {
1850 * x86_bios_cpu_apicid is required to have processors listed
1851 * in same order as logical cpu numbers. Hence the first
1852 * entry is BSP, and so on.
1856 if (apicid
> max_physical_apicid
)
1857 max_physical_apicid
= apicid
;
1859 #ifdef CONFIG_X86_32
1861 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1862 * but we need to work other dependencies like SMP_SUSPEND etc
1863 * before this can be done without some confusion.
1864 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1865 * - Ashok Raj <ashok.raj@intel.com>
1867 if (max_physical_apicid
>= 8) {
1868 switch (boot_cpu_data
.x86_vendor
) {
1869 case X86_VENDOR_INTEL
:
1870 if (!APIC_XAPIC(version
)) {
1874 /* If P4 and above fall through */
1875 case X86_VENDOR_AMD
:
1881 #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1882 /* are we being called early in kernel startup? */
1883 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1884 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1885 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1887 cpu_to_apicid
[cpu
] = apicid
;
1888 bios_cpu_apicid
[cpu
] = apicid
;
1890 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1891 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1895 set_cpu_possible(cpu
, true);
1896 set_cpu_present(cpu
, true);
1899 #ifdef CONFIG_X86_64
1900 int hard_smp_processor_id(void)
1902 return read_apic_id();
1913 * 'active' is true if the local APIC was enabled by us and
1914 * not the BIOS; this signifies that we are also responsible
1915 * for disabling it before entering apm/acpi suspend
1918 /* r/w apic fields */
1919 unsigned int apic_id
;
1920 unsigned int apic_taskpri
;
1921 unsigned int apic_ldr
;
1922 unsigned int apic_dfr
;
1923 unsigned int apic_spiv
;
1924 unsigned int apic_lvtt
;
1925 unsigned int apic_lvtpc
;
1926 unsigned int apic_lvt0
;
1927 unsigned int apic_lvt1
;
1928 unsigned int apic_lvterr
;
1929 unsigned int apic_tmict
;
1930 unsigned int apic_tdcr
;
1931 unsigned int apic_thmr
;
1934 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1936 unsigned long flags
;
1939 if (!apic_pm_state
.active
)
1942 maxlvt
= lapic_get_maxlvt();
1944 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1945 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1946 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1947 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1948 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1949 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1951 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1952 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1953 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1954 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1955 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1956 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1957 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1959 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1962 local_irq_save(flags
);
1963 disable_local_APIC();
1964 local_irq_restore(flags
);
1968 static int lapic_resume(struct sys_device
*dev
)
1971 unsigned long flags
;
1974 if (!apic_pm_state
.active
)
1977 maxlvt
= lapic_get_maxlvt();
1979 local_irq_save(flags
);
1988 * Make sure the APICBASE points to the right address
1990 * FIXME! This will be wrong if we ever support suspend on
1991 * SMP! We'll need to do this as part of the CPU restore!
1993 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1994 l
&= ~MSR_IA32_APICBASE_BASE
;
1995 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1996 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1999 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2000 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2001 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2002 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2003 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2004 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2005 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2006 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2007 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2009 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2012 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2013 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2014 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2015 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2016 apic_write(APIC_ESR
, 0);
2017 apic_read(APIC_ESR
);
2018 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2019 apic_write(APIC_ESR
, 0);
2020 apic_read(APIC_ESR
);
2022 local_irq_restore(flags
);
2028 * This device has no shutdown method - fully functioning local APICs
2029 * are needed on every CPU up until machine_halt/restart/poweroff.
2032 static struct sysdev_class lapic_sysclass
= {
2034 .resume
= lapic_resume
,
2035 .suspend
= lapic_suspend
,
2038 static struct sys_device device_lapic
= {
2040 .cls
= &lapic_sysclass
,
2043 static void __cpuinit
apic_pm_activate(void)
2045 apic_pm_state
.active
= 1;
2048 static int __init
init_lapic_sysfs(void)
2054 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2056 error
= sysdev_class_register(&lapic_sysclass
);
2058 error
= sysdev_register(&device_lapic
);
2061 device_initcall(init_lapic_sysfs
);
2063 #else /* CONFIG_PM */
2065 static void apic_pm_activate(void) { }
2067 #endif /* CONFIG_PM */
2069 #ifdef CONFIG_X86_64
2071 * apic_is_clustered_box() -- Check if we can expect good TSC
2073 * Thus far, the major user of this is IBM's Summit2 series:
2075 * Clustered boxes may have unsynced TSC problems if they are
2076 * multi-chassis. Use available data to take a good guess.
2077 * If in doubt, go HPET.
2079 __cpuinit
int apic_is_clustered_box(void)
2081 int i
, clusters
, zeros
;
2083 u16
*bios_cpu_apicid
;
2084 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2087 * there is not this kind of box with AMD CPU yet.
2088 * Some AMD box with quadcore cpu and 8 sockets apicid
2089 * will be [4, 0x23] or [8, 0x27] could be thought to
2090 * vsmp box still need checking...
2092 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2095 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2096 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2098 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2099 /* are we being called early in kernel startup? */
2100 if (bios_cpu_apicid
) {
2101 id
= bios_cpu_apicid
[i
];
2103 else if (i
< nr_cpu_ids
) {
2105 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2112 if (id
!= BAD_APICID
)
2113 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2116 /* Problem: Partially populated chassis may not have CPUs in some of
2117 * the APIC clusters they have been allocated. Only present CPUs have
2118 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2119 * Since clusters are allocated sequentially, count zeros only if
2120 * they are bounded by ones.
2124 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2125 if (test_bit(i
, clustermap
)) {
2126 clusters
+= 1 + zeros
;
2132 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2133 * not guaranteed to be synced between boards
2135 if (is_vsmp_box() && clusters
> 1)
2139 * If clusters > 2, then should be multi-chassis.
2140 * May have to revisit this when multi-core + hyperthreaded CPUs come
2141 * out, but AFAIK this will work even for them.
2143 return (clusters
> 2);
2148 * APIC command line parameters
2150 static int __init
setup_disableapic(char *arg
)
2153 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2156 early_param("disableapic", setup_disableapic
);
2158 /* same as disableapic, for compatibility */
2159 static int __init
setup_nolapic(char *arg
)
2161 return setup_disableapic(arg
);
2163 early_param("nolapic", setup_nolapic
);
2165 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2167 local_apic_timer_c2_ok
= 1;
2170 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2172 static int __init
parse_disable_apic_timer(char *arg
)
2174 disable_apic_timer
= 1;
2177 early_param("noapictimer", parse_disable_apic_timer
);
2179 static int __init
parse_nolapic_timer(char *arg
)
2181 disable_apic_timer
= 1;
2184 early_param("nolapic_timer", parse_nolapic_timer
);
2186 static int __init
apic_set_verbosity(char *arg
)
2189 #ifdef CONFIG_X86_64
2190 skip_ioapic_setup
= 0;
2196 if (strcmp("debug", arg
) == 0)
2197 apic_verbosity
= APIC_DEBUG
;
2198 else if (strcmp("verbose", arg
) == 0)
2199 apic_verbosity
= APIC_VERBOSE
;
2201 pr_warning("APIC Verbosity level %s not recognised"
2202 " use apic=verbose or apic=debug\n", arg
);
2208 early_param("apic", apic_set_verbosity
);
2210 static int __init
lapic_insert_resource(void)
2215 /* Put local APIC into the resource map. */
2216 lapic_resource
.start
= apic_phys
;
2217 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2218 insert_resource(&iomem_resource
, &lapic_resource
);
2224 * need call insert after e820_reserve_resources()
2225 * that is using request_resource
2227 late_initcall(lapic_insert_resource
);