2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 * --> Errata workaround for NCQ device errors.
30 * --> More errata workarounds for PCI-X.
32 * --> Complete a full errata audit for all chipsets to identify others.
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
40 * --> Develop a low-power-consumption strategy, and implement it.
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <linux/interrupt.h>
62 #include <linux/dmapool.h>
63 #include <linux/dma-mapping.h>
64 #include <linux/device.h>
65 #include <linux/platform_device.h>
66 #include <linux/ata_platform.h>
67 #include <linux/mbus.h>
68 #include <linux/bitops.h>
69 #include <scsi/scsi_host.h>
70 #include <scsi/scsi_cmnd.h>
71 #include <scsi/scsi_device.h>
72 #include <linux/libata.h>
74 #define DRV_NAME "sata_mv"
75 #define DRV_VERSION "1.23"
78 /* BAR's are enumerated in terms of pci_resource_start() terms */
79 MV_PRIMARY_BAR
= 0, /* offset 0x10: memory space */
80 MV_IO_BAR
= 2, /* offset 0x18: IO space */
81 MV_MISC_BAR
= 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
83 MV_MAJOR_REG_AREA_SZ
= 0x10000, /* 64KB */
84 MV_MINOR_REG_AREA_SZ
= 0x2000, /* 8KB */
87 MV_IRQ_COAL_REG_BASE
= 0x18000, /* 6xxx part only */
88 MV_IRQ_COAL_CAUSE
= (MV_IRQ_COAL_REG_BASE
+ 0x08),
89 MV_IRQ_COAL_CAUSE_LO
= (MV_IRQ_COAL_REG_BASE
+ 0x88),
90 MV_IRQ_COAL_CAUSE_HI
= (MV_IRQ_COAL_REG_BASE
+ 0x8c),
91 MV_IRQ_COAL_THRESHOLD
= (MV_IRQ_COAL_REG_BASE
+ 0xcc),
92 MV_IRQ_COAL_TIME_THRESHOLD
= (MV_IRQ_COAL_REG_BASE
+ 0xd0),
94 MV_SATAHC0_REG_BASE
= 0x20000,
95 MV_FLASH_CTL_OFS
= 0x1046c,
96 MV_GPIO_PORT_CTL_OFS
= 0x104f0,
97 MV_RESET_CFG_OFS
= 0x180d8,
99 MV_PCI_REG_SZ
= MV_MAJOR_REG_AREA_SZ
,
100 MV_SATAHC_REG_SZ
= MV_MAJOR_REG_AREA_SZ
,
101 MV_SATAHC_ARBTR_REG_SZ
= MV_MINOR_REG_AREA_SZ
, /* arbiter */
102 MV_PORT_REG_SZ
= MV_MINOR_REG_AREA_SZ
,
105 MV_MAX_Q_DEPTH_MASK
= MV_MAX_Q_DEPTH
- 1,
107 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
108 * CRPB needs alignment on a 256B boundary. Size == 256B
109 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
111 MV_CRQB_Q_SZ
= (32 * MV_MAX_Q_DEPTH
),
112 MV_CRPB_Q_SZ
= (8 * MV_MAX_Q_DEPTH
),
114 MV_SG_TBL_SZ
= (16 * MV_MAX_SG_CT
),
116 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
117 MV_PORT_HC_SHIFT
= 2,
118 MV_PORTS_PER_HC
= (1 << MV_PORT_HC_SHIFT
), /* 4 */
119 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
120 MV_PORT_MASK
= (MV_PORTS_PER_HC
- 1), /* 3 */
123 MV_FLAG_DUAL_HC
= (1 << 30), /* two SATA Host Controllers */
124 MV_FLAG_IRQ_COALESCE
= (1 << 29), /* IRQ coalescing capability */
126 MV_COMMON_FLAGS
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
127 ATA_FLAG_MMIO
| ATA_FLAG_NO_ATAPI
|
128 ATA_FLAG_PIO_POLLING
,
130 MV_6XXX_FLAGS
= MV_FLAG_IRQ_COALESCE
,
132 MV_GENIIE_FLAGS
= MV_COMMON_FLAGS
| MV_6XXX_FLAGS
|
133 ATA_FLAG_PMP
| ATA_FLAG_ACPI_SATA
|
134 ATA_FLAG_NCQ
| ATA_FLAG_AN
,
136 CRQB_FLAG_READ
= (1 << 0),
138 CRQB_IOID_SHIFT
= 6, /* CRQB Gen-II/IIE IO Id shift */
139 CRQB_PMP_SHIFT
= 12, /* CRQB Gen-II/IIE PMP shift */
140 CRQB_HOSTQ_SHIFT
= 17, /* CRQB Gen-II/IIE HostQueTag shift */
141 CRQB_CMD_ADDR_SHIFT
= 8,
142 CRQB_CMD_CS
= (0x2 << 11),
143 CRQB_CMD_LAST
= (1 << 15),
145 CRPB_FLAG_STATUS_SHIFT
= 8,
146 CRPB_IOID_SHIFT_6
= 5, /* CRPB Gen-II IO Id shift */
147 CRPB_IOID_SHIFT_7
= 7, /* CRPB Gen-IIE IO Id shift */
149 EPRD_FLAG_END_OF_TBL
= (1 << 31),
151 /* PCI interface registers */
153 PCI_COMMAND_OFS
= 0xc00,
154 PCI_COMMAND_MRDTRIG
= (1 << 7), /* PCI Master Read Trigger */
156 PCI_MAIN_CMD_STS_OFS
= 0xd30,
157 STOP_PCI_MASTER
= (1 << 2),
158 PCI_MASTER_EMPTY
= (1 << 3),
159 GLOB_SFT_RST
= (1 << 4),
161 MV_PCI_MODE_OFS
= 0xd00,
162 MV_PCI_MODE_MASK
= 0x30,
164 MV_PCI_EXP_ROM_BAR_CTL
= 0xd2c,
165 MV_PCI_DISC_TIMER
= 0xd04,
166 MV_PCI_MSI_TRIGGER
= 0xc38,
167 MV_PCI_SERR_MASK
= 0xc28,
168 MV_PCI_XBAR_TMOUT_OFS
= 0x1d04,
169 MV_PCI_ERR_LOW_ADDRESS
= 0x1d40,
170 MV_PCI_ERR_HIGH_ADDRESS
= 0x1d44,
171 MV_PCI_ERR_ATTRIBUTE
= 0x1d48,
172 MV_PCI_ERR_COMMAND
= 0x1d50,
174 PCI_IRQ_CAUSE_OFS
= 0x1d58,
175 PCI_IRQ_MASK_OFS
= 0x1d5c,
176 PCI_UNMASK_ALL_IRQS
= 0x7fffff, /* bits 22-0 */
178 PCIE_IRQ_CAUSE_OFS
= 0x1900,
179 PCIE_IRQ_MASK_OFS
= 0x1910,
180 PCIE_UNMASK_ALL_IRQS
= 0x40a, /* assorted bits */
182 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
183 PCI_HC_MAIN_IRQ_CAUSE_OFS
= 0x1d60,
184 PCI_HC_MAIN_IRQ_MASK_OFS
= 0x1d64,
185 SOC_HC_MAIN_IRQ_CAUSE_OFS
= 0x20020,
186 SOC_HC_MAIN_IRQ_MASK_OFS
= 0x20024,
187 ERR_IRQ
= (1 << 0), /* shift by port # */
188 DONE_IRQ
= (1 << 1), /* shift by port # */
189 HC0_IRQ_PEND
= 0x1ff, /* bits 0-8 = HC0's ports */
190 HC_SHIFT
= 9, /* bits 9-17 = HC1's ports */
192 TRAN_LO_DONE
= (1 << 19), /* 6xxx: IRQ coalescing */
193 TRAN_HI_DONE
= (1 << 20), /* 6xxx: IRQ coalescing */
194 PORTS_0_3_COAL_DONE
= (1 << 8),
195 PORTS_4_7_COAL_DONE
= (1 << 17),
196 PORTS_0_7_COAL_DONE
= (1 << 21), /* 6xxx: IRQ coalescing */
197 GPIO_INT
= (1 << 22),
198 SELF_INT
= (1 << 23),
199 TWSI_INT
= (1 << 24),
200 HC_MAIN_RSVD
= (0x7f << 25), /* bits 31-25 */
201 HC_MAIN_RSVD_5
= (0x1fff << 19), /* bits 31-19 */
202 HC_MAIN_RSVD_SOC
= (0x3fffffb << 6), /* bits 31-9, 7-6 */
204 /* SATAHC registers */
207 HC_IRQ_CAUSE_OFS
= 0x14,
208 DMA_IRQ
= (1 << 0), /* shift by port # */
209 HC_COAL_IRQ
= (1 << 4), /* IRQ coalescing */
210 DEV_IRQ
= (1 << 8), /* shift by port # */
212 /* Shadow block registers */
214 SHD_CTL_AST_OFS
= 0x20, /* ofs from SHD_BLK_OFS */
217 SATA_STATUS_OFS
= 0x300, /* ctrl, err regs follow status */
218 SATA_ACTIVE_OFS
= 0x350,
219 SATA_FIS_IRQ_CAUSE_OFS
= 0x364,
220 SATA_FIS_IRQ_AN
= (1 << 9), /* async notification */
223 LTMODE_BIT8
= (1 << 8), /* unknown, but necessary */
228 SATA_IFCTL_OFS
= 0x344,
229 SATA_TESTCTL_OFS
= 0x348,
230 SATA_IFSTAT_OFS
= 0x34c,
231 VENDOR_UNIQUE_FIS_OFS
= 0x35c,
234 FISCFG_WAIT_DEV_ERR
= (1 << 8), /* wait for host on DevErr */
235 FISCFG_SINGLE_SYNC
= (1 << 16), /* SYNC on DMA activation */
238 MV5_LTMODE_OFS
= 0x30,
239 MV5_PHY_CTL_OFS
= 0x0C,
240 SATA_INTERFACE_CFG_OFS
= 0x050,
242 MV_M2_PREAMP_MASK
= 0x7e0,
246 EDMA_CFG_Q_DEPTH
= 0x1f, /* max device queue depth */
247 EDMA_CFG_NCQ
= (1 << 5), /* for R/W FPDMA queued */
248 EDMA_CFG_NCQ_GO_ON_ERR
= (1 << 14), /* continue on error */
249 EDMA_CFG_RD_BRST_EXT
= (1 << 11), /* read burst 512B */
250 EDMA_CFG_WR_BUFF_LEN
= (1 << 13), /* write buffer 512B */
251 EDMA_CFG_EDMA_FBS
= (1 << 16), /* EDMA FIS-Based Switching */
252 EDMA_CFG_FBS
= (1 << 26), /* FIS-Based Switching */
254 EDMA_ERR_IRQ_CAUSE_OFS
= 0x8,
255 EDMA_ERR_IRQ_MASK_OFS
= 0xc,
256 EDMA_ERR_D_PAR
= (1 << 0), /* UDMA data parity err */
257 EDMA_ERR_PRD_PAR
= (1 << 1), /* UDMA PRD parity err */
258 EDMA_ERR_DEV
= (1 << 2), /* device error */
259 EDMA_ERR_DEV_DCON
= (1 << 3), /* device disconnect */
260 EDMA_ERR_DEV_CON
= (1 << 4), /* device connected */
261 EDMA_ERR_SERR
= (1 << 5), /* SError bits [WBDST] raised */
262 EDMA_ERR_SELF_DIS
= (1 << 7), /* Gen II/IIE self-disable */
263 EDMA_ERR_SELF_DIS_5
= (1 << 8), /* Gen I self-disable */
264 EDMA_ERR_BIST_ASYNC
= (1 << 8), /* BIST FIS or Async Notify */
265 EDMA_ERR_TRANS_IRQ_7
= (1 << 8), /* Gen IIE transprt layer irq */
266 EDMA_ERR_CRQB_PAR
= (1 << 9), /* CRQB parity error */
267 EDMA_ERR_CRPB_PAR
= (1 << 10), /* CRPB parity error */
268 EDMA_ERR_INTRL_PAR
= (1 << 11), /* internal parity error */
269 EDMA_ERR_IORDY
= (1 << 12), /* IORdy timeout */
271 EDMA_ERR_LNK_CTRL_RX
= (0xf << 13), /* link ctrl rx error */
272 EDMA_ERR_LNK_CTRL_RX_0
= (1 << 13), /* transient: CRC err */
273 EDMA_ERR_LNK_CTRL_RX_1
= (1 << 14), /* transient: FIFO err */
274 EDMA_ERR_LNK_CTRL_RX_2
= (1 << 15), /* fatal: caught SYNC */
275 EDMA_ERR_LNK_CTRL_RX_3
= (1 << 16), /* transient: FIS rx err */
277 EDMA_ERR_LNK_DATA_RX
= (0xf << 17), /* link data rx error */
279 EDMA_ERR_LNK_CTRL_TX
= (0x1f << 21), /* link ctrl tx error */
280 EDMA_ERR_LNK_CTRL_TX_0
= (1 << 21), /* transient: CRC err */
281 EDMA_ERR_LNK_CTRL_TX_1
= (1 << 22), /* transient: FIFO err */
282 EDMA_ERR_LNK_CTRL_TX_2
= (1 << 23), /* transient: caught SYNC */
283 EDMA_ERR_LNK_CTRL_TX_3
= (1 << 24), /* transient: caught DMAT */
284 EDMA_ERR_LNK_CTRL_TX_4
= (1 << 25), /* transient: FIS collision */
286 EDMA_ERR_LNK_DATA_TX
= (0x1f << 26), /* link data tx error */
288 EDMA_ERR_TRANS_PROTO
= (1 << 31), /* transport protocol error */
289 EDMA_ERR_OVERRUN_5
= (1 << 5),
290 EDMA_ERR_UNDERRUN_5
= (1 << 6),
292 EDMA_ERR_IRQ_TRANSIENT
= EDMA_ERR_LNK_CTRL_RX_0
|
293 EDMA_ERR_LNK_CTRL_RX_1
|
294 EDMA_ERR_LNK_CTRL_RX_3
|
295 EDMA_ERR_LNK_CTRL_TX
,
297 EDMA_EH_FREEZE
= EDMA_ERR_D_PAR
|
307 EDMA_ERR_LNK_CTRL_RX_2
|
308 EDMA_ERR_LNK_DATA_RX
|
309 EDMA_ERR_LNK_DATA_TX
|
310 EDMA_ERR_TRANS_PROTO
,
312 EDMA_EH_FREEZE_5
= EDMA_ERR_D_PAR
|
317 EDMA_ERR_UNDERRUN_5
|
318 EDMA_ERR_SELF_DIS_5
|
324 EDMA_REQ_Q_BASE_HI_OFS
= 0x10,
325 EDMA_REQ_Q_IN_PTR_OFS
= 0x14, /* also contains BASE_LO */
327 EDMA_REQ_Q_OUT_PTR_OFS
= 0x18,
328 EDMA_REQ_Q_PTR_SHIFT
= 5,
330 EDMA_RSP_Q_BASE_HI_OFS
= 0x1c,
331 EDMA_RSP_Q_IN_PTR_OFS
= 0x20,
332 EDMA_RSP_Q_OUT_PTR_OFS
= 0x24, /* also contains BASE_LO */
333 EDMA_RSP_Q_PTR_SHIFT
= 3,
335 EDMA_CMD_OFS
= 0x28, /* EDMA command register */
336 EDMA_EN
= (1 << 0), /* enable EDMA */
337 EDMA_DS
= (1 << 1), /* disable EDMA; self-negated */
338 EDMA_RESET
= (1 << 2), /* reset eng/trans/link/phy */
340 EDMA_STATUS_OFS
= 0x30, /* EDMA engine status */
341 EDMA_STATUS_CACHE_EMPTY
= (1 << 6), /* GenIIe command cache empty */
342 EDMA_STATUS_IDLE
= (1 << 7), /* GenIIe EDMA enabled/idle */
344 EDMA_IORDY_TMOUT_OFS
= 0x34,
345 EDMA_ARB_CFG_OFS
= 0x38,
347 EDMA_HALTCOND_OFS
= 0x60, /* GenIIe halt conditions */
349 GEN_II_NCQ_MAX_SECTORS
= 256, /* max sects/io on Gen2 w/NCQ */
351 /* Host private flags (hp_flags) */
352 MV_HP_FLAG_MSI
= (1 << 0),
353 MV_HP_ERRATA_50XXB0
= (1 << 1),
354 MV_HP_ERRATA_50XXB2
= (1 << 2),
355 MV_HP_ERRATA_60X1B2
= (1 << 3),
356 MV_HP_ERRATA_60X1C0
= (1 << 4),
357 MV_HP_GEN_I
= (1 << 6), /* Generation I: 50xx */
358 MV_HP_GEN_II
= (1 << 7), /* Generation II: 60xx */
359 MV_HP_GEN_IIE
= (1 << 8), /* Generation IIE: 6042/7042 */
360 MV_HP_PCIE
= (1 << 9), /* PCIe bus/regs: 7042 */
361 MV_HP_CUT_THROUGH
= (1 << 10), /* can use EDMA cut-through */
362 MV_HP_FLAG_SOC
= (1 << 11), /* SystemOnChip, no PCI */
364 /* Port private flags (pp_flags) */
365 MV_PP_FLAG_EDMA_EN
= (1 << 0), /* is EDMA engine enabled? */
366 MV_PP_FLAG_NCQ_EN
= (1 << 1), /* is EDMA set up for NCQ? */
367 MV_PP_FLAG_FBS_EN
= (1 << 2), /* is EDMA set up for FBS? */
368 MV_PP_FLAG_DELAYED_EH
= (1 << 3), /* delayed dev err handling */
371 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
372 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
373 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
374 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
375 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
377 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
378 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
381 /* DMA boundary 0xffff is required by the s/g splitting
382 * we need on /length/ in mv_fill-sg().
384 MV_DMA_BOUNDARY
= 0xffffU
,
386 /* mask of register bits containing lower 32 bits
387 * of EDMA request queue DMA address
389 EDMA_REQ_Q_BASE_LO_MASK
= 0xfffffc00U
,
391 /* ditto, for response queue */
392 EDMA_RSP_Q_BASE_LO_MASK
= 0xffffff00U
,
406 /* Command ReQuest Block: 32B */
422 /* Command ResPonse Block: 8B */
429 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
437 struct mv_port_priv
{
438 struct mv_crqb
*crqb
;
440 struct mv_crpb
*crpb
;
442 struct mv_sg
*sg_tbl
[MV_MAX_Q_DEPTH
];
443 dma_addr_t sg_tbl_dma
[MV_MAX_Q_DEPTH
];
445 unsigned int req_idx
;
446 unsigned int resp_idx
;
449 unsigned int delayed_eh_pmp_map
;
452 struct mv_port_signal
{
457 struct mv_host_priv
{
460 struct mv_port_signal signal
[8];
461 const struct mv_hw_ops
*ops
;
464 void __iomem
*main_irq_cause_addr
;
465 void __iomem
*main_irq_mask_addr
;
470 * These consistent DMA memory pools give us guaranteed
471 * alignment for hardware-accessed data structures,
472 * and less memory waste in accomplishing the alignment.
474 struct dma_pool
*crqb_pool
;
475 struct dma_pool
*crpb_pool
;
476 struct dma_pool
*sg_tbl_pool
;
480 void (*phy_errata
)(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
482 void (*enable_leds
)(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
483 void (*read_preamp
)(struct mv_host_priv
*hpriv
, int idx
,
485 int (*reset_hc
)(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
487 void (*reset_flash
)(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
488 void (*reset_bus
)(struct ata_host
*host
, void __iomem
*mmio
);
491 static int mv_scr_read(struct ata_port
*ap
, unsigned int sc_reg_in
, u32
*val
);
492 static int mv_scr_write(struct ata_port
*ap
, unsigned int sc_reg_in
, u32 val
);
493 static int mv5_scr_read(struct ata_port
*ap
, unsigned int sc_reg_in
, u32
*val
);
494 static int mv5_scr_write(struct ata_port
*ap
, unsigned int sc_reg_in
, u32 val
);
495 static int mv_port_start(struct ata_port
*ap
);
496 static void mv_port_stop(struct ata_port
*ap
);
497 static int mv_qc_defer(struct ata_queued_cmd
*qc
);
498 static void mv_qc_prep(struct ata_queued_cmd
*qc
);
499 static void mv_qc_prep_iie(struct ata_queued_cmd
*qc
);
500 static unsigned int mv_qc_issue(struct ata_queued_cmd
*qc
);
501 static int mv_hardreset(struct ata_link
*link
, unsigned int *class,
502 unsigned long deadline
);
503 static void mv_eh_freeze(struct ata_port
*ap
);
504 static void mv_eh_thaw(struct ata_port
*ap
);
505 static void mv6_dev_config(struct ata_device
*dev
);
507 static void mv5_phy_errata(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
509 static void mv5_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
510 static void mv5_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
512 static int mv5_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
514 static void mv5_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
515 static void mv5_reset_bus(struct ata_host
*host
, void __iomem
*mmio
);
517 static void mv6_phy_errata(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
519 static void mv6_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
520 static void mv6_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
522 static int mv6_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
524 static void mv6_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
525 static void mv_soc_enable_leds(struct mv_host_priv
*hpriv
,
527 static void mv_soc_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
529 static int mv_soc_reset_hc(struct mv_host_priv
*hpriv
,
530 void __iomem
*mmio
, unsigned int n_hc
);
531 static void mv_soc_reset_flash(struct mv_host_priv
*hpriv
,
533 static void mv_soc_reset_bus(struct ata_host
*host
, void __iomem
*mmio
);
534 static void mv_reset_pci_bus(struct ata_host
*host
, void __iomem
*mmio
);
535 static void mv_reset_channel(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
536 unsigned int port_no
);
537 static int mv_stop_edma(struct ata_port
*ap
);
538 static int mv_stop_edma_engine(void __iomem
*port_mmio
);
539 static void mv_edma_cfg(struct ata_port
*ap
, int want_ncq
);
541 static void mv_pmp_select(struct ata_port
*ap
, int pmp
);
542 static int mv_pmp_hardreset(struct ata_link
*link
, unsigned int *class,
543 unsigned long deadline
);
544 static int mv_softreset(struct ata_link
*link
, unsigned int *class,
545 unsigned long deadline
);
546 static void mv_pmp_error_handler(struct ata_port
*ap
);
547 static void mv_process_crpb_entries(struct ata_port
*ap
,
548 struct mv_port_priv
*pp
);
550 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
551 * because we have to allow room for worst case splitting of
552 * PRDs for 64K boundaries in mv_fill_sg().
554 static struct scsi_host_template mv5_sht
= {
555 ATA_BASE_SHT(DRV_NAME
),
556 .sg_tablesize
= MV_MAX_SG_CT
/ 2,
557 .dma_boundary
= MV_DMA_BOUNDARY
,
560 static struct scsi_host_template mv6_sht
= {
561 ATA_NCQ_SHT(DRV_NAME
),
562 .can_queue
= MV_MAX_Q_DEPTH
- 1,
563 .sg_tablesize
= MV_MAX_SG_CT
/ 2,
564 .dma_boundary
= MV_DMA_BOUNDARY
,
567 static struct ata_port_operations mv5_ops
= {
568 .inherits
= &ata_sff_port_ops
,
570 .qc_defer
= mv_qc_defer
,
571 .qc_prep
= mv_qc_prep
,
572 .qc_issue
= mv_qc_issue
,
574 .freeze
= mv_eh_freeze
,
576 .hardreset
= mv_hardreset
,
577 .error_handler
= ata_std_error_handler
, /* avoid SFF EH */
578 .post_internal_cmd
= ATA_OP_NULL
,
580 .scr_read
= mv5_scr_read
,
581 .scr_write
= mv5_scr_write
,
583 .port_start
= mv_port_start
,
584 .port_stop
= mv_port_stop
,
587 static struct ata_port_operations mv6_ops
= {
588 .inherits
= &mv5_ops
,
589 .dev_config
= mv6_dev_config
,
590 .scr_read
= mv_scr_read
,
591 .scr_write
= mv_scr_write
,
593 .pmp_hardreset
= mv_pmp_hardreset
,
594 .pmp_softreset
= mv_softreset
,
595 .softreset
= mv_softreset
,
596 .error_handler
= mv_pmp_error_handler
,
599 static struct ata_port_operations mv_iie_ops
= {
600 .inherits
= &mv6_ops
,
601 .dev_config
= ATA_OP_NULL
,
602 .qc_prep
= mv_qc_prep_iie
,
605 static const struct ata_port_info mv_port_info
[] = {
607 .flags
= MV_COMMON_FLAGS
,
608 .pio_mask
= 0x1f, /* pio0-4 */
609 .udma_mask
= ATA_UDMA6
,
610 .port_ops
= &mv5_ops
,
613 .flags
= MV_COMMON_FLAGS
| MV_FLAG_DUAL_HC
,
614 .pio_mask
= 0x1f, /* pio0-4 */
615 .udma_mask
= ATA_UDMA6
,
616 .port_ops
= &mv5_ops
,
619 .flags
= MV_COMMON_FLAGS
| MV_FLAG_DUAL_HC
,
620 .pio_mask
= 0x1f, /* pio0-4 */
621 .udma_mask
= ATA_UDMA6
,
622 .port_ops
= &mv5_ops
,
625 .flags
= MV_COMMON_FLAGS
| MV_6XXX_FLAGS
|
626 ATA_FLAG_PMP
| ATA_FLAG_ACPI_SATA
|
628 .pio_mask
= 0x1f, /* pio0-4 */
629 .udma_mask
= ATA_UDMA6
,
630 .port_ops
= &mv6_ops
,
633 .flags
= MV_COMMON_FLAGS
| MV_6XXX_FLAGS
|
634 ATA_FLAG_PMP
| ATA_FLAG_ACPI_SATA
|
635 ATA_FLAG_NCQ
| MV_FLAG_DUAL_HC
,
636 .pio_mask
= 0x1f, /* pio0-4 */
637 .udma_mask
= ATA_UDMA6
,
638 .port_ops
= &mv6_ops
,
641 .flags
= MV_GENIIE_FLAGS
,
642 .pio_mask
= 0x1f, /* pio0-4 */
643 .udma_mask
= ATA_UDMA6
,
644 .port_ops
= &mv_iie_ops
,
647 .flags
= MV_GENIIE_FLAGS
,
648 .pio_mask
= 0x1f, /* pio0-4 */
649 .udma_mask
= ATA_UDMA6
,
650 .port_ops
= &mv_iie_ops
,
653 .flags
= MV_GENIIE_FLAGS
,
654 .pio_mask
= 0x1f, /* pio0-4 */
655 .udma_mask
= ATA_UDMA6
,
656 .port_ops
= &mv_iie_ops
,
660 static const struct pci_device_id mv_pci_tbl
[] = {
661 { PCI_VDEVICE(MARVELL
, 0x5040), chip_504x
},
662 { PCI_VDEVICE(MARVELL
, 0x5041), chip_504x
},
663 { PCI_VDEVICE(MARVELL
, 0x5080), chip_5080
},
664 { PCI_VDEVICE(MARVELL
, 0x5081), chip_508x
},
665 /* RocketRAID 1740/174x have different identifiers */
666 { PCI_VDEVICE(TTI
, 0x1740), chip_508x
},
667 { PCI_VDEVICE(TTI
, 0x1742), chip_508x
},
669 { PCI_VDEVICE(MARVELL
, 0x6040), chip_604x
},
670 { PCI_VDEVICE(MARVELL
, 0x6041), chip_604x
},
671 { PCI_VDEVICE(MARVELL
, 0x6042), chip_6042
},
672 { PCI_VDEVICE(MARVELL
, 0x6080), chip_608x
},
673 { PCI_VDEVICE(MARVELL
, 0x6081), chip_608x
},
675 { PCI_VDEVICE(ADAPTEC2
, 0x0241), chip_604x
},
678 { PCI_VDEVICE(ADAPTEC2
, 0x0243), chip_7042
},
680 /* Marvell 7042 support */
681 { PCI_VDEVICE(MARVELL
, 0x7042), chip_7042
},
683 /* Highpoint RocketRAID PCIe series */
684 { PCI_VDEVICE(TTI
, 0x2300), chip_7042
},
685 { PCI_VDEVICE(TTI
, 0x2310), chip_7042
},
687 { } /* terminate list */
690 static const struct mv_hw_ops mv5xxx_ops
= {
691 .phy_errata
= mv5_phy_errata
,
692 .enable_leds
= mv5_enable_leds
,
693 .read_preamp
= mv5_read_preamp
,
694 .reset_hc
= mv5_reset_hc
,
695 .reset_flash
= mv5_reset_flash
,
696 .reset_bus
= mv5_reset_bus
,
699 static const struct mv_hw_ops mv6xxx_ops
= {
700 .phy_errata
= mv6_phy_errata
,
701 .enable_leds
= mv6_enable_leds
,
702 .read_preamp
= mv6_read_preamp
,
703 .reset_hc
= mv6_reset_hc
,
704 .reset_flash
= mv6_reset_flash
,
705 .reset_bus
= mv_reset_pci_bus
,
708 static const struct mv_hw_ops mv_soc_ops
= {
709 .phy_errata
= mv6_phy_errata
,
710 .enable_leds
= mv_soc_enable_leds
,
711 .read_preamp
= mv_soc_read_preamp
,
712 .reset_hc
= mv_soc_reset_hc
,
713 .reset_flash
= mv_soc_reset_flash
,
714 .reset_bus
= mv_soc_reset_bus
,
721 static inline void writelfl(unsigned long data
, void __iomem
*addr
)
724 (void) readl(addr
); /* flush to avoid PCI posted write */
727 static inline unsigned int mv_hc_from_port(unsigned int port
)
729 return port
>> MV_PORT_HC_SHIFT
;
732 static inline unsigned int mv_hardport_from_port(unsigned int port
)
734 return port
& MV_PORT_MASK
;
738 * Consolidate some rather tricky bit shift calculations.
739 * This is hot-path stuff, so not a function.
740 * Simple code, with two return values, so macro rather than inline.
742 * port is the sole input, in range 0..7.
743 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
744 * hardport is the other output, in range 0..3.
746 * Note that port and hardport may be the same variable in some cases.
748 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
750 shift = mv_hc_from_port(port) * HC_SHIFT; \
751 hardport = mv_hardport_from_port(port); \
752 shift += hardport * 2; \
755 static inline void __iomem
*mv_hc_base(void __iomem
*base
, unsigned int hc
)
757 return (base
+ MV_SATAHC0_REG_BASE
+ (hc
* MV_SATAHC_REG_SZ
));
760 static inline void __iomem
*mv_hc_base_from_port(void __iomem
*base
,
763 return mv_hc_base(base
, mv_hc_from_port(port
));
766 static inline void __iomem
*mv_port_base(void __iomem
*base
, unsigned int port
)
768 return mv_hc_base_from_port(base
, port
) +
769 MV_SATAHC_ARBTR_REG_SZ
+
770 (mv_hardport_from_port(port
) * MV_PORT_REG_SZ
);
773 static void __iomem
*mv5_phy_base(void __iomem
*mmio
, unsigned int port
)
775 void __iomem
*hc_mmio
= mv_hc_base_from_port(mmio
, port
);
776 unsigned long ofs
= (mv_hardport_from_port(port
) + 1) * 0x100UL
;
778 return hc_mmio
+ ofs
;
781 static inline void __iomem
*mv_host_base(struct ata_host
*host
)
783 struct mv_host_priv
*hpriv
= host
->private_data
;
787 static inline void __iomem
*mv_ap_base(struct ata_port
*ap
)
789 return mv_port_base(mv_host_base(ap
->host
), ap
->port_no
);
792 static inline int mv_get_hc_count(unsigned long port_flags
)
794 return ((port_flags
& MV_FLAG_DUAL_HC
) ? 2 : 1);
797 static void mv_set_edma_ptrs(void __iomem
*port_mmio
,
798 struct mv_host_priv
*hpriv
,
799 struct mv_port_priv
*pp
)
804 * initialize request queue
806 pp
->req_idx
&= MV_MAX_Q_DEPTH_MASK
; /* paranoia */
807 index
= pp
->req_idx
<< EDMA_REQ_Q_PTR_SHIFT
;
809 WARN_ON(pp
->crqb_dma
& 0x3ff);
810 writel((pp
->crqb_dma
>> 16) >> 16, port_mmio
+ EDMA_REQ_Q_BASE_HI_OFS
);
811 writelfl((pp
->crqb_dma
& EDMA_REQ_Q_BASE_LO_MASK
) | index
,
812 port_mmio
+ EDMA_REQ_Q_IN_PTR_OFS
);
813 writelfl(index
, port_mmio
+ EDMA_REQ_Q_OUT_PTR_OFS
);
816 * initialize response queue
818 pp
->resp_idx
&= MV_MAX_Q_DEPTH_MASK
; /* paranoia */
819 index
= pp
->resp_idx
<< EDMA_RSP_Q_PTR_SHIFT
;
821 WARN_ON(pp
->crpb_dma
& 0xff);
822 writel((pp
->crpb_dma
>> 16) >> 16, port_mmio
+ EDMA_RSP_Q_BASE_HI_OFS
);
823 writelfl(index
, port_mmio
+ EDMA_RSP_Q_IN_PTR_OFS
);
824 writelfl((pp
->crpb_dma
& EDMA_RSP_Q_BASE_LO_MASK
) | index
,
825 port_mmio
+ EDMA_RSP_Q_OUT_PTR_OFS
);
828 static void mv_set_main_irq_mask(struct ata_host
*host
,
829 u32 disable_bits
, u32 enable_bits
)
831 struct mv_host_priv
*hpriv
= host
->private_data
;
832 u32 old_mask
, new_mask
;
834 old_mask
= hpriv
->main_irq_mask
;
835 new_mask
= (old_mask
& ~disable_bits
) | enable_bits
;
836 if (new_mask
!= old_mask
) {
837 hpriv
->main_irq_mask
= new_mask
;
838 writelfl(new_mask
, hpriv
->main_irq_mask_addr
);
842 static void mv_enable_port_irqs(struct ata_port
*ap
,
843 unsigned int port_bits
)
845 unsigned int shift
, hardport
, port
= ap
->port_no
;
846 u32 disable_bits
, enable_bits
;
848 MV_PORT_TO_SHIFT_AND_HARDPORT(port
, shift
, hardport
);
850 disable_bits
= (DONE_IRQ
| ERR_IRQ
) << shift
;
851 enable_bits
= port_bits
<< shift
;
852 mv_set_main_irq_mask(ap
->host
, disable_bits
, enable_bits
);
856 * mv_start_dma - Enable eDMA engine
857 * @base: port base address
858 * @pp: port private data
860 * Verify the local cache of the eDMA state is accurate with a
864 * Inherited from caller.
866 static void mv_start_dma(struct ata_port
*ap
, void __iomem
*port_mmio
,
867 struct mv_port_priv
*pp
, u8 protocol
)
869 int want_ncq
= (protocol
== ATA_PROT_NCQ
);
871 if (pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
) {
872 int using_ncq
= ((pp
->pp_flags
& MV_PP_FLAG_NCQ_EN
) != 0);
873 if (want_ncq
!= using_ncq
)
876 if (!(pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
)) {
877 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
878 int hardport
= mv_hardport_from_port(ap
->port_no
);
879 void __iomem
*hc_mmio
= mv_hc_base_from_port(
880 mv_host_base(ap
->host
), hardport
);
881 u32 hc_irq_cause
, ipending
;
883 /* clear EDMA event indicators, if any */
884 writelfl(0, port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
886 /* clear EDMA interrupt indicator, if any */
887 hc_irq_cause
= readl(hc_mmio
+ HC_IRQ_CAUSE_OFS
);
888 ipending
= (DEV_IRQ
| DMA_IRQ
) << hardport
;
889 if (hc_irq_cause
& ipending
) {
890 writelfl(hc_irq_cause
& ~ipending
,
891 hc_mmio
+ HC_IRQ_CAUSE_OFS
);
894 mv_edma_cfg(ap
, want_ncq
);
896 /* clear FIS IRQ Cause */
897 if (IS_GEN_IIE(hpriv
))
898 writelfl(0, port_mmio
+ SATA_FIS_IRQ_CAUSE_OFS
);
900 mv_set_edma_ptrs(port_mmio
, hpriv
, pp
);
901 mv_enable_port_irqs(ap
, DONE_IRQ
|ERR_IRQ
);
903 writelfl(EDMA_EN
, port_mmio
+ EDMA_CMD_OFS
);
904 pp
->pp_flags
|= MV_PP_FLAG_EDMA_EN
;
908 static void mv_wait_for_edma_empty_idle(struct ata_port
*ap
)
910 void __iomem
*port_mmio
= mv_ap_base(ap
);
911 const u32 empty_idle
= (EDMA_STATUS_CACHE_EMPTY
| EDMA_STATUS_IDLE
);
912 const int per_loop
= 5, timeout
= (15 * 1000 / per_loop
);
916 * Wait for the EDMA engine to finish transactions in progress.
917 * No idea what a good "timeout" value might be, but measurements
918 * indicate that it often requires hundreds of microseconds
919 * with two drives in-use. So we use the 15msec value above
920 * as a rough guess at what even more drives might require.
922 for (i
= 0; i
< timeout
; ++i
) {
923 u32 edma_stat
= readl(port_mmio
+ EDMA_STATUS_OFS
);
924 if ((edma_stat
& empty_idle
) == empty_idle
)
928 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
932 * mv_stop_edma_engine - Disable eDMA engine
933 * @port_mmio: io base address
936 * Inherited from caller.
938 static int mv_stop_edma_engine(void __iomem
*port_mmio
)
942 /* Disable eDMA. The disable bit auto clears. */
943 writelfl(EDMA_DS
, port_mmio
+ EDMA_CMD_OFS
);
945 /* Wait for the chip to confirm eDMA is off. */
946 for (i
= 10000; i
> 0; i
--) {
947 u32 reg
= readl(port_mmio
+ EDMA_CMD_OFS
);
948 if (!(reg
& EDMA_EN
))
955 static int mv_stop_edma(struct ata_port
*ap
)
957 void __iomem
*port_mmio
= mv_ap_base(ap
);
958 struct mv_port_priv
*pp
= ap
->private_data
;
960 if (!(pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
))
962 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
963 mv_wait_for_edma_empty_idle(ap
);
964 if (mv_stop_edma_engine(port_mmio
)) {
965 ata_port_printk(ap
, KERN_ERR
, "Unable to stop eDMA\n");
972 static void mv_dump_mem(void __iomem
*start
, unsigned bytes
)
975 for (b
= 0; b
< bytes
; ) {
976 DPRINTK("%p: ", start
+ b
);
977 for (w
= 0; b
< bytes
&& w
< 4; w
++) {
978 printk("%08x ", readl(start
+ b
));
986 static void mv_dump_pci_cfg(struct pci_dev
*pdev
, unsigned bytes
)
991 for (b
= 0; b
< bytes
; ) {
992 DPRINTK("%02x: ", b
);
993 for (w
= 0; b
< bytes
&& w
< 4; w
++) {
994 (void) pci_read_config_dword(pdev
, b
, &dw
);
1002 static void mv_dump_all_regs(void __iomem
*mmio_base
, int port
,
1003 struct pci_dev
*pdev
)
1006 void __iomem
*hc_base
= mv_hc_base(mmio_base
,
1007 port
>> MV_PORT_HC_SHIFT
);
1008 void __iomem
*port_base
;
1009 int start_port
, num_ports
, p
, start_hc
, num_hcs
, hc
;
1012 start_hc
= start_port
= 0;
1013 num_ports
= 8; /* shld be benign for 4 port devs */
1016 start_hc
= port
>> MV_PORT_HC_SHIFT
;
1018 num_ports
= num_hcs
= 1;
1020 DPRINTK("All registers for port(s) %u-%u:\n", start_port
,
1021 num_ports
> 1 ? num_ports
- 1 : start_port
);
1024 DPRINTK("PCI config space regs:\n");
1025 mv_dump_pci_cfg(pdev
, 0x68);
1027 DPRINTK("PCI regs:\n");
1028 mv_dump_mem(mmio_base
+0xc00, 0x3c);
1029 mv_dump_mem(mmio_base
+0xd00, 0x34);
1030 mv_dump_mem(mmio_base
+0xf00, 0x4);
1031 mv_dump_mem(mmio_base
+0x1d00, 0x6c);
1032 for (hc
= start_hc
; hc
< start_hc
+ num_hcs
; hc
++) {
1033 hc_base
= mv_hc_base(mmio_base
, hc
);
1034 DPRINTK("HC regs (HC %i):\n", hc
);
1035 mv_dump_mem(hc_base
, 0x1c);
1037 for (p
= start_port
; p
< start_port
+ num_ports
; p
++) {
1038 port_base
= mv_port_base(mmio_base
, p
);
1039 DPRINTK("EDMA regs (port %i):\n", p
);
1040 mv_dump_mem(port_base
, 0x54);
1041 DPRINTK("SATA regs (port %i):\n", p
);
1042 mv_dump_mem(port_base
+0x300, 0x60);
1047 static unsigned int mv_scr_offset(unsigned int sc_reg_in
)
1051 switch (sc_reg_in
) {
1055 ofs
= SATA_STATUS_OFS
+ (sc_reg_in
* sizeof(u32
));
1058 ofs
= SATA_ACTIVE_OFS
; /* active is not with the others */
1067 static int mv_scr_read(struct ata_port
*ap
, unsigned int sc_reg_in
, u32
*val
)
1069 unsigned int ofs
= mv_scr_offset(sc_reg_in
);
1071 if (ofs
!= 0xffffffffU
) {
1072 *val
= readl(mv_ap_base(ap
) + ofs
);
1078 static int mv_scr_write(struct ata_port
*ap
, unsigned int sc_reg_in
, u32 val
)
1080 unsigned int ofs
= mv_scr_offset(sc_reg_in
);
1082 if (ofs
!= 0xffffffffU
) {
1083 writelfl(val
, mv_ap_base(ap
) + ofs
);
1089 static void mv6_dev_config(struct ata_device
*adev
)
1092 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1094 * Gen-II does not support NCQ over a port multiplier
1095 * (no FIS-based switching).
1097 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1098 * See mv_qc_prep() for more info.
1100 if (adev
->flags
& ATA_DFLAG_NCQ
) {
1101 if (sata_pmp_attached(adev
->link
->ap
)) {
1102 adev
->flags
&= ~ATA_DFLAG_NCQ
;
1103 ata_dev_printk(adev
, KERN_INFO
,
1104 "NCQ disabled for command-based switching\n");
1105 } else if (adev
->max_sectors
> GEN_II_NCQ_MAX_SECTORS
) {
1106 adev
->max_sectors
= GEN_II_NCQ_MAX_SECTORS
;
1107 ata_dev_printk(adev
, KERN_INFO
,
1108 "max_sectors limited to %u for NCQ\n",
1114 static int mv_qc_defer(struct ata_queued_cmd
*qc
)
1116 struct ata_link
*link
= qc
->dev
->link
;
1117 struct ata_port
*ap
= link
->ap
;
1118 struct mv_port_priv
*pp
= ap
->private_data
;
1121 * Don't allow new commands if we're in a delayed EH state
1122 * for NCQ and/or FIS-based switching.
1124 if (pp
->pp_flags
& MV_PP_FLAG_DELAYED_EH
)
1125 return ATA_DEFER_PORT
;
1127 * If the port is completely idle, then allow the new qc.
1129 if (ap
->nr_active_links
== 0)
1132 if (pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
) {
1134 * The port is operating in host queuing mode (EDMA).
1135 * It can accomodate a new qc if the qc protocol
1136 * is compatible with the current host queue mode.
1138 if (pp
->pp_flags
& MV_PP_FLAG_NCQ_EN
) {
1140 * The host queue (EDMA) is in NCQ mode.
1141 * If the new qc is also an NCQ command,
1142 * then allow the new qc.
1144 if (qc
->tf
.protocol
== ATA_PROT_NCQ
)
1148 * The host queue (EDMA) is in non-NCQ, DMA mode.
1149 * If the new qc is also a non-NCQ, DMA command,
1150 * then allow the new qc.
1152 if (qc
->tf
.protocol
== ATA_PROT_DMA
)
1156 return ATA_DEFER_PORT
;
1159 static void mv_config_fbs(void __iomem
*port_mmio
, int want_ncq
, int want_fbs
)
1161 u32 new_fiscfg
, old_fiscfg
;
1162 u32 new_ltmode
, old_ltmode
;
1163 u32 new_haltcond
, old_haltcond
;
1165 old_fiscfg
= readl(port_mmio
+ FISCFG_OFS
);
1166 old_ltmode
= readl(port_mmio
+ LTMODE_OFS
);
1167 old_haltcond
= readl(port_mmio
+ EDMA_HALTCOND_OFS
);
1169 new_fiscfg
= old_fiscfg
& ~(FISCFG_SINGLE_SYNC
| FISCFG_WAIT_DEV_ERR
);
1170 new_ltmode
= old_ltmode
& ~LTMODE_BIT8
;
1171 new_haltcond
= old_haltcond
| EDMA_ERR_DEV
;
1174 new_fiscfg
= old_fiscfg
| FISCFG_SINGLE_SYNC
;
1175 new_ltmode
= old_ltmode
| LTMODE_BIT8
;
1177 new_haltcond
&= ~EDMA_ERR_DEV
;
1179 new_fiscfg
|= FISCFG_WAIT_DEV_ERR
;
1182 if (new_fiscfg
!= old_fiscfg
)
1183 writelfl(new_fiscfg
, port_mmio
+ FISCFG_OFS
);
1184 if (new_ltmode
!= old_ltmode
)
1185 writelfl(new_ltmode
, port_mmio
+ LTMODE_OFS
);
1186 if (new_haltcond
!= old_haltcond
)
1187 writelfl(new_haltcond
, port_mmio
+ EDMA_HALTCOND_OFS
);
1190 static void mv_60x1_errata_sata25(struct ata_port
*ap
, int want_ncq
)
1192 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1195 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1196 old
= readl(hpriv
->base
+ MV_GPIO_PORT_CTL_OFS
);
1198 new = old
| (1 << 22);
1200 new = old
& ~(1 << 22);
1202 writel(new, hpriv
->base
+ MV_GPIO_PORT_CTL_OFS
);
1205 static void mv_edma_cfg(struct ata_port
*ap
, int want_ncq
)
1208 struct mv_port_priv
*pp
= ap
->private_data
;
1209 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1210 void __iomem
*port_mmio
= mv_ap_base(ap
);
1212 /* set up non-NCQ EDMA configuration */
1213 cfg
= EDMA_CFG_Q_DEPTH
; /* always 0x1f for *all* chips */
1214 pp
->pp_flags
&= ~MV_PP_FLAG_FBS_EN
;
1216 if (IS_GEN_I(hpriv
))
1217 cfg
|= (1 << 8); /* enab config burst size mask */
1219 else if (IS_GEN_II(hpriv
)) {
1220 cfg
|= EDMA_CFG_RD_BRST_EXT
| EDMA_CFG_WR_BUFF_LEN
;
1221 mv_60x1_errata_sata25(ap
, want_ncq
);
1223 } else if (IS_GEN_IIE(hpriv
)) {
1224 int want_fbs
= sata_pmp_attached(ap
);
1226 * Possible future enhancement:
1228 * The chip can use FBS with non-NCQ, if we allow it,
1229 * But first we need to have the error handling in place
1230 * for this mode (datasheet section 7.3.15.4.2.3).
1231 * So disallow non-NCQ FBS for now.
1233 want_fbs
&= want_ncq
;
1235 mv_config_fbs(port_mmio
, want_ncq
, want_fbs
);
1238 pp
->pp_flags
|= MV_PP_FLAG_FBS_EN
;
1239 cfg
|= EDMA_CFG_EDMA_FBS
; /* FIS-based switching */
1242 cfg
|= (1 << 23); /* do not mask PM field in rx'd FIS */
1243 cfg
|= (1 << 22); /* enab 4-entry host queue cache */
1245 cfg
|= (1 << 18); /* enab early completion */
1246 if (hpriv
->hp_flags
& MV_HP_CUT_THROUGH
)
1247 cfg
|= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1251 cfg
|= EDMA_CFG_NCQ
;
1252 pp
->pp_flags
|= MV_PP_FLAG_NCQ_EN
;
1254 pp
->pp_flags
&= ~MV_PP_FLAG_NCQ_EN
;
1256 writelfl(cfg
, port_mmio
+ EDMA_CFG_OFS
);
1259 static void mv_port_free_dma_mem(struct ata_port
*ap
)
1261 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1262 struct mv_port_priv
*pp
= ap
->private_data
;
1266 dma_pool_free(hpriv
->crqb_pool
, pp
->crqb
, pp
->crqb_dma
);
1270 dma_pool_free(hpriv
->crpb_pool
, pp
->crpb
, pp
->crpb_dma
);
1274 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1275 * For later hardware, we have one unique sg_tbl per NCQ tag.
1277 for (tag
= 0; tag
< MV_MAX_Q_DEPTH
; ++tag
) {
1278 if (pp
->sg_tbl
[tag
]) {
1279 if (tag
== 0 || !IS_GEN_I(hpriv
))
1280 dma_pool_free(hpriv
->sg_tbl_pool
,
1282 pp
->sg_tbl_dma
[tag
]);
1283 pp
->sg_tbl
[tag
] = NULL
;
1289 * mv_port_start - Port specific init/start routine.
1290 * @ap: ATA channel to manipulate
1292 * Allocate and point to DMA memory, init port private memory,
1296 * Inherited from caller.
1298 static int mv_port_start(struct ata_port
*ap
)
1300 struct device
*dev
= ap
->host
->dev
;
1301 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1302 struct mv_port_priv
*pp
;
1305 pp
= devm_kzalloc(dev
, sizeof(*pp
), GFP_KERNEL
);
1308 ap
->private_data
= pp
;
1310 pp
->crqb
= dma_pool_alloc(hpriv
->crqb_pool
, GFP_KERNEL
, &pp
->crqb_dma
);
1313 memset(pp
->crqb
, 0, MV_CRQB_Q_SZ
);
1315 pp
->crpb
= dma_pool_alloc(hpriv
->crpb_pool
, GFP_KERNEL
, &pp
->crpb_dma
);
1317 goto out_port_free_dma_mem
;
1318 memset(pp
->crpb
, 0, MV_CRPB_Q_SZ
);
1321 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1322 * For later hardware, we need one unique sg_tbl per NCQ tag.
1324 for (tag
= 0; tag
< MV_MAX_Q_DEPTH
; ++tag
) {
1325 if (tag
== 0 || !IS_GEN_I(hpriv
)) {
1326 pp
->sg_tbl
[tag
] = dma_pool_alloc(hpriv
->sg_tbl_pool
,
1327 GFP_KERNEL
, &pp
->sg_tbl_dma
[tag
]);
1328 if (!pp
->sg_tbl
[tag
])
1329 goto out_port_free_dma_mem
;
1331 pp
->sg_tbl
[tag
] = pp
->sg_tbl
[0];
1332 pp
->sg_tbl_dma
[tag
] = pp
->sg_tbl_dma
[0];
1337 out_port_free_dma_mem
:
1338 mv_port_free_dma_mem(ap
);
1343 * mv_port_stop - Port specific cleanup/stop routine.
1344 * @ap: ATA channel to manipulate
1346 * Stop DMA, cleanup port memory.
1349 * This routine uses the host lock to protect the DMA stop.
1351 static void mv_port_stop(struct ata_port
*ap
)
1354 mv_enable_port_irqs(ap
, 0);
1355 mv_port_free_dma_mem(ap
);
1359 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1360 * @qc: queued command whose SG list to source from
1362 * Populate the SG list and mark the last entry.
1365 * Inherited from caller.
1367 static void mv_fill_sg(struct ata_queued_cmd
*qc
)
1369 struct mv_port_priv
*pp
= qc
->ap
->private_data
;
1370 struct scatterlist
*sg
;
1371 struct mv_sg
*mv_sg
, *last_sg
= NULL
;
1374 mv_sg
= pp
->sg_tbl
[qc
->tag
];
1375 for_each_sg(qc
->sg
, sg
, qc
->n_elem
, si
) {
1376 dma_addr_t addr
= sg_dma_address(sg
);
1377 u32 sg_len
= sg_dma_len(sg
);
1380 u32 offset
= addr
& 0xffff;
1383 if ((offset
+ sg_len
> 0x10000))
1384 len
= 0x10000 - offset
;
1386 mv_sg
->addr
= cpu_to_le32(addr
& 0xffffffff);
1387 mv_sg
->addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
1388 mv_sg
->flags_size
= cpu_to_le32(len
& 0xffff);
1398 if (likely(last_sg
))
1399 last_sg
->flags_size
|= cpu_to_le32(EPRD_FLAG_END_OF_TBL
);
1402 static void mv_crqb_pack_cmd(__le16
*cmdw
, u8 data
, u8 addr
, unsigned last
)
1404 u16 tmp
= data
| (addr
<< CRQB_CMD_ADDR_SHIFT
) | CRQB_CMD_CS
|
1405 (last
? CRQB_CMD_LAST
: 0);
1406 *cmdw
= cpu_to_le16(tmp
);
1410 * mv_qc_prep - Host specific command preparation.
1411 * @qc: queued command to prepare
1413 * This routine simply redirects to the general purpose routine
1414 * if command is not DMA. Else, it handles prep of the CRQB
1415 * (command request block), does some sanity checking, and calls
1416 * the SG load routine.
1419 * Inherited from caller.
1421 static void mv_qc_prep(struct ata_queued_cmd
*qc
)
1423 struct ata_port
*ap
= qc
->ap
;
1424 struct mv_port_priv
*pp
= ap
->private_data
;
1426 struct ata_taskfile
*tf
;
1430 if ((qc
->tf
.protocol
!= ATA_PROT_DMA
) &&
1431 (qc
->tf
.protocol
!= ATA_PROT_NCQ
))
1434 /* Fill in command request block
1436 if (!(qc
->tf
.flags
& ATA_TFLAG_WRITE
))
1437 flags
|= CRQB_FLAG_READ
;
1438 WARN_ON(MV_MAX_Q_DEPTH
<= qc
->tag
);
1439 flags
|= qc
->tag
<< CRQB_TAG_SHIFT
;
1440 flags
|= (qc
->dev
->link
->pmp
& 0xf) << CRQB_PMP_SHIFT
;
1442 /* get current queue index from software */
1443 in_index
= pp
->req_idx
;
1445 pp
->crqb
[in_index
].sg_addr
=
1446 cpu_to_le32(pp
->sg_tbl_dma
[qc
->tag
] & 0xffffffff);
1447 pp
->crqb
[in_index
].sg_addr_hi
=
1448 cpu_to_le32((pp
->sg_tbl_dma
[qc
->tag
] >> 16) >> 16);
1449 pp
->crqb
[in_index
].ctrl_flags
= cpu_to_le16(flags
);
1451 cw
= &pp
->crqb
[in_index
].ata_cmd
[0];
1454 /* Sadly, the CRQB cannot accomodate all registers--there are
1455 * only 11 bytes...so we must pick and choose required
1456 * registers based on the command. So, we drop feature and
1457 * hob_feature for [RW] DMA commands, but they are needed for
1458 * NCQ. NCQ will drop hob_nsect.
1460 switch (tf
->command
) {
1462 case ATA_CMD_READ_EXT
:
1464 case ATA_CMD_WRITE_EXT
:
1465 case ATA_CMD_WRITE_FUA_EXT
:
1466 mv_crqb_pack_cmd(cw
++, tf
->hob_nsect
, ATA_REG_NSECT
, 0);
1468 case ATA_CMD_FPDMA_READ
:
1469 case ATA_CMD_FPDMA_WRITE
:
1470 mv_crqb_pack_cmd(cw
++, tf
->hob_feature
, ATA_REG_FEATURE
, 0);
1471 mv_crqb_pack_cmd(cw
++, tf
->feature
, ATA_REG_FEATURE
, 0);
1474 /* The only other commands EDMA supports in non-queued and
1475 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1476 * of which are defined/used by Linux. If we get here, this
1477 * driver needs work.
1479 * FIXME: modify libata to give qc_prep a return value and
1480 * return error here.
1482 BUG_ON(tf
->command
);
1485 mv_crqb_pack_cmd(cw
++, tf
->nsect
, ATA_REG_NSECT
, 0);
1486 mv_crqb_pack_cmd(cw
++, tf
->hob_lbal
, ATA_REG_LBAL
, 0);
1487 mv_crqb_pack_cmd(cw
++, tf
->lbal
, ATA_REG_LBAL
, 0);
1488 mv_crqb_pack_cmd(cw
++, tf
->hob_lbam
, ATA_REG_LBAM
, 0);
1489 mv_crqb_pack_cmd(cw
++, tf
->lbam
, ATA_REG_LBAM
, 0);
1490 mv_crqb_pack_cmd(cw
++, tf
->hob_lbah
, ATA_REG_LBAH
, 0);
1491 mv_crqb_pack_cmd(cw
++, tf
->lbah
, ATA_REG_LBAH
, 0);
1492 mv_crqb_pack_cmd(cw
++, tf
->device
, ATA_REG_DEVICE
, 0);
1493 mv_crqb_pack_cmd(cw
++, tf
->command
, ATA_REG_CMD
, 1); /* last */
1495 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
1501 * mv_qc_prep_iie - Host specific command preparation.
1502 * @qc: queued command to prepare
1504 * This routine simply redirects to the general purpose routine
1505 * if command is not DMA. Else, it handles prep of the CRQB
1506 * (command request block), does some sanity checking, and calls
1507 * the SG load routine.
1510 * Inherited from caller.
1512 static void mv_qc_prep_iie(struct ata_queued_cmd
*qc
)
1514 struct ata_port
*ap
= qc
->ap
;
1515 struct mv_port_priv
*pp
= ap
->private_data
;
1516 struct mv_crqb_iie
*crqb
;
1517 struct ata_taskfile
*tf
;
1521 if ((qc
->tf
.protocol
!= ATA_PROT_DMA
) &&
1522 (qc
->tf
.protocol
!= ATA_PROT_NCQ
))
1525 /* Fill in Gen IIE command request block */
1526 if (!(qc
->tf
.flags
& ATA_TFLAG_WRITE
))
1527 flags
|= CRQB_FLAG_READ
;
1529 WARN_ON(MV_MAX_Q_DEPTH
<= qc
->tag
);
1530 flags
|= qc
->tag
<< CRQB_TAG_SHIFT
;
1531 flags
|= qc
->tag
<< CRQB_HOSTQ_SHIFT
;
1532 flags
|= (qc
->dev
->link
->pmp
& 0xf) << CRQB_PMP_SHIFT
;
1534 /* get current queue index from software */
1535 in_index
= pp
->req_idx
;
1537 crqb
= (struct mv_crqb_iie
*) &pp
->crqb
[in_index
];
1538 crqb
->addr
= cpu_to_le32(pp
->sg_tbl_dma
[qc
->tag
] & 0xffffffff);
1539 crqb
->addr_hi
= cpu_to_le32((pp
->sg_tbl_dma
[qc
->tag
] >> 16) >> 16);
1540 crqb
->flags
= cpu_to_le32(flags
);
1543 crqb
->ata_cmd
[0] = cpu_to_le32(
1544 (tf
->command
<< 16) |
1547 crqb
->ata_cmd
[1] = cpu_to_le32(
1553 crqb
->ata_cmd
[2] = cpu_to_le32(
1554 (tf
->hob_lbal
<< 0) |
1555 (tf
->hob_lbam
<< 8) |
1556 (tf
->hob_lbah
<< 16) |
1557 (tf
->hob_feature
<< 24)
1559 crqb
->ata_cmd
[3] = cpu_to_le32(
1561 (tf
->hob_nsect
<< 8)
1564 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
1570 * mv_qc_issue - Initiate a command to the host
1571 * @qc: queued command to start
1573 * This routine simply redirects to the general purpose routine
1574 * if command is not DMA. Else, it sanity checks our local
1575 * caches of the request producer/consumer indices then enables
1576 * DMA and bumps the request producer index.
1579 * Inherited from caller.
1581 static unsigned int mv_qc_issue(struct ata_queued_cmd
*qc
)
1583 struct ata_port
*ap
= qc
->ap
;
1584 void __iomem
*port_mmio
= mv_ap_base(ap
);
1585 struct mv_port_priv
*pp
= ap
->private_data
;
1588 if ((qc
->tf
.protocol
!= ATA_PROT_DMA
) &&
1589 (qc
->tf
.protocol
!= ATA_PROT_NCQ
)) {
1591 * We're about to send a non-EDMA capable command to the
1592 * port. Turn off EDMA so there won't be problems accessing
1593 * shadow block, etc registers.
1596 mv_enable_port_irqs(ap
, ERR_IRQ
);
1597 mv_pmp_select(ap
, qc
->dev
->link
->pmp
);
1598 return ata_sff_qc_issue(qc
);
1601 mv_start_dma(ap
, port_mmio
, pp
, qc
->tf
.protocol
);
1603 pp
->req_idx
= (pp
->req_idx
+ 1) & MV_MAX_Q_DEPTH_MASK
;
1604 in_index
= pp
->req_idx
<< EDMA_REQ_Q_PTR_SHIFT
;
1606 /* and write the request in pointer to kick the EDMA to life */
1607 writelfl((pp
->crqb_dma
& EDMA_REQ_Q_BASE_LO_MASK
) | in_index
,
1608 port_mmio
+ EDMA_REQ_Q_IN_PTR_OFS
);
1613 static struct ata_queued_cmd
*mv_get_active_qc(struct ata_port
*ap
)
1615 struct mv_port_priv
*pp
= ap
->private_data
;
1616 struct ata_queued_cmd
*qc
;
1618 if (pp
->pp_flags
& MV_PP_FLAG_NCQ_EN
)
1620 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
1621 if (qc
&& (qc
->tf
.flags
& ATA_TFLAG_POLLING
))
1626 static void mv_pmp_error_handler(struct ata_port
*ap
)
1628 unsigned int pmp
, pmp_map
;
1629 struct mv_port_priv
*pp
= ap
->private_data
;
1631 if (pp
->pp_flags
& MV_PP_FLAG_DELAYED_EH
) {
1633 * Perform NCQ error analysis on failed PMPs
1634 * before we freeze the port entirely.
1636 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1638 pmp_map
= pp
->delayed_eh_pmp_map
;
1639 pp
->pp_flags
&= ~MV_PP_FLAG_DELAYED_EH
;
1640 for (pmp
= 0; pmp_map
!= 0; pmp
++) {
1641 unsigned int this_pmp
= (1 << pmp
);
1642 if (pmp_map
& this_pmp
) {
1643 struct ata_link
*link
= &ap
->pmp_link
[pmp
];
1644 pmp_map
&= ~this_pmp
;
1645 ata_eh_analyze_ncq_error(link
);
1648 ata_port_freeze(ap
);
1650 sata_pmp_error_handler(ap
);
1653 static unsigned int mv_get_err_pmp_map(struct ata_port
*ap
)
1655 void __iomem
*port_mmio
= mv_ap_base(ap
);
1657 return readl(port_mmio
+ SATA_TESTCTL_OFS
) >> 16;
1660 static void mv_pmp_eh_prep(struct ata_port
*ap
, unsigned int pmp_map
)
1662 struct ata_eh_info
*ehi
;
1666 * Initialize EH info for PMPs which saw device errors
1668 ehi
= &ap
->link
.eh_info
;
1669 for (pmp
= 0; pmp_map
!= 0; pmp
++) {
1670 unsigned int this_pmp
= (1 << pmp
);
1671 if (pmp_map
& this_pmp
) {
1672 struct ata_link
*link
= &ap
->pmp_link
[pmp
];
1674 pmp_map
&= ~this_pmp
;
1675 ehi
= &link
->eh_info
;
1676 ata_ehi_clear_desc(ehi
);
1677 ata_ehi_push_desc(ehi
, "dev err");
1678 ehi
->err_mask
|= AC_ERR_DEV
;
1679 ehi
->action
|= ATA_EH_RESET
;
1680 ata_link_abort(link
);
1685 static int mv_req_q_empty(struct ata_port
*ap
)
1687 void __iomem
*port_mmio
= mv_ap_base(ap
);
1688 u32 in_ptr
, out_ptr
;
1690 in_ptr
= (readl(port_mmio
+ EDMA_REQ_Q_IN_PTR_OFS
)
1691 >> EDMA_REQ_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
;
1692 out_ptr
= (readl(port_mmio
+ EDMA_REQ_Q_OUT_PTR_OFS
)
1693 >> EDMA_REQ_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
;
1694 return (in_ptr
== out_ptr
); /* 1 == queue_is_empty */
1697 static int mv_handle_fbs_ncq_dev_err(struct ata_port
*ap
)
1699 struct mv_port_priv
*pp
= ap
->private_data
;
1701 unsigned int old_map
, new_map
;
1704 * Device error during FBS+NCQ operation:
1706 * Set a port flag to prevent further I/O being enqueued.
1707 * Leave the EDMA running to drain outstanding commands from this port.
1708 * Perform the post-mortem/EH only when all responses are complete.
1709 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1711 if (!(pp
->pp_flags
& MV_PP_FLAG_DELAYED_EH
)) {
1712 pp
->pp_flags
|= MV_PP_FLAG_DELAYED_EH
;
1713 pp
->delayed_eh_pmp_map
= 0;
1715 old_map
= pp
->delayed_eh_pmp_map
;
1716 new_map
= old_map
| mv_get_err_pmp_map(ap
);
1718 if (old_map
!= new_map
) {
1719 pp
->delayed_eh_pmp_map
= new_map
;
1720 mv_pmp_eh_prep(ap
, new_map
& ~old_map
);
1722 failed_links
= hweight16(new_map
);
1724 ata_port_printk(ap
, KERN_INFO
, "%s: pmp_map=%04x qc_map=%04x "
1725 "failed_links=%d nr_active_links=%d\n",
1726 __func__
, pp
->delayed_eh_pmp_map
,
1727 ap
->qc_active
, failed_links
,
1728 ap
->nr_active_links
);
1730 if (ap
->nr_active_links
<= failed_links
&& mv_req_q_empty(ap
)) {
1731 mv_process_crpb_entries(ap
, pp
);
1734 ata_port_printk(ap
, KERN_INFO
, "%s: done\n", __func__
);
1735 return 1; /* handled */
1737 ata_port_printk(ap
, KERN_INFO
, "%s: waiting\n", __func__
);
1738 return 1; /* handled */
1741 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port
*ap
)
1744 * Possible future enhancement:
1746 * FBS+non-NCQ operation is not yet implemented.
1747 * See related notes in mv_edma_cfg().
1749 * Device error during FBS+non-NCQ operation:
1751 * We need to snapshot the shadow registers for each failed command.
1752 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1754 return 0; /* not handled */
1757 static int mv_handle_dev_err(struct ata_port
*ap
, u32 edma_err_cause
)
1759 struct mv_port_priv
*pp
= ap
->private_data
;
1761 if (!(pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
))
1762 return 0; /* EDMA was not active: not handled */
1763 if (!(pp
->pp_flags
& MV_PP_FLAG_FBS_EN
))
1764 return 0; /* FBS was not active: not handled */
1766 if (!(edma_err_cause
& EDMA_ERR_DEV
))
1767 return 0; /* non DEV error: not handled */
1768 edma_err_cause
&= ~EDMA_ERR_IRQ_TRANSIENT
;
1769 if (edma_err_cause
& ~(EDMA_ERR_DEV
| EDMA_ERR_SELF_DIS
))
1770 return 0; /* other problems: not handled */
1772 if (pp
->pp_flags
& MV_PP_FLAG_NCQ_EN
) {
1774 * EDMA should NOT have self-disabled for this case.
1775 * If it did, then something is wrong elsewhere,
1776 * and we cannot handle it here.
1778 if (edma_err_cause
& EDMA_ERR_SELF_DIS
) {
1779 ata_port_printk(ap
, KERN_WARNING
,
1780 "%s: err_cause=0x%x pp_flags=0x%x\n",
1781 __func__
, edma_err_cause
, pp
->pp_flags
);
1782 return 0; /* not handled */
1784 return mv_handle_fbs_ncq_dev_err(ap
);
1787 * EDMA should have self-disabled for this case.
1788 * If it did not, then something is wrong elsewhere,
1789 * and we cannot handle it here.
1791 if (!(edma_err_cause
& EDMA_ERR_SELF_DIS
)) {
1792 ata_port_printk(ap
, KERN_WARNING
,
1793 "%s: err_cause=0x%x pp_flags=0x%x\n",
1794 __func__
, edma_err_cause
, pp
->pp_flags
);
1795 return 0; /* not handled */
1797 return mv_handle_fbs_non_ncq_dev_err(ap
);
1799 return 0; /* not handled */
1802 static void mv_unexpected_intr(struct ata_port
*ap
, int edma_was_enabled
)
1804 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
1805 char *when
= "idle";
1807 ata_ehi_clear_desc(ehi
);
1808 if (!ap
|| (ap
->flags
& ATA_FLAG_DISABLED
)) {
1810 } else if (edma_was_enabled
) {
1811 when
= "EDMA enabled";
1813 struct ata_queued_cmd
*qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
1814 if (qc
&& (qc
->tf
.flags
& ATA_TFLAG_POLLING
))
1817 ata_ehi_push_desc(ehi
, "unexpected device interrupt while %s", when
);
1818 ehi
->err_mask
|= AC_ERR_OTHER
;
1819 ehi
->action
|= ATA_EH_RESET
;
1820 ata_port_freeze(ap
);
1824 * mv_err_intr - Handle error interrupts on the port
1825 * @ap: ATA channel to manipulate
1826 * @qc: affected command (non-NCQ), or NULL
1828 * Most cases require a full reset of the chip's state machine,
1829 * which also performs a COMRESET.
1830 * Also, if the port disabled DMA, update our cached copy to match.
1833 * Inherited from caller.
1835 static void mv_err_intr(struct ata_port
*ap
)
1837 void __iomem
*port_mmio
= mv_ap_base(ap
);
1838 u32 edma_err_cause
, eh_freeze_mask
, serr
= 0;
1840 struct mv_port_priv
*pp
= ap
->private_data
;
1841 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1842 unsigned int action
= 0, err_mask
= 0;
1843 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
1844 struct ata_queued_cmd
*qc
;
1848 * Read and clear the SError and err_cause bits.
1849 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
1850 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
1852 sata_scr_read(&ap
->link
, SCR_ERROR
, &serr
);
1853 sata_scr_write_flush(&ap
->link
, SCR_ERROR
, serr
);
1855 edma_err_cause
= readl(port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
1856 if (IS_GEN_IIE(hpriv
) && (edma_err_cause
& EDMA_ERR_TRANS_IRQ_7
)) {
1857 fis_cause
= readl(port_mmio
+ SATA_FIS_IRQ_CAUSE_OFS
);
1858 writelfl(~fis_cause
, port_mmio
+ SATA_FIS_IRQ_CAUSE_OFS
);
1860 writelfl(~edma_err_cause
, port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
1862 if (edma_err_cause
& EDMA_ERR_DEV
) {
1864 * Device errors during FIS-based switching operation
1865 * require special handling.
1867 if (mv_handle_dev_err(ap
, edma_err_cause
))
1871 qc
= mv_get_active_qc(ap
);
1872 ata_ehi_clear_desc(ehi
);
1873 ata_ehi_push_desc(ehi
, "edma_err_cause=%08x pp_flags=%08x",
1874 edma_err_cause
, pp
->pp_flags
);
1876 if (IS_GEN_IIE(hpriv
) && (edma_err_cause
& EDMA_ERR_TRANS_IRQ_7
)) {
1877 ata_ehi_push_desc(ehi
, "fis_cause=%08x", fis_cause
);
1878 if (fis_cause
& SATA_FIS_IRQ_AN
) {
1879 u32 ec
= edma_err_cause
&
1880 ~(EDMA_ERR_TRANS_IRQ_7
| EDMA_ERR_IRQ_TRANSIENT
);
1881 sata_async_notification(ap
);
1883 return; /* Just an AN; no need for the nukes */
1884 ata_ehi_push_desc(ehi
, "SDB notify");
1888 * All generations share these EDMA error cause bits:
1890 if (edma_err_cause
& EDMA_ERR_DEV
) {
1891 err_mask
|= AC_ERR_DEV
;
1892 action
|= ATA_EH_RESET
;
1893 ata_ehi_push_desc(ehi
, "dev error");
1895 if (edma_err_cause
& (EDMA_ERR_D_PAR
| EDMA_ERR_PRD_PAR
|
1896 EDMA_ERR_CRQB_PAR
| EDMA_ERR_CRPB_PAR
|
1897 EDMA_ERR_INTRL_PAR
)) {
1898 err_mask
|= AC_ERR_ATA_BUS
;
1899 action
|= ATA_EH_RESET
;
1900 ata_ehi_push_desc(ehi
, "parity error");
1902 if (edma_err_cause
& (EDMA_ERR_DEV_DCON
| EDMA_ERR_DEV_CON
)) {
1903 ata_ehi_hotplugged(ehi
);
1904 ata_ehi_push_desc(ehi
, edma_err_cause
& EDMA_ERR_DEV_DCON
?
1905 "dev disconnect" : "dev connect");
1906 action
|= ATA_EH_RESET
;
1910 * Gen-I has a different SELF_DIS bit,
1911 * different FREEZE bits, and no SERR bit:
1913 if (IS_GEN_I(hpriv
)) {
1914 eh_freeze_mask
= EDMA_EH_FREEZE_5
;
1915 if (edma_err_cause
& EDMA_ERR_SELF_DIS_5
) {
1916 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
1917 ata_ehi_push_desc(ehi
, "EDMA self-disable");
1920 eh_freeze_mask
= EDMA_EH_FREEZE
;
1921 if (edma_err_cause
& EDMA_ERR_SELF_DIS
) {
1922 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
1923 ata_ehi_push_desc(ehi
, "EDMA self-disable");
1925 if (edma_err_cause
& EDMA_ERR_SERR
) {
1926 ata_ehi_push_desc(ehi
, "SError=%08x", serr
);
1927 err_mask
|= AC_ERR_ATA_BUS
;
1928 action
|= ATA_EH_RESET
;
1933 err_mask
= AC_ERR_OTHER
;
1934 action
|= ATA_EH_RESET
;
1937 ehi
->serror
|= serr
;
1938 ehi
->action
|= action
;
1941 qc
->err_mask
|= err_mask
;
1943 ehi
->err_mask
|= err_mask
;
1945 if (err_mask
== AC_ERR_DEV
) {
1947 * Cannot do ata_port_freeze() here,
1948 * because it would kill PIO access,
1949 * which is needed for further diagnosis.
1953 } else if (edma_err_cause
& eh_freeze_mask
) {
1955 * Note to self: ata_port_freeze() calls ata_port_abort()
1957 ata_port_freeze(ap
);
1964 ata_link_abort(qc
->dev
->link
);
1970 static void mv_process_crpb_response(struct ata_port
*ap
,
1971 struct mv_crpb
*response
, unsigned int tag
, int ncq_enabled
)
1973 struct ata_queued_cmd
*qc
= ata_qc_from_tag(ap
, tag
);
1977 u16 edma_status
= le16_to_cpu(response
->flags
);
1979 * edma_status from a response queue entry:
1980 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1981 * MSB is saved ATA status from command completion.
1984 u8 err_cause
= edma_status
& 0xff & ~EDMA_ERR_DEV
;
1987 * Error will be seen/handled by mv_err_intr().
1988 * So do nothing at all here.
1993 ata_status
= edma_status
>> CRPB_FLAG_STATUS_SHIFT
;
1994 if (!ac_err_mask(ata_status
))
1995 ata_qc_complete(qc
);
1996 /* else: leave it for mv_err_intr() */
1998 ata_port_printk(ap
, KERN_ERR
, "%s: no qc for tag=%d\n",
2003 static void mv_process_crpb_entries(struct ata_port
*ap
, struct mv_port_priv
*pp
)
2005 void __iomem
*port_mmio
= mv_ap_base(ap
);
2006 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
2008 bool work_done
= false;
2009 int ncq_enabled
= (pp
->pp_flags
& MV_PP_FLAG_NCQ_EN
);
2011 /* Get the hardware queue position index */
2012 in_index
= (readl(port_mmio
+ EDMA_RSP_Q_IN_PTR_OFS
)
2013 >> EDMA_RSP_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
;
2015 /* Process new responses from since the last time we looked */
2016 while (in_index
!= pp
->resp_idx
) {
2018 struct mv_crpb
*response
= &pp
->crpb
[pp
->resp_idx
];
2020 pp
->resp_idx
= (pp
->resp_idx
+ 1) & MV_MAX_Q_DEPTH_MASK
;
2022 if (IS_GEN_I(hpriv
)) {
2023 /* 50xx: no NCQ, only one command active at a time */
2024 tag
= ap
->link
.active_tag
;
2026 /* Gen II/IIE: get command tag from CRPB entry */
2027 tag
= le16_to_cpu(response
->id
) & 0x1f;
2029 mv_process_crpb_response(ap
, response
, tag
, ncq_enabled
);
2033 /* Update the software queue position index in hardware */
2035 writelfl((pp
->crpb_dma
& EDMA_RSP_Q_BASE_LO_MASK
) |
2036 (pp
->resp_idx
<< EDMA_RSP_Q_PTR_SHIFT
),
2037 port_mmio
+ EDMA_RSP_Q_OUT_PTR_OFS
);
2040 static void mv_port_intr(struct ata_port
*ap
, u32 port_cause
)
2042 struct mv_port_priv
*pp
;
2043 int edma_was_enabled
;
2045 if (!ap
|| (ap
->flags
& ATA_FLAG_DISABLED
)) {
2046 mv_unexpected_intr(ap
, 0);
2050 * Grab a snapshot of the EDMA_EN flag setting,
2051 * so that we have a consistent view for this port,
2052 * even if something we call of our routines changes it.
2054 pp
= ap
->private_data
;
2055 edma_was_enabled
= (pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
);
2057 * Process completed CRPB response(s) before other events.
2059 if (edma_was_enabled
&& (port_cause
& DONE_IRQ
)) {
2060 mv_process_crpb_entries(ap
, pp
);
2061 if (pp
->pp_flags
& MV_PP_FLAG_DELAYED_EH
)
2062 mv_handle_fbs_ncq_dev_err(ap
);
2065 * Handle chip-reported errors, or continue on to handle PIO.
2067 if (unlikely(port_cause
& ERR_IRQ
)) {
2069 } else if (!edma_was_enabled
) {
2070 struct ata_queued_cmd
*qc
= mv_get_active_qc(ap
);
2072 ata_sff_host_intr(ap
, qc
);
2074 mv_unexpected_intr(ap
, edma_was_enabled
);
2079 * mv_host_intr - Handle all interrupts on the given host controller
2080 * @host: host specific structure
2081 * @main_irq_cause: Main interrupt cause register for the chip.
2084 * Inherited from caller.
2086 static int mv_host_intr(struct ata_host
*host
, u32 main_irq_cause
)
2088 struct mv_host_priv
*hpriv
= host
->private_data
;
2089 void __iomem
*mmio
= hpriv
->base
, *hc_mmio
;
2090 unsigned int handled
= 0, port
;
2092 for (port
= 0; port
< hpriv
->n_ports
; port
++) {
2093 struct ata_port
*ap
= host
->ports
[port
];
2094 unsigned int p
, shift
, hardport
, port_cause
;
2096 MV_PORT_TO_SHIFT_AND_HARDPORT(port
, shift
, hardport
);
2098 * Each hc within the host has its own hc_irq_cause register,
2099 * where the interrupting ports bits get ack'd.
2101 if (hardport
== 0) { /* first port on this hc ? */
2102 u32 hc_cause
= (main_irq_cause
>> shift
) & HC0_IRQ_PEND
;
2103 u32 port_mask
, ack_irqs
;
2105 * Skip this entire hc if nothing pending for any ports
2108 port
+= MV_PORTS_PER_HC
- 1;
2112 * We don't need/want to read the hc_irq_cause register,
2113 * because doing so hurts performance, and
2114 * main_irq_cause already gives us everything we need.
2116 * But we do have to *write* to the hc_irq_cause to ack
2117 * the ports that we are handling this time through.
2119 * This requires that we create a bitmap for those
2120 * ports which interrupted us, and use that bitmap
2121 * to ack (only) those ports via hc_irq_cause.
2124 for (p
= 0; p
< MV_PORTS_PER_HC
; ++p
) {
2125 if ((port
+ p
) >= hpriv
->n_ports
)
2127 port_mask
= (DONE_IRQ
| ERR_IRQ
) << (p
* 2);
2128 if (hc_cause
& port_mask
)
2129 ack_irqs
|= (DMA_IRQ
| DEV_IRQ
) << p
;
2131 hc_mmio
= mv_hc_base_from_port(mmio
, port
);
2132 writelfl(~ack_irqs
, hc_mmio
+ HC_IRQ_CAUSE_OFS
);
2136 * Handle interrupts signalled for this port:
2138 port_cause
= (main_irq_cause
>> shift
) & (DONE_IRQ
| ERR_IRQ
);
2140 mv_port_intr(ap
, port_cause
);
2145 static int mv_pci_error(struct ata_host
*host
, void __iomem
*mmio
)
2147 struct mv_host_priv
*hpriv
= host
->private_data
;
2148 struct ata_port
*ap
;
2149 struct ata_queued_cmd
*qc
;
2150 struct ata_eh_info
*ehi
;
2151 unsigned int i
, err_mask
, printed
= 0;
2154 err_cause
= readl(mmio
+ hpriv
->irq_cause_ofs
);
2156 dev_printk(KERN_ERR
, host
->dev
, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2159 DPRINTK("All regs @ PCI error\n");
2160 mv_dump_all_regs(mmio
, -1, to_pci_dev(host
->dev
));
2162 writelfl(0, mmio
+ hpriv
->irq_cause_ofs
);
2164 for (i
= 0; i
< host
->n_ports
; i
++) {
2165 ap
= host
->ports
[i
];
2166 if (!ata_link_offline(&ap
->link
)) {
2167 ehi
= &ap
->link
.eh_info
;
2168 ata_ehi_clear_desc(ehi
);
2170 ata_ehi_push_desc(ehi
,
2171 "PCI err cause 0x%08x", err_cause
);
2172 err_mask
= AC_ERR_HOST_BUS
;
2173 ehi
->action
= ATA_EH_RESET
;
2174 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
2176 qc
->err_mask
|= err_mask
;
2178 ehi
->err_mask
|= err_mask
;
2180 ata_port_freeze(ap
);
2183 return 1; /* handled */
2187 * mv_interrupt - Main interrupt event handler
2189 * @dev_instance: private data; in this case the host structure
2191 * Read the read only register to determine if any host
2192 * controllers have pending interrupts. If so, call lower level
2193 * routine to handle. Also check for PCI errors which are only
2197 * This routine holds the host lock while processing pending
2200 static irqreturn_t
mv_interrupt(int irq
, void *dev_instance
)
2202 struct ata_host
*host
= dev_instance
;
2203 struct mv_host_priv
*hpriv
= host
->private_data
;
2204 unsigned int handled
= 0;
2205 u32 main_irq_cause
, pending_irqs
;
2207 spin_lock(&host
->lock
);
2208 main_irq_cause
= readl(hpriv
->main_irq_cause_addr
);
2209 pending_irqs
= main_irq_cause
& hpriv
->main_irq_mask
;
2211 * Deal with cases where we either have nothing pending, or have read
2212 * a bogus register value which can indicate HW removal or PCI fault.
2214 if (pending_irqs
&& main_irq_cause
!= 0xffffffffU
) {
2215 if (unlikely((pending_irqs
& PCI_ERR
) && !IS_SOC(hpriv
)))
2216 handled
= mv_pci_error(host
, hpriv
->base
);
2218 handled
= mv_host_intr(host
, pending_irqs
);
2220 spin_unlock(&host
->lock
);
2221 return IRQ_RETVAL(handled
);
2224 static unsigned int mv5_scr_offset(unsigned int sc_reg_in
)
2228 switch (sc_reg_in
) {
2232 ofs
= sc_reg_in
* sizeof(u32
);
2241 static int mv5_scr_read(struct ata_port
*ap
, unsigned int sc_reg_in
, u32
*val
)
2243 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
2244 void __iomem
*mmio
= hpriv
->base
;
2245 void __iomem
*addr
= mv5_phy_base(mmio
, ap
->port_no
);
2246 unsigned int ofs
= mv5_scr_offset(sc_reg_in
);
2248 if (ofs
!= 0xffffffffU
) {
2249 *val
= readl(addr
+ ofs
);
2255 static int mv5_scr_write(struct ata_port
*ap
, unsigned int sc_reg_in
, u32 val
)
2257 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
2258 void __iomem
*mmio
= hpriv
->base
;
2259 void __iomem
*addr
= mv5_phy_base(mmio
, ap
->port_no
);
2260 unsigned int ofs
= mv5_scr_offset(sc_reg_in
);
2262 if (ofs
!= 0xffffffffU
) {
2263 writelfl(val
, addr
+ ofs
);
2269 static void mv5_reset_bus(struct ata_host
*host
, void __iomem
*mmio
)
2271 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
2274 early_5080
= (pdev
->device
== 0x5080) && (pdev
->revision
== 0);
2277 u32 tmp
= readl(mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
2279 writel(tmp
, mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
2282 mv_reset_pci_bus(host
, mmio
);
2285 static void mv5_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
2287 writel(0x0fcfffff, mmio
+ MV_FLASH_CTL_OFS
);
2290 static void mv5_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
2293 void __iomem
*phy_mmio
= mv5_phy_base(mmio
, idx
);
2296 tmp
= readl(phy_mmio
+ MV5_PHY_MODE
);
2298 hpriv
->signal
[idx
].pre
= tmp
& 0x1800; /* bits 12:11 */
2299 hpriv
->signal
[idx
].amps
= tmp
& 0xe0; /* bits 7:5 */
2302 static void mv5_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
2306 writel(0, mmio
+ MV_GPIO_PORT_CTL_OFS
);
2308 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2310 tmp
= readl(mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
2312 writel(tmp
, mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
2315 static void mv5_phy_errata(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
2318 void __iomem
*phy_mmio
= mv5_phy_base(mmio
, port
);
2319 const u32 mask
= (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2321 int fix_apm_sq
= (hpriv
->hp_flags
& MV_HP_ERRATA_50XXB0
);
2324 tmp
= readl(phy_mmio
+ MV5_LTMODE_OFS
);
2326 writel(tmp
, phy_mmio
+ MV5_LTMODE_OFS
);
2328 tmp
= readl(phy_mmio
+ MV5_PHY_CTL_OFS
);
2331 writel(tmp
, phy_mmio
+ MV5_PHY_CTL_OFS
);
2334 tmp
= readl(phy_mmio
+ MV5_PHY_MODE
);
2336 tmp
|= hpriv
->signal
[port
].pre
;
2337 tmp
|= hpriv
->signal
[port
].amps
;
2338 writel(tmp
, phy_mmio
+ MV5_PHY_MODE
);
2343 #define ZERO(reg) writel(0, port_mmio + (reg))
2344 static void mv5_reset_hc_port(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
2347 void __iomem
*port_mmio
= mv_port_base(mmio
, port
);
2349 mv_reset_channel(hpriv
, mmio
, port
);
2351 ZERO(0x028); /* command */
2352 writel(0x11f, port_mmio
+ EDMA_CFG_OFS
);
2353 ZERO(0x004); /* timer */
2354 ZERO(0x008); /* irq err cause */
2355 ZERO(0x00c); /* irq err mask */
2356 ZERO(0x010); /* rq bah */
2357 ZERO(0x014); /* rq inp */
2358 ZERO(0x018); /* rq outp */
2359 ZERO(0x01c); /* respq bah */
2360 ZERO(0x024); /* respq outp */
2361 ZERO(0x020); /* respq inp */
2362 ZERO(0x02c); /* test control */
2363 writel(0xbc, port_mmio
+ EDMA_IORDY_TMOUT_OFS
);
2367 #define ZERO(reg) writel(0, hc_mmio + (reg))
2368 static void mv5_reset_one_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
2371 void __iomem
*hc_mmio
= mv_hc_base(mmio
, hc
);
2379 tmp
= readl(hc_mmio
+ 0x20);
2382 writel(tmp
, hc_mmio
+ 0x20);
2386 static int mv5_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
2389 unsigned int hc
, port
;
2391 for (hc
= 0; hc
< n_hc
; hc
++) {
2392 for (port
= 0; port
< MV_PORTS_PER_HC
; port
++)
2393 mv5_reset_hc_port(hpriv
, mmio
,
2394 (hc
* MV_PORTS_PER_HC
) + port
);
2396 mv5_reset_one_hc(hpriv
, mmio
, hc
);
2403 #define ZERO(reg) writel(0, mmio + (reg))
2404 static void mv_reset_pci_bus(struct ata_host
*host
, void __iomem
*mmio
)
2406 struct mv_host_priv
*hpriv
= host
->private_data
;
2409 tmp
= readl(mmio
+ MV_PCI_MODE_OFS
);
2411 writel(tmp
, mmio
+ MV_PCI_MODE_OFS
);
2413 ZERO(MV_PCI_DISC_TIMER
);
2414 ZERO(MV_PCI_MSI_TRIGGER
);
2415 writel(0x000100ff, mmio
+ MV_PCI_XBAR_TMOUT_OFS
);
2416 ZERO(MV_PCI_SERR_MASK
);
2417 ZERO(hpriv
->irq_cause_ofs
);
2418 ZERO(hpriv
->irq_mask_ofs
);
2419 ZERO(MV_PCI_ERR_LOW_ADDRESS
);
2420 ZERO(MV_PCI_ERR_HIGH_ADDRESS
);
2421 ZERO(MV_PCI_ERR_ATTRIBUTE
);
2422 ZERO(MV_PCI_ERR_COMMAND
);
2426 static void mv6_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
2430 mv5_reset_flash(hpriv
, mmio
);
2432 tmp
= readl(mmio
+ MV_GPIO_PORT_CTL_OFS
);
2434 tmp
|= (1 << 5) | (1 << 6);
2435 writel(tmp
, mmio
+ MV_GPIO_PORT_CTL_OFS
);
2439 * mv6_reset_hc - Perform the 6xxx global soft reset
2440 * @mmio: base address of the HBA
2442 * This routine only applies to 6xxx parts.
2445 * Inherited from caller.
2447 static int mv6_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
2450 void __iomem
*reg
= mmio
+ PCI_MAIN_CMD_STS_OFS
;
2454 /* Following procedure defined in PCI "main command and status
2458 writel(t
| STOP_PCI_MASTER
, reg
);
2460 for (i
= 0; i
< 1000; i
++) {
2463 if (PCI_MASTER_EMPTY
& t
)
2466 if (!(PCI_MASTER_EMPTY
& t
)) {
2467 printk(KERN_ERR DRV_NAME
": PCI master won't flush\n");
2475 writel(t
| GLOB_SFT_RST
, reg
);
2478 } while (!(GLOB_SFT_RST
& t
) && (i
-- > 0));
2480 if (!(GLOB_SFT_RST
& t
)) {
2481 printk(KERN_ERR DRV_NAME
": can't set global reset\n");
2486 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2489 writel(t
& ~(GLOB_SFT_RST
| STOP_PCI_MASTER
), reg
);
2492 } while ((GLOB_SFT_RST
& t
) && (i
-- > 0));
2494 if (GLOB_SFT_RST
& t
) {
2495 printk(KERN_ERR DRV_NAME
": can't clear global reset\n");
2502 static void mv6_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
2505 void __iomem
*port_mmio
;
2508 tmp
= readl(mmio
+ MV_RESET_CFG_OFS
);
2509 if ((tmp
& (1 << 0)) == 0) {
2510 hpriv
->signal
[idx
].amps
= 0x7 << 8;
2511 hpriv
->signal
[idx
].pre
= 0x1 << 5;
2515 port_mmio
= mv_port_base(mmio
, idx
);
2516 tmp
= readl(port_mmio
+ PHY_MODE2
);
2518 hpriv
->signal
[idx
].amps
= tmp
& 0x700; /* bits 10:8 */
2519 hpriv
->signal
[idx
].pre
= tmp
& 0xe0; /* bits 7:5 */
2522 static void mv6_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
2524 writel(0x00000060, mmio
+ MV_GPIO_PORT_CTL_OFS
);
2527 static void mv6_phy_errata(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
2530 void __iomem
*port_mmio
= mv_port_base(mmio
, port
);
2532 u32 hp_flags
= hpriv
->hp_flags
;
2534 hp_flags
& (MV_HP_ERRATA_60X1B2
| MV_HP_ERRATA_60X1C0
);
2536 hp_flags
& (MV_HP_ERRATA_60X1B2
| MV_HP_ERRATA_60X1C0
);
2539 if (fix_phy_mode2
) {
2540 m2
= readl(port_mmio
+ PHY_MODE2
);
2543 writel(m2
, port_mmio
+ PHY_MODE2
);
2547 m2
= readl(port_mmio
+ PHY_MODE2
);
2548 m2
&= ~((1 << 16) | (1 << 31));
2549 writel(m2
, port_mmio
+ PHY_MODE2
);
2555 * Gen-II/IIe PHY_MODE3 errata RM#2:
2556 * Achieves better receiver noise performance than the h/w default:
2558 m3
= readl(port_mmio
+ PHY_MODE3
);
2559 m3
= (m3
& 0x1f) | (0x5555601 << 5);
2561 if (fix_phy_mode4
) {
2564 m4
= readl(port_mmio
+ PHY_MODE4
);
2566 /* workaround for errata FEr SATA#10 (part 1) */
2567 m4
= (m4
& ~(1 << 1)) | (1 << 0);
2569 /* enforce bit restrictions on GenIIe devices */
2570 if (IS_GEN_IIE(hpriv
))
2571 m4
= (m4
& ~0x5DE3FFFC) | (1 << 2);
2573 writel(m4
, port_mmio
+ PHY_MODE4
);
2576 * Workaround for 60x1-B2 errata SATA#13:
2577 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
2578 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
2580 writel(m3
, port_mmio
+ PHY_MODE3
);
2582 /* Revert values of pre-emphasis and signal amps to the saved ones */
2583 m2
= readl(port_mmio
+ PHY_MODE2
);
2585 m2
&= ~MV_M2_PREAMP_MASK
;
2586 m2
|= hpriv
->signal
[port
].amps
;
2587 m2
|= hpriv
->signal
[port
].pre
;
2590 /* according to mvSata 3.6.1, some IIE values are fixed */
2591 if (IS_GEN_IIE(hpriv
)) {
2596 writel(m2
, port_mmio
+ PHY_MODE2
);
2599 /* TODO: use the generic LED interface to configure the SATA Presence */
2600 /* & Acitivy LEDs on the board */
2601 static void mv_soc_enable_leds(struct mv_host_priv
*hpriv
,
2607 static void mv_soc_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
2610 void __iomem
*port_mmio
;
2613 port_mmio
= mv_port_base(mmio
, idx
);
2614 tmp
= readl(port_mmio
+ PHY_MODE2
);
2616 hpriv
->signal
[idx
].amps
= tmp
& 0x700; /* bits 10:8 */
2617 hpriv
->signal
[idx
].pre
= tmp
& 0xe0; /* bits 7:5 */
2621 #define ZERO(reg) writel(0, port_mmio + (reg))
2622 static void mv_soc_reset_hc_port(struct mv_host_priv
*hpriv
,
2623 void __iomem
*mmio
, unsigned int port
)
2625 void __iomem
*port_mmio
= mv_port_base(mmio
, port
);
2627 mv_reset_channel(hpriv
, mmio
, port
);
2629 ZERO(0x028); /* command */
2630 writel(0x101f, port_mmio
+ EDMA_CFG_OFS
);
2631 ZERO(0x004); /* timer */
2632 ZERO(0x008); /* irq err cause */
2633 ZERO(0x00c); /* irq err mask */
2634 ZERO(0x010); /* rq bah */
2635 ZERO(0x014); /* rq inp */
2636 ZERO(0x018); /* rq outp */
2637 ZERO(0x01c); /* respq bah */
2638 ZERO(0x024); /* respq outp */
2639 ZERO(0x020); /* respq inp */
2640 ZERO(0x02c); /* test control */
2641 writel(0xbc, port_mmio
+ EDMA_IORDY_TMOUT_OFS
);
2646 #define ZERO(reg) writel(0, hc_mmio + (reg))
2647 static void mv_soc_reset_one_hc(struct mv_host_priv
*hpriv
,
2650 void __iomem
*hc_mmio
= mv_hc_base(mmio
, 0);
2660 static int mv_soc_reset_hc(struct mv_host_priv
*hpriv
,
2661 void __iomem
*mmio
, unsigned int n_hc
)
2665 for (port
= 0; port
< hpriv
->n_ports
; port
++)
2666 mv_soc_reset_hc_port(hpriv
, mmio
, port
);
2668 mv_soc_reset_one_hc(hpriv
, mmio
);
2673 static void mv_soc_reset_flash(struct mv_host_priv
*hpriv
,
2679 static void mv_soc_reset_bus(struct ata_host
*host
, void __iomem
*mmio
)
2684 static void mv_setup_ifcfg(void __iomem
*port_mmio
, int want_gen2i
)
2686 u32 ifcfg
= readl(port_mmio
+ SATA_INTERFACE_CFG_OFS
);
2688 ifcfg
= (ifcfg
& 0xf7f) | 0x9b1000; /* from chip spec */
2690 ifcfg
|= (1 << 7); /* enable gen2i speed */
2691 writelfl(ifcfg
, port_mmio
+ SATA_INTERFACE_CFG_OFS
);
2694 static void mv_reset_channel(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
2695 unsigned int port_no
)
2697 void __iomem
*port_mmio
= mv_port_base(mmio
, port_no
);
2700 * The datasheet warns against setting EDMA_RESET when EDMA is active
2701 * (but doesn't say what the problem might be). So we first try
2702 * to disable the EDMA engine before doing the EDMA_RESET operation.
2704 mv_stop_edma_engine(port_mmio
);
2705 writelfl(EDMA_RESET
, port_mmio
+ EDMA_CMD_OFS
);
2707 if (!IS_GEN_I(hpriv
)) {
2708 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2709 mv_setup_ifcfg(port_mmio
, 1);
2712 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
2713 * link, and physical layers. It resets all SATA interface registers
2714 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
2716 writelfl(EDMA_RESET
, port_mmio
+ EDMA_CMD_OFS
);
2717 udelay(25); /* allow reset propagation */
2718 writelfl(0, port_mmio
+ EDMA_CMD_OFS
);
2720 hpriv
->ops
->phy_errata(hpriv
, mmio
, port_no
);
2722 if (IS_GEN_I(hpriv
))
2726 static void mv_pmp_select(struct ata_port
*ap
, int pmp
)
2728 if (sata_pmp_supported(ap
)) {
2729 void __iomem
*port_mmio
= mv_ap_base(ap
);
2730 u32 reg
= readl(port_mmio
+ SATA_IFCTL_OFS
);
2731 int old
= reg
& 0xf;
2734 reg
= (reg
& ~0xf) | pmp
;
2735 writelfl(reg
, port_mmio
+ SATA_IFCTL_OFS
);
2740 static int mv_pmp_hardreset(struct ata_link
*link
, unsigned int *class,
2741 unsigned long deadline
)
2743 mv_pmp_select(link
->ap
, sata_srst_pmp(link
));
2744 return sata_std_hardreset(link
, class, deadline
);
2747 static int mv_softreset(struct ata_link
*link
, unsigned int *class,
2748 unsigned long deadline
)
2750 mv_pmp_select(link
->ap
, sata_srst_pmp(link
));
2751 return ata_sff_softreset(link
, class, deadline
);
2754 static int mv_hardreset(struct ata_link
*link
, unsigned int *class,
2755 unsigned long deadline
)
2757 struct ata_port
*ap
= link
->ap
;
2758 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
2759 struct mv_port_priv
*pp
= ap
->private_data
;
2760 void __iomem
*mmio
= hpriv
->base
;
2761 int rc
, attempts
= 0, extra
= 0;
2765 mv_reset_channel(hpriv
, mmio
, ap
->port_no
);
2766 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
2768 /* Workaround for errata FEr SATA#10 (part 2) */
2770 const unsigned long *timing
=
2771 sata_ehc_deb_timing(&link
->eh_context
);
2773 rc
= sata_link_hardreset(link
, timing
, deadline
+ extra
,
2775 rc
= online
? -EAGAIN
: rc
;
2778 sata_scr_read(link
, SCR_STATUS
, &sstatus
);
2779 if (!IS_GEN_I(hpriv
) && ++attempts
>= 5 && sstatus
== 0x121) {
2780 /* Force 1.5gb/s link speed and try again */
2781 mv_setup_ifcfg(mv_ap_base(ap
), 0);
2782 if (time_after(jiffies
+ HZ
, deadline
))
2783 extra
= HZ
; /* only extend it once, max */
2785 } while (sstatus
!= 0x0 && sstatus
!= 0x113 && sstatus
!= 0x123);
2790 static void mv_eh_freeze(struct ata_port
*ap
)
2793 mv_enable_port_irqs(ap
, 0);
2796 static void mv_eh_thaw(struct ata_port
*ap
)
2798 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
2799 unsigned int port
= ap
->port_no
;
2800 unsigned int hardport
= mv_hardport_from_port(port
);
2801 void __iomem
*hc_mmio
= mv_hc_base_from_port(hpriv
->base
, port
);
2802 void __iomem
*port_mmio
= mv_ap_base(ap
);
2805 /* clear EDMA errors on this port */
2806 writel(0, port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
2808 /* clear pending irq events */
2809 hc_irq_cause
= readl(hc_mmio
+ HC_IRQ_CAUSE_OFS
);
2810 hc_irq_cause
&= ~((DEV_IRQ
| DMA_IRQ
) << hardport
);
2811 writelfl(hc_irq_cause
, hc_mmio
+ HC_IRQ_CAUSE_OFS
);
2813 mv_enable_port_irqs(ap
, ERR_IRQ
);
2817 * mv_port_init - Perform some early initialization on a single port.
2818 * @port: libata data structure storing shadow register addresses
2819 * @port_mmio: base address of the port
2821 * Initialize shadow register mmio addresses, clear outstanding
2822 * interrupts on the port, and unmask interrupts for the future
2823 * start of the port.
2826 * Inherited from caller.
2828 static void mv_port_init(struct ata_ioports
*port
, void __iomem
*port_mmio
)
2830 void __iomem
*shd_base
= port_mmio
+ SHD_BLK_OFS
;
2833 /* PIO related setup
2835 port
->data_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_DATA
);
2837 port
->feature_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_ERR
);
2838 port
->nsect_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_NSECT
);
2839 port
->lbal_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_LBAL
);
2840 port
->lbam_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_LBAM
);
2841 port
->lbah_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_LBAH
);
2842 port
->device_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_DEVICE
);
2844 port
->command_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_STATUS
);
2845 /* special case: control/altstatus doesn't have ATA_REG_ address */
2846 port
->altstatus_addr
= port
->ctl_addr
= shd_base
+ SHD_CTL_AST_OFS
;
2849 port
->cmd_addr
= port
->bmdma_addr
= port
->scr_addr
= NULL
;
2851 /* Clear any currently outstanding port interrupt conditions */
2852 serr_ofs
= mv_scr_offset(SCR_ERROR
);
2853 writelfl(readl(port_mmio
+ serr_ofs
), port_mmio
+ serr_ofs
);
2854 writelfl(0, port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
2856 /* unmask all non-transient EDMA error interrupts */
2857 writelfl(~EDMA_ERR_IRQ_TRANSIENT
, port_mmio
+ EDMA_ERR_IRQ_MASK_OFS
);
2859 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2860 readl(port_mmio
+ EDMA_CFG_OFS
),
2861 readl(port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
),
2862 readl(port_mmio
+ EDMA_ERR_IRQ_MASK_OFS
));
2865 static unsigned int mv_in_pcix_mode(struct ata_host
*host
)
2867 struct mv_host_priv
*hpriv
= host
->private_data
;
2868 void __iomem
*mmio
= hpriv
->base
;
2871 if (IS_SOC(hpriv
) || !IS_PCIE(hpriv
))
2872 return 0; /* not PCI-X capable */
2873 reg
= readl(mmio
+ MV_PCI_MODE_OFS
);
2874 if ((reg
& MV_PCI_MODE_MASK
) == 0)
2875 return 0; /* conventional PCI mode */
2876 return 1; /* chip is in PCI-X mode */
2879 static int mv_pci_cut_through_okay(struct ata_host
*host
)
2881 struct mv_host_priv
*hpriv
= host
->private_data
;
2882 void __iomem
*mmio
= hpriv
->base
;
2885 if (!mv_in_pcix_mode(host
)) {
2886 reg
= readl(mmio
+ PCI_COMMAND_OFS
);
2887 if (reg
& PCI_COMMAND_MRDTRIG
)
2888 return 0; /* not okay */
2890 return 1; /* okay */
2893 static int mv_chip_id(struct ata_host
*host
, unsigned int board_idx
)
2895 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
2896 struct mv_host_priv
*hpriv
= host
->private_data
;
2897 u32 hp_flags
= hpriv
->hp_flags
;
2899 switch (board_idx
) {
2901 hpriv
->ops
= &mv5xxx_ops
;
2902 hp_flags
|= MV_HP_GEN_I
;
2904 switch (pdev
->revision
) {
2906 hp_flags
|= MV_HP_ERRATA_50XXB0
;
2909 hp_flags
|= MV_HP_ERRATA_50XXB2
;
2912 dev_printk(KERN_WARNING
, &pdev
->dev
,
2913 "Applying 50XXB2 workarounds to unknown rev\n");
2914 hp_flags
|= MV_HP_ERRATA_50XXB2
;
2921 hpriv
->ops
= &mv5xxx_ops
;
2922 hp_flags
|= MV_HP_GEN_I
;
2924 switch (pdev
->revision
) {
2926 hp_flags
|= MV_HP_ERRATA_50XXB0
;
2929 hp_flags
|= MV_HP_ERRATA_50XXB2
;
2932 dev_printk(KERN_WARNING
, &pdev
->dev
,
2933 "Applying B2 workarounds to unknown rev\n");
2934 hp_flags
|= MV_HP_ERRATA_50XXB2
;
2941 hpriv
->ops
= &mv6xxx_ops
;
2942 hp_flags
|= MV_HP_GEN_II
;
2944 switch (pdev
->revision
) {
2946 hp_flags
|= MV_HP_ERRATA_60X1B2
;
2949 hp_flags
|= MV_HP_ERRATA_60X1C0
;
2952 dev_printk(KERN_WARNING
, &pdev
->dev
,
2953 "Applying B2 workarounds to unknown rev\n");
2954 hp_flags
|= MV_HP_ERRATA_60X1B2
;
2960 hp_flags
|= MV_HP_PCIE
| MV_HP_CUT_THROUGH
;
2961 if (pdev
->vendor
== PCI_VENDOR_ID_TTI
&&
2962 (pdev
->device
== 0x2300 || pdev
->device
== 0x2310))
2965 * Highpoint RocketRAID PCIe 23xx series cards:
2967 * Unconfigured drives are treated as "Legacy"
2968 * by the BIOS, and it overwrites sector 8 with
2969 * a "Lgcy" metadata block prior to Linux boot.
2971 * Configured drives (RAID or JBOD) leave sector 8
2972 * alone, but instead overwrite a high numbered
2973 * sector for the RAID metadata. This sector can
2974 * be determined exactly, by truncating the physical
2975 * drive capacity to a nice even GB value.
2977 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2979 * Warn the user, lest they think we're just buggy.
2981 printk(KERN_WARNING DRV_NAME
": Highpoint RocketRAID"
2982 " BIOS CORRUPTS DATA on all attached drives,"
2983 " regardless of if/how they are configured."
2985 printk(KERN_WARNING DRV_NAME
": For data safety, do not"
2986 " use sectors 8-9 on \"Legacy\" drives,"
2987 " and avoid the final two gigabytes on"
2988 " all RocketRAID BIOS initialized drives.\n");
2992 hpriv
->ops
= &mv6xxx_ops
;
2993 hp_flags
|= MV_HP_GEN_IIE
;
2994 if (board_idx
== chip_6042
&& mv_pci_cut_through_okay(host
))
2995 hp_flags
|= MV_HP_CUT_THROUGH
;
2997 switch (pdev
->revision
) {
2998 case 0x2: /* Rev.B0: the first/only public release */
2999 hp_flags
|= MV_HP_ERRATA_60X1C0
;
3002 dev_printk(KERN_WARNING
, &pdev
->dev
,
3003 "Applying 60X1C0 workarounds to unknown rev\n");
3004 hp_flags
|= MV_HP_ERRATA_60X1C0
;
3009 hpriv
->ops
= &mv_soc_ops
;
3010 hp_flags
|= MV_HP_FLAG_SOC
| MV_HP_ERRATA_60X1C0
;
3014 dev_printk(KERN_ERR
, host
->dev
,
3015 "BUG: invalid board index %u\n", board_idx
);
3019 hpriv
->hp_flags
= hp_flags
;
3020 if (hp_flags
& MV_HP_PCIE
) {
3021 hpriv
->irq_cause_ofs
= PCIE_IRQ_CAUSE_OFS
;
3022 hpriv
->irq_mask_ofs
= PCIE_IRQ_MASK_OFS
;
3023 hpriv
->unmask_all_irqs
= PCIE_UNMASK_ALL_IRQS
;
3025 hpriv
->irq_cause_ofs
= PCI_IRQ_CAUSE_OFS
;
3026 hpriv
->irq_mask_ofs
= PCI_IRQ_MASK_OFS
;
3027 hpriv
->unmask_all_irqs
= PCI_UNMASK_ALL_IRQS
;
3034 * mv_init_host - Perform some early initialization of the host.
3035 * @host: ATA host to initialize
3036 * @board_idx: controller index
3038 * If possible, do an early global reset of the host. Then do
3039 * our port init and clear/unmask all/relevant host interrupts.
3042 * Inherited from caller.
3044 static int mv_init_host(struct ata_host
*host
, unsigned int board_idx
)
3046 int rc
= 0, n_hc
, port
, hc
;
3047 struct mv_host_priv
*hpriv
= host
->private_data
;
3048 void __iomem
*mmio
= hpriv
->base
;
3050 rc
= mv_chip_id(host
, board_idx
);
3054 if (IS_SOC(hpriv
)) {
3055 hpriv
->main_irq_cause_addr
= mmio
+ SOC_HC_MAIN_IRQ_CAUSE_OFS
;
3056 hpriv
->main_irq_mask_addr
= mmio
+ SOC_HC_MAIN_IRQ_MASK_OFS
;
3058 hpriv
->main_irq_cause_addr
= mmio
+ PCI_HC_MAIN_IRQ_CAUSE_OFS
;
3059 hpriv
->main_irq_mask_addr
= mmio
+ PCI_HC_MAIN_IRQ_MASK_OFS
;
3062 /* global interrupt mask: 0 == mask everything */
3063 mv_set_main_irq_mask(host
, ~0, 0);
3065 n_hc
= mv_get_hc_count(host
->ports
[0]->flags
);
3067 for (port
= 0; port
< host
->n_ports
; port
++)
3068 hpriv
->ops
->read_preamp(hpriv
, port
, mmio
);
3070 rc
= hpriv
->ops
->reset_hc(hpriv
, mmio
, n_hc
);
3074 hpriv
->ops
->reset_flash(hpriv
, mmio
);
3075 hpriv
->ops
->reset_bus(host
, mmio
);
3076 hpriv
->ops
->enable_leds(hpriv
, mmio
);
3078 for (port
= 0; port
< host
->n_ports
; port
++) {
3079 struct ata_port
*ap
= host
->ports
[port
];
3080 void __iomem
*port_mmio
= mv_port_base(mmio
, port
);
3082 mv_port_init(&ap
->ioaddr
, port_mmio
);
3085 if (!IS_SOC(hpriv
)) {
3086 unsigned int offset
= port_mmio
- mmio
;
3087 ata_port_pbar_desc(ap
, MV_PRIMARY_BAR
, -1, "mmio");
3088 ata_port_pbar_desc(ap
, MV_PRIMARY_BAR
, offset
, "port");
3093 for (hc
= 0; hc
< n_hc
; hc
++) {
3094 void __iomem
*hc_mmio
= mv_hc_base(mmio
, hc
);
3096 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3097 "(before clear)=0x%08x\n", hc
,
3098 readl(hc_mmio
+ HC_CFG_OFS
),
3099 readl(hc_mmio
+ HC_IRQ_CAUSE_OFS
));
3101 /* Clear any currently outstanding hc interrupt conditions */
3102 writelfl(0, hc_mmio
+ HC_IRQ_CAUSE_OFS
);
3105 if (!IS_SOC(hpriv
)) {
3106 /* Clear any currently outstanding host interrupt conditions */
3107 writelfl(0, mmio
+ hpriv
->irq_cause_ofs
);
3109 /* and unmask interrupt generation for host regs */
3110 writelfl(hpriv
->unmask_all_irqs
, mmio
+ hpriv
->irq_mask_ofs
);
3113 * enable only global host interrupts for now.
3114 * The per-port interrupts get done later as ports are set up.
3116 mv_set_main_irq_mask(host
, 0, PCI_ERR
);
3122 static int mv_create_dma_pools(struct mv_host_priv
*hpriv
, struct device
*dev
)
3124 hpriv
->crqb_pool
= dmam_pool_create("crqb_q", dev
, MV_CRQB_Q_SZ
,
3126 if (!hpriv
->crqb_pool
)
3129 hpriv
->crpb_pool
= dmam_pool_create("crpb_q", dev
, MV_CRPB_Q_SZ
,
3131 if (!hpriv
->crpb_pool
)
3134 hpriv
->sg_tbl_pool
= dmam_pool_create("sg_tbl", dev
, MV_SG_TBL_SZ
,
3136 if (!hpriv
->sg_tbl_pool
)
3142 static void mv_conf_mbus_windows(struct mv_host_priv
*hpriv
,
3143 struct mbus_dram_target_info
*dram
)
3147 for (i
= 0; i
< 4; i
++) {
3148 writel(0, hpriv
->base
+ WINDOW_CTRL(i
));
3149 writel(0, hpriv
->base
+ WINDOW_BASE(i
));
3152 for (i
= 0; i
< dram
->num_cs
; i
++) {
3153 struct mbus_dram_window
*cs
= dram
->cs
+ i
;
3155 writel(((cs
->size
- 1) & 0xffff0000) |
3156 (cs
->mbus_attr
<< 8) |
3157 (dram
->mbus_dram_target_id
<< 4) | 1,
3158 hpriv
->base
+ WINDOW_CTRL(i
));
3159 writel(cs
->base
, hpriv
->base
+ WINDOW_BASE(i
));
3164 * mv_platform_probe - handle a positive probe of an soc Marvell
3166 * @pdev: platform device found
3169 * Inherited from caller.
3171 static int mv_platform_probe(struct platform_device
*pdev
)
3173 static int printed_version
;
3174 const struct mv_sata_platform_data
*mv_platform_data
;
3175 const struct ata_port_info
*ppi
[] =
3176 { &mv_port_info
[chip_soc
], NULL
};
3177 struct ata_host
*host
;
3178 struct mv_host_priv
*hpriv
;
3179 struct resource
*res
;
3182 if (!printed_version
++)
3183 dev_printk(KERN_INFO
, &pdev
->dev
, "version " DRV_VERSION
"\n");
3186 * Simple resource validation ..
3188 if (unlikely(pdev
->num_resources
!= 2)) {
3189 dev_err(&pdev
->dev
, "invalid number of resources\n");
3194 * Get the register base first
3196 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3201 mv_platform_data
= pdev
->dev
.platform_data
;
3202 n_ports
= mv_platform_data
->n_ports
;
3204 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, n_ports
);
3205 hpriv
= devm_kzalloc(&pdev
->dev
, sizeof(*hpriv
), GFP_KERNEL
);
3207 if (!host
|| !hpriv
)
3209 host
->private_data
= hpriv
;
3210 hpriv
->n_ports
= n_ports
;
3213 hpriv
->base
= devm_ioremap(&pdev
->dev
, res
->start
,
3214 res
->end
- res
->start
+ 1);
3215 hpriv
->base
-= MV_SATAHC0_REG_BASE
;
3218 * (Re-)program MBUS remapping windows if we are asked to.
3220 if (mv_platform_data
->dram
!= NULL
)
3221 mv_conf_mbus_windows(hpriv
, mv_platform_data
->dram
);
3223 rc
= mv_create_dma_pools(hpriv
, &pdev
->dev
);
3227 /* initialize adapter */
3228 rc
= mv_init_host(host
, chip_soc
);
3232 dev_printk(KERN_INFO
, &pdev
->dev
,
3233 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH
,
3236 return ata_host_activate(host
, platform_get_irq(pdev
, 0), mv_interrupt
,
3237 IRQF_SHARED
, &mv6_sht
);
3242 * mv_platform_remove - unplug a platform interface
3243 * @pdev: platform device
3245 * A platform bus SATA device has been unplugged. Perform the needed
3246 * cleanup. Also called on module unload for any active devices.
3248 static int __devexit
mv_platform_remove(struct platform_device
*pdev
)
3250 struct device
*dev
= &pdev
->dev
;
3251 struct ata_host
*host
= dev_get_drvdata(dev
);
3253 ata_host_detach(host
);
3257 static struct platform_driver mv_platform_driver
= {
3258 .probe
= mv_platform_probe
,
3259 .remove
= __devexit_p(mv_platform_remove
),
3262 .owner
= THIS_MODULE
,
3268 static int mv_pci_init_one(struct pci_dev
*pdev
,
3269 const struct pci_device_id
*ent
);
3272 static struct pci_driver mv_pci_driver
= {
3274 .id_table
= mv_pci_tbl
,
3275 .probe
= mv_pci_init_one
,
3276 .remove
= ata_pci_remove_one
,
3282 static int msi
; /* Use PCI msi; either zero (off, default) or non-zero */
3285 /* move to PCI layer or libata core? */
3286 static int pci_go_64(struct pci_dev
*pdev
)
3290 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
3291 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3293 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
3295 dev_printk(KERN_ERR
, &pdev
->dev
,
3296 "64-bit DMA enable failed\n");
3301 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3303 dev_printk(KERN_ERR
, &pdev
->dev
,
3304 "32-bit DMA enable failed\n");
3307 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
3309 dev_printk(KERN_ERR
, &pdev
->dev
,
3310 "32-bit consistent DMA enable failed\n");
3319 * mv_print_info - Dump key info to kernel log for perusal.
3320 * @host: ATA host to print info about
3322 * FIXME: complete this.
3325 * Inherited from caller.
3327 static void mv_print_info(struct ata_host
*host
)
3329 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
3330 struct mv_host_priv
*hpriv
= host
->private_data
;
3332 const char *scc_s
, *gen
;
3334 /* Use this to determine the HW stepping of the chip so we know
3335 * what errata to workaround
3337 pci_read_config_byte(pdev
, PCI_CLASS_DEVICE
, &scc
);
3340 else if (scc
== 0x01)
3345 if (IS_GEN_I(hpriv
))
3347 else if (IS_GEN_II(hpriv
))
3349 else if (IS_GEN_IIE(hpriv
))
3354 dev_printk(KERN_INFO
, &pdev
->dev
,
3355 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3356 gen
, (unsigned)MV_MAX_Q_DEPTH
, host
->n_ports
,
3357 scc_s
, (MV_HP_FLAG_MSI
& hpriv
->hp_flags
) ? "MSI" : "INTx");
3361 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
3362 * @pdev: PCI device found
3363 * @ent: PCI device ID entry for the matched host
3366 * Inherited from caller.
3368 static int mv_pci_init_one(struct pci_dev
*pdev
,
3369 const struct pci_device_id
*ent
)
3371 static int printed_version
;
3372 unsigned int board_idx
= (unsigned int)ent
->driver_data
;
3373 const struct ata_port_info
*ppi
[] = { &mv_port_info
[board_idx
], NULL
};
3374 struct ata_host
*host
;
3375 struct mv_host_priv
*hpriv
;
3378 if (!printed_version
++)
3379 dev_printk(KERN_INFO
, &pdev
->dev
, "version " DRV_VERSION
"\n");
3382 n_ports
= mv_get_hc_count(ppi
[0]->flags
) * MV_PORTS_PER_HC
;
3384 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, n_ports
);
3385 hpriv
= devm_kzalloc(&pdev
->dev
, sizeof(*hpriv
), GFP_KERNEL
);
3386 if (!host
|| !hpriv
)
3388 host
->private_data
= hpriv
;
3389 hpriv
->n_ports
= n_ports
;
3391 /* acquire resources */
3392 rc
= pcim_enable_device(pdev
);
3396 rc
= pcim_iomap_regions(pdev
, 1 << MV_PRIMARY_BAR
, DRV_NAME
);
3398 pcim_pin_device(pdev
);
3401 host
->iomap
= pcim_iomap_table(pdev
);
3402 hpriv
->base
= host
->iomap
[MV_PRIMARY_BAR
];
3404 rc
= pci_go_64(pdev
);
3408 rc
= mv_create_dma_pools(hpriv
, &pdev
->dev
);
3412 /* initialize adapter */
3413 rc
= mv_init_host(host
, board_idx
);
3417 /* Enable interrupts */
3418 if (msi
&& pci_enable_msi(pdev
))
3421 mv_dump_pci_cfg(pdev
, 0x68);
3422 mv_print_info(host
);
3424 pci_set_master(pdev
);
3425 pci_try_set_mwi(pdev
);
3426 return ata_host_activate(host
, pdev
->irq
, mv_interrupt
, IRQF_SHARED
,
3427 IS_GEN_I(hpriv
) ? &mv5_sht
: &mv6_sht
);
3431 static int mv_platform_probe(struct platform_device
*pdev
);
3432 static int __devexit
mv_platform_remove(struct platform_device
*pdev
);
3434 static int __init
mv_init(void)
3438 rc
= pci_register_driver(&mv_pci_driver
);
3442 rc
= platform_driver_register(&mv_platform_driver
);
3446 pci_unregister_driver(&mv_pci_driver
);
3451 static void __exit
mv_exit(void)
3454 pci_unregister_driver(&mv_pci_driver
);
3456 platform_driver_unregister(&mv_platform_driver
);
3459 MODULE_AUTHOR("Brett Russ");
3460 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3461 MODULE_LICENSE("GPL");
3462 MODULE_DEVICE_TABLE(pci
, mv_pci_tbl
);
3463 MODULE_VERSION(DRV_VERSION
);
3464 MODULE_ALIAS("platform:" DRV_NAME
);
3467 module_param(msi
, int, 0444);
3468 MODULE_PARM_DESC(msi
, "Enable use of PCI MSI (0=off, 1=on)");
3471 module_init(mv_init
);
3472 module_exit(mv_exit
);