include/asm-ia64/bitops.h

   1 #ifndef _ASM_IA64_BITOPS_H
   2 #define _ASM_IA64_BITOPS_H
   3
   4 /*
   5  * Copyright (C) 1998-2003 Hewlett-Packard Co
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  *
   8  * 02/06/02 find_next_bit() and find_first_bit() added from Erich Focht's ia64
   9  * O(1) scheduler patch
  10  */
  11
  12 #ifndef _LINUX_BITOPS_H
  13 #error only <linux/bitops.h> can be included directly
  14 #endif
  15
  16 #include <linux/compiler.h>
  17 #include <linux/types.h>
  18 #include <asm/intrinsics.h>
  19
  20 /**
  21  * set_bit - Atomically set a bit in memory
  22  * @nr: the bit to set
  23  * @addr: the address to start counting from
  24  *
  25  * This function is atomic and may not be reordered.  See __set_bit()
  26  * if you do not require the atomic guarantees.
  27  * Note that @nr may be almost arbitrarily large; this function is not
  28  * restricted to acting on a single-word quantity.
  29  *
  30  * The address must be (at least) "long" aligned.
  31  * Note that there are driver (e.g., eepro100) which use these operations to
  32  * operate on hw-defined data-structures, so we can't easily change these
  33  * operations to force a bigger alignment.
  34  *
  35  * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
  36  */
  37 static __inline__ void
  38 set_bit (int nr, volatile void *addr)
  39 {
  40         __u32 bit, old, new;
  41         volatile __u32 *m;
  42         CMPXCHG_BUGCHECK_DECL
  43
  44         m = (volatile __u32 *) addr + (nr >> 5);
  45         bit = 1 << (nr & 31);
  46         do {
  47                 CMPXCHG_BUGCHECK(m);
  48                 old = *m;
  49                 new = old | bit;
  50         } while (cmpxchg_acq(m, old, new) != old);
  51 }
  52
  53 /**
  54  * __set_bit - Set a bit in memory
  55  * @nr: the bit to set
  56  * @addr: the address to start counting from
  57  *
  58  * Unlike set_bit(), this function is non-atomic and may be reordered.
  59  * If it's called on the same region of memory simultaneously, the effect
  60  * may be that only one operation succeeds.
  61  */
  62 static __inline__ void
  63 __set_bit (int nr, volatile void *addr)
  64 {
  65         *((__u32 *) addr + (nr >> 5)) |= (1 << (nr & 31));
  66 }
  67
  68 /*
  69  * clear_bit() has "acquire" semantics.
  70  */
  71 #define smp_mb__before_clear_bit()      smp_mb()
  72 #define smp_mb__after_clear_bit()       do { /* skip */; } while (0)
  73
  74 /**
  75  * clear_bit - Clears a bit in memory
  76  * @nr: Bit to clear
  77  * @addr: Address to start counting from
  78  *
  79  * clear_bit() is atomic and may not be reordered.  However, it does
  80  * not contain a memory barrier, so if it is used for locking purposes,
  81  * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
  82  * in order to ensure changes are visible on other processors.
  83  */
  84 static __inline__ void
  85 clear_bit (int nr, volatile void *addr)
  86 {
  87         __u32 mask, old, new;
  88         volatile __u32 *m;
  89         CMPXCHG_BUGCHECK_DECL
  90
  91         m = (volatile __u32 *) addr + (nr >> 5);
  92         mask = ~(1 << (nr & 31));
  93         do {
  94                 CMPXCHG_BUGCHECK(m);
  95                 old = *m;
  96                 new = old & mask;
  97         } while (cmpxchg_acq(m, old, new) != old);
  98 }
  99
 100 /**
 101  * clear_bit_unlock - Clears a bit in memory with release
 102  * @nr: Bit to clear
 103  * @addr: Address to start counting from
 104  *
 105  * clear_bit_unlock() is atomic and may not be reordered.  It does
 106  * contain a memory barrier suitable for unlock type operations.
 107  */
 108 static __inline__ void
 109 clear_bit_unlock (int nr, volatile void *addr)
 110 {
 111         __u32 mask, old, new;
 112         volatile __u32 *m;
 113         CMPXCHG_BUGCHECK_DECL
 114
 115         m = (volatile __u32 *) addr + (nr >> 5);
 116         mask = ~(1 << (nr & 31));
 117         do {
 118                 CMPXCHG_BUGCHECK(m);
 119                 old = *m;
 120                 new = old & mask;
 121         } while (cmpxchg_rel(m, old, new) != old);
 122 }
 123
 124 /**
 125  * __clear_bit_unlock - Non-atomically clear a bit with release
 126  *
 127  * This is like clear_bit_unlock, but the implementation may use a non-atomic
 128  * store (this one uses an atomic, however).
 129  */
 130 #define __clear_bit_unlock clear_bit_unlock
 131
 132 /**
 133  * __clear_bit - Clears a bit in memory (non-atomic version)
 134  */
 135 static __inline__ void
 136 __clear_bit (int nr, volatile void *addr)
 137 {
 138         volatile __u32 *p = (__u32 *) addr + (nr >> 5);
 139         __u32 m = 1 << (nr & 31);
 140         *p &= ~m;
 141 }
 142
 143 /**
 144  * change_bit - Toggle a bit in memory
 145  * @nr: Bit to clear
 146  * @addr: Address to start counting from
 147  *
 148  * change_bit() is atomic and may not be reordered.
 149  * Note that @nr may be almost arbitrarily large; this function is not
 150  * restricted to acting on a single-word quantity.
 151  */
 152 static __inline__ void
 153 change_bit (int nr, volatile void *addr)
 154 {
 155         __u32 bit, old, new;
 156         volatile __u32 *m;
 157         CMPXCHG_BUGCHECK_DECL
 158
 159         m = (volatile __u32 *) addr + (nr >> 5);
 160         bit = (1 << (nr & 31));
 161         do {
 162                 CMPXCHG_BUGCHECK(m);
 163                 old = *m;
 164                 new = old ^ bit;
 165         } while (cmpxchg_acq(m, old, new) != old);
 166 }
 167
 168 /**
 169  * __change_bit - Toggle a bit in memory
 170  * @nr: the bit to set
 171  * @addr: the address to start counting from
 172  *
 173  * Unlike change_bit(), this function is non-atomic and may be reordered.
 174  * If it's called on the same region of memory simultaneously, the effect
 175  * may be that only one operation succeeds.
 176  */
 177 static __inline__ void
 178 __change_bit (int nr, volatile void *addr)
 179 {
 180         *((__u32 *) addr + (nr >> 5)) ^= (1 << (nr & 31));
 181 }
 182
 183 /**
 184  * test_and_set_bit - Set a bit and return its old value
 185  * @nr: Bit to set
 186  * @addr: Address to count from
 187  *
 188  * This operation is atomic and cannot be reordered.
 189  * It also implies a memory barrier.
 190  */
 191 static __inline__ int
 192 test_and_set_bit (int nr, volatile void *addr)
 193 {
 194         __u32 bit, old, new;
 195         volatile __u32 *m;
 196         CMPXCHG_BUGCHECK_DECL
 197
 198         m = (volatile __u32 *) addr + (nr >> 5);
 199         bit = 1 << (nr & 31);
 200         do {
 201                 CMPXCHG_BUGCHECK(m);
 202                 old = *m;
 203                 new = old | bit;
 204         } while (cmpxchg_acq(m, old, new) != old);
 205         return (old & bit) != 0;
 206 }
 207
 208 /**
 209  * test_and_set_bit_lock - Set a bit and return its old value for lock
 210  * @nr: Bit to set
 211  * @addr: Address to count from
 212  *
 213  * This is the same as test_and_set_bit on ia64
 214  */
 215 #define test_and_set_bit_lock test_and_set_bit
 216
 217 /**
 218  * __test_and_set_bit - Set a bit and return its old value
 219  * @nr: Bit to set
 220  * @addr: Address to count from
 221  *
 222  * This operation is non-atomic and can be reordered.
 223  * If two examples of this operation race, one can appear to succeed
 224  * but actually fail.  You must protect multiple accesses with a lock.
 225  */
 226 static __inline__ int
 227 __test_and_set_bit (int nr, volatile void *addr)
 228 {
 229         __u32 *p = (__u32 *) addr + (nr >> 5);
 230         __u32 m = 1 << (nr & 31);
 231         int oldbitset = (*p & m) != 0;
 232
 233         *p |= m;
 234         return oldbitset;
 235 }
 236
 237 /**
 238  * test_and_clear_bit - Clear a bit and return its old value
 239  * @nr: Bit to set
 240  * @addr: Address to count from
 241  *
 242  * This operation is atomic and cannot be reordered.
 243  * It also implies a memory barrier.
 244  */
 245 static __inline__ int
 246 test_and_clear_bit (int nr, volatile void *addr)
 247 {
 248         __u32 mask, old, new;
 249         volatile __u32 *m;
 250         CMPXCHG_BUGCHECK_DECL
 251
 252         m = (volatile __u32 *) addr + (nr >> 5);
 253         mask = ~(1 << (nr & 31));
 254         do {
 255                 CMPXCHG_BUGCHECK(m);
 256                 old = *m;
 257                 new = old & mask;
 258         } while (cmpxchg_acq(m, old, new) != old);
 259         return (old & ~mask) != 0;
 260 }
 261
 262 /**
 263  * __test_and_clear_bit - Clear a bit and return its old value
 264  * @nr: Bit to set
 265  * @addr: Address to count from
 266  *
 267  * This operation is non-atomic and can be reordered.
 268  * If two examples of this operation race, one can appear to succeed
 269  * but actually fail.  You must protect multiple accesses with a lock.
 270  */
 271 static __inline__ int
 272 __test_and_clear_bit(int nr, volatile void * addr)
 273 {
 274         __u32 *p = (__u32 *) addr + (nr >> 5);
 275         __u32 m = 1 << (nr & 31);
 276         int oldbitset = *p & m;
 277
 278         *p &= ~m;
 279         return oldbitset;
 280 }
 281
 282 /**
 283  * test_and_change_bit - Change a bit and return its old value
 284  * @nr: Bit to set
 285  * @addr: Address to count from
 286  *
 287  * This operation is atomic and cannot be reordered.
 288  * It also implies a memory barrier.
 289  */
 290 static __inline__ int
 291 test_and_change_bit (int nr, volatile void *addr)
 292 {
 293         __u32 bit, old, new;
 294         volatile __u32 *m;
 295         CMPXCHG_BUGCHECK_DECL
 296
 297         m = (volatile __u32 *) addr + (nr >> 5);
 298         bit = (1 << (nr & 31));
 299         do {
 300                 CMPXCHG_BUGCHECK(m);
 301                 old = *m;
 302                 new = old ^ bit;
 303         } while (cmpxchg_acq(m, old, new) != old);
 304         return (old & bit) != 0;
 305 }
 306
 307 /*
 308  * WARNING: non atomic version.
 309  */
 310 static __inline__ int
 311 __test_and_change_bit (int nr, void *addr)
 312 {
 313         __u32 old, bit = (1 << (nr & 31));
 314         __u32 *m = (__u32 *) addr + (nr >> 5);
 315
 316         old = *m;
 317         *m = old ^ bit;
 318         return (old & bit) != 0;
 319 }
 320
 321 static __inline__ int
 322 test_bit (int nr, const volatile void *addr)
 323 {
 324         return 1 & (((const volatile __u32 *) addr)[nr >> 5] >> (nr & 31));
 325 }
 326
 327 /**
 328  * ffz - find the first zero bit in a long word
 329  * @x: The long word to find the bit in
 330  *
 331  * Returns the bit-number (0..63) of the first (least significant) zero bit.
 332  * Undefined if no zero exists, so code should check against ~0UL first...
 333  */
 334 static inline unsigned long
 335 ffz (unsigned long x)
 336 {
 337         unsigned long result;
 338
 339         result = ia64_popcnt(x & (~x - 1));
 340         return result;
 341 }
 342
 343 /**
 344  * __ffs - find first bit in word.
 345  * @x: The word to search
 346  *
 347  * Undefined if no bit exists, so code should check against 0 first.
 348  */
 349 static __inline__ unsigned long
 350 __ffs (unsigned long x)
 351 {
 352         unsigned long result;
 353
 354         result = ia64_popcnt((x-1) & ~x);
 355         return result;
 356 }
 357
 358 #ifdef __KERNEL__
 359
 360 /*
 361  * Return bit number of last (most-significant) bit set.  Undefined
 362  * for x==0.  Bits are numbered from 0..63 (e.g., ia64_fls(9) == 3).
 363  */
 364 static inline unsigned long
 365 ia64_fls (unsigned long x)
 366 {
 367         long double d = x;
 368         long exp;
 369
 370         exp = ia64_getf_exp(d);
 371         return exp - 0xffff;
 372 }
 373
 374 /*
 375  * Find the last (most significant) bit set.  Returns 0 for x==0 and
 376  * bits are numbered from 1..32 (e.g., fls(9) == 4).
 377  */
 378 static inline int
 379 fls (int t)
 380 {
 381         unsigned long x = t & 0xffffffffu;
 382
 383         if (!x)
 384                 return 0;
 385         x |= x >> 1;
 386         x |= x >> 2;
 387         x |= x >> 4;
 388         x |= x >> 8;
 389         x |= x >> 16;
 390         return ia64_popcnt(x);
 391 }
 392
 393 #include <asm-generic/bitops/fls64.h>
 394
 395 /*
 396  * ffs: find first bit set. This is defined the same way as the libc and
 397  * compiler builtin ffs routines, therefore differs in spirit from the above
 398  * ffz (man ffs): it operates on "int" values only and the result value is the
 399  * bit number + 1.  ffs(0) is defined to return zero.
 400  */
 401 #define ffs(x)  __builtin_ffs(x)
 402
 403 /*
 404  * hweightN: returns the hamming weight (i.e. the number
 405  * of bits set) of a N-bit word
 406  */
 407 static __inline__ unsigned long
 408 hweight64 (unsigned long x)
 409 {
 410         unsigned long result;
 411         result = ia64_popcnt(x);
 412         return result;
 413 }
 414
 415 #define hweight32(x)    (unsigned int) hweight64((x) & 0xfffffffful)
 416 #define hweight16(x)    (unsigned int) hweight64((x) & 0xfffful)
 417 #define hweight8(x)     (unsigned int) hweight64((x) & 0xfful)
 418
 419 #endif /* __KERNEL__ */
 420
 421 #include <asm-generic/bitops/find.h>
 422
 423 #ifdef __KERNEL__
 424
 425 #include <asm-generic/bitops/ext2-non-atomic.h>
 426
 427 #define ext2_set_bit_atomic(l,n,a)      test_and_set_bit(n,a)
 428 #define ext2_clear_bit_atomic(l,n,a)    test_and_clear_bit(n,a)
 429
 430 #include <asm-generic/bitops/minix.h>
 431 #include <asm-generic/bitops/sched.h>
 432
 433 #endif /* __KERNEL__ */
 434
 435 #endif /* _ASM_IA64_BITOPS_H */