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Merge branch 'linus' into release
[linux-2.6/mini2440.git] / drivers / usb / musb / musb_host.c
blob99fa612348769a1134228bfd09a85ad69250285d
1 /*
2 * MUSB OTG driver host support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 #include <linux/module.h>
36 #include <linux/kernel.h>
37 #include <linux/delay.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/errno.h>
41 #include <linux/init.h>
42 #include <linux/list.h>
43
44 #include "musb_core.h"
45 #include "musb_host.h"
46
47
48 /* MUSB HOST status 22-mar-2006
49 *
50 * - There's still lots of partial code duplication for fault paths, so
51 * they aren't handled as consistently as they need to be.
52 *
53 * - PIO mostly behaved when last tested.
54 * + including ep0, with all usbtest cases 9, 10
55 * + usbtest 14 (ep0out) doesn't seem to run at all
56 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
57 * configurations, but otherwise double buffering passes basic tests.
58 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
59 *
60 * - DMA (CPPI) ... partially behaves, not currently recommended
61 * + about 1/15 the speed of typical EHCI implementations (PCI)
62 * + RX, all too often reqpkt seems to misbehave after tx
63 * + TX, no known issues (other than evident silicon issue)
64 *
65 * - DMA (Mentor/OMAP) ...has at least toggle update problems
66 *
67 * - Still no traffic scheduling code to make NAKing for bulk or control
68 * transfers unable to starve other requests; or to make efficient use
69 * of hardware with periodic transfers. (Note that network drivers
70 * commonly post bulk reads that stay pending for a long time; these
71 * would make very visible trouble.)
72 *
73 * - Not tested with HNP, but some SRP paths seem to behave.
74 *
75 * NOTE 24-August-2006:
76 *
77 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
78 * extra endpoint for periodic use enabling hub + keybd + mouse. That
79 * mostly works, except that with "usbnet" it's easy to trigger cases
80 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
81 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
82 * although ARP RX wins. (That test was done with a full speed link.)
83 */
84
85
86 /*
87 * NOTE on endpoint usage:
88 *
89 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
90 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
91 *
92 * (Yes, bulk _could_ use more of the endpoints than that, and would even
93 * benefit from it ... one remote device may easily be NAKing while others
94 * need to perform transfers in that same direction. The same thing could
95 * be done in software though, assuming dma cooperates.)
96 *
97 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
98 * So far that scheduling is both dumb and optimistic: the endpoint will be
99 * "claimed" until its software queue is no longer refilled. No multiplexing
100 * of transfers between endpoints, or anything clever.
101 */
102
103
104 static void musb_ep_program(struct musb *musb, u8 epnum,
105 struct urb *urb, unsigned int nOut,
106 u8 *buf, u32 len);
107
108 /*
109 * Clear TX fifo. Needed to avoid BABBLE errors.
110 */
111 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
112 {
113 void __iomem *epio = ep->regs;
114 u16 csr;
115 u16 lastcsr = 0;
116 int retries = 1000;
117
118 csr = musb_readw(epio, MUSB_TXCSR);
119 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
120 if (csr != lastcsr)
121 DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
122 lastcsr = csr;
123 csr |= MUSB_TXCSR_FLUSHFIFO;
124 musb_writew(epio, MUSB_TXCSR, csr);
125 csr = musb_readw(epio, MUSB_TXCSR);
126 if (WARN(retries-- < 1,
127 "Could not flush host TX%d fifo: csr: %04x\n",
128 ep->epnum, csr))
129 return;
130 mdelay(1);
131 }
132 }
133
134 /*
135 * Start transmit. Caller is responsible for locking shared resources.
136 * musb must be locked.
137 */
138 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
139 {
140 u16 txcsr;
141
142 /* NOTE: no locks here; caller should lock and select EP */
143 if (ep->epnum) {
144 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
145 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
146 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
147 } else {
148 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
149 musb_writew(ep->regs, MUSB_CSR0, txcsr);
150 }
151
152 }
153
154 static inline void cppi_host_txdma_start(struct musb_hw_ep *ep)
155 {
156 u16 txcsr;
157
158 /* NOTE: no locks here; caller should lock and select EP */
159 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
160 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
161 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
162 }
163
164 /*
165 * Start the URB at the front of an endpoint's queue
166 * end must be claimed from the caller.
167 *
168 * Context: controller locked, irqs blocked
169 */
170 static void
171 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
172 {
173 u16 frame;
174 u32 len;
175 void *buf;
176 void __iomem *mbase = musb->mregs;
177 struct urb *urb = next_urb(qh);
178 struct musb_hw_ep *hw_ep = qh->hw_ep;
179 unsigned pipe = urb->pipe;
180 u8 address = usb_pipedevice(pipe);
181 int epnum = hw_ep->epnum;
182
183 /* initialize software qh state */
184 qh->offset = 0;
185 qh->segsize = 0;
186
187 /* gather right source of data */
188 switch (qh->type) {
189 case USB_ENDPOINT_XFER_CONTROL:
190 /* control transfers always start with SETUP */
191 is_in = 0;
192 hw_ep->out_qh = qh;
193 musb->ep0_stage = MUSB_EP0_START;
194 buf = urb->setup_packet;
195 len = 8;
196 break;
197 case USB_ENDPOINT_XFER_ISOC:
198 qh->iso_idx = 0;
199 qh->frame = 0;
200 buf = urb->transfer_buffer + urb->iso_frame_desc[0].offset;
201 len = urb->iso_frame_desc[0].length;
202 break;
203 default: /* bulk, interrupt */
204 buf = urb->transfer_buffer;
205 len = urb->transfer_buffer_length;
206 }
207
208 DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
209 qh, urb, address, qh->epnum,
210 is_in ? "in" : "out",
211 ({char *s; switch (qh->type) {
212 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
213 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
214 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
215 default: s = "-intr"; break;
216 }; s; }),
217 epnum, buf, len);
218
219 /* Configure endpoint */
220 if (is_in || hw_ep->is_shared_fifo)
221 hw_ep->in_qh = qh;
222 else
223 hw_ep->out_qh = qh;
224 musb_ep_program(musb, epnum, urb, !is_in, buf, len);
225
226 /* transmit may have more work: start it when it is time */
227 if (is_in)
228 return;
229
230 /* determine if the time is right for a periodic transfer */
231 switch (qh->type) {
232 case USB_ENDPOINT_XFER_ISOC:
233 case USB_ENDPOINT_XFER_INT:
234 DBG(3, "check whether there's still time for periodic Tx\n");
235 qh->iso_idx = 0;
236 frame = musb_readw(mbase, MUSB_FRAME);
237 /* FIXME this doesn't implement that scheduling policy ...
238 * or handle framecounter wrapping
239 */
240 if ((urb->transfer_flags & URB_ISO_ASAP)
241 || (frame >= urb->start_frame)) {
242 /* REVISIT the SOF irq handler shouldn't duplicate
243 * this code; and we don't init urb->start_frame...
244 */
245 qh->frame = 0;
246 goto start;
247 } else {
248 qh->frame = urb->start_frame;
249 /* enable SOF interrupt so we can count down */
250 DBG(1, "SOF for %d\n", epnum);
251 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
252 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
253 #endif
254 }
255 break;
256 default:
257 start:
258 DBG(4, "Start TX%d %s\n", epnum,
259 hw_ep->tx_channel ? "dma" : "pio");
260
261 if (!hw_ep->tx_channel)
262 musb_h_tx_start(hw_ep);
263 else if (is_cppi_enabled() || tusb_dma_omap())
264 cppi_host_txdma_start(hw_ep);
265 }
266 }
267
268 /* caller owns controller lock, irqs are blocked */
269 static void
270 __musb_giveback(struct musb *musb, struct urb *urb, int status)
271 __releases(musb->lock)
272 __acquires(musb->lock)
273 {
274 DBG(({ int level; switch (status) {
275 case 0:
276 level = 4;
277 break;
278 /* common/boring faults */
279 case -EREMOTEIO:
280 case -ESHUTDOWN:
281 case -ECONNRESET:
282 case -EPIPE:
283 level = 3;
284 break;
285 default:
286 level = 2;
287 break;
288 }; level; }),
289 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
290 urb, urb->complete, status,
291 usb_pipedevice(urb->pipe),
292 usb_pipeendpoint(urb->pipe),
293 usb_pipein(urb->pipe) ? "in" : "out",
294 urb->actual_length, urb->transfer_buffer_length
295 );
296
297 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
298 spin_unlock(&musb->lock);
299 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
300 spin_lock(&musb->lock);
301 }
302
303 /* for bulk/interrupt endpoints only */
304 static inline void
305 musb_save_toggle(struct musb_hw_ep *ep, int is_in, struct urb *urb)
306 {
307 struct usb_device *udev = urb->dev;
308 u16 csr;
309 void __iomem *epio = ep->regs;
310 struct musb_qh *qh;
311
312 /* FIXME: the current Mentor DMA code seems to have
313 * problems getting toggle correct.
314 */
315
316 if (is_in || ep->is_shared_fifo)
317 qh = ep->in_qh;
318 else
319 qh = ep->out_qh;
320
321 if (!is_in) {
322 csr = musb_readw(epio, MUSB_TXCSR);
323 usb_settoggle(udev, qh->epnum, 1,
324 (csr & MUSB_TXCSR_H_DATATOGGLE)
325 ? 1 : 0);
326 } else {
327 csr = musb_readw(epio, MUSB_RXCSR);
328 usb_settoggle(udev, qh->epnum, 0,
329 (csr & MUSB_RXCSR_H_DATATOGGLE)
330 ? 1 : 0);
331 }
332 }
333
334 /* caller owns controller lock, irqs are blocked */
335 static struct musb_qh *
336 musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
337 {
338 int is_in;
339 struct musb_hw_ep *ep = qh->hw_ep;
340 struct musb *musb = ep->musb;
341 int ready = qh->is_ready;
342
343 if (ep->is_shared_fifo)
344 is_in = 1;
345 else
346 is_in = usb_pipein(urb->pipe);
347
348 /* save toggle eagerly, for paranoia */
349 switch (qh->type) {
350 case USB_ENDPOINT_XFER_BULK:
351 case USB_ENDPOINT_XFER_INT:
352 musb_save_toggle(ep, is_in, urb);
353 break;
354 case USB_ENDPOINT_XFER_ISOC:
355 if (status == 0 && urb->error_count)
356 status = -EXDEV;
357 break;
358 }
359
360 qh->is_ready = 0;
361 __musb_giveback(musb, urb, status);
362 qh->is_ready = ready;
363
364 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
365 * invalidate qh as soon as list_empty(&hep->urb_list)
366 */
367 if (list_empty(&qh->hep->urb_list)) {
368 struct list_head *head;
369
370 if (is_in)
371 ep->rx_reinit = 1;
372 else
373 ep->tx_reinit = 1;
374
375 /* clobber old pointers to this qh */
376 if (is_in || ep->is_shared_fifo)
377 ep->in_qh = NULL;
378 else
379 ep->out_qh = NULL;
380 qh->hep->hcpriv = NULL;
381
382 switch (qh->type) {
383
384 case USB_ENDPOINT_XFER_CONTROL:
385 case USB_ENDPOINT_XFER_BULK:
386 /* fifo policy for these lists, except that NAKing
387 * should rotate a qh to the end (for fairness).
388 */
389 if (qh->mux == 1) {
390 head = qh->ring.prev;
391 list_del(&qh->ring);
392 kfree(qh);
393 qh = first_qh(head);
394 break;
395 }
396
397 case USB_ENDPOINT_XFER_ISOC:
398 case USB_ENDPOINT_XFER_INT:
399 /* this is where periodic bandwidth should be
400 * de-allocated if it's tracked and allocated;
401 * and where we'd update the schedule tree...
402 */
403 musb->periodic[ep->epnum] = NULL;
404 kfree(qh);
405 qh = NULL;
406 break;
407 }
408 }
409 return qh;
410 }
411
412 /*
413 * Advance this hardware endpoint's queue, completing the specified urb and
414 * advancing to either the next urb queued to that qh, or else invalidating
415 * that qh and advancing to the next qh scheduled after the current one.
416 *
417 * Context: caller owns controller lock, irqs are blocked
418 */
419 static void
420 musb_advance_schedule(struct musb *musb, struct urb *urb,
421 struct musb_hw_ep *hw_ep, int is_in)
422 {
423 struct musb_qh *qh;
424
425 if (is_in || hw_ep->is_shared_fifo)
426 qh = hw_ep->in_qh;
427 else
428 qh = hw_ep->out_qh;
429
430 if (urb->status == -EINPROGRESS)
431 qh = musb_giveback(qh, urb, 0);
432 else
433 qh = musb_giveback(qh, urb, urb->status);
434
435 if (qh && qh->is_ready && !list_empty(&qh->hep->urb_list)) {
436 DBG(4, "... next ep%d %cX urb %p\n",
437 hw_ep->epnum, is_in ? 'R' : 'T',
438 next_urb(qh));
439 musb_start_urb(musb, is_in, qh);
440 }
441 }
442
443 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
444 {
445 /* we don't want fifo to fill itself again;
446 * ignore dma (various models),
447 * leave toggle alone (may not have been saved yet)
448 */
449 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
450 csr &= ~(MUSB_RXCSR_H_REQPKT
451 | MUSB_RXCSR_H_AUTOREQ
452 | MUSB_RXCSR_AUTOCLEAR);
453
454 /* write 2x to allow double buffering */
455 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
456 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
457
458 /* flush writebuffer */
459 return musb_readw(hw_ep->regs, MUSB_RXCSR);
460 }
461
462 /*
463 * PIO RX for a packet (or part of it).
464 */
465 static bool
466 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
467 {
468 u16 rx_count;
469 u8 *buf;
470 u16 csr;
471 bool done = false;
472 u32 length;
473 int do_flush = 0;
474 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
475 void __iomem *epio = hw_ep->regs;
476 struct musb_qh *qh = hw_ep->in_qh;
477 int pipe = urb->pipe;
478 void *buffer = urb->transfer_buffer;
479
480 /* musb_ep_select(mbase, epnum); */
481 rx_count = musb_readw(epio, MUSB_RXCOUNT);
482 DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
483 urb->transfer_buffer, qh->offset,
484 urb->transfer_buffer_length);
485
486 /* unload FIFO */
487 if (usb_pipeisoc(pipe)) {
488 int status = 0;
489 struct usb_iso_packet_descriptor *d;
490
491 if (iso_err) {
492 status = -EILSEQ;
493 urb->error_count++;
494 }
495
496 d = urb->iso_frame_desc + qh->iso_idx;
497 buf = buffer + d->offset;
498 length = d->length;
499 if (rx_count > length) {
500 if (status == 0) {
501 status = -EOVERFLOW;
502 urb->error_count++;
503 }
504 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
505 do_flush = 1;
506 } else
507 length = rx_count;
508 urb->actual_length += length;
509 d->actual_length = length;
510
511 d->status = status;
512
513 /* see if we are done */
514 done = (++qh->iso_idx >= urb->number_of_packets);
515 } else {
516 /* non-isoch */
517 buf = buffer + qh->offset;
518 length = urb->transfer_buffer_length - qh->offset;
519 if (rx_count > length) {
520 if (urb->status == -EINPROGRESS)
521 urb->status = -EOVERFLOW;
522 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
523 do_flush = 1;
524 } else
525 length = rx_count;
526 urb->actual_length += length;
527 qh->offset += length;
528
529 /* see if we are done */
530 done = (urb->actual_length == urb->transfer_buffer_length)
531 || (rx_count < qh->maxpacket)
532 || (urb->status != -EINPROGRESS);
533 if (done
534 && (urb->status == -EINPROGRESS)
535 && (urb->transfer_flags & URB_SHORT_NOT_OK)
536 && (urb->actual_length
537 < urb->transfer_buffer_length))
538 urb->status = -EREMOTEIO;
539 }
540
541 musb_read_fifo(hw_ep, length, buf);
542
543 csr = musb_readw(epio, MUSB_RXCSR);
544 csr |= MUSB_RXCSR_H_WZC_BITS;
545 if (unlikely(do_flush))
546 musb_h_flush_rxfifo(hw_ep, csr);
547 else {
548 /* REVISIT this assumes AUTOCLEAR is never set */
549 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
550 if (!done)
551 csr |= MUSB_RXCSR_H_REQPKT;
552 musb_writew(epio, MUSB_RXCSR, csr);
553 }
554
555 return done;
556 }
557
558 /* we don't always need to reinit a given side of an endpoint...
559 * when we do, use tx/rx reinit routine and then construct a new CSR
560 * to address data toggle, NYET, and DMA or PIO.
561 *
562 * it's possible that driver bugs (especially for DMA) or aborting a
563 * transfer might have left the endpoint busier than it should be.
564 * the busy/not-empty tests are basically paranoia.
565 */
566 static void
567 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
568 {
569 u16 csr;
570
571 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
572 * That always uses tx_reinit since ep0 repurposes TX register
573 * offsets; the initial SETUP packet is also a kind of OUT.
574 */
575
576 /* if programmed for Tx, put it in RX mode */
577 if (ep->is_shared_fifo) {
578 csr = musb_readw(ep->regs, MUSB_TXCSR);
579 if (csr & MUSB_TXCSR_MODE) {
580 musb_h_tx_flush_fifo(ep);
581 musb_writew(ep->regs, MUSB_TXCSR,
582 MUSB_TXCSR_FRCDATATOG);
583 }
584 /* clear mode (and everything else) to enable Rx */
585 musb_writew(ep->regs, MUSB_TXCSR, 0);
586
587 /* scrub all previous state, clearing toggle */
588 } else {
589 csr = musb_readw(ep->regs, MUSB_RXCSR);
590 if (csr & MUSB_RXCSR_RXPKTRDY)
591 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
592 musb_readw(ep->regs, MUSB_RXCOUNT));
593
594 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
595 }
596
597 /* target addr and (for multipoint) hub addr/port */
598 if (musb->is_multipoint) {
599 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
600 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
601 musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
602
603 } else
604 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
605
606 /* protocol/endpoint, interval/NAKlimit, i/o size */
607 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
608 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
609 /* NOTE: bulk combining rewrites high bits of maxpacket */
610 musb_writew(ep->regs, MUSB_RXMAXP, qh->maxpacket);
611
612 ep->rx_reinit = 0;
613 }
614
615
616 /*
617 * Program an HDRC endpoint as per the given URB
618 * Context: irqs blocked, controller lock held
619 */
620 static void musb_ep_program(struct musb *musb, u8 epnum,
621 struct urb *urb, unsigned int is_out,
622 u8 *buf, u32 len)
623 {
624 struct dma_controller *dma_controller;
625 struct dma_channel *dma_channel;
626 u8 dma_ok;
627 void __iomem *mbase = musb->mregs;
628 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
629 void __iomem *epio = hw_ep->regs;
630 struct musb_qh *qh;
631 u16 packet_sz;
632
633 if (!is_out || hw_ep->is_shared_fifo)
634 qh = hw_ep->in_qh;
635 else
636 qh = hw_ep->out_qh;
637
638 packet_sz = qh->maxpacket;
639
640 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
641 "h_addr%02x h_port%02x bytes %d\n",
642 is_out ? "-->" : "<--",
643 epnum, urb, urb->dev->speed,
644 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
645 qh->h_addr_reg, qh->h_port_reg,
646 len);
647
648 musb_ep_select(mbase, epnum);
649
650 /* candidate for DMA? */
651 dma_controller = musb->dma_controller;
652 if (is_dma_capable() && epnum && dma_controller) {
653 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
654 if (!dma_channel) {
655 dma_channel = dma_controller->channel_alloc(
656 dma_controller, hw_ep, is_out);
657 if (is_out)
658 hw_ep->tx_channel = dma_channel;
659 else
660 hw_ep->rx_channel = dma_channel;
661 }
662 } else
663 dma_channel = NULL;
664
665 /* make sure we clear DMAEnab, autoSet bits from previous run */
666
667 /* OUT/transmit/EP0 or IN/receive? */
668 if (is_out) {
669 u16 csr;
670 u16 int_txe;
671 u16 load_count;
672
673 csr = musb_readw(epio, MUSB_TXCSR);
674
675 /* disable interrupt in case we flush */
676 int_txe = musb_readw(mbase, MUSB_INTRTXE);
677 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
678
679 /* general endpoint setup */
680 if (epnum) {
681 /* ASSERT: TXCSR_DMAENAB was already cleared */
682
683 /* flush all old state, set default */
684 musb_h_tx_flush_fifo(hw_ep);
685 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
686 | MUSB_TXCSR_DMAMODE
687 | MUSB_TXCSR_FRCDATATOG
688 | MUSB_TXCSR_H_RXSTALL
689 | MUSB_TXCSR_H_ERROR
690 | MUSB_TXCSR_TXPKTRDY
691 );
692 csr |= MUSB_TXCSR_MODE;
693
694 if (usb_gettoggle(urb->dev,
695 qh->epnum, 1))
696 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
697 | MUSB_TXCSR_H_DATATOGGLE;
698 else
699 csr |= MUSB_TXCSR_CLRDATATOG;
700
701 /* twice in case of double packet buffering */
702 musb_writew(epio, MUSB_TXCSR, csr);
703 /* REVISIT may need to clear FLUSHFIFO ... */
704 musb_writew(epio, MUSB_TXCSR, csr);
705 csr = musb_readw(epio, MUSB_TXCSR);
706 } else {
707 /* endpoint 0: just flush */
708 musb_writew(epio, MUSB_CSR0,
709 csr | MUSB_CSR0_FLUSHFIFO);
710 musb_writew(epio, MUSB_CSR0,
711 csr | MUSB_CSR0_FLUSHFIFO);
712 }
713
714 /* target addr and (for multipoint) hub addr/port */
715 if (musb->is_multipoint) {
716 musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
717 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
718 musb_write_txhubport(mbase, epnum, qh->h_port_reg);
719 /* FIXME if !epnum, do the same for RX ... */
720 } else
721 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
722
723 /* protocol/endpoint/interval/NAKlimit */
724 if (epnum) {
725 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
726 if (can_bulk_split(musb, qh->type))
727 musb_writew(epio, MUSB_TXMAXP,
728 packet_sz
729 | ((hw_ep->max_packet_sz_tx /
730 packet_sz) - 1) << 11);
731 else
732 musb_writew(epio, MUSB_TXMAXP,
733 packet_sz);
734 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
735 } else {
736 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
737 if (musb->is_multipoint)
738 musb_writeb(epio, MUSB_TYPE0,
739 qh->type_reg);
740 }
741
742 if (can_bulk_split(musb, qh->type))
743 load_count = min((u32) hw_ep->max_packet_sz_tx,
744 len);
745 else
746 load_count = min((u32) packet_sz, len);
747
748 #ifdef CONFIG_USB_INVENTRA_DMA
749 if (dma_channel) {
750
751 /* clear previous state */
752 csr = musb_readw(epio, MUSB_TXCSR);
753 csr &= ~(MUSB_TXCSR_AUTOSET
754 | MUSB_TXCSR_DMAMODE
755 | MUSB_TXCSR_DMAENAB);
756 csr |= MUSB_TXCSR_MODE;
757 musb_writew(epio, MUSB_TXCSR,
758 csr | MUSB_TXCSR_MODE);
759
760 qh->segsize = min(len, dma_channel->max_len);
761
762 if (qh->segsize <= packet_sz)
763 dma_channel->desired_mode = 0;
764 else
765 dma_channel->desired_mode = 1;
766
767
768 if (dma_channel->desired_mode == 0) {
769 csr &= ~(MUSB_TXCSR_AUTOSET
770 | MUSB_TXCSR_DMAMODE);
771 csr |= (MUSB_TXCSR_DMAENAB);
772 /* against programming guide */
773 } else
774 csr |= (MUSB_TXCSR_AUTOSET
775 | MUSB_TXCSR_DMAENAB
776 | MUSB_TXCSR_DMAMODE);
777
778 musb_writew(epio, MUSB_TXCSR, csr);
779
780 dma_ok = dma_controller->channel_program(
781 dma_channel, packet_sz,
782 dma_channel->desired_mode,
783 urb->transfer_dma,
784 qh->segsize);
785 if (dma_ok) {
786 load_count = 0;
787 } else {
788 dma_controller->channel_release(dma_channel);
789 if (is_out)
790 hw_ep->tx_channel = NULL;
791 else
792 hw_ep->rx_channel = NULL;
793 dma_channel = NULL;
794 }
795 }
796 #endif
797
798 /* candidate for DMA */
799 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
800
801 /* program endpoint CSRs first, then setup DMA.
802 * assume CPPI setup succeeds.
803 * defer enabling dma.
804 */
805 csr = musb_readw(epio, MUSB_TXCSR);
806 csr &= ~(MUSB_TXCSR_AUTOSET
807 | MUSB_TXCSR_DMAMODE
808 | MUSB_TXCSR_DMAENAB);
809 csr |= MUSB_TXCSR_MODE;
810 musb_writew(epio, MUSB_TXCSR,
811 csr | MUSB_TXCSR_MODE);
812
813 dma_channel->actual_len = 0L;
814 qh->segsize = len;
815
816 /* TX uses "rndis" mode automatically, but needs help
817 * to identify the zero-length-final-packet case.
818 */
819 dma_ok = dma_controller->channel_program(
820 dma_channel, packet_sz,
821 (urb->transfer_flags
822 & URB_ZERO_PACKET)
823 == URB_ZERO_PACKET,
824 urb->transfer_dma,
825 qh->segsize);
826 if (dma_ok) {
827 load_count = 0;
828 } else {
829 dma_controller->channel_release(dma_channel);
830 hw_ep->tx_channel = NULL;
831 dma_channel = NULL;
832
833 /* REVISIT there's an error path here that
834 * needs handling: can't do dma, but
835 * there's no pio buffer address...
836 */
837 }
838 }
839
840 if (load_count) {
841 /* ASSERT: TXCSR_DMAENAB was already cleared */
842
843 /* PIO to load FIFO */
844 qh->segsize = load_count;
845 musb_write_fifo(hw_ep, load_count, buf);
846 csr = musb_readw(epio, MUSB_TXCSR);
847 csr &= ~(MUSB_TXCSR_DMAENAB
848 | MUSB_TXCSR_DMAMODE
849 | MUSB_TXCSR_AUTOSET);
850 /* write CSR */
851 csr |= MUSB_TXCSR_MODE;
852
853 if (epnum)
854 musb_writew(epio, MUSB_TXCSR, csr);
855 }
856
857 /* re-enable interrupt */
858 musb_writew(mbase, MUSB_INTRTXE, int_txe);
859
860 /* IN/receive */
861 } else {
862 u16 csr;
863
864 if (hw_ep->rx_reinit) {
865 musb_rx_reinit(musb, qh, hw_ep);
866
867 /* init new state: toggle and NYET, maybe DMA later */
868 if (usb_gettoggle(urb->dev, qh->epnum, 0))
869 csr = MUSB_RXCSR_H_WR_DATATOGGLE
870 | MUSB_RXCSR_H_DATATOGGLE;
871 else
872 csr = 0;
873 if (qh->type == USB_ENDPOINT_XFER_INT)
874 csr |= MUSB_RXCSR_DISNYET;
875
876 } else {
877 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
878
879 if (csr & (MUSB_RXCSR_RXPKTRDY
880 | MUSB_RXCSR_DMAENAB
881 | MUSB_RXCSR_H_REQPKT))
882 ERR("broken !rx_reinit, ep%d csr %04x\n",
883 hw_ep->epnum, csr);
884
885 /* scrub any stale state, leaving toggle alone */
886 csr &= MUSB_RXCSR_DISNYET;
887 }
888
889 /* kick things off */
890
891 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
892 /* candidate for DMA */
893 if (dma_channel) {
894 dma_channel->actual_len = 0L;
895 qh->segsize = len;
896
897 /* AUTOREQ is in a DMA register */
898 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
899 csr = musb_readw(hw_ep->regs,
900 MUSB_RXCSR);
901
902 /* unless caller treats short rx transfers as
903 * errors, we dare not queue multiple transfers.
904 */
905 dma_ok = dma_controller->channel_program(
906 dma_channel, packet_sz,
907 !(urb->transfer_flags
908 & URB_SHORT_NOT_OK),
909 urb->transfer_dma,
910 qh->segsize);
911 if (!dma_ok) {
912 dma_controller->channel_release(
913 dma_channel);
914 hw_ep->rx_channel = NULL;
915 dma_channel = NULL;
916 } else
917 csr |= MUSB_RXCSR_DMAENAB;
918 }
919 }
920
921 csr |= MUSB_RXCSR_H_REQPKT;
922 DBG(7, "RXCSR%d := %04x\n", epnum, csr);
923 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
924 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
925 }
926 }
927
928
929 /*
930 * Service the default endpoint (ep0) as host.
931 * Return true until it's time to start the status stage.
932 */
933 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
934 {
935 bool more = false;
936 u8 *fifo_dest = NULL;
937 u16 fifo_count = 0;
938 struct musb_hw_ep *hw_ep = musb->control_ep;
939 struct musb_qh *qh = hw_ep->in_qh;
940 struct usb_ctrlrequest *request;
941
942 switch (musb->ep0_stage) {
943 case MUSB_EP0_IN:
944 fifo_dest = urb->transfer_buffer + urb->actual_length;
945 fifo_count = min(len, ((u16) (urb->transfer_buffer_length
946 - urb->actual_length)));
947 if (fifo_count < len)
948 urb->status = -EOVERFLOW;
949
950 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
951
952 urb->actual_length += fifo_count;
953 if (len < qh->maxpacket) {
954 /* always terminate on short read; it's
955 * rarely reported as an error.
956 */
957 } else if (urb->actual_length <
958 urb->transfer_buffer_length)
959 more = true;
960 break;
961 case MUSB_EP0_START:
962 request = (struct usb_ctrlrequest *) urb->setup_packet;
963
964 if (!request->wLength) {
965 DBG(4, "start no-DATA\n");
966 break;
967 } else if (request->bRequestType & USB_DIR_IN) {
968 DBG(4, "start IN-DATA\n");
969 musb->ep0_stage = MUSB_EP0_IN;
970 more = true;
971 break;
972 } else {
973 DBG(4, "start OUT-DATA\n");
974 musb->ep0_stage = MUSB_EP0_OUT;
975 more = true;
976 }
977 /* FALLTHROUGH */
978 case MUSB_EP0_OUT:
979 fifo_count = min(qh->maxpacket, ((u16)
980 (urb->transfer_buffer_length
981 - urb->actual_length)));
982
983 if (fifo_count) {
984 fifo_dest = (u8 *) (urb->transfer_buffer
985 + urb->actual_length);
986 DBG(3, "Sending %d byte%s to ep0 fifo %p\n",
987 fifo_count,
988 (fifo_count == 1) ? "" : "s",
989 fifo_dest);
990 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
991
992 urb->actual_length += fifo_count;
993 more = true;
994 }
995 break;
996 default:
997 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
998 break;
999 }
1000
1001 return more;
1002 }
1003
1004 /*
1005 * Handle default endpoint interrupt as host. Only called in IRQ time
1006 * from musb_interrupt().
1007 *
1008 * called with controller irqlocked
1009 */
1010 irqreturn_t musb_h_ep0_irq(struct musb *musb)
1011 {
1012 struct urb *urb;
1013 u16 csr, len;
1014 int status = 0;
1015 void __iomem *mbase = musb->mregs;
1016 struct musb_hw_ep *hw_ep = musb->control_ep;
1017 void __iomem *epio = hw_ep->regs;
1018 struct musb_qh *qh = hw_ep->in_qh;
1019 bool complete = false;
1020 irqreturn_t retval = IRQ_NONE;
1021
1022 /* ep0 only has one queue, "in" */
1023 urb = next_urb(qh);
1024
1025 musb_ep_select(mbase, 0);
1026 csr = musb_readw(epio, MUSB_CSR0);
1027 len = (csr & MUSB_CSR0_RXPKTRDY)
1028 ? musb_readb(epio, MUSB_COUNT0)
1029 : 0;
1030
1031 DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
1032 csr, qh, len, urb, musb->ep0_stage);
1033
1034 /* if we just did status stage, we are done */
1035 if (MUSB_EP0_STATUS == musb->ep0_stage) {
1036 retval = IRQ_HANDLED;
1037 complete = true;
1038 }
1039
1040 /* prepare status */
1041 if (csr & MUSB_CSR0_H_RXSTALL) {
1042 DBG(6, "STALLING ENDPOINT\n");
1043 status = -EPIPE;
1044
1045 } else if (csr & MUSB_CSR0_H_ERROR) {
1046 DBG(2, "no response, csr0 %04x\n", csr);
1047 status = -EPROTO;
1048
1049 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1050 DBG(2, "control NAK timeout\n");
1051
1052 /* NOTE: this code path would be a good place to PAUSE a
1053 * control transfer, if another one is queued, so that
1054 * ep0 is more likely to stay busy.
1055 *
1056 * if (qh->ring.next != &musb->control), then
1057 * we have a candidate... NAKing is *NOT* an error
1058 */
1059 musb_writew(epio, MUSB_CSR0, 0);
1060 retval = IRQ_HANDLED;
1061 }
1062
1063 if (status) {
1064 DBG(6, "aborting\n");
1065 retval = IRQ_HANDLED;
1066 if (urb)
1067 urb->status = status;
1068 complete = true;
1069
1070 /* use the proper sequence to abort the transfer */
1071 if (csr & MUSB_CSR0_H_REQPKT) {
1072 csr &= ~MUSB_CSR0_H_REQPKT;
1073 musb_writew(epio, MUSB_CSR0, csr);
1074 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1075 musb_writew(epio, MUSB_CSR0, csr);
1076 } else {
1077 csr |= MUSB_CSR0_FLUSHFIFO;
1078 musb_writew(epio, MUSB_CSR0, csr);
1079 musb_writew(epio, MUSB_CSR0, csr);
1080 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1081 musb_writew(epio, MUSB_CSR0, csr);
1082 }
1083
1084 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1085
1086 /* clear it */
1087 musb_writew(epio, MUSB_CSR0, 0);
1088 }
1089
1090 if (unlikely(!urb)) {
1091 /* stop endpoint since we have no place for its data, this
1092 * SHOULD NEVER HAPPEN! */
1093 ERR("no URB for end 0\n");
1094
1095 musb_writew(epio, MUSB_CSR0, MUSB_CSR0_FLUSHFIFO);
1096 musb_writew(epio, MUSB_CSR0, MUSB_CSR0_FLUSHFIFO);
1097 musb_writew(epio, MUSB_CSR0, 0);
1098
1099 goto done;
1100 }
1101
1102 if (!complete) {
1103 /* call common logic and prepare response */
1104 if (musb_h_ep0_continue(musb, len, urb)) {
1105 /* more packets required */
1106 csr = (MUSB_EP0_IN == musb->ep0_stage)
1107 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1108 } else {
1109 /* data transfer complete; perform status phase */
1110 if (usb_pipeout(urb->pipe)
1111 || !urb->transfer_buffer_length)
1112 csr = MUSB_CSR0_H_STATUSPKT
1113 | MUSB_CSR0_H_REQPKT;
1114 else
1115 csr = MUSB_CSR0_H_STATUSPKT
1116 | MUSB_CSR0_TXPKTRDY;
1117
1118 /* flag status stage */
1119 musb->ep0_stage = MUSB_EP0_STATUS;
1120
1121 DBG(5, "ep0 STATUS, csr %04x\n", csr);
1122
1123 }
1124 musb_writew(epio, MUSB_CSR0, csr);
1125 retval = IRQ_HANDLED;
1126 } else
1127 musb->ep0_stage = MUSB_EP0_IDLE;
1128
1129 /* call completion handler if done */
1130 if (complete)
1131 musb_advance_schedule(musb, urb, hw_ep, 1);
1132 done:
1133 return retval;
1134 }
1135
1136
1137 #ifdef CONFIG_USB_INVENTRA_DMA
1138
1139 /* Host side TX (OUT) using Mentor DMA works as follows:
1140 submit_urb ->
1141 - if queue was empty, Program Endpoint
1142 - ... which starts DMA to fifo in mode 1 or 0
1143
1144 DMA Isr (transfer complete) -> TxAvail()
1145 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1146 only in musb_cleanup_urb)
1147 - TxPktRdy has to be set in mode 0 or for
1148 short packets in mode 1.
1149 */
1150
1151 #endif
1152
1153 /* Service a Tx-Available or dma completion irq for the endpoint */
1154 void musb_host_tx(struct musb *musb, u8 epnum)
1155 {
1156 int pipe;
1157 bool done = false;
1158 u16 tx_csr;
1159 size_t wLength = 0;
1160 u8 *buf = NULL;
1161 struct urb *urb;
1162 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1163 void __iomem *epio = hw_ep->regs;
1164 struct musb_qh *qh = hw_ep->out_qh;
1165 u32 status = 0;
1166 void __iomem *mbase = musb->mregs;
1167 struct dma_channel *dma;
1168
1169 urb = next_urb(qh);
1170
1171 musb_ep_select(mbase, epnum);
1172 tx_csr = musb_readw(epio, MUSB_TXCSR);
1173
1174 /* with CPPI, DMA sometimes triggers "extra" irqs */
1175 if (!urb) {
1176 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1177 goto finish;
1178 }
1179
1180 pipe = urb->pipe;
1181 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1182 DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1183 dma ? ", dma" : "");
1184
1185 /* check for errors */
1186 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1187 /* dma was disabled, fifo flushed */
1188 DBG(3, "TX end %d stall\n", epnum);
1189
1190 /* stall; record URB status */
1191 status = -EPIPE;
1192
1193 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1194 /* (NON-ISO) dma was disabled, fifo flushed */
1195 DBG(3, "TX 3strikes on ep=%d\n", epnum);
1196
1197 status = -ETIMEDOUT;
1198
1199 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1200 DBG(6, "TX end=%d device not responding\n", epnum);
1201
1202 /* NOTE: this code path would be a good place to PAUSE a
1203 * transfer, if there's some other (nonperiodic) tx urb
1204 * that could use this fifo. (dma complicates it...)
1205 *
1206 * if (bulk && qh->ring.next != &musb->out_bulk), then
1207 * we have a candidate... NAKing is *NOT* an error
1208 */
1209 musb_ep_select(mbase, epnum);
1210 musb_writew(epio, MUSB_TXCSR,
1211 MUSB_TXCSR_H_WZC_BITS
1212 | MUSB_TXCSR_TXPKTRDY);
1213 goto finish;
1214 }
1215
1216 if (status) {
1217 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1218 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1219 (void) musb->dma_controller->channel_abort(dma);
1220 }
1221
1222 /* do the proper sequence to abort the transfer in the
1223 * usb core; the dma engine should already be stopped.
1224 */
1225 musb_h_tx_flush_fifo(hw_ep);
1226 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1227 | MUSB_TXCSR_DMAENAB
1228 | MUSB_TXCSR_H_ERROR
1229 | MUSB_TXCSR_H_RXSTALL
1230 | MUSB_TXCSR_H_NAKTIMEOUT
1231 );
1232
1233 musb_ep_select(mbase, epnum);
1234 musb_writew(epio, MUSB_TXCSR, tx_csr);
1235 /* REVISIT may need to clear FLUSHFIFO ... */
1236 musb_writew(epio, MUSB_TXCSR, tx_csr);
1237 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1238
1239 done = true;
1240 }
1241
1242 /* second cppi case */
1243 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1244 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1245 goto finish;
1246
1247 }
1248
1249 /* REVISIT this looks wrong... */
1250 if (!status || dma || usb_pipeisoc(pipe)) {
1251 if (dma)
1252 wLength = dma->actual_len;
1253 else
1254 wLength = qh->segsize;
1255 qh->offset += wLength;
1256
1257 if (usb_pipeisoc(pipe)) {
1258 struct usb_iso_packet_descriptor *d;
1259
1260 d = urb->iso_frame_desc + qh->iso_idx;
1261 d->actual_length = qh->segsize;
1262 if (++qh->iso_idx >= urb->number_of_packets) {
1263 done = true;
1264 } else {
1265 d++;
1266 buf = urb->transfer_buffer + d->offset;
1267 wLength = d->length;
1268 }
1269 } else if (dma) {
1270 done = true;
1271 } else {
1272 /* see if we need to send more data, or ZLP */
1273 if (qh->segsize < qh->maxpacket)
1274 done = true;
1275 else if (qh->offset == urb->transfer_buffer_length
1276 && !(urb->transfer_flags
1277 & URB_ZERO_PACKET))
1278 done = true;
1279 if (!done) {
1280 buf = urb->transfer_buffer
1281 + qh->offset;
1282 wLength = urb->transfer_buffer_length
1283 - qh->offset;
1284 }
1285 }
1286 }
1287
1288 /* urb->status != -EINPROGRESS means request has been faulted,
1289 * so we must abort this transfer after cleanup
1290 */
1291 if (urb->status != -EINPROGRESS) {
1292 done = true;
1293 if (status == 0)
1294 status = urb->status;
1295 }
1296
1297 if (done) {
1298 /* set status */
1299 urb->status = status;
1300 urb->actual_length = qh->offset;
1301 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1302
1303 } else if (!(tx_csr & MUSB_TXCSR_DMAENAB)) {
1304 /* WARN_ON(!buf); */
1305
1306 /* REVISIT: some docs say that when hw_ep->tx_double_buffered,
1307 * (and presumably, fifo is not half-full) we should write TWO
1308 * packets before updating TXCSR ... other docs disagree ...
1309 */
1310 /* PIO: start next packet in this URB */
1311 wLength = min(qh->maxpacket, (u16) wLength);
1312 musb_write_fifo(hw_ep, wLength, buf);
1313 qh->segsize = wLength;
1314
1315 musb_ep_select(mbase, epnum);
1316 musb_writew(epio, MUSB_TXCSR,
1317 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1318 } else
1319 DBG(1, "not complete, but dma enabled?\n");
1320
1321 finish:
1322 return;
1323 }
1324
1325
1326 #ifdef CONFIG_USB_INVENTRA_DMA
1327
1328 /* Host side RX (IN) using Mentor DMA works as follows:
1329 submit_urb ->
1330 - if queue was empty, ProgramEndpoint
1331 - first IN token is sent out (by setting ReqPkt)
1332 LinuxIsr -> RxReady()
1333 /\ => first packet is received
1334 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1335 | -> DMA Isr (transfer complete) -> RxReady()
1336 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1337 | - if urb not complete, send next IN token (ReqPkt)
1338 | | else complete urb.
1339 | |
1340 ---------------------------
1341 *
1342 * Nuances of mode 1:
1343 * For short packets, no ack (+RxPktRdy) is sent automatically
1344 * (even if AutoClear is ON)
1345 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1346 * automatically => major problem, as collecting the next packet becomes
1347 * difficult. Hence mode 1 is not used.
1348 *
1349 * REVISIT
1350 * All we care about at this driver level is that
1351 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1352 * (b) termination conditions are: short RX, or buffer full;
1353 * (c) fault modes include
1354 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1355 * (and that endpoint's dma queue stops immediately)
1356 * - overflow (full, PLUS more bytes in the terminal packet)
1357 *
1358 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1359 * thus be a great candidate for using mode 1 ... for all but the
1360 * last packet of one URB's transfer.
1361 */
1362
1363 #endif
1364
1365 /*
1366 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1367 * and high-bandwidth IN transfer cases.
1368 */
1369 void musb_host_rx(struct musb *musb, u8 epnum)
1370 {
1371 struct urb *urb;
1372 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1373 void __iomem *epio = hw_ep->regs;
1374 struct musb_qh *qh = hw_ep->in_qh;
1375 size_t xfer_len;
1376 void __iomem *mbase = musb->mregs;
1377 int pipe;
1378 u16 rx_csr, val;
1379 bool iso_err = false;
1380 bool done = false;
1381 u32 status;
1382 struct dma_channel *dma;
1383
1384 musb_ep_select(mbase, epnum);
1385
1386 urb = next_urb(qh);
1387 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1388 status = 0;
1389 xfer_len = 0;
1390
1391 rx_csr = musb_readw(epio, MUSB_RXCSR);
1392 val = rx_csr;
1393
1394 if (unlikely(!urb)) {
1395 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1396 * usbtest #11 (unlinks) triggers it regularly, sometimes
1397 * with fifo full. (Only with DMA??)
1398 */
1399 DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1400 musb_readw(epio, MUSB_RXCOUNT));
1401 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1402 return;
1403 }
1404
1405 pipe = urb->pipe;
1406
1407 DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1408 epnum, rx_csr, urb->actual_length,
1409 dma ? dma->actual_len : 0);
1410
1411 /* check for errors, concurrent stall & unlink is not really
1412 * handled yet! */
1413 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1414 DBG(3, "RX end %d STALL\n", epnum);
1415
1416 /* stall; record URB status */
1417 status = -EPIPE;
1418
1419 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1420 DBG(3, "end %d RX proto error\n", epnum);
1421
1422 status = -EPROTO;
1423 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1424
1425 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1426
1427 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1428 /* NOTE this code path would be a good place to PAUSE a
1429 * transfer, if there's some other (nonperiodic) rx urb
1430 * that could use this fifo. (dma complicates it...)
1431 *
1432 * if (bulk && qh->ring.next != &musb->in_bulk), then
1433 * we have a candidate... NAKing is *NOT* an error
1434 */
1435 DBG(6, "RX end %d NAK timeout\n", epnum);
1436 musb_ep_select(mbase, epnum);
1437 musb_writew(epio, MUSB_RXCSR,
1438 MUSB_RXCSR_H_WZC_BITS
1439 | MUSB_RXCSR_H_REQPKT);
1440
1441 goto finish;
1442 } else {
1443 DBG(4, "RX end %d ISO data error\n", epnum);
1444 /* packet error reported later */
1445 iso_err = true;
1446 }
1447 }
1448
1449 /* faults abort the transfer */
1450 if (status) {
1451 /* clean up dma and collect transfer count */
1452 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1453 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1454 (void) musb->dma_controller->channel_abort(dma);
1455 xfer_len = dma->actual_len;
1456 }
1457 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1458 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1459 done = true;
1460 goto finish;
1461 }
1462
1463 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1464 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1465 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1466 goto finish;
1467 }
1468
1469 /* thorough shutdown for now ... given more precise fault handling
1470 * and better queueing support, we might keep a DMA pipeline going
1471 * while processing this irq for earlier completions.
1472 */
1473
1474 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1475
1476 #ifndef CONFIG_USB_INVENTRA_DMA
1477 if (rx_csr & MUSB_RXCSR_H_REQPKT) {
1478 /* REVISIT this happened for a while on some short reads...
1479 * the cleanup still needs investigation... looks bad...
1480 * and also duplicates dma cleanup code above ... plus,
1481 * shouldn't this be the "half full" double buffer case?
1482 */
1483 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1484 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1485 (void) musb->dma_controller->channel_abort(dma);
1486 xfer_len = dma->actual_len;
1487 done = true;
1488 }
1489
1490 DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1491 xfer_len, dma ? ", dma" : "");
1492 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1493
1494 musb_ep_select(mbase, epnum);
1495 musb_writew(epio, MUSB_RXCSR,
1496 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1497 }
1498 #endif
1499 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1500 xfer_len = dma->actual_len;
1501
1502 val &= ~(MUSB_RXCSR_DMAENAB
1503 | MUSB_RXCSR_H_AUTOREQ
1504 | MUSB_RXCSR_AUTOCLEAR
1505 | MUSB_RXCSR_RXPKTRDY);
1506 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1507
1508 #ifdef CONFIG_USB_INVENTRA_DMA
1509 if (usb_pipeisoc(pipe)) {
1510 struct usb_iso_packet_descriptor *d;
1511
1512 d = urb->iso_frame_desc + qh->iso_idx;
1513 d->actual_length = xfer_len;
1514
1515 /* even if there was an error, we did the dma
1516 * for iso_frame_desc->length
1517 */
1518 if (d->status != EILSEQ && d->status != -EOVERFLOW)
1519 d->status = 0;
1520
1521 if (++qh->iso_idx >= urb->number_of_packets)
1522 done = true;
1523 else
1524 done = false;
1525
1526 } else {
1527 /* done if urb buffer is full or short packet is recd */
1528 done = (urb->actual_length + xfer_len >=
1529 urb->transfer_buffer_length
1530 || dma->actual_len < qh->maxpacket);
1531 }
1532
1533 /* send IN token for next packet, without AUTOREQ */
1534 if (!done) {
1535 val |= MUSB_RXCSR_H_REQPKT;
1536 musb_writew(epio, MUSB_RXCSR,
1537 MUSB_RXCSR_H_WZC_BITS | val);
1538 }
1539
1540 DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
1541 done ? "off" : "reset",
1542 musb_readw(epio, MUSB_RXCSR),
1543 musb_readw(epio, MUSB_RXCOUNT));
1544 #else
1545 done = true;
1546 #endif
1547 } else if (urb->status == -EINPROGRESS) {
1548 /* if no errors, be sure a packet is ready for unloading */
1549 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1550 status = -EPROTO;
1551 ERR("Rx interrupt with no errors or packet!\n");
1552
1553 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1554
1555 /* SCRUB (RX) */
1556 /* do the proper sequence to abort the transfer */
1557 musb_ep_select(mbase, epnum);
1558 val &= ~MUSB_RXCSR_H_REQPKT;
1559 musb_writew(epio, MUSB_RXCSR, val);
1560 goto finish;
1561 }
1562
1563 /* we are expecting IN packets */
1564 #ifdef CONFIG_USB_INVENTRA_DMA
1565 if (dma) {
1566 struct dma_controller *c;
1567 u16 rx_count;
1568 int ret, length;
1569 dma_addr_t buf;
1570
1571 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1572
1573 DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
1574 epnum, rx_count,
1575 urb->transfer_dma
1576 + urb->actual_length,
1577 qh->offset,
1578 urb->transfer_buffer_length);
1579
1580 c = musb->dma_controller;
1581
1582 if (usb_pipeisoc(pipe)) {
1583 int status = 0;
1584 struct usb_iso_packet_descriptor *d;
1585
1586 d = urb->iso_frame_desc + qh->iso_idx;
1587
1588 if (iso_err) {
1589 status = -EILSEQ;
1590 urb->error_count++;
1591 }
1592 if (rx_count > d->length) {
1593 if (status == 0) {
1594 status = -EOVERFLOW;
1595 urb->error_count++;
1596 }
1597 DBG(2, "** OVERFLOW %d into %d\n",\
1598 rx_count, d->length);
1599
1600 length = d->length;
1601 } else
1602 length = rx_count;
1603 d->status = status;
1604 buf = urb->transfer_dma + d->offset;
1605 } else {
1606 length = rx_count;
1607 buf = urb->transfer_dma +
1608 urb->actual_length;
1609 }
1610
1611 dma->desired_mode = 0;
1612 #ifdef USE_MODE1
1613 /* because of the issue below, mode 1 will
1614 * only rarely behave with correct semantics.
1615 */
1616 if ((urb->transfer_flags &
1617 URB_SHORT_NOT_OK)
1618 && (urb->transfer_buffer_length -
1619 urb->actual_length)
1620 > qh->maxpacket)
1621 dma->desired_mode = 1;
1622 if (rx_count < hw_ep->max_packet_sz_rx) {
1623 length = rx_count;
1624 dma->bDesiredMode = 0;
1625 } else {
1626 length = urb->transfer_buffer_length;
1627 }
1628 #endif
1629
1630 /* Disadvantage of using mode 1:
1631 * It's basically usable only for mass storage class; essentially all
1632 * other protocols also terminate transfers on short packets.
1633 *
1634 * Details:
1635 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1636 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1637 * to use the extra IN token to grab the last packet using mode 0, then
1638 * the problem is that you cannot be sure when the device will send the
1639 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1640 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1641 * transfer, while sometimes it is recd just a little late so that if you
1642 * try to configure for mode 0 soon after the mode 1 transfer is
1643 * completed, you will find rxcount 0. Okay, so you might think why not
1644 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1645 */
1646
1647 val = musb_readw(epio, MUSB_RXCSR);
1648 val &= ~MUSB_RXCSR_H_REQPKT;
1649
1650 if (dma->desired_mode == 0)
1651 val &= ~MUSB_RXCSR_H_AUTOREQ;
1652 else
1653 val |= MUSB_RXCSR_H_AUTOREQ;
1654 val |= MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAENAB;
1655
1656 musb_writew(epio, MUSB_RXCSR,
1657 MUSB_RXCSR_H_WZC_BITS | val);
1658
1659 /* REVISIT if when actual_length != 0,
1660 * transfer_buffer_length needs to be
1661 * adjusted first...
1662 */
1663 ret = c->channel_program(
1664 dma, qh->maxpacket,
1665 dma->desired_mode, buf, length);
1666
1667 if (!ret) {
1668 c->channel_release(dma);
1669 hw_ep->rx_channel = NULL;
1670 dma = NULL;
1671 /* REVISIT reset CSR */
1672 }
1673 }
1674 #endif /* Mentor DMA */
1675
1676 if (!dma) {
1677 done = musb_host_packet_rx(musb, urb,
1678 epnum, iso_err);
1679 DBG(6, "read %spacket\n", done ? "last " : "");
1680 }
1681 }
1682
1683 finish:
1684 urb->actual_length += xfer_len;
1685 qh->offset += xfer_len;
1686 if (done) {
1687 if (urb->status == -EINPROGRESS)
1688 urb->status = status;
1689 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
1690 }
1691 }
1692
1693 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1694 * the software schedule associates multiple such nodes with a given
1695 * host side hardware endpoint + direction; scheduling may activate
1696 * that hardware endpoint.
1697 */
1698 static int musb_schedule(
1699 struct musb *musb,
1700 struct musb_qh *qh,
1701 int is_in)
1702 {
1703 int idle;
1704 int best_diff;
1705 int best_end, epnum;
1706 struct musb_hw_ep *hw_ep = NULL;
1707 struct list_head *head = NULL;
1708
1709 /* use fixed hardware for control and bulk */
1710 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
1711 head = &musb->control;
1712 hw_ep = musb->control_ep;
1713 goto success;
1714 }
1715
1716 /* else, periodic transfers get muxed to other endpoints */
1717
1718 /* FIXME this doesn't consider direction, so it can only
1719 * work for one half of the endpoint hardware, and assumes
1720 * the previous cases handled all non-shared endpoints...
1721 */
1722
1723 /* we know this qh hasn't been scheduled, so all we need to do
1724 * is choose which hardware endpoint to put it on ...
1725 *
1726 * REVISIT what we really want here is a regular schedule tree
1727 * like e.g. OHCI uses, but for now musb->periodic is just an
1728 * array of the _single_ logical endpoint associated with a
1729 * given physical one (identity mapping logical->physical).
1730 *
1731 * that simplistic approach makes TT scheduling a lot simpler;
1732 * there is none, and thus none of its complexity...
1733 */
1734 best_diff = 4096;
1735 best_end = -1;
1736
1737 for (epnum = 1; epnum < musb->nr_endpoints; epnum++) {
1738 int diff;
1739
1740 if (musb->periodic[epnum])
1741 continue;
1742 hw_ep = &musb->endpoints[epnum];
1743 if (hw_ep == musb->bulk_ep)
1744 continue;
1745
1746 if (is_in)
1747 diff = hw_ep->max_packet_sz_rx - qh->maxpacket;
1748 else
1749 diff = hw_ep->max_packet_sz_tx - qh->maxpacket;
1750
1751 if (diff >= 0 && best_diff > diff) {
1752 best_diff = diff;
1753 best_end = epnum;
1754 }
1755 }
1756 /* use bulk reserved ep1 if no other ep is free */
1757 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
1758 hw_ep = musb->bulk_ep;
1759 if (is_in)
1760 head = &musb->in_bulk;
1761 else
1762 head = &musb->out_bulk;
1763 goto success;
1764 } else if (best_end < 0) {
1765 return -ENOSPC;
1766 }
1767
1768 idle = 1;
1769 qh->mux = 0;
1770 hw_ep = musb->endpoints + best_end;
1771 musb->periodic[best_end] = qh;
1772 DBG(4, "qh %p periodic slot %d\n", qh, best_end);
1773 success:
1774 if (head) {
1775 idle = list_empty(head);
1776 list_add_tail(&qh->ring, head);
1777 qh->mux = 1;
1778 }
1779 qh->hw_ep = hw_ep;
1780 qh->hep->hcpriv = qh;
1781 if (idle)
1782 musb_start_urb(musb, is_in, qh);
1783 return 0;
1784 }
1785
1786 static int musb_urb_enqueue(
1787 struct usb_hcd *hcd,
1788 struct urb *urb,
1789 gfp_t mem_flags)
1790 {
1791 unsigned long flags;
1792 struct musb *musb = hcd_to_musb(hcd);
1793 struct usb_host_endpoint *hep = urb->ep;
1794 struct musb_qh *qh = hep->hcpriv;
1795 struct usb_endpoint_descriptor *epd = &hep->desc;
1796 int ret;
1797 unsigned type_reg;
1798 unsigned interval;
1799
1800 /* host role must be active */
1801 if (!is_host_active(musb) || !musb->is_active)
1802 return -ENODEV;
1803
1804 spin_lock_irqsave(&musb->lock, flags);
1805 ret = usb_hcd_link_urb_to_ep(hcd, urb);
1806 spin_unlock_irqrestore(&musb->lock, flags);
1807 if (ret)
1808 return ret;
1809
1810 /* DMA mapping was already done, if needed, and this urb is on
1811 * hep->urb_list ... so there's little to do unless hep wasn't
1812 * yet scheduled onto a live qh.
1813 *
1814 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
1815 * disabled, testing for empty qh->ring and avoiding qh setup costs
1816 * except for the first urb queued after a config change.
1817 */
1818 if (qh) {
1819 urb->hcpriv = qh;
1820 return 0;
1821 }
1822
1823 /* Allocate and initialize qh, minimizing the work done each time
1824 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
1825 *
1826 * REVISIT consider a dedicated qh kmem_cache, so it's harder
1827 * for bugs in other kernel code to break this driver...
1828 */
1829 qh = kzalloc(sizeof *qh, mem_flags);
1830 if (!qh) {
1831 spin_lock_irqsave(&musb->lock, flags);
1832 usb_hcd_unlink_urb_from_ep(hcd, urb);
1833 spin_unlock_irqrestore(&musb->lock, flags);
1834 return -ENOMEM;
1835 }
1836
1837 qh->hep = hep;
1838 qh->dev = urb->dev;
1839 INIT_LIST_HEAD(&qh->ring);
1840 qh->is_ready = 1;
1841
1842 qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize);
1843
1844 /* no high bandwidth support yet */
1845 if (qh->maxpacket & ~0x7ff) {
1846 ret = -EMSGSIZE;
1847 goto done;
1848 }
1849
1850 qh->epnum = epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
1851 qh->type = epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1852
1853 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
1854 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
1855
1856 /* precompute rxtype/txtype/type0 register */
1857 type_reg = (qh->type << 4) | qh->epnum;
1858 switch (urb->dev->speed) {
1859 case USB_SPEED_LOW:
1860 type_reg |= 0xc0;
1861 break;
1862 case USB_SPEED_FULL:
1863 type_reg |= 0x80;
1864 break;
1865 default:
1866 type_reg |= 0x40;
1867 }
1868 qh->type_reg = type_reg;
1869
1870 /* precompute rxinterval/txinterval register */
1871 interval = min((u8)16, epd->bInterval); /* log encoding */
1872 switch (qh->type) {
1873 case USB_ENDPOINT_XFER_INT:
1874 /* fullspeed uses linear encoding */
1875 if (USB_SPEED_FULL == urb->dev->speed) {
1876 interval = epd->bInterval;
1877 if (!interval)
1878 interval = 1;
1879 }
1880 /* FALLTHROUGH */
1881 case USB_ENDPOINT_XFER_ISOC:
1882 /* iso always uses log encoding */
1883 break;
1884 default:
1885 /* REVISIT we actually want to use NAK limits, hinting to the
1886 * transfer scheduling logic to try some other qh, e.g. try
1887 * for 2 msec first:
1888 *
1889 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
1890 *
1891 * The downside of disabling this is that transfer scheduling
1892 * gets VERY unfair for nonperiodic transfers; a misbehaving
1893 * peripheral could make that hurt. Or for reads, one that's
1894 * perfectly normal: network and other drivers keep reads
1895 * posted at all times, having one pending for a week should
1896 * be perfectly safe.
1897 *
1898 * The upside of disabling it is avoidng transfer scheduling
1899 * code to put this aside for while.
1900 */
1901 interval = 0;
1902 }
1903 qh->intv_reg = interval;
1904
1905 /* precompute addressing for external hub/tt ports */
1906 if (musb->is_multipoint) {
1907 struct usb_device *parent = urb->dev->parent;
1908
1909 if (parent != hcd->self.root_hub) {
1910 qh->h_addr_reg = (u8) parent->devnum;
1911
1912 /* set up tt info if needed */
1913 if (urb->dev->tt) {
1914 qh->h_port_reg = (u8) urb->dev->ttport;
1915 if (urb->dev->tt->hub)
1916 qh->h_addr_reg =
1917 (u8) urb->dev->tt->hub->devnum;
1918 if (urb->dev->tt->multi)
1919 qh->h_addr_reg |= 0x80;
1920 }
1921 }
1922 }
1923
1924 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
1925 * until we get real dma queues (with an entry for each urb/buffer),
1926 * we only have work to do in the former case.
1927 */
1928 spin_lock_irqsave(&musb->lock, flags);
1929 if (hep->hcpriv) {
1930 /* some concurrent activity submitted another urb to hep...
1931 * odd, rare, error prone, but legal.
1932 */
1933 kfree(qh);
1934 ret = 0;
1935 } else
1936 ret = musb_schedule(musb, qh,
1937 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
1938
1939 if (ret == 0) {
1940 urb->hcpriv = qh;
1941 /* FIXME set urb->start_frame for iso/intr, it's tested in
1942 * musb_start_urb(), but otherwise only konicawc cares ...
1943 */
1944 }
1945 spin_unlock_irqrestore(&musb->lock, flags);
1946
1947 done:
1948 if (ret != 0) {
1949 spin_lock_irqsave(&musb->lock, flags);
1950 usb_hcd_unlink_urb_from_ep(hcd, urb);
1951 spin_unlock_irqrestore(&musb->lock, flags);
1952 kfree(qh);
1953 }
1954 return ret;
1955 }
1956
1957
1958 /*
1959 * abort a transfer that's at the head of a hardware queue.
1960 * called with controller locked, irqs blocked
1961 * that hardware queue advances to the next transfer, unless prevented
1962 */
1963 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh, int is_in)
1964 {
1965 struct musb_hw_ep *ep = qh->hw_ep;
1966 void __iomem *epio = ep->regs;
1967 unsigned hw_end = ep->epnum;
1968 void __iomem *regs = ep->musb->mregs;
1969 u16 csr;
1970 int status = 0;
1971
1972 musb_ep_select(regs, hw_end);
1973
1974 if (is_dma_capable()) {
1975 struct dma_channel *dma;
1976
1977 dma = is_in ? ep->rx_channel : ep->tx_channel;
1978 if (dma) {
1979 status = ep->musb->dma_controller->channel_abort(dma);
1980 DBG(status ? 1 : 3,
1981 "abort %cX%d DMA for urb %p --> %d\n",
1982 is_in ? 'R' : 'T', ep->epnum,
1983 urb, status);
1984 urb->actual_length += dma->actual_len;
1985 }
1986 }
1987
1988 /* turn off DMA requests, discard state, stop polling ... */
1989 if (is_in) {
1990 /* giveback saves bulk toggle */
1991 csr = musb_h_flush_rxfifo(ep, 0);
1992
1993 /* REVISIT we still get an irq; should likely clear the
1994 * endpoint's irq status here to avoid bogus irqs.
1995 * clearing that status is platform-specific...
1996 */
1997 } else {
1998 musb_h_tx_flush_fifo(ep);
1999 csr = musb_readw(epio, MUSB_TXCSR);
2000 csr &= ~(MUSB_TXCSR_AUTOSET
2001 | MUSB_TXCSR_DMAENAB
2002 | MUSB_TXCSR_H_RXSTALL
2003 | MUSB_TXCSR_H_NAKTIMEOUT
2004 | MUSB_TXCSR_H_ERROR
2005 | MUSB_TXCSR_TXPKTRDY);
2006 musb_writew(epio, MUSB_TXCSR, csr);
2007 /* REVISIT may need to clear FLUSHFIFO ... */
2008 musb_writew(epio, MUSB_TXCSR, csr);
2009 /* flush cpu writebuffer */
2010 csr = musb_readw(epio, MUSB_TXCSR);
2011 }
2012 if (status == 0)
2013 musb_advance_schedule(ep->musb, urb, ep, is_in);
2014 return status;
2015 }
2016
2017 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2018 {
2019 struct musb *musb = hcd_to_musb(hcd);
2020 struct musb_qh *qh;
2021 struct list_head *sched;
2022 unsigned long flags;
2023 int ret;
2024
2025 DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
2026 usb_pipedevice(urb->pipe),
2027 usb_pipeendpoint(urb->pipe),
2028 usb_pipein(urb->pipe) ? "in" : "out");
2029
2030 spin_lock_irqsave(&musb->lock, flags);
2031 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2032 if (ret)
2033 goto done;
2034
2035 qh = urb->hcpriv;
2036 if (!qh)
2037 goto done;
2038
2039 /* Any URB not actively programmed into endpoint hardware can be
2040 * immediately given back. Such an URB must be at the head of its
2041 * endpoint queue, unless someday we get real DMA queues. And even
2042 * then, it might not be known to the hardware...
2043 *
2044 * Otherwise abort current transfer, pending dma, etc.; urb->status
2045 * has already been updated. This is a synchronous abort; it'd be
2046 * OK to hold off until after some IRQ, though.
2047 */
2048 if (!qh->is_ready || urb->urb_list.prev != &qh->hep->urb_list)
2049 ret = -EINPROGRESS;
2050 else {
2051 switch (qh->type) {
2052 case USB_ENDPOINT_XFER_CONTROL:
2053 sched = &musb->control;
2054 break;
2055 case USB_ENDPOINT_XFER_BULK:
2056 if (qh->mux == 1) {
2057 if (usb_pipein(urb->pipe))
2058 sched = &musb->in_bulk;
2059 else
2060 sched = &musb->out_bulk;
2061 break;
2062 }
2063 default:
2064 /* REVISIT when we get a schedule tree, periodic
2065 * transfers won't always be at the head of a
2066 * singleton queue...
2067 */
2068 sched = NULL;
2069 break;
2070 }
2071 }
2072
2073 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2074 if (ret < 0 || (sched && qh != first_qh(sched))) {
2075 int ready = qh->is_ready;
2076
2077 ret = 0;
2078 qh->is_ready = 0;
2079 __musb_giveback(musb, urb, 0);
2080 qh->is_ready = ready;
2081 } else
2082 ret = musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
2083 done:
2084 spin_unlock_irqrestore(&musb->lock, flags);
2085 return ret;
2086 }
2087
2088 /* disable an endpoint */
2089 static void
2090 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2091 {
2092 u8 epnum = hep->desc.bEndpointAddress;
2093 unsigned long flags;
2094 struct musb *musb = hcd_to_musb(hcd);
2095 u8 is_in = epnum & USB_DIR_IN;
2096 struct musb_qh *qh = hep->hcpriv;
2097 struct urb *urb, *tmp;
2098 struct list_head *sched;
2099
2100 if (!qh)
2101 return;
2102
2103 spin_lock_irqsave(&musb->lock, flags);
2104
2105 switch (qh->type) {
2106 case USB_ENDPOINT_XFER_CONTROL:
2107 sched = &musb->control;
2108 break;
2109 case USB_ENDPOINT_XFER_BULK:
2110 if (qh->mux == 1) {
2111 if (is_in)
2112 sched = &musb->in_bulk;
2113 else
2114 sched = &musb->out_bulk;
2115 break;
2116 }
2117 default:
2118 /* REVISIT when we get a schedule tree, periodic transfers
2119 * won't always be at the head of a singleton queue...
2120 */
2121 sched = NULL;
2122 break;
2123 }
2124
2125 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2126
2127 /* kick first urb off the hardware, if needed */
2128 qh->is_ready = 0;
2129 if (!sched || qh == first_qh(sched)) {
2130 urb = next_urb(qh);
2131
2132 /* make software (then hardware) stop ASAP */
2133 if (!urb->unlinked)
2134 urb->status = -ESHUTDOWN;
2135
2136 /* cleanup */
2137 musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
2138 } else
2139 urb = NULL;
2140
2141 /* then just nuke all the others */
2142 list_for_each_entry_safe_from(urb, tmp, &hep->urb_list, urb_list)
2143 musb_giveback(qh, urb, -ESHUTDOWN);
2144
2145 spin_unlock_irqrestore(&musb->lock, flags);
2146 }
2147
2148 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2149 {
2150 struct musb *musb = hcd_to_musb(hcd);
2151
2152 return musb_readw(musb->mregs, MUSB_FRAME);
2153 }
2154
2155 static int musb_h_start(struct usb_hcd *hcd)
2156 {
2157 struct musb *musb = hcd_to_musb(hcd);
2158
2159 /* NOTE: musb_start() is called when the hub driver turns
2160 * on port power, or when (OTG) peripheral starts.
2161 */
2162 hcd->state = HC_STATE_RUNNING;
2163 musb->port1_status = 0;
2164 return 0;
2165 }
2166
2167 static void musb_h_stop(struct usb_hcd *hcd)
2168 {
2169 musb_stop(hcd_to_musb(hcd));
2170 hcd->state = HC_STATE_HALT;
2171 }
2172
2173 static int musb_bus_suspend(struct usb_hcd *hcd)
2174 {
2175 struct musb *musb = hcd_to_musb(hcd);
2176
2177 if (musb->xceiv.state == OTG_STATE_A_SUSPEND)
2178 return 0;
2179
2180 if (is_host_active(musb) && musb->is_active) {
2181 WARNING("trying to suspend as %s is_active=%i\n",
2182 otg_state_string(musb), musb->is_active);
2183 return -EBUSY;
2184 } else
2185 return 0;
2186 }
2187
2188 static int musb_bus_resume(struct usb_hcd *hcd)
2189 {
2190 /* resuming child port does the work */
2191 return 0;
2192 }
2193
2194 const struct hc_driver musb_hc_driver = {
2195 .description = "musb-hcd",
2196 .product_desc = "MUSB HDRC host driver",
2197 .hcd_priv_size = sizeof(struct musb),
2198 .flags = HCD_USB2 | HCD_MEMORY,
2199
2200 /* not using irq handler or reset hooks from usbcore, since
2201 * those must be shared with peripheral code for OTG configs
2202 */
2203
2204 .start = musb_h_start,
2205 .stop = musb_h_stop,
2206
2207 .get_frame_number = musb_h_get_frame_number,
2208
2209 .urb_enqueue = musb_urb_enqueue,
2210 .urb_dequeue = musb_urb_dequeue,
2211 .endpoint_disable = musb_h_disable,
2212
2213 .hub_status_data = musb_hub_status_data,
2214 .hub_control = musb_hub_control,
2215 .bus_suspend = musb_bus_suspend,
2216 .bus_resume = musb_bus_resume,
2217 /* .start_port_reset = NULL, */
2218 /* .hub_irq_enable = NULL, */
2219 };
Support for the Chinese Samsung S3C2440 based development boards