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ptrace: reintroduce __ptrace_detach() as a callee of ptrace_exit()
[linux-2.6/mini2440.git] / drivers / char / synclink_gt.c
blob6ec6e13d47d72c641293b6a1819e5b5a38a12d29
1 /*
2 * Device driver for Microgate SyncLink GT serial adapters.
3 *
4 * written by Paul Fulghum for Microgate Corporation
5 * paulkf@microgate.com
6 *
7 * Microgate and SyncLink are trademarks of Microgate Corporation
8 *
9 * This code is released under the GNU General Public License (GPL)
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
21 * OF THE POSSIBILITY OF SUCH DAMAGE.
22 */
23
24 /*
25 * DEBUG OUTPUT DEFINITIONS
26 *
27 * uncomment lines below to enable specific types of debug output
28 *
29 * DBGINFO information - most verbose output
30 * DBGERR serious errors
31 * DBGBH bottom half service routine debugging
32 * DBGISR interrupt service routine debugging
33 * DBGDATA output receive and transmit data
34 * DBGTBUF output transmit DMA buffers and registers
35 * DBGRBUF output receive DMA buffers and registers
36 */
37
38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
43 //#define DBGTBUF(info) dump_tbufs(info)
44 //#define DBGRBUF(info) dump_rbufs(info)
45
46
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/signal.h>
50 #include <linux/sched.h>
51 #include <linux/timer.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/tty.h>
55 #include <linux/tty_flip.h>
56 #include <linux/serial.h>
57 #include <linux/major.h>
58 #include <linux/string.h>
59 #include <linux/fcntl.h>
60 #include <linux/ptrace.h>
61 #include <linux/ioport.h>
62 #include <linux/mm.h>
63 #include <linux/seq_file.h>
64 #include <linux/slab.h>
65 #include <linux/netdevice.h>
66 #include <linux/vmalloc.h>
67 #include <linux/init.h>
68 #include <linux/delay.h>
69 #include <linux/ioctl.h>
70 #include <linux/termios.h>
71 #include <linux/bitops.h>
72 #include <linux/workqueue.h>
73 #include <linux/hdlc.h>
74 #include <linux/synclink.h>
75
76 #include <asm/system.h>
77 #include <asm/io.h>
78 #include <asm/irq.h>
79 #include <asm/dma.h>
80 #include <asm/types.h>
81 #include <asm/uaccess.h>
82
83 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
84 #define SYNCLINK_GENERIC_HDLC 1
85 #else
86 #define SYNCLINK_GENERIC_HDLC 0
87 #endif
88
89 /*
90 * module identification
91 */
92 static char *driver_name = "SyncLink GT";
93 static char *tty_driver_name = "synclink_gt";
94 static char *tty_dev_prefix = "ttySLG";
95 MODULE_LICENSE("GPL");
96 #define MGSL_MAGIC 0x5401
97 #define MAX_DEVICES 32
98
99 static struct pci_device_id pci_table[] = {
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
104 {0,}, /* terminate list */
105 };
106 MODULE_DEVICE_TABLE(pci, pci_table);
107
108 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
109 static void remove_one(struct pci_dev *dev);
110 static struct pci_driver pci_driver = {
111 .name = "synclink_gt",
112 .id_table = pci_table,
113 .probe = init_one,
114 .remove = __devexit_p(remove_one),
115 };
116
117 static bool pci_registered;
118
119 /*
120 * module configuration and status
121 */
122 static struct slgt_info *slgt_device_list;
123 static int slgt_device_count;
124
125 static int ttymajor;
126 static int debug_level;
127 static int maxframe[MAX_DEVICES];
128
129 module_param(ttymajor, int, 0);
130 module_param(debug_level, int, 0);
131 module_param_array(maxframe, int, NULL, 0);
132
133 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
134 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
135 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
136
137 /*
138 * tty support and callbacks
139 */
140 static struct tty_driver *serial_driver;
141
142 static int open(struct tty_struct *tty, struct file * filp);
143 static void close(struct tty_struct *tty, struct file * filp);
144 static void hangup(struct tty_struct *tty);
145 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
146
147 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
148 static int put_char(struct tty_struct *tty, unsigned char ch);
149 static void send_xchar(struct tty_struct *tty, char ch);
150 static void wait_until_sent(struct tty_struct *tty, int timeout);
151 static int write_room(struct tty_struct *tty);
152 static void flush_chars(struct tty_struct *tty);
153 static void flush_buffer(struct tty_struct *tty);
154 static void tx_hold(struct tty_struct *tty);
155 static void tx_release(struct tty_struct *tty);
156
157 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
158 static int chars_in_buffer(struct tty_struct *tty);
159 static void throttle(struct tty_struct * tty);
160 static void unthrottle(struct tty_struct * tty);
161 static int set_break(struct tty_struct *tty, int break_state);
162
163 /*
164 * generic HDLC support and callbacks
165 */
166 #if SYNCLINK_GENERIC_HDLC
167 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
168 static void hdlcdev_tx_done(struct slgt_info *info);
169 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
170 static int hdlcdev_init(struct slgt_info *info);
171 static void hdlcdev_exit(struct slgt_info *info);
172 #endif
173
174
175 /*
176 * device specific structures, macros and functions
177 */
178
179 #define SLGT_MAX_PORTS 4
180 #define SLGT_REG_SIZE 256
181
182 /*
183 * conditional wait facility
184 */
185 struct cond_wait {
186 struct cond_wait *next;
187 wait_queue_head_t q;
188 wait_queue_t wait;
189 unsigned int data;
190 };
191 static void init_cond_wait(struct cond_wait *w, unsigned int data);
192 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
193 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
194 static void flush_cond_wait(struct cond_wait **head);
195
196 /*
197 * DMA buffer descriptor and access macros
198 */
199 struct slgt_desc
200 {
201 __le16 count;
202 __le16 status;
203 __le32 pbuf; /* physical address of data buffer */
204 __le32 next; /* physical address of next descriptor */
205
206 /* driver book keeping */
207 char *buf; /* virtual address of data buffer */
208 unsigned int pdesc; /* physical address of this descriptor */
209 dma_addr_t buf_dma_addr;
210 unsigned short buf_count;
211 };
212
213 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
214 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
215 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
216 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
217 #define desc_count(a) (le16_to_cpu((a).count))
218 #define desc_status(a) (le16_to_cpu((a).status))
219 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
220 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
221 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
222 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
223 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
224
225 struct _input_signal_events {
226 int ri_up;
227 int ri_down;
228 int dsr_up;
229 int dsr_down;
230 int dcd_up;
231 int dcd_down;
232 int cts_up;
233 int cts_down;
234 };
235
236 /*
237 * device instance data structure
238 */
239 struct slgt_info {
240 void *if_ptr; /* General purpose pointer (used by SPPP) */
241 struct tty_port port;
242
243 struct slgt_info *next_device; /* device list link */
244
245 int magic;
246
247 char device_name[25];
248 struct pci_dev *pdev;
249
250 int port_count; /* count of ports on adapter */
251 int adapter_num; /* adapter instance number */
252 int port_num; /* port instance number */
253
254 /* array of pointers to port contexts on this adapter */
255 struct slgt_info *port_array[SLGT_MAX_PORTS];
256
257 int line; /* tty line instance number */
258
259 struct mgsl_icount icount;
260
261 int timeout;
262 int x_char; /* xon/xoff character */
263 unsigned int read_status_mask;
264 unsigned int ignore_status_mask;
265
266 wait_queue_head_t status_event_wait_q;
267 wait_queue_head_t event_wait_q;
268 struct timer_list tx_timer;
269 struct timer_list rx_timer;
270
271 unsigned int gpio_present;
272 struct cond_wait *gpio_wait_q;
273
274 spinlock_t lock; /* spinlock for synchronizing with ISR */
275
276 struct work_struct task;
277 u32 pending_bh;
278 bool bh_requested;
279 bool bh_running;
280
281 int isr_overflow;
282 bool irq_requested; /* true if IRQ requested */
283 bool irq_occurred; /* for diagnostics use */
284
285 /* device configuration */
286
287 unsigned int bus_type;
288 unsigned int irq_level;
289 unsigned long irq_flags;
290
291 unsigned char __iomem * reg_addr; /* memory mapped registers address */
292 u32 phys_reg_addr;
293 bool reg_addr_requested;
294
295 MGSL_PARAMS params; /* communications parameters */
296 u32 idle_mode;
297 u32 max_frame_size; /* as set by device config */
298
299 unsigned int rbuf_fill_level;
300 unsigned int if_mode;
301
302 /* device status */
303
304 bool rx_enabled;
305 bool rx_restart;
306
307 bool tx_enabled;
308 bool tx_active;
309
310 unsigned char signals; /* serial signal states */
311 int init_error; /* initialization error */
312
313 unsigned char *tx_buf;
314 int tx_count;
315
316 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
317 char char_buf[MAX_ASYNC_BUFFER_SIZE];
318 bool drop_rts_on_tx_done;
319 struct _input_signal_events input_signal_events;
320
321 int dcd_chkcount; /* check counts to prevent */
322 int cts_chkcount; /* too many IRQs if a signal */
323 int dsr_chkcount; /* is floating */
324 int ri_chkcount;
325
326 char *bufs; /* virtual address of DMA buffer lists */
327 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
328
329 unsigned int rbuf_count;
330 struct slgt_desc *rbufs;
331 unsigned int rbuf_current;
332 unsigned int rbuf_index;
333
334 unsigned int tbuf_count;
335 struct slgt_desc *tbufs;
336 unsigned int tbuf_current;
337 unsigned int tbuf_start;
338
339 unsigned char *tmp_rbuf;
340 unsigned int tmp_rbuf_count;
341
342 /* SPPP/Cisco HDLC device parts */
343
344 int netcount;
345 spinlock_t netlock;
346 #if SYNCLINK_GENERIC_HDLC
347 struct net_device *netdev;
348 #endif
349
350 };
351
352 static MGSL_PARAMS default_params = {
353 .mode = MGSL_MODE_HDLC,
354 .loopback = 0,
355 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
356 .encoding = HDLC_ENCODING_NRZI_SPACE,
357 .clock_speed = 0,
358 .addr_filter = 0xff,
359 .crc_type = HDLC_CRC_16_CCITT,
360 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
361 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
362 .data_rate = 9600,
363 .data_bits = 8,
364 .stop_bits = 1,
365 .parity = ASYNC_PARITY_NONE
366 };
367
368
369 #define BH_RECEIVE 1
370 #define BH_TRANSMIT 2
371 #define BH_STATUS 4
372 #define IO_PIN_SHUTDOWN_LIMIT 100
373
374 #define DMABUFSIZE 256
375 #define DESC_LIST_SIZE 4096
376
377 #define MASK_PARITY BIT1
378 #define MASK_FRAMING BIT0
379 #define MASK_BREAK BIT14
380 #define MASK_OVERRUN BIT4
381
382 #define GSR 0x00 /* global status */
383 #define JCR 0x04 /* JTAG control */
384 #define IODR 0x08 /* GPIO direction */
385 #define IOER 0x0c /* GPIO interrupt enable */
386 #define IOVR 0x10 /* GPIO value */
387 #define IOSR 0x14 /* GPIO interrupt status */
388 #define TDR 0x80 /* tx data */
389 #define RDR 0x80 /* rx data */
390 #define TCR 0x82 /* tx control */
391 #define TIR 0x84 /* tx idle */
392 #define TPR 0x85 /* tx preamble */
393 #define RCR 0x86 /* rx control */
394 #define VCR 0x88 /* V.24 control */
395 #define CCR 0x89 /* clock control */
396 #define BDR 0x8a /* baud divisor */
397 #define SCR 0x8c /* serial control */
398 #define SSR 0x8e /* serial status */
399 #define RDCSR 0x90 /* rx DMA control/status */
400 #define TDCSR 0x94 /* tx DMA control/status */
401 #define RDDAR 0x98 /* rx DMA descriptor address */
402 #define TDDAR 0x9c /* tx DMA descriptor address */
403
404 #define RXIDLE BIT14
405 #define RXBREAK BIT14
406 #define IRQ_TXDATA BIT13
407 #define IRQ_TXIDLE BIT12
408 #define IRQ_TXUNDER BIT11 /* HDLC */
409 #define IRQ_RXDATA BIT10
410 #define IRQ_RXIDLE BIT9 /* HDLC */
411 #define IRQ_RXBREAK BIT9 /* async */
412 #define IRQ_RXOVER BIT8
413 #define IRQ_DSR BIT7
414 #define IRQ_CTS BIT6
415 #define IRQ_DCD BIT5
416 #define IRQ_RI BIT4
417 #define IRQ_ALL 0x3ff0
418 #define IRQ_MASTER BIT0
419
420 #define slgt_irq_on(info, mask) \
421 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
422 #define slgt_irq_off(info, mask) \
423 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
424
425 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
426 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
427 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
428 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
429 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
430 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
431
432 static void msc_set_vcr(struct slgt_info *info);
433
434 static int startup(struct slgt_info *info);
435 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
436 static void shutdown(struct slgt_info *info);
437 static void program_hw(struct slgt_info *info);
438 static void change_params(struct slgt_info *info);
439
440 static int register_test(struct slgt_info *info);
441 static int irq_test(struct slgt_info *info);
442 static int loopback_test(struct slgt_info *info);
443 static int adapter_test(struct slgt_info *info);
444
445 static void reset_adapter(struct slgt_info *info);
446 static void reset_port(struct slgt_info *info);
447 static void async_mode(struct slgt_info *info);
448 static void sync_mode(struct slgt_info *info);
449
450 static void rx_stop(struct slgt_info *info);
451 static void rx_start(struct slgt_info *info);
452 static void reset_rbufs(struct slgt_info *info);
453 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
454 static void rdma_reset(struct slgt_info *info);
455 static bool rx_get_frame(struct slgt_info *info);
456 static bool rx_get_buf(struct slgt_info *info);
457
458 static void tx_start(struct slgt_info *info);
459 static void tx_stop(struct slgt_info *info);
460 static void tx_set_idle(struct slgt_info *info);
461 static unsigned int free_tbuf_count(struct slgt_info *info);
462 static unsigned int tbuf_bytes(struct slgt_info *info);
463 static void reset_tbufs(struct slgt_info *info);
464 static void tdma_reset(struct slgt_info *info);
465 static void tdma_start(struct slgt_info *info);
466 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
467
468 static void get_signals(struct slgt_info *info);
469 static void set_signals(struct slgt_info *info);
470 static void enable_loopback(struct slgt_info *info);
471 static void set_rate(struct slgt_info *info, u32 data_rate);
472
473 static int bh_action(struct slgt_info *info);
474 static void bh_handler(struct work_struct *work);
475 static void bh_transmit(struct slgt_info *info);
476 static void isr_serial(struct slgt_info *info);
477 static void isr_rdma(struct slgt_info *info);
478 static void isr_txeom(struct slgt_info *info, unsigned short status);
479 static void isr_tdma(struct slgt_info *info);
480
481 static int alloc_dma_bufs(struct slgt_info *info);
482 static void free_dma_bufs(struct slgt_info *info);
483 static int alloc_desc(struct slgt_info *info);
484 static void free_desc(struct slgt_info *info);
485 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
486 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
487
488 static int alloc_tmp_rbuf(struct slgt_info *info);
489 static void free_tmp_rbuf(struct slgt_info *info);
490
491 static void tx_timeout(unsigned long context);
492 static void rx_timeout(unsigned long context);
493
494 /*
495 * ioctl handlers
496 */
497 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
498 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
499 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
500 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
501 static int set_txidle(struct slgt_info *info, int idle_mode);
502 static int tx_enable(struct slgt_info *info, int enable);
503 static int tx_abort(struct slgt_info *info);
504 static int rx_enable(struct slgt_info *info, int enable);
505 static int modem_input_wait(struct slgt_info *info,int arg);
506 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
507 static int tiocmget(struct tty_struct *tty, struct file *file);
508 static int tiocmset(struct tty_struct *tty, struct file *file,
509 unsigned int set, unsigned int clear);
510 static int set_break(struct tty_struct *tty, int break_state);
511 static int get_interface(struct slgt_info *info, int __user *if_mode);
512 static int set_interface(struct slgt_info *info, int if_mode);
513 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
514 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
515 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
516
517 /*
518 * driver functions
519 */
520 static void add_device(struct slgt_info *info);
521 static void device_init(int adapter_num, struct pci_dev *pdev);
522 static int claim_resources(struct slgt_info *info);
523 static void release_resources(struct slgt_info *info);
524
525 /*
526 * DEBUG OUTPUT CODE
527 */
528 #ifndef DBGINFO
529 #define DBGINFO(fmt)
530 #endif
531 #ifndef DBGERR
532 #define DBGERR(fmt)
533 #endif
534 #ifndef DBGBH
535 #define DBGBH(fmt)
536 #endif
537 #ifndef DBGISR
538 #define DBGISR(fmt)
539 #endif
540
541 #ifdef DBGDATA
542 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
543 {
544 int i;
545 int linecount;
546 printk("%s %s data:\n",info->device_name, label);
547 while(count) {
548 linecount = (count > 16) ? 16 : count;
549 for(i=0; i < linecount; i++)
550 printk("%02X ",(unsigned char)data[i]);
551 for(;i<17;i++)
552 printk(" ");
553 for(i=0;i<linecount;i++) {
554 if (data[i]>=040 && data[i]<=0176)
555 printk("%c",data[i]);
556 else
557 printk(".");
558 }
559 printk("\n");
560 data += linecount;
561 count -= linecount;
562 }
563 }
564 #else
565 #define DBGDATA(info, buf, size, label)
566 #endif
567
568 #ifdef DBGTBUF
569 static void dump_tbufs(struct slgt_info *info)
570 {
571 int i;
572 printk("tbuf_current=%d\n", info->tbuf_current);
573 for (i=0 ; i < info->tbuf_count ; i++) {
574 printk("%d: count=%04X status=%04X\n",
575 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
576 }
577 }
578 #else
579 #define DBGTBUF(info)
580 #endif
581
582 #ifdef DBGRBUF
583 static void dump_rbufs(struct slgt_info *info)
584 {
585 int i;
586 printk("rbuf_current=%d\n", info->rbuf_current);
587 for (i=0 ; i < info->rbuf_count ; i++) {
588 printk("%d: count=%04X status=%04X\n",
589 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
590 }
591 }
592 #else
593 #define DBGRBUF(info)
594 #endif
595
596 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
597 {
598 #ifdef SANITY_CHECK
599 if (!info) {
600 printk("null struct slgt_info for (%s) in %s\n", devname, name);
601 return 1;
602 }
603 if (info->magic != MGSL_MAGIC) {
604 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
605 return 1;
606 }
607 #else
608 if (!info)
609 return 1;
610 #endif
611 return 0;
612 }
613
614 /**
615 * line discipline callback wrappers
616 *
617 * The wrappers maintain line discipline references
618 * while calling into the line discipline.
619 *
620 * ldisc_receive_buf - pass receive data to line discipline
621 */
622 static void ldisc_receive_buf(struct tty_struct *tty,
623 const __u8 *data, char *flags, int count)
624 {
625 struct tty_ldisc *ld;
626 if (!tty)
627 return;
628 ld = tty_ldisc_ref(tty);
629 if (ld) {
630 if (ld->ops->receive_buf)
631 ld->ops->receive_buf(tty, data, flags, count);
632 tty_ldisc_deref(ld);
633 }
634 }
635
636 /* tty callbacks */
637
638 static int open(struct tty_struct *tty, struct file *filp)
639 {
640 struct slgt_info *info;
641 int retval, line;
642 unsigned long flags;
643
644 line = tty->index;
645 if ((line < 0) || (line >= slgt_device_count)) {
646 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
647 return -ENODEV;
648 }
649
650 info = slgt_device_list;
651 while(info && info->line != line)
652 info = info->next_device;
653 if (sanity_check(info, tty->name, "open"))
654 return -ENODEV;
655 if (info->init_error) {
656 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
657 return -ENODEV;
658 }
659
660 tty->driver_data = info;
661 info->port.tty = tty;
662
663 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
664
665 /* If port is closing, signal caller to try again */
666 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
667 if (info->port.flags & ASYNC_CLOSING)
668 interruptible_sleep_on(&info->port.close_wait);
669 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
670 -EAGAIN : -ERESTARTSYS);
671 goto cleanup;
672 }
673
674 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
675
676 spin_lock_irqsave(&info->netlock, flags);
677 if (info->netcount) {
678 retval = -EBUSY;
679 spin_unlock_irqrestore(&info->netlock, flags);
680 goto cleanup;
681 }
682 info->port.count++;
683 spin_unlock_irqrestore(&info->netlock, flags);
684
685 if (info->port.count == 1) {
686 /* 1st open on this device, init hardware */
687 retval = startup(info);
688 if (retval < 0)
689 goto cleanup;
690 }
691
692 retval = block_til_ready(tty, filp, info);
693 if (retval) {
694 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
695 goto cleanup;
696 }
697
698 retval = 0;
699
700 cleanup:
701 if (retval) {
702 if (tty->count == 1)
703 info->port.tty = NULL; /* tty layer will release tty struct */
704 if(info->port.count)
705 info->port.count--;
706 }
707
708 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
709 return retval;
710 }
711
712 static void close(struct tty_struct *tty, struct file *filp)
713 {
714 struct slgt_info *info = tty->driver_data;
715
716 if (sanity_check(info, tty->name, "close"))
717 return;
718 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
719
720 if (tty_port_close_start(&info->port, tty, filp) == 0)
721 goto cleanup;
722
723 if (info->port.flags & ASYNC_INITIALIZED)
724 wait_until_sent(tty, info->timeout);
725 flush_buffer(tty);
726 tty_ldisc_flush(tty);
727
728 shutdown(info);
729
730 tty_port_close_end(&info->port, tty);
731 info->port.tty = NULL;
732 cleanup:
733 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
734 }
735
736 static void hangup(struct tty_struct *tty)
737 {
738 struct slgt_info *info = tty->driver_data;
739
740 if (sanity_check(info, tty->name, "hangup"))
741 return;
742 DBGINFO(("%s hangup\n", info->device_name));
743
744 flush_buffer(tty);
745 shutdown(info);
746
747 info->port.count = 0;
748 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
749 info->port.tty = NULL;
750
751 wake_up_interruptible(&info->port.open_wait);
752 }
753
754 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
755 {
756 struct slgt_info *info = tty->driver_data;
757 unsigned long flags;
758
759 DBGINFO(("%s set_termios\n", tty->driver->name));
760
761 change_params(info);
762
763 /* Handle transition to B0 status */
764 if (old_termios->c_cflag & CBAUD &&
765 !(tty->termios->c_cflag & CBAUD)) {
766 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
767 spin_lock_irqsave(&info->lock,flags);
768 set_signals(info);
769 spin_unlock_irqrestore(&info->lock,flags);
770 }
771
772 /* Handle transition away from B0 status */
773 if (!(old_termios->c_cflag & CBAUD) &&
774 tty->termios->c_cflag & CBAUD) {
775 info->signals |= SerialSignal_DTR;
776 if (!(tty->termios->c_cflag & CRTSCTS) ||
777 !test_bit(TTY_THROTTLED, &tty->flags)) {
778 info->signals |= SerialSignal_RTS;
779 }
780 spin_lock_irqsave(&info->lock,flags);
781 set_signals(info);
782 spin_unlock_irqrestore(&info->lock,flags);
783 }
784
785 /* Handle turning off CRTSCTS */
786 if (old_termios->c_cflag & CRTSCTS &&
787 !(tty->termios->c_cflag & CRTSCTS)) {
788 tty->hw_stopped = 0;
789 tx_release(tty);
790 }
791 }
792
793 static int write(struct tty_struct *tty,
794 const unsigned char *buf, int count)
795 {
796 int ret = 0;
797 struct slgt_info *info = tty->driver_data;
798 unsigned long flags;
799 unsigned int bufs_needed;
800
801 if (sanity_check(info, tty->name, "write"))
802 goto cleanup;
803 DBGINFO(("%s write count=%d\n", info->device_name, count));
804
805 if (!info->tx_buf)
806 goto cleanup;
807
808 if (count > info->max_frame_size) {
809 ret = -EIO;
810 goto cleanup;
811 }
812
813 if (!count)
814 goto cleanup;
815
816 if (!info->tx_active && info->tx_count) {
817 /* send accumulated data from send_char() */
818 tx_load(info, info->tx_buf, info->tx_count);
819 goto start;
820 }
821 bufs_needed = (count/DMABUFSIZE);
822 if (count % DMABUFSIZE)
823 ++bufs_needed;
824 if (bufs_needed > free_tbuf_count(info))
825 goto cleanup;
826
827 ret = info->tx_count = count;
828 tx_load(info, buf, count);
829 goto start;
830
831 start:
832 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
833 spin_lock_irqsave(&info->lock,flags);
834 if (!info->tx_active)
835 tx_start(info);
836 else
837 tdma_start(info);
838 spin_unlock_irqrestore(&info->lock,flags);
839 }
840
841 cleanup:
842 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
843 return ret;
844 }
845
846 static int put_char(struct tty_struct *tty, unsigned char ch)
847 {
848 struct slgt_info *info = tty->driver_data;
849 unsigned long flags;
850 int ret = 0;
851
852 if (sanity_check(info, tty->name, "put_char"))
853 return 0;
854 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
855 if (!info->tx_buf)
856 return 0;
857 spin_lock_irqsave(&info->lock,flags);
858 if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
859 info->tx_buf[info->tx_count++] = ch;
860 ret = 1;
861 }
862 spin_unlock_irqrestore(&info->lock,flags);
863 return ret;
864 }
865
866 static void send_xchar(struct tty_struct *tty, char ch)
867 {
868 struct slgt_info *info = tty->driver_data;
869 unsigned long flags;
870
871 if (sanity_check(info, tty->name, "send_xchar"))
872 return;
873 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
874 info->x_char = ch;
875 if (ch) {
876 spin_lock_irqsave(&info->lock,flags);
877 if (!info->tx_enabled)
878 tx_start(info);
879 spin_unlock_irqrestore(&info->lock,flags);
880 }
881 }
882
883 static void wait_until_sent(struct tty_struct *tty, int timeout)
884 {
885 struct slgt_info *info = tty->driver_data;
886 unsigned long orig_jiffies, char_time;
887
888 if (!info )
889 return;
890 if (sanity_check(info, tty->name, "wait_until_sent"))
891 return;
892 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
893 if (!(info->port.flags & ASYNC_INITIALIZED))
894 goto exit;
895
896 orig_jiffies = jiffies;
897
898 /* Set check interval to 1/5 of estimated time to
899 * send a character, and make it at least 1. The check
900 * interval should also be less than the timeout.
901 * Note: use tight timings here to satisfy the NIST-PCTS.
902 */
903
904 lock_kernel();
905
906 if (info->params.data_rate) {
907 char_time = info->timeout/(32 * 5);
908 if (!char_time)
909 char_time++;
910 } else
911 char_time = 1;
912
913 if (timeout)
914 char_time = min_t(unsigned long, char_time, timeout);
915
916 while (info->tx_active) {
917 msleep_interruptible(jiffies_to_msecs(char_time));
918 if (signal_pending(current))
919 break;
920 if (timeout && time_after(jiffies, orig_jiffies + timeout))
921 break;
922 }
923 unlock_kernel();
924
925 exit:
926 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
927 }
928
929 static int write_room(struct tty_struct *tty)
930 {
931 struct slgt_info *info = tty->driver_data;
932 int ret;
933
934 if (sanity_check(info, tty->name, "write_room"))
935 return 0;
936 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
937 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
938 return ret;
939 }
940
941 static void flush_chars(struct tty_struct *tty)
942 {
943 struct slgt_info *info = tty->driver_data;
944 unsigned long flags;
945
946 if (sanity_check(info, tty->name, "flush_chars"))
947 return;
948 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
949
950 if (info->tx_count <= 0 || tty->stopped ||
951 tty->hw_stopped || !info->tx_buf)
952 return;
953
954 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
955
956 spin_lock_irqsave(&info->lock,flags);
957 if (!info->tx_active && info->tx_count) {
958 tx_load(info, info->tx_buf,info->tx_count);
959 tx_start(info);
960 }
961 spin_unlock_irqrestore(&info->lock,flags);
962 }
963
964 static void flush_buffer(struct tty_struct *tty)
965 {
966 struct slgt_info *info = tty->driver_data;
967 unsigned long flags;
968
969 if (sanity_check(info, tty->name, "flush_buffer"))
970 return;
971 DBGINFO(("%s flush_buffer\n", info->device_name));
972
973 spin_lock_irqsave(&info->lock,flags);
974 if (!info->tx_active)
975 info->tx_count = 0;
976 spin_unlock_irqrestore(&info->lock,flags);
977
978 tty_wakeup(tty);
979 }
980
981 /*
982 * throttle (stop) transmitter
983 */
984 static void tx_hold(struct tty_struct *tty)
985 {
986 struct slgt_info *info = tty->driver_data;
987 unsigned long flags;
988
989 if (sanity_check(info, tty->name, "tx_hold"))
990 return;
991 DBGINFO(("%s tx_hold\n", info->device_name));
992 spin_lock_irqsave(&info->lock,flags);
993 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
994 tx_stop(info);
995 spin_unlock_irqrestore(&info->lock,flags);
996 }
997
998 /*
999 * release (start) transmitter
1000 */
1001 static void tx_release(struct tty_struct *tty)
1002 {
1003 struct slgt_info *info = tty->driver_data;
1004 unsigned long flags;
1005
1006 if (sanity_check(info, tty->name, "tx_release"))
1007 return;
1008 DBGINFO(("%s tx_release\n", info->device_name));
1009 spin_lock_irqsave(&info->lock,flags);
1010 if (!info->tx_active && info->tx_count) {
1011 tx_load(info, info->tx_buf, info->tx_count);
1012 tx_start(info);
1013 }
1014 spin_unlock_irqrestore(&info->lock,flags);
1015 }
1016
1017 /*
1018 * Service an IOCTL request
1019 *
1020 * Arguments
1021 *
1022 * tty pointer to tty instance data
1023 * file pointer to associated file object for device
1024 * cmd IOCTL command code
1025 * arg command argument/context
1026 *
1027 * Return 0 if success, otherwise error code
1028 */
1029 static int ioctl(struct tty_struct *tty, struct file *file,
1030 unsigned int cmd, unsigned long arg)
1031 {
1032 struct slgt_info *info = tty->driver_data;
1033 struct mgsl_icount cnow; /* kernel counter temps */
1034 struct serial_icounter_struct __user *p_cuser; /* user space */
1035 unsigned long flags;
1036 void __user *argp = (void __user *)arg;
1037 int ret;
1038
1039 if (sanity_check(info, tty->name, "ioctl"))
1040 return -ENODEV;
1041 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1042
1043 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1044 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1045 if (tty->flags & (1 << TTY_IO_ERROR))
1046 return -EIO;
1047 }
1048
1049 lock_kernel();
1050
1051 switch (cmd) {
1052 case MGSL_IOCGPARAMS:
1053 ret = get_params(info, argp);
1054 break;
1055 case MGSL_IOCSPARAMS:
1056 ret = set_params(info, argp);
1057 break;
1058 case MGSL_IOCGTXIDLE:
1059 ret = get_txidle(info, argp);
1060 break;
1061 case MGSL_IOCSTXIDLE:
1062 ret = set_txidle(info, (int)arg);
1063 break;
1064 case MGSL_IOCTXENABLE:
1065 ret = tx_enable(info, (int)arg);
1066 break;
1067 case MGSL_IOCRXENABLE:
1068 ret = rx_enable(info, (int)arg);
1069 break;
1070 case MGSL_IOCTXABORT:
1071 ret = tx_abort(info);
1072 break;
1073 case MGSL_IOCGSTATS:
1074 ret = get_stats(info, argp);
1075 break;
1076 case MGSL_IOCWAITEVENT:
1077 ret = wait_mgsl_event(info, argp);
1078 break;
1079 case TIOCMIWAIT:
1080 ret = modem_input_wait(info,(int)arg);
1081 break;
1082 case MGSL_IOCGIF:
1083 ret = get_interface(info, argp);
1084 break;
1085 case MGSL_IOCSIF:
1086 ret = set_interface(info,(int)arg);
1087 break;
1088 case MGSL_IOCSGPIO:
1089 ret = set_gpio(info, argp);
1090 break;
1091 case MGSL_IOCGGPIO:
1092 ret = get_gpio(info, argp);
1093 break;
1094 case MGSL_IOCWAITGPIO:
1095 ret = wait_gpio(info, argp);
1096 break;
1097 case TIOCGICOUNT:
1098 spin_lock_irqsave(&info->lock,flags);
1099 cnow = info->icount;
1100 spin_unlock_irqrestore(&info->lock,flags);
1101 p_cuser = argp;
1102 if (put_user(cnow.cts, &p_cuser->cts) ||
1103 put_user(cnow.dsr, &p_cuser->dsr) ||
1104 put_user(cnow.rng, &p_cuser->rng) ||
1105 put_user(cnow.dcd, &p_cuser->dcd) ||
1106 put_user(cnow.rx, &p_cuser->rx) ||
1107 put_user(cnow.tx, &p_cuser->tx) ||
1108 put_user(cnow.frame, &p_cuser->frame) ||
1109 put_user(cnow.overrun, &p_cuser->overrun) ||
1110 put_user(cnow.parity, &p_cuser->parity) ||
1111 put_user(cnow.brk, &p_cuser->brk) ||
1112 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1113 ret = -EFAULT;
1114 ret = 0;
1115 break;
1116 default:
1117 ret = -ENOIOCTLCMD;
1118 }
1119 unlock_kernel();
1120 return ret;
1121 }
1122
1123 /*
1124 * support for 32 bit ioctl calls on 64 bit systems
1125 */
1126 #ifdef CONFIG_COMPAT
1127 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1128 {
1129 struct MGSL_PARAMS32 tmp_params;
1130
1131 DBGINFO(("%s get_params32\n", info->device_name));
1132 tmp_params.mode = (compat_ulong_t)info->params.mode;
1133 tmp_params.loopback = info->params.loopback;
1134 tmp_params.flags = info->params.flags;
1135 tmp_params.encoding = info->params.encoding;
1136 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1137 tmp_params.addr_filter = info->params.addr_filter;
1138 tmp_params.crc_type = info->params.crc_type;
1139 tmp_params.preamble_length = info->params.preamble_length;
1140 tmp_params.preamble = info->params.preamble;
1141 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1142 tmp_params.data_bits = info->params.data_bits;
1143 tmp_params.stop_bits = info->params.stop_bits;
1144 tmp_params.parity = info->params.parity;
1145 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1146 return -EFAULT;
1147 return 0;
1148 }
1149
1150 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1151 {
1152 struct MGSL_PARAMS32 tmp_params;
1153
1154 DBGINFO(("%s set_params32\n", info->device_name));
1155 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1156 return -EFAULT;
1157
1158 spin_lock(&info->lock);
1159 info->params.mode = tmp_params.mode;
1160 info->params.loopback = tmp_params.loopback;
1161 info->params.flags = tmp_params.flags;
1162 info->params.encoding = tmp_params.encoding;
1163 info->params.clock_speed = tmp_params.clock_speed;
1164 info->params.addr_filter = tmp_params.addr_filter;
1165 info->params.crc_type = tmp_params.crc_type;
1166 info->params.preamble_length = tmp_params.preamble_length;
1167 info->params.preamble = tmp_params.preamble;
1168 info->params.data_rate = tmp_params.data_rate;
1169 info->params.data_bits = tmp_params.data_bits;
1170 info->params.stop_bits = tmp_params.stop_bits;
1171 info->params.parity = tmp_params.parity;
1172 spin_unlock(&info->lock);
1173
1174 change_params(info);
1175
1176 return 0;
1177 }
1178
1179 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1180 unsigned int cmd, unsigned long arg)
1181 {
1182 struct slgt_info *info = tty->driver_data;
1183 int rc = -ENOIOCTLCMD;
1184
1185 if (sanity_check(info, tty->name, "compat_ioctl"))
1186 return -ENODEV;
1187 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1188
1189 switch (cmd) {
1190
1191 case MGSL_IOCSPARAMS32:
1192 rc = set_params32(info, compat_ptr(arg));
1193 break;
1194
1195 case MGSL_IOCGPARAMS32:
1196 rc = get_params32(info, compat_ptr(arg));
1197 break;
1198
1199 case MGSL_IOCGPARAMS:
1200 case MGSL_IOCSPARAMS:
1201 case MGSL_IOCGTXIDLE:
1202 case MGSL_IOCGSTATS:
1203 case MGSL_IOCWAITEVENT:
1204 case MGSL_IOCGIF:
1205 case MGSL_IOCSGPIO:
1206 case MGSL_IOCGGPIO:
1207 case MGSL_IOCWAITGPIO:
1208 case TIOCGICOUNT:
1209 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1210 break;
1211
1212 case MGSL_IOCSTXIDLE:
1213 case MGSL_IOCTXENABLE:
1214 case MGSL_IOCRXENABLE:
1215 case MGSL_IOCTXABORT:
1216 case TIOCMIWAIT:
1217 case MGSL_IOCSIF:
1218 rc = ioctl(tty, file, cmd, arg);
1219 break;
1220 }
1221
1222 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1223 return rc;
1224 }
1225 #else
1226 #define slgt_compat_ioctl NULL
1227 #endif /* ifdef CONFIG_COMPAT */
1228
1229 /*
1230 * proc fs support
1231 */
1232 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1233 {
1234 char stat_buf[30];
1235 unsigned long flags;
1236
1237 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1238 info->device_name, info->phys_reg_addr,
1239 info->irq_level, info->max_frame_size);
1240
1241 /* output current serial signal states */
1242 spin_lock_irqsave(&info->lock,flags);
1243 get_signals(info);
1244 spin_unlock_irqrestore(&info->lock,flags);
1245
1246 stat_buf[0] = 0;
1247 stat_buf[1] = 0;
1248 if (info->signals & SerialSignal_RTS)
1249 strcat(stat_buf, "|RTS");
1250 if (info->signals & SerialSignal_CTS)
1251 strcat(stat_buf, "|CTS");
1252 if (info->signals & SerialSignal_DTR)
1253 strcat(stat_buf, "|DTR");
1254 if (info->signals & SerialSignal_DSR)
1255 strcat(stat_buf, "|DSR");
1256 if (info->signals & SerialSignal_DCD)
1257 strcat(stat_buf, "|CD");
1258 if (info->signals & SerialSignal_RI)
1259 strcat(stat_buf, "|RI");
1260
1261 if (info->params.mode != MGSL_MODE_ASYNC) {
1262 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1263 info->icount.txok, info->icount.rxok);
1264 if (info->icount.txunder)
1265 seq_printf(m, " txunder:%d", info->icount.txunder);
1266 if (info->icount.txabort)
1267 seq_printf(m, " txabort:%d", info->icount.txabort);
1268 if (info->icount.rxshort)
1269 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1270 if (info->icount.rxlong)
1271 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1272 if (info->icount.rxover)
1273 seq_printf(m, " rxover:%d", info->icount.rxover);
1274 if (info->icount.rxcrc)
1275 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1276 } else {
1277 seq_printf(m, "\tASYNC tx:%d rx:%d",
1278 info->icount.tx, info->icount.rx);
1279 if (info->icount.frame)
1280 seq_printf(m, " fe:%d", info->icount.frame);
1281 if (info->icount.parity)
1282 seq_printf(m, " pe:%d", info->icount.parity);
1283 if (info->icount.brk)
1284 seq_printf(m, " brk:%d", info->icount.brk);
1285 if (info->icount.overrun)
1286 seq_printf(m, " oe:%d", info->icount.overrun);
1287 }
1288
1289 /* Append serial signal status to end */
1290 seq_printf(m, " %s\n", stat_buf+1);
1291
1292 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1293 info->tx_active,info->bh_requested,info->bh_running,
1294 info->pending_bh);
1295 }
1296
1297 /* Called to print information about devices
1298 */
1299 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1300 {
1301 struct slgt_info *info;
1302
1303 seq_puts(m, "synclink_gt driver\n");
1304
1305 info = slgt_device_list;
1306 while( info ) {
1307 line_info(m, info);
1308 info = info->next_device;
1309 }
1310 return 0;
1311 }
1312
1313 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1314 {
1315 return single_open(file, synclink_gt_proc_show, NULL);
1316 }
1317
1318 static const struct file_operations synclink_gt_proc_fops = {
1319 .owner = THIS_MODULE,
1320 .open = synclink_gt_proc_open,
1321 .read = seq_read,
1322 .llseek = seq_lseek,
1323 .release = single_release,
1324 };
1325
1326 /*
1327 * return count of bytes in transmit buffer
1328 */
1329 static int chars_in_buffer(struct tty_struct *tty)
1330 {
1331 struct slgt_info *info = tty->driver_data;
1332 int count;
1333 if (sanity_check(info, tty->name, "chars_in_buffer"))
1334 return 0;
1335 count = tbuf_bytes(info);
1336 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1337 return count;
1338 }
1339
1340 /*
1341 * signal remote device to throttle send data (our receive data)
1342 */
1343 static void throttle(struct tty_struct * tty)
1344 {
1345 struct slgt_info *info = tty->driver_data;
1346 unsigned long flags;
1347
1348 if (sanity_check(info, tty->name, "throttle"))
1349 return;
1350 DBGINFO(("%s throttle\n", info->device_name));
1351 if (I_IXOFF(tty))
1352 send_xchar(tty, STOP_CHAR(tty));
1353 if (tty->termios->c_cflag & CRTSCTS) {
1354 spin_lock_irqsave(&info->lock,flags);
1355 info->signals &= ~SerialSignal_RTS;
1356 set_signals(info);
1357 spin_unlock_irqrestore(&info->lock,flags);
1358 }
1359 }
1360
1361 /*
1362 * signal remote device to stop throttling send data (our receive data)
1363 */
1364 static void unthrottle(struct tty_struct * tty)
1365 {
1366 struct slgt_info *info = tty->driver_data;
1367 unsigned long flags;
1368
1369 if (sanity_check(info, tty->name, "unthrottle"))
1370 return;
1371 DBGINFO(("%s unthrottle\n", info->device_name));
1372 if (I_IXOFF(tty)) {
1373 if (info->x_char)
1374 info->x_char = 0;
1375 else
1376 send_xchar(tty, START_CHAR(tty));
1377 }
1378 if (tty->termios->c_cflag & CRTSCTS) {
1379 spin_lock_irqsave(&info->lock,flags);
1380 info->signals |= SerialSignal_RTS;
1381 set_signals(info);
1382 spin_unlock_irqrestore(&info->lock,flags);
1383 }
1384 }
1385
1386 /*
1387 * set or clear transmit break condition
1388 * break_state -1=set break condition, 0=clear
1389 */
1390 static int set_break(struct tty_struct *tty, int break_state)
1391 {
1392 struct slgt_info *info = tty->driver_data;
1393 unsigned short value;
1394 unsigned long flags;
1395
1396 if (sanity_check(info, tty->name, "set_break"))
1397 return -EINVAL;
1398 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1399
1400 spin_lock_irqsave(&info->lock,flags);
1401 value = rd_reg16(info, TCR);
1402 if (break_state == -1)
1403 value |= BIT6;
1404 else
1405 value &= ~BIT6;
1406 wr_reg16(info, TCR, value);
1407 spin_unlock_irqrestore(&info->lock,flags);
1408 return 0;
1409 }
1410
1411 #if SYNCLINK_GENERIC_HDLC
1412
1413 /**
1414 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1415 * set encoding and frame check sequence (FCS) options
1416 *
1417 * dev pointer to network device structure
1418 * encoding serial encoding setting
1419 * parity FCS setting
1420 *
1421 * returns 0 if success, otherwise error code
1422 */
1423 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1424 unsigned short parity)
1425 {
1426 struct slgt_info *info = dev_to_port(dev);
1427 unsigned char new_encoding;
1428 unsigned short new_crctype;
1429
1430 /* return error if TTY interface open */
1431 if (info->port.count)
1432 return -EBUSY;
1433
1434 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1435
1436 switch (encoding)
1437 {
1438 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1439 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1440 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1441 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1442 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1443 default: return -EINVAL;
1444 }
1445
1446 switch (parity)
1447 {
1448 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1449 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1450 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1451 default: return -EINVAL;
1452 }
1453
1454 info->params.encoding = new_encoding;
1455 info->params.crc_type = new_crctype;
1456
1457 /* if network interface up, reprogram hardware */
1458 if (info->netcount)
1459 program_hw(info);
1460
1461 return 0;
1462 }
1463
1464 /**
1465 * called by generic HDLC layer to send frame
1466 *
1467 * skb socket buffer containing HDLC frame
1468 * dev pointer to network device structure
1469 *
1470 * returns 0 if success, otherwise error code
1471 */
1472 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1473 {
1474 struct slgt_info *info = dev_to_port(dev);
1475 unsigned long flags;
1476
1477 DBGINFO(("%s hdlc_xmit\n", dev->name));
1478
1479 /* stop sending until this frame completes */
1480 netif_stop_queue(dev);
1481
1482 /* copy data to device buffers */
1483 info->tx_count = skb->len;
1484 tx_load(info, skb->data, skb->len);
1485
1486 /* update network statistics */
1487 dev->stats.tx_packets++;
1488 dev->stats.tx_bytes += skb->len;
1489
1490 /* done with socket buffer, so free it */
1491 dev_kfree_skb(skb);
1492
1493 /* save start time for transmit timeout detection */
1494 dev->trans_start = jiffies;
1495
1496 /* start hardware transmitter if necessary */
1497 spin_lock_irqsave(&info->lock,flags);
1498 if (!info->tx_active)
1499 tx_start(info);
1500 spin_unlock_irqrestore(&info->lock,flags);
1501
1502 return 0;
1503 }
1504
1505 /**
1506 * called by network layer when interface enabled
1507 * claim resources and initialize hardware
1508 *
1509 * dev pointer to network device structure
1510 *
1511 * returns 0 if success, otherwise error code
1512 */
1513 static int hdlcdev_open(struct net_device *dev)
1514 {
1515 struct slgt_info *info = dev_to_port(dev);
1516 int rc;
1517 unsigned long flags;
1518
1519 if (!try_module_get(THIS_MODULE))
1520 return -EBUSY;
1521
1522 DBGINFO(("%s hdlcdev_open\n", dev->name));
1523
1524 /* generic HDLC layer open processing */
1525 if ((rc = hdlc_open(dev)))
1526 return rc;
1527
1528 /* arbitrate between network and tty opens */
1529 spin_lock_irqsave(&info->netlock, flags);
1530 if (info->port.count != 0 || info->netcount != 0) {
1531 DBGINFO(("%s hdlc_open busy\n", dev->name));
1532 spin_unlock_irqrestore(&info->netlock, flags);
1533 return -EBUSY;
1534 }
1535 info->netcount=1;
1536 spin_unlock_irqrestore(&info->netlock, flags);
1537
1538 /* claim resources and init adapter */
1539 if ((rc = startup(info)) != 0) {
1540 spin_lock_irqsave(&info->netlock, flags);
1541 info->netcount=0;
1542 spin_unlock_irqrestore(&info->netlock, flags);
1543 return rc;
1544 }
1545
1546 /* assert DTR and RTS, apply hardware settings */
1547 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1548 program_hw(info);
1549
1550 /* enable network layer transmit */
1551 dev->trans_start = jiffies;
1552 netif_start_queue(dev);
1553
1554 /* inform generic HDLC layer of current DCD status */
1555 spin_lock_irqsave(&info->lock, flags);
1556 get_signals(info);
1557 spin_unlock_irqrestore(&info->lock, flags);
1558 if (info->signals & SerialSignal_DCD)
1559 netif_carrier_on(dev);
1560 else
1561 netif_carrier_off(dev);
1562 return 0;
1563 }
1564
1565 /**
1566 * called by network layer when interface is disabled
1567 * shutdown hardware and release resources
1568 *
1569 * dev pointer to network device structure
1570 *
1571 * returns 0 if success, otherwise error code
1572 */
1573 static int hdlcdev_close(struct net_device *dev)
1574 {
1575 struct slgt_info *info = dev_to_port(dev);
1576 unsigned long flags;
1577
1578 DBGINFO(("%s hdlcdev_close\n", dev->name));
1579
1580 netif_stop_queue(dev);
1581
1582 /* shutdown adapter and release resources */
1583 shutdown(info);
1584
1585 hdlc_close(dev);
1586
1587 spin_lock_irqsave(&info->netlock, flags);
1588 info->netcount=0;
1589 spin_unlock_irqrestore(&info->netlock, flags);
1590
1591 module_put(THIS_MODULE);
1592 return 0;
1593 }
1594
1595 /**
1596 * called by network layer to process IOCTL call to network device
1597 *
1598 * dev pointer to network device structure
1599 * ifr pointer to network interface request structure
1600 * cmd IOCTL command code
1601 *
1602 * returns 0 if success, otherwise error code
1603 */
1604 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1605 {
1606 const size_t size = sizeof(sync_serial_settings);
1607 sync_serial_settings new_line;
1608 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1609 struct slgt_info *info = dev_to_port(dev);
1610 unsigned int flags;
1611
1612 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1613
1614 /* return error if TTY interface open */
1615 if (info->port.count)
1616 return -EBUSY;
1617
1618 if (cmd != SIOCWANDEV)
1619 return hdlc_ioctl(dev, ifr, cmd);
1620
1621 switch(ifr->ifr_settings.type) {
1622 case IF_GET_IFACE: /* return current sync_serial_settings */
1623
1624 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1625 if (ifr->ifr_settings.size < size) {
1626 ifr->ifr_settings.size = size; /* data size wanted */
1627 return -ENOBUFS;
1628 }
1629
1630 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1631 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1632 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1633 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1634
1635 switch (flags){
1636 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1637 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1638 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1639 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1640 default: new_line.clock_type = CLOCK_DEFAULT;
1641 }
1642
1643 new_line.clock_rate = info->params.clock_speed;
1644 new_line.loopback = info->params.loopback ? 1:0;
1645
1646 if (copy_to_user(line, &new_line, size))
1647 return -EFAULT;
1648 return 0;
1649
1650 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1651
1652 if(!capable(CAP_NET_ADMIN))
1653 return -EPERM;
1654 if (copy_from_user(&new_line, line, size))
1655 return -EFAULT;
1656
1657 switch (new_line.clock_type)
1658 {
1659 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1660 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1661 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1662 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1663 case CLOCK_DEFAULT: flags = info->params.flags &
1664 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1665 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1666 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1667 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1668 default: return -EINVAL;
1669 }
1670
1671 if (new_line.loopback != 0 && new_line.loopback != 1)
1672 return -EINVAL;
1673
1674 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1675 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1676 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1677 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1678 info->params.flags |= flags;
1679
1680 info->params.loopback = new_line.loopback;
1681
1682 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1683 info->params.clock_speed = new_line.clock_rate;
1684 else
1685 info->params.clock_speed = 0;
1686
1687 /* if network interface up, reprogram hardware */
1688 if (info->netcount)
1689 program_hw(info);
1690 return 0;
1691
1692 default:
1693 return hdlc_ioctl(dev, ifr, cmd);
1694 }
1695 }
1696
1697 /**
1698 * called by network layer when transmit timeout is detected
1699 *
1700 * dev pointer to network device structure
1701 */
1702 static void hdlcdev_tx_timeout(struct net_device *dev)
1703 {
1704 struct slgt_info *info = dev_to_port(dev);
1705 unsigned long flags;
1706
1707 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1708
1709 dev->stats.tx_errors++;
1710 dev->stats.tx_aborted_errors++;
1711
1712 spin_lock_irqsave(&info->lock,flags);
1713 tx_stop(info);
1714 spin_unlock_irqrestore(&info->lock,flags);
1715
1716 netif_wake_queue(dev);
1717 }
1718
1719 /**
1720 * called by device driver when transmit completes
1721 * reenable network layer transmit if stopped
1722 *
1723 * info pointer to device instance information
1724 */
1725 static void hdlcdev_tx_done(struct slgt_info *info)
1726 {
1727 if (netif_queue_stopped(info->netdev))
1728 netif_wake_queue(info->netdev);
1729 }
1730
1731 /**
1732 * called by device driver when frame received
1733 * pass frame to network layer
1734 *
1735 * info pointer to device instance information
1736 * buf pointer to buffer contianing frame data
1737 * size count of data bytes in buf
1738 */
1739 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1740 {
1741 struct sk_buff *skb = dev_alloc_skb(size);
1742 struct net_device *dev = info->netdev;
1743
1744 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1745
1746 if (skb == NULL) {
1747 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1748 dev->stats.rx_dropped++;
1749 return;
1750 }
1751
1752 memcpy(skb_put(skb, size), buf, size);
1753
1754 skb->protocol = hdlc_type_trans(skb, dev);
1755
1756 dev->stats.rx_packets++;
1757 dev->stats.rx_bytes += size;
1758
1759 netif_rx(skb);
1760 }
1761
1762 static const struct net_device_ops hdlcdev_ops = {
1763 .ndo_open = hdlcdev_open,
1764 .ndo_stop = hdlcdev_close,
1765 .ndo_change_mtu = hdlc_change_mtu,
1766 .ndo_start_xmit = hdlc_start_xmit,
1767 .ndo_do_ioctl = hdlcdev_ioctl,
1768 .ndo_tx_timeout = hdlcdev_tx_timeout,
1769 };
1770
1771 /**
1772 * called by device driver when adding device instance
1773 * do generic HDLC initialization
1774 *
1775 * info pointer to device instance information
1776 *
1777 * returns 0 if success, otherwise error code
1778 */
1779 static int hdlcdev_init(struct slgt_info *info)
1780 {
1781 int rc;
1782 struct net_device *dev;
1783 hdlc_device *hdlc;
1784
1785 /* allocate and initialize network and HDLC layer objects */
1786
1787 if (!(dev = alloc_hdlcdev(info))) {
1788 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1789 return -ENOMEM;
1790 }
1791
1792 /* for network layer reporting purposes only */
1793 dev->mem_start = info->phys_reg_addr;
1794 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1795 dev->irq = info->irq_level;
1796
1797 /* network layer callbacks and settings */
1798 dev->netdev_ops = &hdlcdev_ops;
1799 dev->watchdog_timeo = 10 * HZ;
1800 dev->tx_queue_len = 50;
1801
1802 /* generic HDLC layer callbacks and settings */
1803 hdlc = dev_to_hdlc(dev);
1804 hdlc->attach = hdlcdev_attach;
1805 hdlc->xmit = hdlcdev_xmit;
1806
1807 /* register objects with HDLC layer */
1808 if ((rc = register_hdlc_device(dev))) {
1809 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1810 free_netdev(dev);
1811 return rc;
1812 }
1813
1814 info->netdev = dev;
1815 return 0;
1816 }
1817
1818 /**
1819 * called by device driver when removing device instance
1820 * do generic HDLC cleanup
1821 *
1822 * info pointer to device instance information
1823 */
1824 static void hdlcdev_exit(struct slgt_info *info)
1825 {
1826 unregister_hdlc_device(info->netdev);
1827 free_netdev(info->netdev);
1828 info->netdev = NULL;
1829 }
1830
1831 #endif /* ifdef CONFIG_HDLC */
1832
1833 /*
1834 * get async data from rx DMA buffers
1835 */
1836 static void rx_async(struct slgt_info *info)
1837 {
1838 struct tty_struct *tty = info->port.tty;
1839 struct mgsl_icount *icount = &info->icount;
1840 unsigned int start, end;
1841 unsigned char *p;
1842 unsigned char status;
1843 struct slgt_desc *bufs = info->rbufs;
1844 int i, count;
1845 int chars = 0;
1846 int stat;
1847 unsigned char ch;
1848
1849 start = end = info->rbuf_current;
1850
1851 while(desc_complete(bufs[end])) {
1852 count = desc_count(bufs[end]) - info->rbuf_index;
1853 p = bufs[end].buf + info->rbuf_index;
1854
1855 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1856 DBGDATA(info, p, count, "rx");
1857
1858 for(i=0 ; i < count; i+=2, p+=2) {
1859 ch = *p;
1860 icount->rx++;
1861
1862 stat = 0;
1863
1864 if ((status = *(p+1) & (BIT1 + BIT0))) {
1865 if (status & BIT1)
1866 icount->parity++;
1867 else if (status & BIT0)
1868 icount->frame++;
1869 /* discard char if tty control flags say so */
1870 if (status & info->ignore_status_mask)
1871 continue;
1872 if (status & BIT1)
1873 stat = TTY_PARITY;
1874 else if (status & BIT0)
1875 stat = TTY_FRAME;
1876 }
1877 if (tty) {
1878 tty_insert_flip_char(tty, ch, stat);
1879 chars++;
1880 }
1881 }
1882
1883 if (i < count) {
1884 /* receive buffer not completed */
1885 info->rbuf_index += i;
1886 mod_timer(&info->rx_timer, jiffies + 1);
1887 break;
1888 }
1889
1890 info->rbuf_index = 0;
1891 free_rbufs(info, end, end);
1892
1893 if (++end == info->rbuf_count)
1894 end = 0;
1895
1896 /* if entire list searched then no frame available */
1897 if (end == start)
1898 break;
1899 }
1900
1901 if (tty && chars)
1902 tty_flip_buffer_push(tty);
1903 }
1904
1905 /*
1906 * return next bottom half action to perform
1907 */
1908 static int bh_action(struct slgt_info *info)
1909 {
1910 unsigned long flags;
1911 int rc;
1912
1913 spin_lock_irqsave(&info->lock,flags);
1914
1915 if (info->pending_bh & BH_RECEIVE) {
1916 info->pending_bh &= ~BH_RECEIVE;
1917 rc = BH_RECEIVE;
1918 } else if (info->pending_bh & BH_TRANSMIT) {
1919 info->pending_bh &= ~BH_TRANSMIT;
1920 rc = BH_TRANSMIT;
1921 } else if (info->pending_bh & BH_STATUS) {
1922 info->pending_bh &= ~BH_STATUS;
1923 rc = BH_STATUS;
1924 } else {
1925 /* Mark BH routine as complete */
1926 info->bh_running = false;
1927 info->bh_requested = false;
1928 rc = 0;
1929 }
1930
1931 spin_unlock_irqrestore(&info->lock,flags);
1932
1933 return rc;
1934 }
1935
1936 /*
1937 * perform bottom half processing
1938 */
1939 static void bh_handler(struct work_struct *work)
1940 {
1941 struct slgt_info *info = container_of(work, struct slgt_info, task);
1942 int action;
1943
1944 if (!info)
1945 return;
1946 info->bh_running = true;
1947
1948 while((action = bh_action(info))) {
1949 switch (action) {
1950 case BH_RECEIVE:
1951 DBGBH(("%s bh receive\n", info->device_name));
1952 switch(info->params.mode) {
1953 case MGSL_MODE_ASYNC:
1954 rx_async(info);
1955 break;
1956 case MGSL_MODE_HDLC:
1957 while(rx_get_frame(info));
1958 break;
1959 case MGSL_MODE_RAW:
1960 case MGSL_MODE_MONOSYNC:
1961 case MGSL_MODE_BISYNC:
1962 while(rx_get_buf(info));
1963 break;
1964 }
1965 /* restart receiver if rx DMA buffers exhausted */
1966 if (info->rx_restart)
1967 rx_start(info);
1968 break;
1969 case BH_TRANSMIT:
1970 bh_transmit(info);
1971 break;
1972 case BH_STATUS:
1973 DBGBH(("%s bh status\n", info->device_name));
1974 info->ri_chkcount = 0;
1975 info->dsr_chkcount = 0;
1976 info->dcd_chkcount = 0;
1977 info->cts_chkcount = 0;
1978 break;
1979 default:
1980 DBGBH(("%s unknown action\n", info->device_name));
1981 break;
1982 }
1983 }
1984 DBGBH(("%s bh_handler exit\n", info->device_name));
1985 }
1986
1987 static void bh_transmit(struct slgt_info *info)
1988 {
1989 struct tty_struct *tty = info->port.tty;
1990
1991 DBGBH(("%s bh_transmit\n", info->device_name));
1992 if (tty)
1993 tty_wakeup(tty);
1994 }
1995
1996 static void dsr_change(struct slgt_info *info, unsigned short status)
1997 {
1998 if (status & BIT3) {
1999 info->signals |= SerialSignal_DSR;
2000 info->input_signal_events.dsr_up++;
2001 } else {
2002 info->signals &= ~SerialSignal_DSR;
2003 info->input_signal_events.dsr_down++;
2004 }
2005 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2006 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2007 slgt_irq_off(info, IRQ_DSR);
2008 return;
2009 }
2010 info->icount.dsr++;
2011 wake_up_interruptible(&info->status_event_wait_q);
2012 wake_up_interruptible(&info->event_wait_q);
2013 info->pending_bh |= BH_STATUS;
2014 }
2015
2016 static void cts_change(struct slgt_info *info, unsigned short status)
2017 {
2018 if (status & BIT2) {
2019 info->signals |= SerialSignal_CTS;
2020 info->input_signal_events.cts_up++;
2021 } else {
2022 info->signals &= ~SerialSignal_CTS;
2023 info->input_signal_events.cts_down++;
2024 }
2025 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2026 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2027 slgt_irq_off(info, IRQ_CTS);
2028 return;
2029 }
2030 info->icount.cts++;
2031 wake_up_interruptible(&info->status_event_wait_q);
2032 wake_up_interruptible(&info->event_wait_q);
2033 info->pending_bh |= BH_STATUS;
2034
2035 if (info->port.flags & ASYNC_CTS_FLOW) {
2036 if (info->port.tty) {
2037 if (info->port.tty->hw_stopped) {
2038 if (info->signals & SerialSignal_CTS) {
2039 info->port.tty->hw_stopped = 0;
2040 info->pending_bh |= BH_TRANSMIT;
2041 return;
2042 }
2043 } else {
2044 if (!(info->signals & SerialSignal_CTS))
2045 info->port.tty->hw_stopped = 1;
2046 }
2047 }
2048 }
2049 }
2050
2051 static void dcd_change(struct slgt_info *info, unsigned short status)
2052 {
2053 if (status & BIT1) {
2054 info->signals |= SerialSignal_DCD;
2055 info->input_signal_events.dcd_up++;
2056 } else {
2057 info->signals &= ~SerialSignal_DCD;
2058 info->input_signal_events.dcd_down++;
2059 }
2060 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2061 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2062 slgt_irq_off(info, IRQ_DCD);
2063 return;
2064 }
2065 info->icount.dcd++;
2066 #if SYNCLINK_GENERIC_HDLC
2067 if (info->netcount) {
2068 if (info->signals & SerialSignal_DCD)
2069 netif_carrier_on(info->netdev);
2070 else
2071 netif_carrier_off(info->netdev);
2072 }
2073 #endif
2074 wake_up_interruptible(&info->status_event_wait_q);
2075 wake_up_interruptible(&info->event_wait_q);
2076 info->pending_bh |= BH_STATUS;
2077
2078 if (info->port.flags & ASYNC_CHECK_CD) {
2079 if (info->signals & SerialSignal_DCD)
2080 wake_up_interruptible(&info->port.open_wait);
2081 else {
2082 if (info->port.tty)
2083 tty_hangup(info->port.tty);
2084 }
2085 }
2086 }
2087
2088 static void ri_change(struct slgt_info *info, unsigned short status)
2089 {
2090 if (status & BIT0) {
2091 info->signals |= SerialSignal_RI;
2092 info->input_signal_events.ri_up++;
2093 } else {
2094 info->signals &= ~SerialSignal_RI;
2095 info->input_signal_events.ri_down++;
2096 }
2097 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2098 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2099 slgt_irq_off(info, IRQ_RI);
2100 return;
2101 }
2102 info->icount.rng++;
2103 wake_up_interruptible(&info->status_event_wait_q);
2104 wake_up_interruptible(&info->event_wait_q);
2105 info->pending_bh |= BH_STATUS;
2106 }
2107
2108 static void isr_serial(struct slgt_info *info)
2109 {
2110 unsigned short status = rd_reg16(info, SSR);
2111
2112 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2113
2114 wr_reg16(info, SSR, status); /* clear pending */
2115
2116 info->irq_occurred = true;
2117
2118 if (info->params.mode == MGSL_MODE_ASYNC) {
2119 if (status & IRQ_TXIDLE) {
2120 if (info->tx_count)
2121 isr_txeom(info, status);
2122 }
2123 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2124 info->icount.brk++;
2125 /* process break detection if tty control allows */
2126 if (info->port.tty) {
2127 if (!(status & info->ignore_status_mask)) {
2128 if (info->read_status_mask & MASK_BREAK) {
2129 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2130 if (info->port.flags & ASYNC_SAK)
2131 do_SAK(info->port.tty);
2132 }
2133 }
2134 }
2135 }
2136 } else {
2137 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2138 isr_txeom(info, status);
2139
2140 if (status & IRQ_RXIDLE) {
2141 if (status & RXIDLE)
2142 info->icount.rxidle++;
2143 else
2144 info->icount.exithunt++;
2145 wake_up_interruptible(&info->event_wait_q);
2146 }
2147
2148 if (status & IRQ_RXOVER)
2149 rx_start(info);
2150 }
2151
2152 if (status & IRQ_DSR)
2153 dsr_change(info, status);
2154 if (status & IRQ_CTS)
2155 cts_change(info, status);
2156 if (status & IRQ_DCD)
2157 dcd_change(info, status);
2158 if (status & IRQ_RI)
2159 ri_change(info, status);
2160 }
2161
2162 static void isr_rdma(struct slgt_info *info)
2163 {
2164 unsigned int status = rd_reg32(info, RDCSR);
2165
2166 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2167
2168 /* RDCSR (rx DMA control/status)
2169 *
2170 * 31..07 reserved
2171 * 06 save status byte to DMA buffer
2172 * 05 error
2173 * 04 eol (end of list)
2174 * 03 eob (end of buffer)
2175 * 02 IRQ enable
2176 * 01 reset
2177 * 00 enable
2178 */
2179 wr_reg32(info, RDCSR, status); /* clear pending */
2180
2181 if (status & (BIT5 + BIT4)) {
2182 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2183 info->rx_restart = true;
2184 }
2185 info->pending_bh |= BH_RECEIVE;
2186 }
2187
2188 static void isr_tdma(struct slgt_info *info)
2189 {
2190 unsigned int status = rd_reg32(info, TDCSR);
2191
2192 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2193
2194 /* TDCSR (tx DMA control/status)
2195 *
2196 * 31..06 reserved
2197 * 05 error
2198 * 04 eol (end of list)
2199 * 03 eob (end of buffer)
2200 * 02 IRQ enable
2201 * 01 reset
2202 * 00 enable
2203 */
2204 wr_reg32(info, TDCSR, status); /* clear pending */
2205
2206 if (status & (BIT5 + BIT4 + BIT3)) {
2207 // another transmit buffer has completed
2208 // run bottom half to get more send data from user
2209 info->pending_bh |= BH_TRANSMIT;
2210 }
2211 }
2212
2213 static void isr_txeom(struct slgt_info *info, unsigned short status)
2214 {
2215 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2216
2217 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2218 tdma_reset(info);
2219 reset_tbufs(info);
2220 if (status & IRQ_TXUNDER) {
2221 unsigned short val = rd_reg16(info, TCR);
2222 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2223 wr_reg16(info, TCR, val); /* clear reset bit */
2224 }
2225
2226 if (info->tx_active) {
2227 if (info->params.mode != MGSL_MODE_ASYNC) {
2228 if (status & IRQ_TXUNDER)
2229 info->icount.txunder++;
2230 else if (status & IRQ_TXIDLE)
2231 info->icount.txok++;
2232 }
2233
2234 info->tx_active = false;
2235 info->tx_count = 0;
2236
2237 del_timer(&info->tx_timer);
2238
2239 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2240 info->signals &= ~SerialSignal_RTS;
2241 info->drop_rts_on_tx_done = false;
2242 set_signals(info);
2243 }
2244
2245 #if SYNCLINK_GENERIC_HDLC
2246 if (info->netcount)
2247 hdlcdev_tx_done(info);
2248 else
2249 #endif
2250 {
2251 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2252 tx_stop(info);
2253 return;
2254 }
2255 info->pending_bh |= BH_TRANSMIT;
2256 }
2257 }
2258 }
2259
2260 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2261 {
2262 struct cond_wait *w, *prev;
2263
2264 /* wake processes waiting for specific transitions */
2265 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2266 if (w->data & changed) {
2267 w->data = state;
2268 wake_up_interruptible(&w->q);
2269 if (prev != NULL)
2270 prev->next = w->next;
2271 else
2272 info->gpio_wait_q = w->next;
2273 } else
2274 prev = w;
2275 }
2276 }
2277
2278 /* interrupt service routine
2279 *
2280 * irq interrupt number
2281 * dev_id device ID supplied during interrupt registration
2282 */
2283 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2284 {
2285 struct slgt_info *info = dev_id;
2286 unsigned int gsr;
2287 unsigned int i;
2288
2289 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2290
2291 spin_lock(&info->lock);
2292
2293 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2294 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2295 info->irq_occurred = true;
2296 for(i=0; i < info->port_count ; i++) {
2297 if (info->port_array[i] == NULL)
2298 continue;
2299 if (gsr & (BIT8 << i))
2300 isr_serial(info->port_array[i]);
2301 if (gsr & (BIT16 << (i*2)))
2302 isr_rdma(info->port_array[i]);
2303 if (gsr & (BIT17 << (i*2)))
2304 isr_tdma(info->port_array[i]);
2305 }
2306 }
2307
2308 if (info->gpio_present) {
2309 unsigned int state;
2310 unsigned int changed;
2311 while ((changed = rd_reg32(info, IOSR)) != 0) {
2312 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2313 /* read latched state of GPIO signals */
2314 state = rd_reg32(info, IOVR);
2315 /* clear pending GPIO interrupt bits */
2316 wr_reg32(info, IOSR, changed);
2317 for (i=0 ; i < info->port_count ; i++) {
2318 if (info->port_array[i] != NULL)
2319 isr_gpio(info->port_array[i], changed, state);
2320 }
2321 }
2322 }
2323
2324 for(i=0; i < info->port_count ; i++) {
2325 struct slgt_info *port = info->port_array[i];
2326
2327 if (port && (port->port.count || port->netcount) &&
2328 port->pending_bh && !port->bh_running &&
2329 !port->bh_requested) {
2330 DBGISR(("%s bh queued\n", port->device_name));
2331 schedule_work(&port->task);
2332 port->bh_requested = true;
2333 }
2334 }
2335
2336 spin_unlock(&info->lock);
2337
2338 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2339 return IRQ_HANDLED;
2340 }
2341
2342 static int startup(struct slgt_info *info)
2343 {
2344 DBGINFO(("%s startup\n", info->device_name));
2345
2346 if (info->port.flags & ASYNC_INITIALIZED)
2347 return 0;
2348
2349 if (!info->tx_buf) {
2350 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2351 if (!info->tx_buf) {
2352 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2353 return -ENOMEM;
2354 }
2355 }
2356
2357 info->pending_bh = 0;
2358
2359 memset(&info->icount, 0, sizeof(info->icount));
2360
2361 /* program hardware for current parameters */
2362 change_params(info);
2363
2364 if (info->port.tty)
2365 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2366
2367 info->port.flags |= ASYNC_INITIALIZED;
2368
2369 return 0;
2370 }
2371
2372 /*
2373 * called by close() and hangup() to shutdown hardware
2374 */
2375 static void shutdown(struct slgt_info *info)
2376 {
2377 unsigned long flags;
2378
2379 if (!(info->port.flags & ASYNC_INITIALIZED))
2380 return;
2381
2382 DBGINFO(("%s shutdown\n", info->device_name));
2383
2384 /* clear status wait queue because status changes */
2385 /* can't happen after shutting down the hardware */
2386 wake_up_interruptible(&info->status_event_wait_q);
2387 wake_up_interruptible(&info->event_wait_q);
2388
2389 del_timer_sync(&info->tx_timer);
2390 del_timer_sync(&info->rx_timer);
2391
2392 kfree(info->tx_buf);
2393 info->tx_buf = NULL;
2394
2395 spin_lock_irqsave(&info->lock,flags);
2396
2397 tx_stop(info);
2398 rx_stop(info);
2399
2400 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2401
2402 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2403 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2404 set_signals(info);
2405 }
2406
2407 flush_cond_wait(&info->gpio_wait_q);
2408
2409 spin_unlock_irqrestore(&info->lock,flags);
2410
2411 if (info->port.tty)
2412 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2413
2414 info->port.flags &= ~ASYNC_INITIALIZED;
2415 }
2416
2417 static void program_hw(struct slgt_info *info)
2418 {
2419 unsigned long flags;
2420
2421 spin_lock_irqsave(&info->lock,flags);
2422
2423 rx_stop(info);
2424 tx_stop(info);
2425
2426 if (info->params.mode != MGSL_MODE_ASYNC ||
2427 info->netcount)
2428 sync_mode(info);
2429 else
2430 async_mode(info);
2431
2432 set_signals(info);
2433
2434 info->dcd_chkcount = 0;
2435 info->cts_chkcount = 0;
2436 info->ri_chkcount = 0;
2437 info->dsr_chkcount = 0;
2438
2439 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2440 get_signals(info);
2441
2442 if (info->netcount ||
2443 (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2444 rx_start(info);
2445
2446 spin_unlock_irqrestore(&info->lock,flags);
2447 }
2448
2449 /*
2450 * reconfigure adapter based on new parameters
2451 */
2452 static void change_params(struct slgt_info *info)
2453 {
2454 unsigned cflag;
2455 int bits_per_char;
2456
2457 if (!info->port.tty || !info->port.tty->termios)
2458 return;
2459 DBGINFO(("%s change_params\n", info->device_name));
2460
2461 cflag = info->port.tty->termios->c_cflag;
2462
2463 /* if B0 rate (hangup) specified then negate DTR and RTS */
2464 /* otherwise assert DTR and RTS */
2465 if (cflag & CBAUD)
2466 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2467 else
2468 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2469
2470 /* byte size and parity */
2471
2472 switch (cflag & CSIZE) {
2473 case CS5: info->params.data_bits = 5; break;
2474 case CS6: info->params.data_bits = 6; break;
2475 case CS7: info->params.data_bits = 7; break;
2476 case CS8: info->params.data_bits = 8; break;
2477 default: info->params.data_bits = 7; break;
2478 }
2479
2480 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2481
2482 if (cflag & PARENB)
2483 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2484 else
2485 info->params.parity = ASYNC_PARITY_NONE;
2486
2487 /* calculate number of jiffies to transmit a full
2488 * FIFO (32 bytes) at specified data rate
2489 */
2490 bits_per_char = info->params.data_bits +
2491 info->params.stop_bits + 1;
2492
2493 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2494
2495 if (info->params.data_rate) {
2496 info->timeout = (32*HZ*bits_per_char) /
2497 info->params.data_rate;
2498 }
2499 info->timeout += HZ/50; /* Add .02 seconds of slop */
2500
2501 if (cflag & CRTSCTS)
2502 info->port.flags |= ASYNC_CTS_FLOW;
2503 else
2504 info->port.flags &= ~ASYNC_CTS_FLOW;
2505
2506 if (cflag & CLOCAL)
2507 info->port.flags &= ~ASYNC_CHECK_CD;
2508 else
2509 info->port.flags |= ASYNC_CHECK_CD;
2510
2511 /* process tty input control flags */
2512
2513 info->read_status_mask = IRQ_RXOVER;
2514 if (I_INPCK(info->port.tty))
2515 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2516 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2517 info->read_status_mask |= MASK_BREAK;
2518 if (I_IGNPAR(info->port.tty))
2519 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2520 if (I_IGNBRK(info->port.tty)) {
2521 info->ignore_status_mask |= MASK_BREAK;
2522 /* If ignoring parity and break indicators, ignore
2523 * overruns too. (For real raw support).
2524 */
2525 if (I_IGNPAR(info->port.tty))
2526 info->ignore_status_mask |= MASK_OVERRUN;
2527 }
2528
2529 program_hw(info);
2530 }
2531
2532 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2533 {
2534 DBGINFO(("%s get_stats\n", info->device_name));
2535 if (!user_icount) {
2536 memset(&info->icount, 0, sizeof(info->icount));
2537 } else {
2538 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2539 return -EFAULT;
2540 }
2541 return 0;
2542 }
2543
2544 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2545 {
2546 DBGINFO(("%s get_params\n", info->device_name));
2547 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2548 return -EFAULT;
2549 return 0;
2550 }
2551
2552 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2553 {
2554 unsigned long flags;
2555 MGSL_PARAMS tmp_params;
2556
2557 DBGINFO(("%s set_params\n", info->device_name));
2558 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2559 return -EFAULT;
2560
2561 spin_lock_irqsave(&info->lock, flags);
2562 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2563 spin_unlock_irqrestore(&info->lock, flags);
2564
2565 change_params(info);
2566
2567 return 0;
2568 }
2569
2570 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2571 {
2572 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2573 if (put_user(info->idle_mode, idle_mode))
2574 return -EFAULT;
2575 return 0;
2576 }
2577
2578 static int set_txidle(struct slgt_info *info, int idle_mode)
2579 {
2580 unsigned long flags;
2581 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2582 spin_lock_irqsave(&info->lock,flags);
2583 info->idle_mode = idle_mode;
2584 if (info->params.mode != MGSL_MODE_ASYNC)
2585 tx_set_idle(info);
2586 spin_unlock_irqrestore(&info->lock,flags);
2587 return 0;
2588 }
2589
2590 static int tx_enable(struct slgt_info *info, int enable)
2591 {
2592 unsigned long flags;
2593 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2594 spin_lock_irqsave(&info->lock,flags);
2595 if (enable) {
2596 if (!info->tx_enabled)
2597 tx_start(info);
2598 } else {
2599 if (info->tx_enabled)
2600 tx_stop(info);
2601 }
2602 spin_unlock_irqrestore(&info->lock,flags);
2603 return 0;
2604 }
2605
2606 /*
2607 * abort transmit HDLC frame
2608 */
2609 static int tx_abort(struct slgt_info *info)
2610 {
2611 unsigned long flags;
2612 DBGINFO(("%s tx_abort\n", info->device_name));
2613 spin_lock_irqsave(&info->lock,flags);
2614 tdma_reset(info);
2615 spin_unlock_irqrestore(&info->lock,flags);
2616 return 0;
2617 }
2618
2619 static int rx_enable(struct slgt_info *info, int enable)
2620 {
2621 unsigned long flags;
2622 unsigned int rbuf_fill_level;
2623 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2624 spin_lock_irqsave(&info->lock,flags);
2625 /*
2626 * enable[31..16] = receive DMA buffer fill level
2627 * 0 = noop (leave fill level unchanged)
2628 * fill level must be multiple of 4 and <= buffer size
2629 */
2630 rbuf_fill_level = ((unsigned int)enable) >> 16;
2631 if (rbuf_fill_level) {
2632 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2633 spin_unlock_irqrestore(&info->lock, flags);
2634 return -EINVAL;
2635 }
2636 info->rbuf_fill_level = rbuf_fill_level;
2637 rx_stop(info); /* restart receiver to use new fill level */
2638 }
2639
2640 /*
2641 * enable[1..0] = receiver enable command
2642 * 0 = disable
2643 * 1 = enable
2644 * 2 = enable or force hunt mode if already enabled
2645 */
2646 enable &= 3;
2647 if (enable) {
2648 if (!info->rx_enabled)
2649 rx_start(info);
2650 else if (enable == 2) {
2651 /* force hunt mode (write 1 to RCR[3]) */
2652 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2653 }
2654 } else {
2655 if (info->rx_enabled)
2656 rx_stop(info);
2657 }
2658 spin_unlock_irqrestore(&info->lock,flags);
2659 return 0;
2660 }
2661
2662 /*
2663 * wait for specified event to occur
2664 */
2665 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2666 {
2667 unsigned long flags;
2668 int s;
2669 int rc=0;
2670 struct mgsl_icount cprev, cnow;
2671 int events;
2672 int mask;
2673 struct _input_signal_events oldsigs, newsigs;
2674 DECLARE_WAITQUEUE(wait, current);
2675
2676 if (get_user(mask, mask_ptr))
2677 return -EFAULT;
2678
2679 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2680
2681 spin_lock_irqsave(&info->lock,flags);
2682
2683 /* return immediately if state matches requested events */
2684 get_signals(info);
2685 s = info->signals;
2686
2687 events = mask &
2688 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2689 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2690 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2691 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2692 if (events) {
2693 spin_unlock_irqrestore(&info->lock,flags);
2694 goto exit;
2695 }
2696
2697 /* save current irq counts */
2698 cprev = info->icount;
2699 oldsigs = info->input_signal_events;
2700
2701 /* enable hunt and idle irqs if needed */
2702 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2703 unsigned short val = rd_reg16(info, SCR);
2704 if (!(val & IRQ_RXIDLE))
2705 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2706 }
2707
2708 set_current_state(TASK_INTERRUPTIBLE);
2709 add_wait_queue(&info->event_wait_q, &wait);
2710
2711 spin_unlock_irqrestore(&info->lock,flags);
2712
2713 for(;;) {
2714 schedule();
2715 if (signal_pending(current)) {
2716 rc = -ERESTARTSYS;
2717 break;
2718 }
2719
2720 /* get current irq counts */
2721 spin_lock_irqsave(&info->lock,flags);
2722 cnow = info->icount;
2723 newsigs = info->input_signal_events;
2724 set_current_state(TASK_INTERRUPTIBLE);
2725 spin_unlock_irqrestore(&info->lock,flags);
2726
2727 /* if no change, wait aborted for some reason */
2728 if (newsigs.dsr_up == oldsigs.dsr_up &&
2729 newsigs.dsr_down == oldsigs.dsr_down &&
2730 newsigs.dcd_up == oldsigs.dcd_up &&
2731 newsigs.dcd_down == oldsigs.dcd_down &&
2732 newsigs.cts_up == oldsigs.cts_up &&
2733 newsigs.cts_down == oldsigs.cts_down &&
2734 newsigs.ri_up == oldsigs.ri_up &&
2735 newsigs.ri_down == oldsigs.ri_down &&
2736 cnow.exithunt == cprev.exithunt &&
2737 cnow.rxidle == cprev.rxidle) {
2738 rc = -EIO;
2739 break;
2740 }
2741
2742 events = mask &
2743 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2744 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2745 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2746 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2747 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2748 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2749 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2750 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2751 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2752 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2753 if (events)
2754 break;
2755
2756 cprev = cnow;
2757 oldsigs = newsigs;
2758 }
2759
2760 remove_wait_queue(&info->event_wait_q, &wait);
2761 set_current_state(TASK_RUNNING);
2762
2763
2764 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2765 spin_lock_irqsave(&info->lock,flags);
2766 if (!waitqueue_active(&info->event_wait_q)) {
2767 /* disable enable exit hunt mode/idle rcvd IRQs */
2768 wr_reg16(info, SCR,
2769 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2770 }
2771 spin_unlock_irqrestore(&info->lock,flags);
2772 }
2773 exit:
2774 if (rc == 0)
2775 rc = put_user(events, mask_ptr);
2776 return rc;
2777 }
2778
2779 static int get_interface(struct slgt_info *info, int __user *if_mode)
2780 {
2781 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2782 if (put_user(info->if_mode, if_mode))
2783 return -EFAULT;
2784 return 0;
2785 }
2786
2787 static int set_interface(struct slgt_info *info, int if_mode)
2788 {
2789 unsigned long flags;
2790 unsigned short val;
2791
2792 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2793 spin_lock_irqsave(&info->lock,flags);
2794 info->if_mode = if_mode;
2795
2796 msc_set_vcr(info);
2797
2798 /* TCR (tx control) 07 1=RTS driver control */
2799 val = rd_reg16(info, TCR);
2800 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2801 val |= BIT7;
2802 else
2803 val &= ~BIT7;
2804 wr_reg16(info, TCR, val);
2805
2806 spin_unlock_irqrestore(&info->lock,flags);
2807 return 0;
2808 }
2809
2810 /*
2811 * set general purpose IO pin state and direction
2812 *
2813 * user_gpio fields:
2814 * state each bit indicates a pin state
2815 * smask set bit indicates pin state to set
2816 * dir each bit indicates a pin direction (0=input, 1=output)
2817 * dmask set bit indicates pin direction to set
2818 */
2819 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2820 {
2821 unsigned long flags;
2822 struct gpio_desc gpio;
2823 __u32 data;
2824
2825 if (!info->gpio_present)
2826 return -EINVAL;
2827 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2828 return -EFAULT;
2829 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2830 info->device_name, gpio.state, gpio.smask,
2831 gpio.dir, gpio.dmask));
2832
2833 spin_lock_irqsave(&info->lock,flags);
2834 if (gpio.dmask) {
2835 data = rd_reg32(info, IODR);
2836 data |= gpio.dmask & gpio.dir;
2837 data &= ~(gpio.dmask & ~gpio.dir);
2838 wr_reg32(info, IODR, data);
2839 }
2840 if (gpio.smask) {
2841 data = rd_reg32(info, IOVR);
2842 data |= gpio.smask & gpio.state;
2843 data &= ~(gpio.smask & ~gpio.state);
2844 wr_reg32(info, IOVR, data);
2845 }
2846 spin_unlock_irqrestore(&info->lock,flags);
2847
2848 return 0;
2849 }
2850
2851 /*
2852 * get general purpose IO pin state and direction
2853 */
2854 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2855 {
2856 struct gpio_desc gpio;
2857 if (!info->gpio_present)
2858 return -EINVAL;
2859 gpio.state = rd_reg32(info, IOVR);
2860 gpio.smask = 0xffffffff;
2861 gpio.dir = rd_reg32(info, IODR);
2862 gpio.dmask = 0xffffffff;
2863 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2864 return -EFAULT;
2865 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2866 info->device_name, gpio.state, gpio.dir));
2867 return 0;
2868 }
2869
2870 /*
2871 * conditional wait facility
2872 */
2873 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2874 {
2875 init_waitqueue_head(&w->q);
2876 init_waitqueue_entry(&w->wait, current);
2877 w->data = data;
2878 }
2879
2880 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2881 {
2882 set_current_state(TASK_INTERRUPTIBLE);
2883 add_wait_queue(&w->q, &w->wait);
2884 w->next = *head;
2885 *head = w;
2886 }
2887
2888 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2889 {
2890 struct cond_wait *w, *prev;
2891 remove_wait_queue(&cw->q, &cw->wait);
2892 set_current_state(TASK_RUNNING);
2893 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2894 if (w == cw) {
2895 if (prev != NULL)
2896 prev->next = w->next;
2897 else
2898 *head = w->next;
2899 break;
2900 }
2901 }
2902 }
2903
2904 static void flush_cond_wait(struct cond_wait **head)
2905 {
2906 while (*head != NULL) {
2907 wake_up_interruptible(&(*head)->q);
2908 *head = (*head)->next;
2909 }
2910 }
2911
2912 /*
2913 * wait for general purpose I/O pin(s) to enter specified state
2914 *
2915 * user_gpio fields:
2916 * state - bit indicates target pin state
2917 * smask - set bit indicates watched pin
2918 *
2919 * The wait ends when at least one watched pin enters the specified
2920 * state. When 0 (no error) is returned, user_gpio->state is set to the
2921 * state of all GPIO pins when the wait ends.
2922 *
2923 * Note: Each pin may be a dedicated input, dedicated output, or
2924 * configurable input/output. The number and configuration of pins
2925 * varies with the specific adapter model. Only input pins (dedicated
2926 * or configured) can be monitored with this function.
2927 */
2928 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2929 {
2930 unsigned long flags;
2931 int rc = 0;
2932 struct gpio_desc gpio;
2933 struct cond_wait wait;
2934 u32 state;
2935
2936 if (!info->gpio_present)
2937 return -EINVAL;
2938 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2939 return -EFAULT;
2940 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2941 info->device_name, gpio.state, gpio.smask));
2942 /* ignore output pins identified by set IODR bit */
2943 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2944 return -EINVAL;
2945 init_cond_wait(&wait, gpio.smask);
2946
2947 spin_lock_irqsave(&info->lock, flags);
2948 /* enable interrupts for watched pins */
2949 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2950 /* get current pin states */
2951 state = rd_reg32(info, IOVR);
2952
2953 if (gpio.smask & ~(state ^ gpio.state)) {
2954 /* already in target state */
2955 gpio.state = state;
2956 } else {
2957 /* wait for target state */
2958 add_cond_wait(&info->gpio_wait_q, &wait);
2959 spin_unlock_irqrestore(&info->lock, flags);
2960 schedule();
2961 if (signal_pending(current))
2962 rc = -ERESTARTSYS;
2963 else
2964 gpio.state = wait.data;
2965 spin_lock_irqsave(&info->lock, flags);
2966 remove_cond_wait(&info->gpio_wait_q, &wait);
2967 }
2968
2969 /* disable all GPIO interrupts if no waiting processes */
2970 if (info->gpio_wait_q == NULL)
2971 wr_reg32(info, IOER, 0);
2972 spin_unlock_irqrestore(&info->lock,flags);
2973
2974 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2975 rc = -EFAULT;
2976 return rc;
2977 }
2978
2979 static int modem_input_wait(struct slgt_info *info,int arg)
2980 {
2981 unsigned long flags;
2982 int rc;
2983 struct mgsl_icount cprev, cnow;
2984 DECLARE_WAITQUEUE(wait, current);
2985
2986 /* save current irq counts */
2987 spin_lock_irqsave(&info->lock,flags);
2988 cprev = info->icount;
2989 add_wait_queue(&info->status_event_wait_q, &wait);
2990 set_current_state(TASK_INTERRUPTIBLE);
2991 spin_unlock_irqrestore(&info->lock,flags);
2992
2993 for(;;) {
2994 schedule();
2995 if (signal_pending(current)) {
2996 rc = -ERESTARTSYS;
2997 break;
2998 }
2999
3000 /* get new irq counts */
3001 spin_lock_irqsave(&info->lock,flags);
3002 cnow = info->icount;
3003 set_current_state(TASK_INTERRUPTIBLE);
3004 spin_unlock_irqrestore(&info->lock,flags);
3005
3006 /* if no change, wait aborted for some reason */
3007 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3008 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3009 rc = -EIO;
3010 break;
3011 }
3012
3013 /* check for change in caller specified modem input */
3014 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3015 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3016 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3017 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3018 rc = 0;
3019 break;
3020 }
3021
3022 cprev = cnow;
3023 }
3024 remove_wait_queue(&info->status_event_wait_q, &wait);
3025 set_current_state(TASK_RUNNING);
3026 return rc;
3027 }
3028
3029 /*
3030 * return state of serial control and status signals
3031 */
3032 static int tiocmget(struct tty_struct *tty, struct file *file)
3033 {
3034 struct slgt_info *info = tty->driver_data;
3035 unsigned int result;
3036 unsigned long flags;
3037
3038 spin_lock_irqsave(&info->lock,flags);
3039 get_signals(info);
3040 spin_unlock_irqrestore(&info->lock,flags);
3041
3042 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3043 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3044 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3045 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3046 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3047 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3048
3049 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3050 return result;
3051 }
3052
3053 /*
3054 * set modem control signals (DTR/RTS)
3055 *
3056 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3057 * TIOCMSET = set/clear signal values
3058 * value bit mask for command
3059 */
3060 static int tiocmset(struct tty_struct *tty, struct file *file,
3061 unsigned int set, unsigned int clear)
3062 {
3063 struct slgt_info *info = tty->driver_data;
3064 unsigned long flags;
3065
3066 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3067
3068 if (set & TIOCM_RTS)
3069 info->signals |= SerialSignal_RTS;
3070 if (set & TIOCM_DTR)
3071 info->signals |= SerialSignal_DTR;
3072 if (clear & TIOCM_RTS)
3073 info->signals &= ~SerialSignal_RTS;
3074 if (clear & TIOCM_DTR)
3075 info->signals &= ~SerialSignal_DTR;
3076
3077 spin_lock_irqsave(&info->lock,flags);
3078 set_signals(info);
3079 spin_unlock_irqrestore(&info->lock,flags);
3080 return 0;
3081 }
3082
3083 static int carrier_raised(struct tty_port *port)
3084 {
3085 unsigned long flags;
3086 struct slgt_info *info = container_of(port, struct slgt_info, port);
3087
3088 spin_lock_irqsave(&info->lock,flags);
3089 get_signals(info);
3090 spin_unlock_irqrestore(&info->lock,flags);
3091 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3092 }
3093
3094 static void raise_dtr_rts(struct tty_port *port)
3095 {
3096 unsigned long flags;
3097 struct slgt_info *info = container_of(port, struct slgt_info, port);
3098
3099 spin_lock_irqsave(&info->lock,flags);
3100 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3101 set_signals(info);
3102 spin_unlock_irqrestore(&info->lock,flags);
3103 }
3104
3105
3106 /*
3107 * block current process until the device is ready to open
3108 */
3109 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3110 struct slgt_info *info)
3111 {
3112 DECLARE_WAITQUEUE(wait, current);
3113 int retval;
3114 bool do_clocal = false;
3115 bool extra_count = false;
3116 unsigned long flags;
3117 int cd;
3118 struct tty_port *port = &info->port;
3119
3120 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3121
3122 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3123 /* nonblock mode is set or port is not enabled */
3124 port->flags |= ASYNC_NORMAL_ACTIVE;
3125 return 0;
3126 }
3127
3128 if (tty->termios->c_cflag & CLOCAL)
3129 do_clocal = true;
3130
3131 /* Wait for carrier detect and the line to become
3132 * free (i.e., not in use by the callout). While we are in
3133 * this loop, port->count is dropped by one, so that
3134 * close() knows when to free things. We restore it upon
3135 * exit, either normal or abnormal.
3136 */
3137
3138 retval = 0;
3139 add_wait_queue(&port->open_wait, &wait);
3140
3141 spin_lock_irqsave(&info->lock, flags);
3142 if (!tty_hung_up_p(filp)) {
3143 extra_count = true;
3144 port->count--;
3145 }
3146 spin_unlock_irqrestore(&info->lock, flags);
3147 port->blocked_open++;
3148
3149 while (1) {
3150 if ((tty->termios->c_cflag & CBAUD))
3151 tty_port_raise_dtr_rts(port);
3152
3153 set_current_state(TASK_INTERRUPTIBLE);
3154
3155 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3156 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3157 -EAGAIN : -ERESTARTSYS;
3158 break;
3159 }
3160
3161 cd = tty_port_carrier_raised(port);
3162
3163 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3164 break;
3165
3166 if (signal_pending(current)) {
3167 retval = -ERESTARTSYS;
3168 break;
3169 }
3170
3171 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3172 schedule();
3173 }
3174
3175 set_current_state(TASK_RUNNING);
3176 remove_wait_queue(&port->open_wait, &wait);
3177
3178 if (extra_count)
3179 port->count++;
3180 port->blocked_open--;
3181
3182 if (!retval)
3183 port->flags |= ASYNC_NORMAL_ACTIVE;
3184
3185 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3186 return retval;
3187 }
3188
3189 static int alloc_tmp_rbuf(struct slgt_info *info)
3190 {
3191 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3192 if (info->tmp_rbuf == NULL)
3193 return -ENOMEM;
3194 return 0;
3195 }
3196
3197 static void free_tmp_rbuf(struct slgt_info *info)
3198 {
3199 kfree(info->tmp_rbuf);
3200 info->tmp_rbuf = NULL;
3201 }
3202
3203 /*
3204 * allocate DMA descriptor lists.
3205 */
3206 static int alloc_desc(struct slgt_info *info)
3207 {
3208 unsigned int i;
3209 unsigned int pbufs;
3210
3211 /* allocate memory to hold descriptor lists */
3212 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3213 if (info->bufs == NULL)
3214 return -ENOMEM;
3215
3216 memset(info->bufs, 0, DESC_LIST_SIZE);
3217
3218 info->rbufs = (struct slgt_desc*)info->bufs;
3219 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3220
3221 pbufs = (unsigned int)info->bufs_dma_addr;
3222
3223 /*
3224 * Build circular lists of descriptors
3225 */
3226
3227 for (i=0; i < info->rbuf_count; i++) {
3228 /* physical address of this descriptor */
3229 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3230
3231 /* physical address of next descriptor */
3232 if (i == info->rbuf_count - 1)
3233 info->rbufs[i].next = cpu_to_le32(pbufs);
3234 else
3235 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3236 set_desc_count(info->rbufs[i], DMABUFSIZE);
3237 }
3238
3239 for (i=0; i < info->tbuf_count; i++) {
3240 /* physical address of this descriptor */
3241 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3242
3243 /* physical address of next descriptor */
3244 if (i == info->tbuf_count - 1)
3245 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3246 else
3247 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3248 }
3249
3250 return 0;
3251 }
3252
3253 static void free_desc(struct slgt_info *info)
3254 {
3255 if (info->bufs != NULL) {
3256 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3257 info->bufs = NULL;
3258 info->rbufs = NULL;
3259 info->tbufs = NULL;
3260 }
3261 }
3262
3263 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3264 {
3265 int i;
3266 for (i=0; i < count; i++) {
3267 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3268 return -ENOMEM;
3269 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3270 }
3271 return 0;
3272 }
3273
3274 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3275 {
3276 int i;
3277 for (i=0; i < count; i++) {
3278 if (bufs[i].buf == NULL)
3279 continue;
3280 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3281 bufs[i].buf = NULL;
3282 }
3283 }
3284
3285 static int alloc_dma_bufs(struct slgt_info *info)
3286 {
3287 info->rbuf_count = 32;
3288 info->tbuf_count = 32;
3289
3290 if (alloc_desc(info) < 0 ||
3291 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3292 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3293 alloc_tmp_rbuf(info) < 0) {
3294 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3295 return -ENOMEM;
3296 }
3297 reset_rbufs(info);
3298 return 0;
3299 }
3300
3301 static void free_dma_bufs(struct slgt_info *info)
3302 {
3303 if (info->bufs) {
3304 free_bufs(info, info->rbufs, info->rbuf_count);
3305 free_bufs(info, info->tbufs, info->tbuf_count);
3306 free_desc(info);
3307 }
3308 free_tmp_rbuf(info);
3309 }
3310
3311 static int claim_resources(struct slgt_info *info)
3312 {
3313 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3314 DBGERR(("%s reg addr conflict, addr=%08X\n",
3315 info->device_name, info->phys_reg_addr));
3316 info->init_error = DiagStatus_AddressConflict;
3317 goto errout;
3318 }
3319 else
3320 info->reg_addr_requested = true;
3321
3322 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3323 if (!info->reg_addr) {
3324 DBGERR(("%s cant map device registers, addr=%08X\n",
3325 info->device_name, info->phys_reg_addr));
3326 info->init_error = DiagStatus_CantAssignPciResources;
3327 goto errout;
3328 }
3329 return 0;
3330
3331 errout:
3332 release_resources(info);
3333 return -ENODEV;
3334 }
3335
3336 static void release_resources(struct slgt_info *info)
3337 {
3338 if (info->irq_requested) {
3339 free_irq(info->irq_level, info);
3340 info->irq_requested = false;
3341 }
3342
3343 if (info->reg_addr_requested) {
3344 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3345 info->reg_addr_requested = false;
3346 }
3347
3348 if (info->reg_addr) {
3349 iounmap(info->reg_addr);
3350 info->reg_addr = NULL;
3351 }
3352 }
3353
3354 /* Add the specified device instance data structure to the
3355 * global linked list of devices and increment the device count.
3356 */
3357 static void add_device(struct slgt_info *info)
3358 {
3359 char *devstr;
3360
3361 info->next_device = NULL;
3362 info->line = slgt_device_count;
3363 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3364
3365 if (info->line < MAX_DEVICES) {
3366 if (maxframe[info->line])
3367 info->max_frame_size = maxframe[info->line];
3368 }
3369
3370 slgt_device_count++;
3371
3372 if (!slgt_device_list)
3373 slgt_device_list = info;
3374 else {
3375 struct slgt_info *current_dev = slgt_device_list;
3376 while(current_dev->next_device)
3377 current_dev = current_dev->next_device;
3378 current_dev->next_device = info;
3379 }
3380
3381 if (info->max_frame_size < 4096)
3382 info->max_frame_size = 4096;
3383 else if (info->max_frame_size > 65535)
3384 info->max_frame_size = 65535;
3385
3386 switch(info->pdev->device) {
3387 case SYNCLINK_GT_DEVICE_ID:
3388 devstr = "GT";
3389 break;
3390 case SYNCLINK_GT2_DEVICE_ID:
3391 devstr = "GT2";
3392 break;
3393 case SYNCLINK_GT4_DEVICE_ID:
3394 devstr = "GT4";
3395 break;
3396 case SYNCLINK_AC_DEVICE_ID:
3397 devstr = "AC";
3398 info->params.mode = MGSL_MODE_ASYNC;
3399 break;
3400 default:
3401 devstr = "(unknown model)";
3402 }
3403 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3404 devstr, info->device_name, info->phys_reg_addr,
3405 info->irq_level, info->max_frame_size);
3406
3407 #if SYNCLINK_GENERIC_HDLC
3408 hdlcdev_init(info);
3409 #endif
3410 }
3411
3412 static const struct tty_port_operations slgt_port_ops = {
3413 .carrier_raised = carrier_raised,
3414 .raise_dtr_rts = raise_dtr_rts,
3415 };
3416
3417 /*
3418 * allocate device instance structure, return NULL on failure
3419 */
3420 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3421 {
3422 struct slgt_info *info;
3423
3424 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3425
3426 if (!info) {
3427 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3428 driver_name, adapter_num, port_num));
3429 } else {
3430 tty_port_init(&info->port);
3431 info->port.ops = &slgt_port_ops;
3432 info->magic = MGSL_MAGIC;
3433 INIT_WORK(&info->task, bh_handler);
3434 info->max_frame_size = 4096;
3435 info->rbuf_fill_level = DMABUFSIZE;
3436 info->port.close_delay = 5*HZ/10;
3437 info->port.closing_wait = 30*HZ;
3438 init_waitqueue_head(&info->status_event_wait_q);
3439 init_waitqueue_head(&info->event_wait_q);
3440 spin_lock_init(&info->netlock);
3441 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3442 info->idle_mode = HDLC_TXIDLE_FLAGS;
3443 info->adapter_num = adapter_num;
3444 info->port_num = port_num;
3445
3446 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3447 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3448
3449 /* Copy configuration info to device instance data */
3450 info->pdev = pdev;
3451 info->irq_level = pdev->irq;
3452 info->phys_reg_addr = pci_resource_start(pdev,0);
3453
3454 info->bus_type = MGSL_BUS_TYPE_PCI;
3455 info->irq_flags = IRQF_SHARED;
3456
3457 info->init_error = -1; /* assume error, set to 0 on successful init */
3458 }
3459
3460 return info;
3461 }
3462
3463 static void device_init(int adapter_num, struct pci_dev *pdev)
3464 {
3465 struct slgt_info *port_array[SLGT_MAX_PORTS];
3466 int i;
3467 int port_count = 1;
3468
3469 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3470 port_count = 2;
3471 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3472 port_count = 4;
3473
3474 /* allocate device instances for all ports */
3475 for (i=0; i < port_count; ++i) {
3476 port_array[i] = alloc_dev(adapter_num, i, pdev);
3477 if (port_array[i] == NULL) {
3478 for (--i; i >= 0; --i)
3479 kfree(port_array[i]);
3480 return;
3481 }
3482 }
3483
3484 /* give copy of port_array to all ports and add to device list */
3485 for (i=0; i < port_count; ++i) {
3486 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3487 add_device(port_array[i]);
3488 port_array[i]->port_count = port_count;
3489 spin_lock_init(&port_array[i]->lock);
3490 }
3491
3492 /* Allocate and claim adapter resources */
3493 if (!claim_resources(port_array[0])) {
3494
3495 alloc_dma_bufs(port_array[0]);
3496
3497 /* copy resource information from first port to others */
3498 for (i = 1; i < port_count; ++i) {
3499 port_array[i]->lock = port_array[0]->lock;
3500 port_array[i]->irq_level = port_array[0]->irq_level;
3501 port_array[i]->reg_addr = port_array[0]->reg_addr;
3502 alloc_dma_bufs(port_array[i]);
3503 }
3504
3505 if (request_irq(port_array[0]->irq_level,
3506 slgt_interrupt,
3507 port_array[0]->irq_flags,
3508 port_array[0]->device_name,
3509 port_array[0]) < 0) {
3510 DBGERR(("%s request_irq failed IRQ=%d\n",
3511 port_array[0]->device_name,
3512 port_array[0]->irq_level));
3513 } else {
3514 port_array[0]->irq_requested = true;
3515 adapter_test(port_array[0]);
3516 for (i=1 ; i < port_count ; i++) {
3517 port_array[i]->init_error = port_array[0]->init_error;
3518 port_array[i]->gpio_present = port_array[0]->gpio_present;
3519 }
3520 }
3521 }
3522
3523 for (i=0; i < port_count; ++i)
3524 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3525 }
3526
3527 static int __devinit init_one(struct pci_dev *dev,
3528 const struct pci_device_id *ent)
3529 {
3530 if (pci_enable_device(dev)) {
3531 printk("error enabling pci device %p\n", dev);
3532 return -EIO;
3533 }
3534 pci_set_master(dev);
3535 device_init(slgt_device_count, dev);
3536 return 0;
3537 }
3538
3539 static void __devexit remove_one(struct pci_dev *dev)
3540 {
3541 }
3542
3543 static const struct tty_operations ops = {
3544 .open = open,
3545 .close = close,
3546 .write = write,
3547 .put_char = put_char,
3548 .flush_chars = flush_chars,
3549 .write_room = write_room,
3550 .chars_in_buffer = chars_in_buffer,
3551 .flush_buffer = flush_buffer,
3552 .ioctl = ioctl,
3553 .compat_ioctl = slgt_compat_ioctl,
3554 .throttle = throttle,
3555 .unthrottle = unthrottle,
3556 .send_xchar = send_xchar,
3557 .break_ctl = set_break,
3558 .wait_until_sent = wait_until_sent,
3559 .set_termios = set_termios,
3560 .stop = tx_hold,
3561 .start = tx_release,
3562 .hangup = hangup,
3563 .tiocmget = tiocmget,
3564 .tiocmset = tiocmset,
3565 .proc_fops = &synclink_gt_proc_fops,
3566 };
3567
3568 static void slgt_cleanup(void)
3569 {
3570 int rc;
3571 struct slgt_info *info;
3572 struct slgt_info *tmp;
3573
3574 printk(KERN_INFO "unload %s\n", driver_name);
3575
3576 if (serial_driver) {
3577 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3578 tty_unregister_device(serial_driver, info->line);
3579 if ((rc = tty_unregister_driver(serial_driver)))
3580 DBGERR(("tty_unregister_driver error=%d\n", rc));
3581 put_tty_driver(serial_driver);
3582 }
3583
3584 /* reset devices */
3585 info = slgt_device_list;
3586 while(info) {
3587 reset_port(info);
3588 info = info->next_device;
3589 }
3590
3591 /* release devices */
3592 info = slgt_device_list;
3593 while(info) {
3594 #if SYNCLINK_GENERIC_HDLC
3595 hdlcdev_exit(info);
3596 #endif
3597 free_dma_bufs(info);
3598 free_tmp_rbuf(info);
3599 if (info->port_num == 0)
3600 release_resources(info);
3601 tmp = info;
3602 info = info->next_device;
3603 kfree(tmp);
3604 }
3605
3606 if (pci_registered)
3607 pci_unregister_driver(&pci_driver);
3608 }
3609
3610 /*
3611 * Driver initialization entry point.
3612 */
3613 static int __init slgt_init(void)
3614 {
3615 int rc;
3616
3617 printk(KERN_INFO "%s\n", driver_name);
3618
3619 serial_driver = alloc_tty_driver(MAX_DEVICES);
3620 if (!serial_driver) {
3621 printk("%s can't allocate tty driver\n", driver_name);
3622 return -ENOMEM;
3623 }
3624
3625 /* Initialize the tty_driver structure */
3626
3627 serial_driver->owner = THIS_MODULE;
3628 serial_driver->driver_name = tty_driver_name;
3629 serial_driver->name = tty_dev_prefix;
3630 serial_driver->major = ttymajor;
3631 serial_driver->minor_start = 64;
3632 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3633 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3634 serial_driver->init_termios = tty_std_termios;
3635 serial_driver->init_termios.c_cflag =
3636 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3637 serial_driver->init_termios.c_ispeed = 9600;
3638 serial_driver->init_termios.c_ospeed = 9600;
3639 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3640 tty_set_operations(serial_driver, &ops);
3641 if ((rc = tty_register_driver(serial_driver)) < 0) {
3642 DBGERR(("%s can't register serial driver\n", driver_name));
3643 put_tty_driver(serial_driver);
3644 serial_driver = NULL;
3645 goto error;
3646 }
3647
3648 printk(KERN_INFO "%s, tty major#%d\n",
3649 driver_name, serial_driver->major);
3650
3651 slgt_device_count = 0;
3652 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3653 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3654 goto error;
3655 }
3656 pci_registered = true;
3657
3658 if (!slgt_device_list)
3659 printk("%s no devices found\n",driver_name);
3660
3661 return 0;
3662
3663 error:
3664 slgt_cleanup();
3665 return rc;
3666 }
3667
3668 static void __exit slgt_exit(void)
3669 {
3670 slgt_cleanup();
3671 }
3672
3673 module_init(slgt_init);
3674 module_exit(slgt_exit);
3675
3676 /*
3677 * register access routines
3678 */
3679
3680 #define CALC_REGADDR() \
3681 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3682 if (addr >= 0x80) \
3683 reg_addr += (info->port_num) * 32;
3684
3685 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3686 {
3687 CALC_REGADDR();
3688 return readb((void __iomem *)reg_addr);
3689 }
3690
3691 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3692 {
3693 CALC_REGADDR();
3694 writeb(value, (void __iomem *)reg_addr);
3695 }
3696
3697 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3698 {
3699 CALC_REGADDR();
3700 return readw((void __iomem *)reg_addr);
3701 }
3702
3703 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3704 {
3705 CALC_REGADDR();
3706 writew(value, (void __iomem *)reg_addr);
3707 }
3708
3709 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3710 {
3711 CALC_REGADDR();
3712 return readl((void __iomem *)reg_addr);
3713 }
3714
3715 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3716 {
3717 CALC_REGADDR();
3718 writel(value, (void __iomem *)reg_addr);
3719 }
3720
3721 static void rdma_reset(struct slgt_info *info)
3722 {
3723 unsigned int i;
3724
3725 /* set reset bit */
3726 wr_reg32(info, RDCSR, BIT1);
3727
3728 /* wait for enable bit cleared */
3729 for(i=0 ; i < 1000 ; i++)
3730 if (!(rd_reg32(info, RDCSR) & BIT0))
3731 break;
3732 }
3733
3734 static void tdma_reset(struct slgt_info *info)
3735 {
3736 unsigned int i;
3737
3738 /* set reset bit */
3739 wr_reg32(info, TDCSR, BIT1);
3740
3741 /* wait for enable bit cleared */
3742 for(i=0 ; i < 1000 ; i++)
3743 if (!(rd_reg32(info, TDCSR) & BIT0))
3744 break;
3745 }
3746
3747 /*
3748 * enable internal loopback
3749 * TxCLK and RxCLK are generated from BRG
3750 * and TxD is looped back to RxD internally.
3751 */
3752 static void enable_loopback(struct slgt_info *info)
3753 {
3754 /* SCR (serial control) BIT2=looopback enable */
3755 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3756
3757 if (info->params.mode != MGSL_MODE_ASYNC) {
3758 /* CCR (clock control)
3759 * 07..05 tx clock source (010 = BRG)
3760 * 04..02 rx clock source (010 = BRG)
3761 * 01 auxclk enable (0 = disable)
3762 * 00 BRG enable (1 = enable)
3763 *
3764 * 0100 1001
3765 */
3766 wr_reg8(info, CCR, 0x49);
3767
3768 /* set speed if available, otherwise use default */
3769 if (info->params.clock_speed)
3770 set_rate(info, info->params.clock_speed);
3771 else
3772 set_rate(info, 3686400);
3773 }
3774 }
3775
3776 /*
3777 * set baud rate generator to specified rate
3778 */
3779 static void set_rate(struct slgt_info *info, u32 rate)
3780 {
3781 unsigned int div;
3782 static unsigned int osc = 14745600;
3783
3784 /* div = osc/rate - 1
3785 *
3786 * Round div up if osc/rate is not integer to
3787 * force to next slowest rate.
3788 */
3789
3790 if (rate) {
3791 div = osc/rate;
3792 if (!(osc % rate) && div)
3793 div--;
3794 wr_reg16(info, BDR, (unsigned short)div);
3795 }
3796 }
3797
3798 static void rx_stop(struct slgt_info *info)
3799 {
3800 unsigned short val;
3801
3802 /* disable and reset receiver */
3803 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3804 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3805 wr_reg16(info, RCR, val); /* clear reset bit */
3806
3807 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3808
3809 /* clear pending rx interrupts */
3810 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3811
3812 rdma_reset(info);
3813
3814 info->rx_enabled = false;
3815 info->rx_restart = false;
3816 }
3817
3818 static void rx_start(struct slgt_info *info)
3819 {
3820 unsigned short val;
3821
3822 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3823
3824 /* clear pending rx overrun IRQ */
3825 wr_reg16(info, SSR, IRQ_RXOVER);
3826
3827 /* reset and disable receiver */
3828 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3829 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3830 wr_reg16(info, RCR, val); /* clear reset bit */
3831
3832 rdma_reset(info);
3833 reset_rbufs(info);
3834
3835 /* set 1st descriptor address */
3836 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3837
3838 if (info->params.mode != MGSL_MODE_ASYNC) {
3839 /* enable rx DMA and DMA interrupt */
3840 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3841 } else {
3842 /* enable saving of rx status, rx DMA and DMA interrupt */
3843 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3844 }
3845
3846 slgt_irq_on(info, IRQ_RXOVER);
3847
3848 /* enable receiver */
3849 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3850
3851 info->rx_restart = false;
3852 info->rx_enabled = true;
3853 }
3854
3855 static void tx_start(struct slgt_info *info)
3856 {
3857 if (!info->tx_enabled) {
3858 wr_reg16(info, TCR,
3859 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3860 info->tx_enabled = true;
3861 }
3862
3863 if (info->tx_count) {
3864 info->drop_rts_on_tx_done = false;
3865
3866 if (info->params.mode != MGSL_MODE_ASYNC) {
3867 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3868 get_signals(info);
3869 if (!(info->signals & SerialSignal_RTS)) {
3870 info->signals |= SerialSignal_RTS;
3871 set_signals(info);
3872 info->drop_rts_on_tx_done = true;
3873 }
3874 }
3875
3876 slgt_irq_off(info, IRQ_TXDATA);
3877 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3878 /* clear tx idle and underrun status bits */
3879 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3880 if (info->params.mode == MGSL_MODE_HDLC)
3881 mod_timer(&info->tx_timer, jiffies +
3882 msecs_to_jiffies(5000));
3883 } else {
3884 slgt_irq_off(info, IRQ_TXDATA);
3885 slgt_irq_on(info, IRQ_TXIDLE);
3886 /* clear tx idle status bit */
3887 wr_reg16(info, SSR, IRQ_TXIDLE);
3888 }
3889 tdma_start(info);
3890 info->tx_active = true;
3891 }
3892 }
3893
3894 /*
3895 * start transmit DMA if inactive and there are unsent buffers
3896 */
3897 static void tdma_start(struct slgt_info *info)
3898 {
3899 unsigned int i;
3900
3901 if (rd_reg32(info, TDCSR) & BIT0)
3902 return;
3903
3904 /* transmit DMA inactive, check for unsent buffers */
3905 i = info->tbuf_start;
3906 while (!desc_count(info->tbufs[i])) {
3907 if (++i == info->tbuf_count)
3908 i = 0;
3909 if (i == info->tbuf_current)
3910 return;
3911 }
3912 info->tbuf_start = i;
3913
3914 /* there are unsent buffers, start transmit DMA */
3915
3916 /* reset needed if previous error condition */
3917 tdma_reset(info);
3918
3919 /* set 1st descriptor address */
3920 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3921 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3922 }
3923
3924 static void tx_stop(struct slgt_info *info)
3925 {
3926 unsigned short val;
3927
3928 del_timer(&info->tx_timer);
3929
3930 tdma_reset(info);
3931
3932 /* reset and disable transmitter */
3933 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3934 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3935
3936 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3937
3938 /* clear tx idle and underrun status bit */
3939 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3940
3941 reset_tbufs(info);
3942
3943 info->tx_enabled = false;
3944 info->tx_active = false;
3945 }
3946
3947 static void reset_port(struct slgt_info *info)
3948 {
3949 if (!info->reg_addr)
3950 return;
3951
3952 tx_stop(info);
3953 rx_stop(info);
3954
3955 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3956 set_signals(info);
3957
3958 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3959 }
3960
3961 static void reset_adapter(struct slgt_info *info)
3962 {
3963 int i;
3964 for (i=0; i < info->port_count; ++i) {
3965 if (info->port_array[i])
3966 reset_port(info->port_array[i]);
3967 }
3968 }
3969
3970 static void async_mode(struct slgt_info *info)
3971 {
3972 unsigned short val;
3973
3974 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3975 tx_stop(info);
3976 rx_stop(info);
3977
3978 /* TCR (tx control)
3979 *
3980 * 15..13 mode, 010=async
3981 * 12..10 encoding, 000=NRZ
3982 * 09 parity enable
3983 * 08 1=odd parity, 0=even parity
3984 * 07 1=RTS driver control
3985 * 06 1=break enable
3986 * 05..04 character length
3987 * 00=5 bits
3988 * 01=6 bits
3989 * 10=7 bits
3990 * 11=8 bits
3991 * 03 0=1 stop bit, 1=2 stop bits
3992 * 02 reset
3993 * 01 enable
3994 * 00 auto-CTS enable
3995 */
3996 val = 0x4000;
3997
3998 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
3999 val |= BIT7;
4000
4001 if (info->params.parity != ASYNC_PARITY_NONE) {
4002 val |= BIT9;
4003 if (info->params.parity == ASYNC_PARITY_ODD)
4004 val |= BIT8;
4005 }
4006
4007 switch (info->params.data_bits)
4008 {
4009 case 6: val |= BIT4; break;
4010 case 7: val |= BIT5; break;
4011 case 8: val |= BIT5 + BIT4; break;
4012 }
4013
4014 if (info->params.stop_bits != 1)
4015 val |= BIT3;
4016
4017 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4018 val |= BIT0;
4019
4020 wr_reg16(info, TCR, val);
4021
4022 /* RCR (rx control)
4023 *
4024 * 15..13 mode, 010=async
4025 * 12..10 encoding, 000=NRZ
4026 * 09 parity enable
4027 * 08 1=odd parity, 0=even parity
4028 * 07..06 reserved, must be 0
4029 * 05..04 character length
4030 * 00=5 bits
4031 * 01=6 bits
4032 * 10=7 bits
4033 * 11=8 bits
4034 * 03 reserved, must be zero
4035 * 02 reset
4036 * 01 enable
4037 * 00 auto-DCD enable
4038 */
4039 val = 0x4000;
4040
4041 if (info->params.parity != ASYNC_PARITY_NONE) {
4042 val |= BIT9;
4043 if (info->params.parity == ASYNC_PARITY_ODD)
4044 val |= BIT8;
4045 }
4046
4047 switch (info->params.data_bits)
4048 {
4049 case 6: val |= BIT4; break;
4050 case 7: val |= BIT5; break;
4051 case 8: val |= BIT5 + BIT4; break;
4052 }
4053
4054 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4055 val |= BIT0;
4056
4057 wr_reg16(info, RCR, val);
4058
4059 /* CCR (clock control)
4060 *
4061 * 07..05 011 = tx clock source is BRG/16
4062 * 04..02 010 = rx clock source is BRG
4063 * 01 0 = auxclk disabled
4064 * 00 1 = BRG enabled
4065 *
4066 * 0110 1001
4067 */
4068 wr_reg8(info, CCR, 0x69);
4069
4070 msc_set_vcr(info);
4071
4072 /* SCR (serial control)
4073 *
4074 * 15 1=tx req on FIFO half empty
4075 * 14 1=rx req on FIFO half full
4076 * 13 tx data IRQ enable
4077 * 12 tx idle IRQ enable
4078 * 11 rx break on IRQ enable
4079 * 10 rx data IRQ enable
4080 * 09 rx break off IRQ enable
4081 * 08 overrun IRQ enable
4082 * 07 DSR IRQ enable
4083 * 06 CTS IRQ enable
4084 * 05 DCD IRQ enable
4085 * 04 RI IRQ enable
4086 * 03 reserved, must be zero
4087 * 02 1=txd->rxd internal loopback enable
4088 * 01 reserved, must be zero
4089 * 00 1=master IRQ enable
4090 */
4091 val = BIT15 + BIT14 + BIT0;
4092 wr_reg16(info, SCR, val);
4093
4094 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4095
4096 set_rate(info, info->params.data_rate * 16);
4097
4098 if (info->params.loopback)
4099 enable_loopback(info);
4100 }
4101
4102 static void sync_mode(struct slgt_info *info)
4103 {
4104 unsigned short val;
4105
4106 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4107 tx_stop(info);
4108 rx_stop(info);
4109
4110 /* TCR (tx control)
4111 *
4112 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4113 * 12..10 encoding
4114 * 09 CRC enable
4115 * 08 CRC32
4116 * 07 1=RTS driver control
4117 * 06 preamble enable
4118 * 05..04 preamble length
4119 * 03 share open/close flag
4120 * 02 reset
4121 * 01 enable
4122 * 00 auto-CTS enable
4123 */
4124 val = BIT2;
4125
4126 switch(info->params.mode) {
4127 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4128 case MGSL_MODE_BISYNC: val |= BIT15; break;
4129 case MGSL_MODE_RAW: val |= BIT13; break;
4130 }
4131 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4132 val |= BIT7;
4133
4134 switch(info->params.encoding)
4135 {
4136 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4137 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4138 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4139 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4140 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4141 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4142 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4143 }
4144
4145 switch (info->params.crc_type & HDLC_CRC_MASK)
4146 {
4147 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4148 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4149 }
4150
4151 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4152 val |= BIT6;
4153
4154 switch (info->params.preamble_length)
4155 {
4156 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4157 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4158 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4159 }
4160
4161 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4162 val |= BIT0;
4163
4164 wr_reg16(info, TCR, val);
4165
4166 /* TPR (transmit preamble) */
4167
4168 switch (info->params.preamble)
4169 {
4170 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4171 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4172 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4173 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4174 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4175 default: val = 0x7e; break;
4176 }
4177 wr_reg8(info, TPR, (unsigned char)val);
4178
4179 /* RCR (rx control)
4180 *
4181 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4182 * 12..10 encoding
4183 * 09 CRC enable
4184 * 08 CRC32
4185 * 07..03 reserved, must be 0
4186 * 02 reset
4187 * 01 enable
4188 * 00 auto-DCD enable
4189 */
4190 val = 0;
4191
4192 switch(info->params.mode) {
4193 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4194 case MGSL_MODE_BISYNC: val |= BIT15; break;
4195 case MGSL_MODE_RAW: val |= BIT13; break;
4196 }
4197
4198 switch(info->params.encoding)
4199 {
4200 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4201 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4202 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4203 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4204 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4205 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4206 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4207 }
4208
4209 switch (info->params.crc_type & HDLC_CRC_MASK)
4210 {
4211 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4212 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4213 }
4214
4215 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4216 val |= BIT0;
4217
4218 wr_reg16(info, RCR, val);
4219
4220 /* CCR (clock control)
4221 *
4222 * 07..05 tx clock source
4223 * 04..02 rx clock source
4224 * 01 auxclk enable
4225 * 00 BRG enable
4226 */
4227 val = 0;
4228
4229 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4230 {
4231 // when RxC source is DPLL, BRG generates 16X DPLL
4232 // reference clock, so take TxC from BRG/16 to get
4233 // transmit clock at actual data rate
4234 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4235 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4236 else
4237 val |= BIT6; /* 010, txclk = BRG */
4238 }
4239 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4240 val |= BIT7; /* 100, txclk = DPLL Input */
4241 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4242 val |= BIT5; /* 001, txclk = RXC Input */
4243
4244 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4245 val |= BIT3; /* 010, rxclk = BRG */
4246 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4247 val |= BIT4; /* 100, rxclk = DPLL */
4248 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4249 val |= BIT2; /* 001, rxclk = TXC Input */
4250
4251 if (info->params.clock_speed)
4252 val |= BIT1 + BIT0;
4253
4254 wr_reg8(info, CCR, (unsigned char)val);
4255
4256 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4257 {
4258 // program DPLL mode
4259 switch(info->params.encoding)
4260 {
4261 case HDLC_ENCODING_BIPHASE_MARK:
4262 case HDLC_ENCODING_BIPHASE_SPACE:
4263 val = BIT7; break;
4264 case HDLC_ENCODING_BIPHASE_LEVEL:
4265 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4266 val = BIT7 + BIT6; break;
4267 default: val = BIT6; // NRZ encodings
4268 }
4269 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4270
4271 // DPLL requires a 16X reference clock from BRG
4272 set_rate(info, info->params.clock_speed * 16);
4273 }
4274 else
4275 set_rate(info, info->params.clock_speed);
4276
4277 tx_set_idle(info);
4278
4279 msc_set_vcr(info);
4280
4281 /* SCR (serial control)
4282 *
4283 * 15 1=tx req on FIFO half empty
4284 * 14 1=rx req on FIFO half full
4285 * 13 tx data IRQ enable
4286 * 12 tx idle IRQ enable
4287 * 11 underrun IRQ enable
4288 * 10 rx data IRQ enable
4289 * 09 rx idle IRQ enable
4290 * 08 overrun IRQ enable
4291 * 07 DSR IRQ enable
4292 * 06 CTS IRQ enable
4293 * 05 DCD IRQ enable
4294 * 04 RI IRQ enable
4295 * 03 reserved, must be zero
4296 * 02 1=txd->rxd internal loopback enable
4297 * 01 reserved, must be zero
4298 * 00 1=master IRQ enable
4299 */
4300 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4301
4302 if (info->params.loopback)
4303 enable_loopback(info);
4304 }
4305
4306 /*
4307 * set transmit idle mode
4308 */
4309 static void tx_set_idle(struct slgt_info *info)
4310 {
4311 unsigned char val;
4312 unsigned short tcr;
4313
4314 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4315 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4316 */
4317 tcr = rd_reg16(info, TCR);
4318 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4319 /* disable preamble, set idle size to 16 bits */
4320 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4321 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4322 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4323 } else if (!(tcr & BIT6)) {
4324 /* preamble is disabled, set idle size to 8 bits */
4325 tcr &= ~(BIT5 + BIT4);
4326 }
4327 wr_reg16(info, TCR, tcr);
4328
4329 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4330 /* LSB of custom tx idle specified in tx idle register */
4331 val = (unsigned char)(info->idle_mode & 0xff);
4332 } else {
4333 /* standard 8 bit idle patterns */
4334 switch(info->idle_mode)
4335 {
4336 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4337 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4338 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4339 case HDLC_TXIDLE_ZEROS:
4340 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4341 default: val = 0xff;
4342 }
4343 }
4344
4345 wr_reg8(info, TIR, val);
4346 }
4347
4348 /*
4349 * get state of V24 status (input) signals
4350 */
4351 static void get_signals(struct slgt_info *info)
4352 {
4353 unsigned short status = rd_reg16(info, SSR);
4354
4355 /* clear all serial signals except DTR and RTS */
4356 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4357
4358 if (status & BIT3)
4359 info->signals |= SerialSignal_DSR;
4360 if (status & BIT2)
4361 info->signals |= SerialSignal_CTS;
4362 if (status & BIT1)
4363 info->signals |= SerialSignal_DCD;
4364 if (status & BIT0)
4365 info->signals |= SerialSignal_RI;
4366 }
4367
4368 /*
4369 * set V.24 Control Register based on current configuration
4370 */
4371 static void msc_set_vcr(struct slgt_info *info)
4372 {
4373 unsigned char val = 0;
4374
4375 /* VCR (V.24 control)
4376 *
4377 * 07..04 serial IF select
4378 * 03 DTR
4379 * 02 RTS
4380 * 01 LL
4381 * 00 RL
4382 */
4383
4384 switch(info->if_mode & MGSL_INTERFACE_MASK)
4385 {
4386 case MGSL_INTERFACE_RS232:
4387 val |= BIT5; /* 0010 */
4388 break;
4389 case MGSL_INTERFACE_V35:
4390 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4391 break;
4392 case MGSL_INTERFACE_RS422:
4393 val |= BIT6; /* 0100 */
4394 break;
4395 }
4396
4397 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4398 val |= BIT4;
4399 if (info->signals & SerialSignal_DTR)
4400 val |= BIT3;
4401 if (info->signals & SerialSignal_RTS)
4402 val |= BIT2;
4403 if (info->if_mode & MGSL_INTERFACE_LL)
4404 val |= BIT1;
4405 if (info->if_mode & MGSL_INTERFACE_RL)
4406 val |= BIT0;
4407 wr_reg8(info, VCR, val);
4408 }
4409
4410 /*
4411 * set state of V24 control (output) signals
4412 */
4413 static void set_signals(struct slgt_info *info)
4414 {
4415 unsigned char val = rd_reg8(info, VCR);
4416 if (info->signals & SerialSignal_DTR)
4417 val |= BIT3;
4418 else
4419 val &= ~BIT3;
4420 if (info->signals & SerialSignal_RTS)
4421 val |= BIT2;
4422 else
4423 val &= ~BIT2;
4424 wr_reg8(info, VCR, val);
4425 }
4426
4427 /*
4428 * free range of receive DMA buffers (i to last)
4429 */
4430 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4431 {
4432 int done = 0;
4433
4434 while(!done) {
4435 /* reset current buffer for reuse */
4436 info->rbufs[i].status = 0;
4437 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4438 if (i == last)
4439 done = 1;
4440 if (++i == info->rbuf_count)
4441 i = 0;
4442 }
4443 info->rbuf_current = i;
4444 }
4445
4446 /*
4447 * mark all receive DMA buffers as free
4448 */
4449 static void reset_rbufs(struct slgt_info *info)
4450 {
4451 free_rbufs(info, 0, info->rbuf_count - 1);
4452 }
4453
4454 /*
4455 * pass receive HDLC frame to upper layer
4456 *
4457 * return true if frame available, otherwise false
4458 */
4459 static bool rx_get_frame(struct slgt_info *info)
4460 {
4461 unsigned int start, end;
4462 unsigned short status;
4463 unsigned int framesize = 0;
4464 unsigned long flags;
4465 struct tty_struct *tty = info->port.tty;
4466 unsigned char addr_field = 0xff;
4467 unsigned int crc_size = 0;
4468
4469 switch (info->params.crc_type & HDLC_CRC_MASK) {
4470 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4471 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4472 }
4473
4474 check_again:
4475
4476 framesize = 0;
4477 addr_field = 0xff;
4478 start = end = info->rbuf_current;
4479
4480 for (;;) {
4481 if (!desc_complete(info->rbufs[end]))
4482 goto cleanup;
4483
4484 if (framesize == 0 && info->params.addr_filter != 0xff)
4485 addr_field = info->rbufs[end].buf[0];
4486
4487 framesize += desc_count(info->rbufs[end]);
4488
4489 if (desc_eof(info->rbufs[end]))
4490 break;
4491
4492 if (++end == info->rbuf_count)
4493 end = 0;
4494
4495 if (end == info->rbuf_current) {
4496 if (info->rx_enabled){
4497 spin_lock_irqsave(&info->lock,flags);
4498 rx_start(info);
4499 spin_unlock_irqrestore(&info->lock,flags);
4500 }
4501 goto cleanup;
4502 }
4503 }
4504
4505 /* status
4506 *
4507 * 15 buffer complete
4508 * 14..06 reserved
4509 * 05..04 residue
4510 * 02 eof (end of frame)
4511 * 01 CRC error
4512 * 00 abort
4513 */
4514 status = desc_status(info->rbufs[end]);
4515
4516 /* ignore CRC bit if not using CRC (bit is undefined) */
4517 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4518 status &= ~BIT1;
4519
4520 if (framesize == 0 ||
4521 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4522 free_rbufs(info, start, end);
4523 goto check_again;
4524 }
4525
4526 if (framesize < (2 + crc_size) || status & BIT0) {
4527 info->icount.rxshort++;
4528 framesize = 0;
4529 } else if (status & BIT1) {
4530 info->icount.rxcrc++;
4531 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4532 framesize = 0;
4533 }
4534
4535 #if SYNCLINK_GENERIC_HDLC
4536 if (framesize == 0) {
4537 info->netdev->stats.rx_errors++;
4538 info->netdev->stats.rx_frame_errors++;
4539 }
4540 #endif
4541
4542 DBGBH(("%s rx frame status=%04X size=%d\n",
4543 info->device_name, status, framesize));
4544 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4545
4546 if (framesize) {
4547 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4548 framesize -= crc_size;
4549 crc_size = 0;
4550 }
4551
4552 if (framesize > info->max_frame_size + crc_size)
4553 info->icount.rxlong++;
4554 else {
4555 /* copy dma buffer(s) to contiguous temp buffer */
4556 int copy_count = framesize;
4557 int i = start;
4558 unsigned char *p = info->tmp_rbuf;
4559 info->tmp_rbuf_count = framesize;
4560
4561 info->icount.rxok++;
4562
4563 while(copy_count) {
4564 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4565 memcpy(p, info->rbufs[i].buf, partial_count);
4566 p += partial_count;
4567 copy_count -= partial_count;
4568 if (++i == info->rbuf_count)
4569 i = 0;
4570 }
4571
4572 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4573 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4574 framesize++;
4575 }
4576
4577 #if SYNCLINK_GENERIC_HDLC
4578 if (info->netcount)
4579 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4580 else
4581 #endif
4582 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4583 }
4584 }
4585 free_rbufs(info, start, end);
4586 return true;
4587
4588 cleanup:
4589 return false;
4590 }
4591
4592 /*
4593 * pass receive buffer (RAW synchronous mode) to tty layer
4594 * return true if buffer available, otherwise false
4595 */
4596 static bool rx_get_buf(struct slgt_info *info)
4597 {
4598 unsigned int i = info->rbuf_current;
4599 unsigned int count;
4600
4601 if (!desc_complete(info->rbufs[i]))
4602 return false;
4603 count = desc_count(info->rbufs[i]);
4604 switch(info->params.mode) {
4605 case MGSL_MODE_MONOSYNC:
4606 case MGSL_MODE_BISYNC:
4607 /* ignore residue in byte synchronous modes */
4608 if (desc_residue(info->rbufs[i]))
4609 count--;
4610 break;
4611 }
4612 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4613 DBGINFO(("rx_get_buf size=%d\n", count));
4614 if (count)
4615 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4616 info->flag_buf, count);
4617 free_rbufs(info, i, i);
4618 return true;
4619 }
4620
4621 static void reset_tbufs(struct slgt_info *info)
4622 {
4623 unsigned int i;
4624 info->tbuf_current = 0;
4625 for (i=0 ; i < info->tbuf_count ; i++) {
4626 info->tbufs[i].status = 0;
4627 info->tbufs[i].count = 0;
4628 }
4629 }
4630
4631 /*
4632 * return number of free transmit DMA buffers
4633 */
4634 static unsigned int free_tbuf_count(struct slgt_info *info)
4635 {
4636 unsigned int count = 0;
4637 unsigned int i = info->tbuf_current;
4638
4639 do
4640 {
4641 if (desc_count(info->tbufs[i]))
4642 break; /* buffer in use */
4643 ++count;
4644 if (++i == info->tbuf_count)
4645 i=0;
4646 } while (i != info->tbuf_current);
4647
4648 /* if tx DMA active, last zero count buffer is in use */
4649 if (count && (rd_reg32(info, TDCSR) & BIT0))
4650 --count;
4651
4652 return count;
4653 }
4654
4655 /*
4656 * return number of bytes in unsent transmit DMA buffers
4657 * and the serial controller tx FIFO
4658 */
4659 static unsigned int tbuf_bytes(struct slgt_info *info)
4660 {
4661 unsigned int total_count = 0;
4662 unsigned int i = info->tbuf_current;
4663 unsigned int reg_value;
4664 unsigned int count;
4665 unsigned int active_buf_count = 0;
4666
4667 /*
4668 * Add descriptor counts for all tx DMA buffers.
4669 * If count is zero (cleared by DMA controller after read),
4670 * the buffer is complete or is actively being read from.
4671 *
4672 * Record buf_count of last buffer with zero count starting
4673 * from current ring position. buf_count is mirror
4674 * copy of count and is not cleared by serial controller.
4675 * If DMA controller is active, that buffer is actively
4676 * being read so add to total.
4677 */
4678 do {
4679 count = desc_count(info->tbufs[i]);
4680 if (count)
4681 total_count += count;
4682 else if (!total_count)
4683 active_buf_count = info->tbufs[i].buf_count;
4684 if (++i == info->tbuf_count)
4685 i = 0;
4686 } while (i != info->tbuf_current);
4687
4688 /* read tx DMA status register */
4689 reg_value = rd_reg32(info, TDCSR);
4690
4691 /* if tx DMA active, last zero count buffer is in use */
4692 if (reg_value & BIT0)
4693 total_count += active_buf_count;
4694
4695 /* add tx FIFO count = reg_value[15..8] */
4696 total_count += (reg_value >> 8) & 0xff;
4697
4698 /* if transmitter active add one byte for shift register */
4699 if (info->tx_active)
4700 total_count++;
4701
4702 return total_count;
4703 }
4704
4705 /*
4706 * load transmit DMA buffer(s) with data
4707 */
4708 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4709 {
4710 unsigned short count;
4711 unsigned int i;
4712 struct slgt_desc *d;
4713
4714 if (size == 0)
4715 return;
4716
4717 DBGDATA(info, buf, size, "tx");
4718
4719 info->tbuf_start = i = info->tbuf_current;
4720
4721 while (size) {
4722 d = &info->tbufs[i];
4723 if (++i == info->tbuf_count)
4724 i = 0;
4725
4726 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4727 memcpy(d->buf, buf, count);
4728
4729 size -= count;
4730 buf += count;
4731
4732 /*
4733 * set EOF bit for last buffer of HDLC frame or
4734 * for every buffer in raw mode
4735 */
4736 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4737 info->params.mode == MGSL_MODE_RAW)
4738 set_desc_eof(*d, 1);
4739 else
4740 set_desc_eof(*d, 0);
4741
4742 set_desc_count(*d, count);
4743 d->buf_count = count;
4744 }
4745
4746 info->tbuf_current = i;
4747 }
4748
4749 static int register_test(struct slgt_info *info)
4750 {
4751 static unsigned short patterns[] =
4752 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4753 static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4754 unsigned int i;
4755 int rc = 0;
4756
4757 for (i=0 ; i < count ; i++) {
4758 wr_reg16(info, TIR, patterns[i]);
4759 wr_reg16(info, BDR, patterns[(i+1)%count]);
4760 if ((rd_reg16(info, TIR) != patterns[i]) ||
4761 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4762 rc = -ENODEV;
4763 break;
4764 }
4765 }
4766 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4767 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4768 return rc;
4769 }
4770
4771 static int irq_test(struct slgt_info *info)
4772 {
4773 unsigned long timeout;
4774 unsigned long flags;
4775 struct tty_struct *oldtty = info->port.tty;
4776 u32 speed = info->params.data_rate;
4777
4778 info->params.data_rate = 921600;
4779 info->port.tty = NULL;
4780
4781 spin_lock_irqsave(&info->lock, flags);
4782 async_mode(info);
4783 slgt_irq_on(info, IRQ_TXIDLE);
4784
4785 /* enable transmitter */
4786 wr_reg16(info, TCR,
4787 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4788
4789 /* write one byte and wait for tx idle */
4790 wr_reg16(info, TDR, 0);
4791
4792 /* assume failure */
4793 info->init_error = DiagStatus_IrqFailure;
4794 info->irq_occurred = false;
4795
4796 spin_unlock_irqrestore(&info->lock, flags);
4797
4798 timeout=100;
4799 while(timeout-- && !info->irq_occurred)
4800 msleep_interruptible(10);
4801
4802 spin_lock_irqsave(&info->lock,flags);
4803 reset_port(info);
4804 spin_unlock_irqrestore(&info->lock,flags);
4805
4806 info->params.data_rate = speed;
4807 info->port.tty = oldtty;
4808
4809 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4810 return info->irq_occurred ? 0 : -ENODEV;
4811 }
4812
4813 static int loopback_test_rx(struct slgt_info *info)
4814 {
4815 unsigned char *src, *dest;
4816 int count;
4817
4818 if (desc_complete(info->rbufs[0])) {
4819 count = desc_count(info->rbufs[0]);
4820 src = info->rbufs[0].buf;
4821 dest = info->tmp_rbuf;
4822
4823 for( ; count ; count-=2, src+=2) {
4824 /* src=data byte (src+1)=status byte */
4825 if (!(*(src+1) & (BIT9 + BIT8))) {
4826 *dest = *src;
4827 dest++;
4828 info->tmp_rbuf_count++;
4829 }
4830 }
4831 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4832 return 1;
4833 }
4834 return 0;
4835 }
4836
4837 static int loopback_test(struct slgt_info *info)
4838 {
4839 #define TESTFRAMESIZE 20
4840
4841 unsigned long timeout;
4842 u16 count = TESTFRAMESIZE;
4843 unsigned char buf[TESTFRAMESIZE];
4844 int rc = -ENODEV;
4845 unsigned long flags;
4846
4847 struct tty_struct *oldtty = info->port.tty;
4848 MGSL_PARAMS params;
4849
4850 memcpy(&params, &info->params, sizeof(params));
4851
4852 info->params.mode = MGSL_MODE_ASYNC;
4853 info->params.data_rate = 921600;
4854 info->params.loopback = 1;
4855 info->port.tty = NULL;
4856
4857 /* build and send transmit frame */
4858 for (count = 0; count < TESTFRAMESIZE; ++count)
4859 buf[count] = (unsigned char)count;
4860
4861 info->tmp_rbuf_count = 0;
4862 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4863
4864 /* program hardware for HDLC and enabled receiver */
4865 spin_lock_irqsave(&info->lock,flags);
4866 async_mode(info);
4867 rx_start(info);
4868 info->tx_count = count;
4869 tx_load(info, buf, count);
4870 tx_start(info);
4871 spin_unlock_irqrestore(&info->lock, flags);
4872
4873 /* wait for receive complete */
4874 for (timeout = 100; timeout; --timeout) {
4875 msleep_interruptible(10);
4876 if (loopback_test_rx(info)) {
4877 rc = 0;
4878 break;
4879 }
4880 }
4881
4882 /* verify received frame length and contents */
4883 if (!rc && (info->tmp_rbuf_count != count ||
4884 memcmp(buf, info->tmp_rbuf, count))) {
4885 rc = -ENODEV;
4886 }
4887
4888 spin_lock_irqsave(&info->lock,flags);
4889 reset_adapter(info);
4890 spin_unlock_irqrestore(&info->lock,flags);
4891
4892 memcpy(&info->params, &params, sizeof(info->params));
4893 info->port.tty = oldtty;
4894
4895 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4896 return rc;
4897 }
4898
4899 static int adapter_test(struct slgt_info *info)
4900 {
4901 DBGINFO(("testing %s\n", info->device_name));
4902 if (register_test(info) < 0) {
4903 printk("register test failure %s addr=%08X\n",
4904 info->device_name, info->phys_reg_addr);
4905 } else if (irq_test(info) < 0) {
4906 printk("IRQ test failure %s IRQ=%d\n",
4907 info->device_name, info->irq_level);
4908 } else if (loopback_test(info) < 0) {
4909 printk("loopback test failure %s\n", info->device_name);
4910 }
4911 return info->init_error;
4912 }
4913
4914 /*
4915 * transmit timeout handler
4916 */
4917 static void tx_timeout(unsigned long context)
4918 {
4919 struct slgt_info *info = (struct slgt_info*)context;
4920 unsigned long flags;
4921
4922 DBGINFO(("%s tx_timeout\n", info->device_name));
4923 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4924 info->icount.txtimeout++;
4925 }
4926 spin_lock_irqsave(&info->lock,flags);
4927 info->tx_active = false;
4928 info->tx_count = 0;
4929 spin_unlock_irqrestore(&info->lock,flags);
4930
4931 #if SYNCLINK_GENERIC_HDLC
4932 if (info->netcount)
4933 hdlcdev_tx_done(info);
4934 else
4935 #endif
4936 bh_transmit(info);
4937 }
4938
4939 /*
4940 * receive buffer polling timer
4941 */
4942 static void rx_timeout(unsigned long context)
4943 {
4944 struct slgt_info *info = (struct slgt_info*)context;
4945 unsigned long flags;
4946
4947 DBGINFO(("%s rx_timeout\n", info->device_name));
4948 spin_lock_irqsave(&info->lock, flags);
4949 info->pending_bh |= BH_RECEIVE;
4950 spin_unlock_irqrestore(&info->lock, flags);
4951 bh_handler(&info->task);
4952 }
4953
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