arch/x86/kernel/irqinit_32.c

   1 #include <linux/errno.h>
   2 #include <linux/signal.h>
   3 #include <linux/sched.h>
   4 #include <linux/ioport.h>
   5 #include <linux/interrupt.h>
   6 #include <linux/slab.h>
   7 #include <linux/random.h>
   8 #include <linux/init.h>
   9 #include <linux/kernel_stat.h>
  10 #include <linux/sysdev.h>
  11 #include <linux/bitops.h>
  12 #include <linux/io.h>
  13 #include <linux/delay.h>
  14
  15 #include <asm/atomic.h>
  16 #include <asm/system.h>
  17 #include <asm/timer.h>
  18 #include <asm/pgtable.h>
  19 #include <asm/desc.h>
  20 #include <asm/apic.h>
  21 #include <asm/setup.h>
  22 #include <asm/i8259.h>
  23 #include <asm/traps.h>
  24
  25
  26 /*
  27  * Note that on a 486, we don't want to do a SIGFPE on an irq13
  28  * as the irq is unreliable, and exception 16 works correctly
  29  * (ie as explained in the intel literature). On a 386, you
  30  * can't use exception 16 due to bad IBM design, so we have to
  31  * rely on the less exact irq13.
  32  *
  33  * Careful.. Not only is IRQ13 unreliable, but it is also
  34  * leads to races. IBM designers who came up with it should
  35  * be shot.
  36  */
  37
  38 static irqreturn_t math_error_irq(int cpl, void *dev_id)
  39 {
  40         outb(0, 0xF0);
  41         if (ignore_fpu_irq || !boot_cpu_data.hard_math)
  42                 return IRQ_NONE;
  43         math_error((void __user *)get_irq_regs()->ip);
  44         return IRQ_HANDLED;
  45 }
  46
  47 /*
  48  * New motherboards sometimes make IRQ 13 be a PCI interrupt,
  49  * so allow interrupt sharing.
  50  */
  51 static struct irqaction fpu_irq = {
  52         .handler = math_error_irq,
  53         .name = "fpu",
  54 };
  55
  56 /*
  57  * IRQ2 is cascade interrupt to second interrupt controller
  58  */
  59 static struct irqaction irq2 = {
  60         .handler = no_action,
  61         .name = "cascade",
  62 };
  63
  64 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
  65         [0 ... IRQ0_VECTOR - 1] = -1,
  66         [IRQ0_VECTOR] = 0,
  67         [IRQ1_VECTOR] = 1,
  68         [IRQ2_VECTOR] = 2,
  69         [IRQ3_VECTOR] = 3,
  70         [IRQ4_VECTOR] = 4,
  71         [IRQ5_VECTOR] = 5,
  72         [IRQ6_VECTOR] = 6,
  73         [IRQ7_VECTOR] = 7,
  74         [IRQ8_VECTOR] = 8,
  75         [IRQ9_VECTOR] = 9,
  76         [IRQ10_VECTOR] = 10,
  77         [IRQ11_VECTOR] = 11,
  78         [IRQ12_VECTOR] = 12,
  79         [IRQ13_VECTOR] = 13,
  80         [IRQ14_VECTOR] = 14,
  81         [IRQ15_VECTOR] = 15,
  82         [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
  83 };
  84
  85 int vector_used_by_percpu_irq(unsigned int vector)
  86 {
  87         int cpu;
  88
  89         for_each_online_cpu(cpu) {
  90                 if (per_cpu(vector_irq, cpu)[vector] != -1)
  91                         return 1;
  92         }
  93
  94         return 0;
  95 }
  96
  97 static void __init init_ISA_irqs(void)
  98 {
  99         int i;
 100
 101 #ifdef CONFIG_X86_LOCAL_APIC
 102         init_bsp_APIC();
 103 #endif
 104         init_8259A(0);
 105
 106         /*
 107          * 16 old-style INTA-cycle interrupts:
 108          */
 109         for (i = 0; i < NR_IRQS_LEGACY; i++) {
 110                 struct irq_desc *desc = irq_to_desc(i);
 111
 112                 desc->status = IRQ_DISABLED;
 113                 desc->action = NULL;
 114                 desc->depth = 1;
 115
 116                 set_irq_chip_and_handler_name(i, &i8259A_chip,
 117                                               handle_level_irq, "XT");
 118         }
 119 }
 120
 121 /* Overridden in paravirt.c */
 122 void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
 123
 124 static void __init smp_intr_init(void)
 125 {
 126 #ifdef CONFIG_SMP
 127 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
 128         /*
 129          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 130          * IPI, driven by wakeup.
 131          */
 132         alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 133
 134         /* IPIs for invalidation */
 135         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
 136         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
 137         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
 138         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
 139         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
 140         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
 141         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
 142         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
 143
 144         /* IPI for generic function call */
 145         alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 146
 147         /* IPI for generic single function call */
 148         alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
 149                         call_function_single_interrupt);
 150
 151         /* Low priority IPI to cleanup after moving an irq */
 152         set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
 153         set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);
 154 #endif
 155 #endif /* CONFIG_SMP */
 156 }
 157
 158 /**
 159  * x86_quirk_pre_intr_init - initialisation prior to setting up interrupt vectors
 160  *
 161  * Description:
 162  *      Perform any necessary interrupt initialisation prior to setting up
 163  *      the "ordinary" interrupt call gates.  For legacy reasons, the ISA
 164  *      interrupts should be initialised here if the machine emulates a PC
 165  *      in any way.
 166  **/
 167 static void __init x86_quirk_pre_intr_init(void)
 168 {
 169         if (x86_quirks->arch_pre_intr_init) {
 170                 if (x86_quirks->arch_pre_intr_init())
 171                         return;
 172         }
 173         init_ISA_irqs();
 174 }
 175
 176 static void __init apic_intr_init(void)
 177 {
 178         smp_intr_init();
 179
 180 #ifdef CONFIG_X86_LOCAL_APIC
 181         /* self generated IPI for local APIC timer */
 182         alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 183
 184         /* generic IPI for platform specific use */
 185         alloc_intr_gate(GENERIC_INTERRUPT_VECTOR, generic_interrupt);
 186
 187         /* IPI vectors for APIC spurious and error interrupts */
 188         alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 189         alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 190 #endif
 191
 192 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_MCE_P4THERMAL)
 193         /* thermal monitor LVT interrupt */
 194         alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 195 #endif
 196 }
 197
 198 void __init native_init_IRQ(void)
 199 {
 200         int i;
 201
 202         /* Execute any quirks before the call gates are initialised: */
 203         x86_quirk_pre_intr_init();
 204
 205         /*
 206          * Cover the whole vector space, no vector can escape
 207          * us. (some of these will be overridden and become
 208          * 'special' SMP interrupts)
 209          */
 210         for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) {
 211                 /* SYSCALL_VECTOR was reserved in trap_init. */
 212                 if (i != SYSCALL_VECTOR)
 213                         set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
 214         }
 215
 216         apic_intr_init();
 217
 218         if (!acpi_ioapic)
 219                 setup_irq(2, &irq2);
 220
 221         /*
 222          * Call quirks after call gates are initialised (usually add in
 223          * the architecture specific gates):
 224          */
 225         x86_quirk_intr_init();
 226
 227         /*
 228          * External FPU? Set up irq13 if so, for
 229          * original braindamaged IBM FERR coupling.
 230          */
 231         if (boot_cpu_data.hard_math && !cpu_has_fpu)
 232                 setup_irq(FPU_IRQ, &fpu_irq);
 233
 234         irq_ctx_init(smp_processor_id());
 235 }